am43xx-clocks.dtsi revision 279377
1279377Simp/* 2279377Simp * Device Tree Source for AM43xx clock data 3279377Simp * 4279377Simp * Copyright (C) 2013 Texas Instruments, Inc. 5279377Simp * 6279377Simp * This program is free software; you can redistribute it and/or modify 7279377Simp * it under the terms of the GNU General Public License version 2 as 8279377Simp * published by the Free Software Foundation. 9279377Simp */ 10279377Simp&scrm_clocks { 11279377Simp sys_clkin_ck: sys_clkin_ck { 12279377Simp #clock-cells = <0>; 13279377Simp compatible = "ti,mux-clock"; 14279377Simp clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; 15279377Simp ti,bit-shift = <31>; 16279377Simp reg = <0x0040>; 17279377Simp }; 18279377Simp 19279377Simp crystal_freq_sel_ck: crystal_freq_sel_ck { 20279377Simp #clock-cells = <0>; 21279377Simp compatible = "ti,mux-clock"; 22279377Simp clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; 23279377Simp ti,bit-shift = <29>; 24279377Simp reg = <0x0040>; 25279377Simp }; 26279377Simp 27279377Simp sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 { 28279377Simp #clock-cells = <0>; 29279377Simp compatible = "ti,mux-clock"; 30279377Simp clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; 31279377Simp ti,bit-shift = <22>; 32279377Simp reg = <0x0040>; 33279377Simp }; 34279377Simp 35279377Simp adc_tsc_fck: adc_tsc_fck { 36279377Simp #clock-cells = <0>; 37279377Simp compatible = "fixed-factor-clock"; 38279377Simp clocks = <&sys_clkin_ck>; 39279377Simp clock-mult = <1>; 40279377Simp clock-div = <1>; 41279377Simp }; 42279377Simp 43279377Simp dcan0_fck: dcan0_fck { 44279377Simp #clock-cells = <0>; 45279377Simp compatible = "fixed-factor-clock"; 46279377Simp clocks = <&sys_clkin_ck>; 47279377Simp clock-mult = <1>; 48279377Simp clock-div = <1>; 49279377Simp }; 50279377Simp 51279377Simp dcan1_fck: dcan1_fck { 52279377Simp #clock-cells = <0>; 53279377Simp compatible = "fixed-factor-clock"; 54279377Simp clocks = <&sys_clkin_ck>; 55279377Simp clock-mult = <1>; 56279377Simp clock-div = <1>; 57279377Simp }; 58279377Simp 59279377Simp mcasp0_fck: mcasp0_fck { 60279377Simp #clock-cells = <0>; 61279377Simp compatible = "fixed-factor-clock"; 62279377Simp clocks = <&sys_clkin_ck>; 63279377Simp clock-mult = <1>; 64279377Simp clock-div = <1>; 65279377Simp }; 66279377Simp 67279377Simp mcasp1_fck: mcasp1_fck { 68279377Simp #clock-cells = <0>; 69279377Simp compatible = "fixed-factor-clock"; 70279377Simp clocks = <&sys_clkin_ck>; 71279377Simp clock-mult = <1>; 72279377Simp clock-div = <1>; 73279377Simp }; 74279377Simp 75279377Simp smartreflex0_fck: smartreflex0_fck { 76279377Simp #clock-cells = <0>; 77279377Simp compatible = "fixed-factor-clock"; 78279377Simp clocks = <&sys_clkin_ck>; 79279377Simp clock-mult = <1>; 80279377Simp clock-div = <1>; 81279377Simp }; 82279377Simp 83279377Simp smartreflex1_fck: smartreflex1_fck { 84279377Simp #clock-cells = <0>; 85279377Simp compatible = "fixed-factor-clock"; 86279377Simp clocks = <&sys_clkin_ck>; 87279377Simp clock-mult = <1>; 88279377Simp clock-div = <1>; 89279377Simp }; 90279377Simp 91279377Simp sha0_fck: sha0_fck { 92279377Simp #clock-cells = <0>; 93279377Simp compatible = "fixed-factor-clock"; 94279377Simp clocks = <&sys_clkin_ck>; 95279377Simp clock-mult = <1>; 96279377Simp clock-div = <1>; 97279377Simp }; 98279377Simp 99279377Simp aes0_fck: aes0_fck { 100279377Simp #clock-cells = <0>; 101279377Simp compatible = "fixed-factor-clock"; 102279377Simp clocks = <&sys_clkin_ck>; 103279377Simp clock-mult = <1>; 104279377Simp clock-div = <1>; 105279377Simp }; 106279377Simp 107279377Simp ehrpwm0_tbclk: ehrpwm0_tbclk { 108279377Simp #clock-cells = <0>; 109279377Simp compatible = "ti,gate-clock"; 110279377Simp clocks = <&dpll_per_m2_ck>; 111279377Simp ti,bit-shift = <0>; 112279377Simp reg = <0x0664>; 113279377Simp }; 114279377Simp 115279377Simp ehrpwm1_tbclk: ehrpwm1_tbclk { 116279377Simp #clock-cells = <0>; 117279377Simp compatible = "ti,gate-clock"; 118279377Simp clocks = <&dpll_per_m2_ck>; 119279377Simp ti,bit-shift = <1>; 120279377Simp reg = <0x0664>; 121279377Simp }; 122279377Simp 123279377Simp ehrpwm2_tbclk: ehrpwm2_tbclk { 124279377Simp #clock-cells = <0>; 125279377Simp compatible = "ti,gate-clock"; 126279377Simp clocks = <&dpll_per_m2_ck>; 127279377Simp ti,bit-shift = <2>; 128279377Simp reg = <0x0664>; 129279377Simp }; 130279377Simp 131279377Simp ehrpwm3_tbclk: ehrpwm3_tbclk { 132279377Simp #clock-cells = <0>; 133279377Simp compatible = "ti,gate-clock"; 134279377Simp clocks = <&dpll_per_m2_ck>; 135279377Simp ti,bit-shift = <4>; 136279377Simp reg = <0x0664>; 137279377Simp }; 138279377Simp 139279377Simp ehrpwm4_tbclk: ehrpwm4_tbclk { 140279377Simp #clock-cells = <0>; 141279377Simp compatible = "ti,gate-clock"; 142279377Simp clocks = <&dpll_per_m2_ck>; 143279377Simp ti,bit-shift = <5>; 144279377Simp reg = <0x0664>; 145279377Simp }; 146279377Simp 147279377Simp ehrpwm5_tbclk: ehrpwm5_tbclk { 148279377Simp #clock-cells = <0>; 149279377Simp compatible = "ti,gate-clock"; 150279377Simp clocks = <&dpll_per_m2_ck>; 151279377Simp ti,bit-shift = <6>; 152279377Simp reg = <0x0664>; 153279377Simp }; 154279377Simp}; 155279377Simp&prcm_clocks { 156279377Simp clk_32768_ck: clk_32768_ck { 157279377Simp #clock-cells = <0>; 158279377Simp compatible = "fixed-clock"; 159279377Simp clock-frequency = <32768>; 160279377Simp }; 161279377Simp 162279377Simp clk_rc32k_ck: clk_rc32k_ck { 163279377Simp #clock-cells = <0>; 164279377Simp compatible = "fixed-clock"; 165279377Simp clock-frequency = <32768>; 166279377Simp }; 167279377Simp 168279377Simp virt_19200000_ck: virt_19200000_ck { 169279377Simp #clock-cells = <0>; 170279377Simp compatible = "fixed-clock"; 171279377Simp clock-frequency = <19200000>; 172279377Simp }; 173279377Simp 174279377Simp virt_24000000_ck: virt_24000000_ck { 175279377Simp #clock-cells = <0>; 176279377Simp compatible = "fixed-clock"; 177279377Simp clock-frequency = <24000000>; 178279377Simp }; 179279377Simp 180279377Simp virt_25000000_ck: virt_25000000_ck { 181279377Simp #clock-cells = <0>; 182279377Simp compatible = "fixed-clock"; 183279377Simp clock-frequency = <25000000>; 184279377Simp }; 185279377Simp 186279377Simp virt_26000000_ck: virt_26000000_ck { 187279377Simp #clock-cells = <0>; 188279377Simp compatible = "fixed-clock"; 189279377Simp clock-frequency = <26000000>; 190279377Simp }; 191279377Simp 192279377Simp tclkin_ck: tclkin_ck { 193279377Simp #clock-cells = <0>; 194279377Simp compatible = "fixed-clock"; 195279377Simp clock-frequency = <26000000>; 196279377Simp }; 197279377Simp 198279377Simp dpll_core_ck: dpll_core_ck { 199279377Simp #clock-cells = <0>; 200279377Simp compatible = "ti,am3-dpll-core-clock"; 201279377Simp clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 202279377Simp reg = <0x2d20>, <0x2d24>, <0x2d2c>; 203279377Simp }; 204279377Simp 205279377Simp dpll_core_x2_ck: dpll_core_x2_ck { 206279377Simp #clock-cells = <0>; 207279377Simp compatible = "ti,am3-dpll-x2-clock"; 208279377Simp clocks = <&dpll_core_ck>; 209279377Simp }; 210279377Simp 211279377Simp dpll_core_m4_ck: dpll_core_m4_ck { 212279377Simp #clock-cells = <0>; 213279377Simp compatible = "ti,divider-clock"; 214279377Simp clocks = <&dpll_core_x2_ck>; 215279377Simp ti,max-div = <31>; 216279377Simp ti,autoidle-shift = <8>; 217279377Simp reg = <0x2d38>; 218279377Simp ti,index-starts-at-one; 219279377Simp ti,invert-autoidle-bit; 220279377Simp }; 221279377Simp 222279377Simp dpll_core_m5_ck: dpll_core_m5_ck { 223279377Simp #clock-cells = <0>; 224279377Simp compatible = "ti,divider-clock"; 225279377Simp clocks = <&dpll_core_x2_ck>; 226279377Simp ti,max-div = <31>; 227279377Simp ti,autoidle-shift = <8>; 228279377Simp reg = <0x2d3c>; 229279377Simp ti,index-starts-at-one; 230279377Simp ti,invert-autoidle-bit; 231279377Simp }; 232279377Simp 233279377Simp dpll_core_m6_ck: dpll_core_m6_ck { 234279377Simp #clock-cells = <0>; 235279377Simp compatible = "ti,divider-clock"; 236279377Simp clocks = <&dpll_core_x2_ck>; 237279377Simp ti,max-div = <31>; 238279377Simp ti,autoidle-shift = <8>; 239279377Simp reg = <0x2d40>; 240279377Simp ti,index-starts-at-one; 241279377Simp ti,invert-autoidle-bit; 242279377Simp }; 243279377Simp 244279377Simp dpll_mpu_ck: dpll_mpu_ck { 245279377Simp #clock-cells = <0>; 246279377Simp compatible = "ti,am3-dpll-clock"; 247279377Simp clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 248279377Simp reg = <0x2d60>, <0x2d64>, <0x2d6c>; 249279377Simp }; 250279377Simp 251279377Simp dpll_mpu_m2_ck: dpll_mpu_m2_ck { 252279377Simp #clock-cells = <0>; 253279377Simp compatible = "ti,divider-clock"; 254279377Simp clocks = <&dpll_mpu_ck>; 255279377Simp ti,max-div = <31>; 256279377Simp ti,autoidle-shift = <8>; 257279377Simp reg = <0x2d70>; 258279377Simp ti,index-starts-at-one; 259279377Simp ti,invert-autoidle-bit; 260279377Simp }; 261279377Simp 262279377Simp dpll_ddr_ck: dpll_ddr_ck { 263279377Simp #clock-cells = <0>; 264279377Simp compatible = "ti,am3-dpll-clock"; 265279377Simp clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 266279377Simp reg = <0x2da0>, <0x2da4>, <0x2dac>; 267279377Simp }; 268279377Simp 269279377Simp dpll_ddr_m2_ck: dpll_ddr_m2_ck { 270279377Simp #clock-cells = <0>; 271279377Simp compatible = "ti,divider-clock"; 272279377Simp clocks = <&dpll_ddr_ck>; 273279377Simp ti,max-div = <31>; 274279377Simp ti,autoidle-shift = <8>; 275279377Simp reg = <0x2db0>; 276279377Simp ti,index-starts-at-one; 277279377Simp ti,invert-autoidle-bit; 278279377Simp }; 279279377Simp 280279377Simp dpll_disp_ck: dpll_disp_ck { 281279377Simp #clock-cells = <0>; 282279377Simp compatible = "ti,am3-dpll-clock"; 283279377Simp clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 284279377Simp reg = <0x2e20>, <0x2e24>, <0x2e2c>; 285279377Simp }; 286279377Simp 287279377Simp dpll_disp_m2_ck: dpll_disp_m2_ck { 288279377Simp #clock-cells = <0>; 289279377Simp compatible = "ti,divider-clock"; 290279377Simp clocks = <&dpll_disp_ck>; 291279377Simp ti,max-div = <31>; 292279377Simp ti,autoidle-shift = <8>; 293279377Simp reg = <0x2e30>; 294279377Simp ti,index-starts-at-one; 295279377Simp ti,invert-autoidle-bit; 296279377Simp ti,set-rate-parent; 297279377Simp }; 298279377Simp 299279377Simp dpll_per_ck: dpll_per_ck { 300279377Simp #clock-cells = <0>; 301279377Simp compatible = "ti,am3-dpll-j-type-clock"; 302279377Simp clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 303279377Simp reg = <0x2de0>, <0x2de4>, <0x2dec>; 304279377Simp }; 305279377Simp 306279377Simp dpll_per_m2_ck: dpll_per_m2_ck { 307279377Simp #clock-cells = <0>; 308279377Simp compatible = "ti,divider-clock"; 309279377Simp clocks = <&dpll_per_ck>; 310279377Simp ti,max-div = <127>; 311279377Simp ti,autoidle-shift = <8>; 312279377Simp reg = <0x2df0>; 313279377Simp ti,index-starts-at-one; 314279377Simp ti,invert-autoidle-bit; 315279377Simp }; 316279377Simp 317279377Simp dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { 318279377Simp #clock-cells = <0>; 319279377Simp compatible = "fixed-factor-clock"; 320279377Simp clocks = <&dpll_per_m2_ck>; 321279377Simp clock-mult = <1>; 322279377Simp clock-div = <4>; 323279377Simp }; 324279377Simp 325279377Simp dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { 326279377Simp #clock-cells = <0>; 327279377Simp compatible = "fixed-factor-clock"; 328279377Simp clocks = <&dpll_per_m2_ck>; 329279377Simp clock-mult = <1>; 330279377Simp clock-div = <4>; 331279377Simp }; 332279377Simp 333279377Simp clk_24mhz: clk_24mhz { 334279377Simp #clock-cells = <0>; 335279377Simp compatible = "fixed-factor-clock"; 336279377Simp clocks = <&dpll_per_m2_ck>; 337279377Simp clock-mult = <1>; 338279377Simp clock-div = <8>; 339279377Simp }; 340279377Simp 341279377Simp clkdiv32k_ck: clkdiv32k_ck { 342279377Simp #clock-cells = <0>; 343279377Simp compatible = "fixed-factor-clock"; 344279377Simp clocks = <&clk_24mhz>; 345279377Simp clock-mult = <1>; 346279377Simp clock-div = <732>; 347279377Simp }; 348279377Simp 349279377Simp clkdiv32k_ick: clkdiv32k_ick { 350279377Simp #clock-cells = <0>; 351279377Simp compatible = "ti,gate-clock"; 352279377Simp clocks = <&clkdiv32k_ck>; 353279377Simp ti,bit-shift = <8>; 354279377Simp reg = <0x2a38>; 355279377Simp }; 356279377Simp 357279377Simp sysclk_div: sysclk_div { 358279377Simp #clock-cells = <0>; 359279377Simp compatible = "fixed-factor-clock"; 360279377Simp clocks = <&dpll_core_m4_ck>; 361279377Simp clock-mult = <1>; 362279377Simp clock-div = <1>; 363279377Simp }; 364279377Simp 365279377Simp pruss_ocp_gclk: pruss_ocp_gclk { 366279377Simp #clock-cells = <0>; 367279377Simp compatible = "ti,mux-clock"; 368279377Simp clocks = <&sysclk_div>, <&dpll_disp_m2_ck>; 369279377Simp reg = <0x4248>; 370279377Simp }; 371279377Simp 372279377Simp clk_32k_tpm_ck: clk_32k_tpm_ck { 373279377Simp #clock-cells = <0>; 374279377Simp compatible = "fixed-clock"; 375279377Simp clock-frequency = <32768>; 376279377Simp }; 377279377Simp 378279377Simp timer1_fck: timer1_fck { 379279377Simp #clock-cells = <0>; 380279377Simp compatible = "ti,mux-clock"; 381279377Simp clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>; 382279377Simp reg = <0x4200>; 383279377Simp }; 384279377Simp 385279377Simp timer2_fck: timer2_fck { 386279377Simp #clock-cells = <0>; 387279377Simp compatible = "ti,mux-clock"; 388279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 389279377Simp reg = <0x4204>; 390279377Simp }; 391279377Simp 392279377Simp timer3_fck: timer3_fck { 393279377Simp #clock-cells = <0>; 394279377Simp compatible = "ti,mux-clock"; 395279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 396279377Simp reg = <0x4208>; 397279377Simp }; 398279377Simp 399279377Simp timer4_fck: timer4_fck { 400279377Simp #clock-cells = <0>; 401279377Simp compatible = "ti,mux-clock"; 402279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 403279377Simp reg = <0x420c>; 404279377Simp }; 405279377Simp 406279377Simp timer5_fck: timer5_fck { 407279377Simp #clock-cells = <0>; 408279377Simp compatible = "ti,mux-clock"; 409279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 410279377Simp reg = <0x4210>; 411279377Simp }; 412279377Simp 413279377Simp timer6_fck: timer6_fck { 414279377Simp #clock-cells = <0>; 415279377Simp compatible = "ti,mux-clock"; 416279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 417279377Simp reg = <0x4214>; 418279377Simp }; 419279377Simp 420279377Simp timer7_fck: timer7_fck { 421279377Simp #clock-cells = <0>; 422279377Simp compatible = "ti,mux-clock"; 423279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 424279377Simp reg = <0x4218>; 425279377Simp }; 426279377Simp 427279377Simp wdt1_fck: wdt1_fck { 428279377Simp #clock-cells = <0>; 429279377Simp compatible = "ti,mux-clock"; 430279377Simp clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; 431279377Simp reg = <0x422c>; 432279377Simp }; 433279377Simp 434279377Simp l3_gclk: l3_gclk { 435279377Simp #clock-cells = <0>; 436279377Simp compatible = "fixed-factor-clock"; 437279377Simp clocks = <&dpll_core_m4_ck>; 438279377Simp clock-mult = <1>; 439279377Simp clock-div = <1>; 440279377Simp }; 441279377Simp 442279377Simp dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { 443279377Simp #clock-cells = <0>; 444279377Simp compatible = "fixed-factor-clock"; 445279377Simp clocks = <&sysclk_div>; 446279377Simp clock-mult = <1>; 447279377Simp clock-div = <2>; 448279377Simp }; 449279377Simp 450279377Simp l4hs_gclk: l4hs_gclk { 451279377Simp #clock-cells = <0>; 452279377Simp compatible = "fixed-factor-clock"; 453279377Simp clocks = <&dpll_core_m4_ck>; 454279377Simp clock-mult = <1>; 455279377Simp clock-div = <1>; 456279377Simp }; 457279377Simp 458279377Simp l3s_gclk: l3s_gclk { 459279377Simp #clock-cells = <0>; 460279377Simp compatible = "fixed-factor-clock"; 461279377Simp clocks = <&dpll_core_m4_div2_ck>; 462279377Simp clock-mult = <1>; 463279377Simp clock-div = <1>; 464279377Simp }; 465279377Simp 466279377Simp l4ls_gclk: l4ls_gclk { 467279377Simp #clock-cells = <0>; 468279377Simp compatible = "fixed-factor-clock"; 469279377Simp clocks = <&dpll_core_m4_div2_ck>; 470279377Simp clock-mult = <1>; 471279377Simp clock-div = <1>; 472279377Simp }; 473279377Simp 474279377Simp cpsw_125mhz_gclk: cpsw_125mhz_gclk { 475279377Simp #clock-cells = <0>; 476279377Simp compatible = "fixed-factor-clock"; 477279377Simp clocks = <&dpll_core_m5_ck>; 478279377Simp clock-mult = <1>; 479279377Simp clock-div = <2>; 480279377Simp }; 481279377Simp 482279377Simp cpsw_cpts_rft_clk: cpsw_cpts_rft_clk { 483279377Simp #clock-cells = <0>; 484279377Simp compatible = "ti,mux-clock"; 485279377Simp clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>; 486279377Simp reg = <0x4238>; 487279377Simp }; 488279377Simp 489279377Simp clk_32k_mosc_ck: clk_32k_mosc_ck { 490279377Simp #clock-cells = <0>; 491279377Simp compatible = "fixed-clock"; 492279377Simp clock-frequency = <32768>; 493279377Simp }; 494279377Simp 495279377Simp gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck { 496279377Simp #clock-cells = <0>; 497279377Simp compatible = "ti,mux-clock"; 498279377Simp clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>; 499279377Simp reg = <0x4240>; 500279377Simp }; 501279377Simp 502279377Simp gpio0_dbclk: gpio0_dbclk { 503279377Simp #clock-cells = <0>; 504279377Simp compatible = "ti,gate-clock"; 505279377Simp clocks = <&gpio0_dbclk_mux_ck>; 506279377Simp ti,bit-shift = <8>; 507279377Simp reg = <0x2b68>; 508279377Simp }; 509279377Simp 510279377Simp gpio1_dbclk: gpio1_dbclk { 511279377Simp #clock-cells = <0>; 512279377Simp compatible = "ti,gate-clock"; 513279377Simp clocks = <&clkdiv32k_ick>; 514279377Simp ti,bit-shift = <8>; 515279377Simp reg = <0x8c78>; 516279377Simp }; 517279377Simp 518279377Simp gpio2_dbclk: gpio2_dbclk { 519279377Simp #clock-cells = <0>; 520279377Simp compatible = "ti,gate-clock"; 521279377Simp clocks = <&clkdiv32k_ick>; 522279377Simp ti,bit-shift = <8>; 523279377Simp reg = <0x8c80>; 524279377Simp }; 525279377Simp 526279377Simp gpio3_dbclk: gpio3_dbclk { 527279377Simp #clock-cells = <0>; 528279377Simp compatible = "ti,gate-clock"; 529279377Simp clocks = <&clkdiv32k_ick>; 530279377Simp ti,bit-shift = <8>; 531279377Simp reg = <0x8c88>; 532279377Simp }; 533279377Simp 534279377Simp gpio4_dbclk: gpio4_dbclk { 535279377Simp #clock-cells = <0>; 536279377Simp compatible = "ti,gate-clock"; 537279377Simp clocks = <&clkdiv32k_ick>; 538279377Simp ti,bit-shift = <8>; 539279377Simp reg = <0x8c90>; 540279377Simp }; 541279377Simp 542279377Simp gpio5_dbclk: gpio5_dbclk { 543279377Simp #clock-cells = <0>; 544279377Simp compatible = "ti,gate-clock"; 545279377Simp clocks = <&clkdiv32k_ick>; 546279377Simp ti,bit-shift = <8>; 547279377Simp reg = <0x8c98>; 548279377Simp }; 549279377Simp 550279377Simp mmc_clk: mmc_clk { 551279377Simp #clock-cells = <0>; 552279377Simp compatible = "fixed-factor-clock"; 553279377Simp clocks = <&dpll_per_m2_ck>; 554279377Simp clock-mult = <1>; 555279377Simp clock-div = <2>; 556279377Simp }; 557279377Simp 558279377Simp gfx_fclk_clksel_ck: gfx_fclk_clksel_ck { 559279377Simp #clock-cells = <0>; 560279377Simp compatible = "ti,mux-clock"; 561279377Simp clocks = <&sysclk_div>, <&dpll_per_m2_ck>; 562279377Simp ti,bit-shift = <1>; 563279377Simp reg = <0x423c>; 564279377Simp }; 565279377Simp 566279377Simp gfx_fck_div_ck: gfx_fck_div_ck { 567279377Simp #clock-cells = <0>; 568279377Simp compatible = "ti,divider-clock"; 569279377Simp clocks = <&gfx_fclk_clksel_ck>; 570279377Simp reg = <0x423c>; 571279377Simp ti,max-div = <2>; 572279377Simp }; 573279377Simp 574279377Simp disp_clk: disp_clk { 575279377Simp #clock-cells = <0>; 576279377Simp compatible = "ti,mux-clock"; 577279377Simp clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; 578279377Simp reg = <0x4244>; 579279377Simp ti,set-rate-parent; 580279377Simp }; 581279377Simp 582279377Simp dpll_extdev_ck: dpll_extdev_ck { 583279377Simp #clock-cells = <0>; 584279377Simp compatible = "ti,am3-dpll-clock"; 585279377Simp clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 586279377Simp reg = <0x2e60>, <0x2e64>, <0x2e6c>; 587279377Simp }; 588279377Simp 589279377Simp dpll_extdev_m2_ck: dpll_extdev_m2_ck { 590279377Simp #clock-cells = <0>; 591279377Simp compatible = "ti,divider-clock"; 592279377Simp clocks = <&dpll_extdev_ck>; 593279377Simp ti,max-div = <127>; 594279377Simp ti,autoidle-shift = <8>; 595279377Simp reg = <0x2e70>; 596279377Simp ti,index-starts-at-one; 597279377Simp ti,invert-autoidle-bit; 598279377Simp }; 599279377Simp 600279377Simp mux_synctimer32k_ck: mux_synctimer32k_ck { 601279377Simp #clock-cells = <0>; 602279377Simp compatible = "ti,mux-clock"; 603279377Simp clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>; 604279377Simp reg = <0x4230>; 605279377Simp }; 606279377Simp 607279377Simp synctimer_32kclk: synctimer_32kclk { 608279377Simp #clock-cells = <0>; 609279377Simp compatible = "ti,gate-clock"; 610279377Simp clocks = <&mux_synctimer32k_ck>; 611279377Simp ti,bit-shift = <8>; 612279377Simp reg = <0x2a30>; 613279377Simp }; 614279377Simp 615279377Simp timer8_fck: timer8_fck { 616279377Simp #clock-cells = <0>; 617279377Simp compatible = "ti,mux-clock"; 618279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; 619279377Simp reg = <0x421c>; 620279377Simp }; 621279377Simp 622279377Simp timer9_fck: timer9_fck { 623279377Simp #clock-cells = <0>; 624279377Simp compatible = "ti,mux-clock"; 625279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; 626279377Simp reg = <0x4220>; 627279377Simp }; 628279377Simp 629279377Simp timer10_fck: timer10_fck { 630279377Simp #clock-cells = <0>; 631279377Simp compatible = "ti,mux-clock"; 632279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; 633279377Simp reg = <0x4224>; 634279377Simp }; 635279377Simp 636279377Simp timer11_fck: timer11_fck { 637279377Simp #clock-cells = <0>; 638279377Simp compatible = "ti,mux-clock"; 639279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; 640279377Simp reg = <0x4228>; 641279377Simp }; 642279377Simp 643279377Simp cpsw_50m_clkdiv: cpsw_50m_clkdiv { 644279377Simp #clock-cells = <0>; 645279377Simp compatible = "fixed-factor-clock"; 646279377Simp clocks = <&dpll_core_m5_ck>; 647279377Simp clock-mult = <1>; 648279377Simp clock-div = <1>; 649279377Simp }; 650279377Simp 651279377Simp cpsw_5m_clkdiv: cpsw_5m_clkdiv { 652279377Simp #clock-cells = <0>; 653279377Simp compatible = "fixed-factor-clock"; 654279377Simp clocks = <&cpsw_50m_clkdiv>; 655279377Simp clock-mult = <1>; 656279377Simp clock-div = <10>; 657279377Simp }; 658279377Simp 659279377Simp dpll_ddr_x2_ck: dpll_ddr_x2_ck { 660279377Simp #clock-cells = <0>; 661279377Simp compatible = "ti,am3-dpll-x2-clock"; 662279377Simp clocks = <&dpll_ddr_ck>; 663279377Simp }; 664279377Simp 665279377Simp dpll_ddr_m4_ck: dpll_ddr_m4_ck { 666279377Simp #clock-cells = <0>; 667279377Simp compatible = "ti,divider-clock"; 668279377Simp clocks = <&dpll_ddr_x2_ck>; 669279377Simp ti,max-div = <31>; 670279377Simp ti,autoidle-shift = <8>; 671279377Simp reg = <0x2db8>; 672279377Simp ti,index-starts-at-one; 673279377Simp ti,invert-autoidle-bit; 674279377Simp }; 675279377Simp 676279377Simp dpll_per_clkdcoldo: dpll_per_clkdcoldo { 677279377Simp #clock-cells = <0>; 678279377Simp compatible = "ti,fixed-factor-clock"; 679279377Simp clocks = <&dpll_per_ck>; 680279377Simp ti,clock-mult = <1>; 681279377Simp ti,clock-div = <1>; 682279377Simp ti,autoidle-shift = <8>; 683279377Simp reg = <0x2e14>; 684279377Simp ti,invert-autoidle-bit; 685279377Simp }; 686279377Simp 687279377Simp dll_aging_clk_div: dll_aging_clk_div { 688279377Simp #clock-cells = <0>; 689279377Simp compatible = "ti,divider-clock"; 690279377Simp clocks = <&sys_clkin_ck>; 691279377Simp reg = <0x4250>; 692279377Simp ti,dividers = <8>, <16>, <32>; 693279377Simp }; 694279377Simp 695279377Simp div_core_25m_ck: div_core_25m_ck { 696279377Simp #clock-cells = <0>; 697279377Simp compatible = "fixed-factor-clock"; 698279377Simp clocks = <&sysclk_div>; 699279377Simp clock-mult = <1>; 700279377Simp clock-div = <8>; 701279377Simp }; 702279377Simp 703279377Simp func_12m_clk: func_12m_clk { 704279377Simp #clock-cells = <0>; 705279377Simp compatible = "fixed-factor-clock"; 706279377Simp clocks = <&dpll_per_m2_ck>; 707279377Simp clock-mult = <1>; 708279377Simp clock-div = <16>; 709279377Simp }; 710279377Simp 711279377Simp vtp_clk_div: vtp_clk_div { 712279377Simp #clock-cells = <0>; 713279377Simp compatible = "fixed-factor-clock"; 714279377Simp clocks = <&sys_clkin_ck>; 715279377Simp clock-mult = <1>; 716279377Simp clock-div = <2>; 717279377Simp }; 718279377Simp 719279377Simp usbphy_32khz_clkmux: usbphy_32khz_clkmux { 720279377Simp #clock-cells = <0>; 721279377Simp compatible = "ti,mux-clock"; 722279377Simp clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; 723279377Simp reg = <0x4260>; 724279377Simp }; 725279377Simp 726279377Simp usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k { 727279377Simp #clock-cells = <0>; 728279377Simp compatible = "ti,gate-clock"; 729279377Simp clocks = <&usbphy_32khz_clkmux>; 730279377Simp ti,bit-shift = <8>; 731279377Simp reg = <0x2a40>; 732279377Simp }; 733279377Simp 734279377Simp usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k { 735279377Simp #clock-cells = <0>; 736279377Simp compatible = "ti,gate-clock"; 737279377Simp clocks = <&usbphy_32khz_clkmux>; 738279377Simp ti,bit-shift = <8>; 739279377Simp reg = <0x2a48>; 740279377Simp }; 741279377Simp 742279377Simp usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m { 743279377Simp #clock-cells = <0>; 744279377Simp compatible = "ti,gate-clock"; 745279377Simp clocks = <&dpll_per_clkdcoldo>; 746279377Simp ti,bit-shift = <8>; 747279377Simp reg = <0x8a60>; 748279377Simp }; 749279377Simp 750279377Simp usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m { 751279377Simp #clock-cells = <0>; 752279377Simp compatible = "ti,gate-clock"; 753279377Simp clocks = <&dpll_per_clkdcoldo>; 754279377Simp ti,bit-shift = <8>; 755279377Simp reg = <0x8a68>; 756279377Simp }; 757279377Simp}; 758