1279377Simp/* 2279377Simp * Device Tree Source for AM43xx clock data 3279377Simp * 4279377Simp * Copyright (C) 2013 Texas Instruments, Inc. 5279377Simp * 6279377Simp * This program is free software; you can redistribute it and/or modify 7279377Simp * it under the terms of the GNU General Public License version 2 as 8279377Simp * published by the Free Software Foundation. 9279377Simp */ 10295436Sandrew&scm_clocks { 11279377Simp sys_clkin_ck: sys_clkin_ck { 12279377Simp #clock-cells = <0>; 13279377Simp compatible = "ti,mux-clock"; 14279377Simp clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; 15279377Simp ti,bit-shift = <31>; 16279377Simp reg = <0x0040>; 17279377Simp }; 18279377Simp 19279377Simp crystal_freq_sel_ck: crystal_freq_sel_ck { 20279377Simp #clock-cells = <0>; 21279377Simp compatible = "ti,mux-clock"; 22279377Simp clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; 23279377Simp ti,bit-shift = <29>; 24279377Simp reg = <0x0040>; 25279377Simp }; 26279377Simp 27279377Simp sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 { 28279377Simp #clock-cells = <0>; 29279377Simp compatible = "ti,mux-clock"; 30279377Simp clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; 31279377Simp ti,bit-shift = <22>; 32279377Simp reg = <0x0040>; 33279377Simp }; 34279377Simp 35279377Simp adc_tsc_fck: adc_tsc_fck { 36279377Simp #clock-cells = <0>; 37279377Simp compatible = "fixed-factor-clock"; 38279377Simp clocks = <&sys_clkin_ck>; 39279377Simp clock-mult = <1>; 40279377Simp clock-div = <1>; 41279377Simp }; 42279377Simp 43279377Simp dcan0_fck: dcan0_fck { 44279377Simp #clock-cells = <0>; 45279377Simp compatible = "fixed-factor-clock"; 46279377Simp clocks = <&sys_clkin_ck>; 47279377Simp clock-mult = <1>; 48279377Simp clock-div = <1>; 49279377Simp }; 50279377Simp 51279377Simp dcan1_fck: dcan1_fck { 52279377Simp #clock-cells = <0>; 53279377Simp compatible = "fixed-factor-clock"; 54279377Simp clocks = <&sys_clkin_ck>; 55279377Simp clock-mult = <1>; 56279377Simp clock-div = <1>; 57279377Simp }; 58279377Simp 59279377Simp mcasp0_fck: mcasp0_fck { 60279377Simp #clock-cells = <0>; 61279377Simp compatible = "fixed-factor-clock"; 62279377Simp clocks = <&sys_clkin_ck>; 63279377Simp clock-mult = <1>; 64279377Simp clock-div = <1>; 65279377Simp }; 66279377Simp 67279377Simp mcasp1_fck: mcasp1_fck { 68279377Simp #clock-cells = <0>; 69279377Simp compatible = "fixed-factor-clock"; 70279377Simp clocks = <&sys_clkin_ck>; 71279377Simp clock-mult = <1>; 72279377Simp clock-div = <1>; 73279377Simp }; 74279377Simp 75279377Simp smartreflex0_fck: smartreflex0_fck { 76279377Simp #clock-cells = <0>; 77279377Simp compatible = "fixed-factor-clock"; 78279377Simp clocks = <&sys_clkin_ck>; 79279377Simp clock-mult = <1>; 80279377Simp clock-div = <1>; 81279377Simp }; 82279377Simp 83279377Simp smartreflex1_fck: smartreflex1_fck { 84279377Simp #clock-cells = <0>; 85279377Simp compatible = "fixed-factor-clock"; 86279377Simp clocks = <&sys_clkin_ck>; 87279377Simp clock-mult = <1>; 88279377Simp clock-div = <1>; 89279377Simp }; 90279377Simp 91279377Simp sha0_fck: sha0_fck { 92279377Simp #clock-cells = <0>; 93279377Simp compatible = "fixed-factor-clock"; 94279377Simp clocks = <&sys_clkin_ck>; 95279377Simp clock-mult = <1>; 96279377Simp clock-div = <1>; 97279377Simp }; 98279377Simp 99279377Simp aes0_fck: aes0_fck { 100279377Simp #clock-cells = <0>; 101279377Simp compatible = "fixed-factor-clock"; 102279377Simp clocks = <&sys_clkin_ck>; 103279377Simp clock-mult = <1>; 104279377Simp clock-div = <1>; 105279377Simp }; 106279377Simp 107279377Simp ehrpwm0_tbclk: ehrpwm0_tbclk { 108279377Simp #clock-cells = <0>; 109279377Simp compatible = "ti,gate-clock"; 110295436Sandrew clocks = <&l4ls_gclk>; 111279377Simp ti,bit-shift = <0>; 112279377Simp reg = <0x0664>; 113279377Simp }; 114279377Simp 115279377Simp ehrpwm1_tbclk: ehrpwm1_tbclk { 116279377Simp #clock-cells = <0>; 117279377Simp compatible = "ti,gate-clock"; 118295436Sandrew clocks = <&l4ls_gclk>; 119279377Simp ti,bit-shift = <1>; 120279377Simp reg = <0x0664>; 121279377Simp }; 122279377Simp 123279377Simp ehrpwm2_tbclk: ehrpwm2_tbclk { 124279377Simp #clock-cells = <0>; 125279377Simp compatible = "ti,gate-clock"; 126295436Sandrew clocks = <&l4ls_gclk>; 127279377Simp ti,bit-shift = <2>; 128279377Simp reg = <0x0664>; 129279377Simp }; 130279377Simp 131279377Simp ehrpwm3_tbclk: ehrpwm3_tbclk { 132279377Simp #clock-cells = <0>; 133279377Simp compatible = "ti,gate-clock"; 134295436Sandrew clocks = <&l4ls_gclk>; 135279377Simp ti,bit-shift = <4>; 136279377Simp reg = <0x0664>; 137279377Simp }; 138279377Simp 139279377Simp ehrpwm4_tbclk: ehrpwm4_tbclk { 140279377Simp #clock-cells = <0>; 141279377Simp compatible = "ti,gate-clock"; 142295436Sandrew clocks = <&l4ls_gclk>; 143279377Simp ti,bit-shift = <5>; 144279377Simp reg = <0x0664>; 145279377Simp }; 146279377Simp 147279377Simp ehrpwm5_tbclk: ehrpwm5_tbclk { 148279377Simp #clock-cells = <0>; 149279377Simp compatible = "ti,gate-clock"; 150295436Sandrew clocks = <&l4ls_gclk>; 151279377Simp ti,bit-shift = <6>; 152279377Simp reg = <0x0664>; 153279377Simp }; 154279377Simp}; 155279377Simp&prcm_clocks { 156279377Simp clk_32768_ck: clk_32768_ck { 157279377Simp #clock-cells = <0>; 158279377Simp compatible = "fixed-clock"; 159279377Simp clock-frequency = <32768>; 160279377Simp }; 161279377Simp 162279377Simp clk_rc32k_ck: clk_rc32k_ck { 163279377Simp #clock-cells = <0>; 164279377Simp compatible = "fixed-clock"; 165279377Simp clock-frequency = <32768>; 166279377Simp }; 167279377Simp 168279377Simp virt_19200000_ck: virt_19200000_ck { 169279377Simp #clock-cells = <0>; 170279377Simp compatible = "fixed-clock"; 171279377Simp clock-frequency = <19200000>; 172279377Simp }; 173279377Simp 174279377Simp virt_24000000_ck: virt_24000000_ck { 175279377Simp #clock-cells = <0>; 176279377Simp compatible = "fixed-clock"; 177279377Simp clock-frequency = <24000000>; 178279377Simp }; 179279377Simp 180279377Simp virt_25000000_ck: virt_25000000_ck { 181279377Simp #clock-cells = <0>; 182279377Simp compatible = "fixed-clock"; 183279377Simp clock-frequency = <25000000>; 184279377Simp }; 185279377Simp 186279377Simp virt_26000000_ck: virt_26000000_ck { 187279377Simp #clock-cells = <0>; 188279377Simp compatible = "fixed-clock"; 189279377Simp clock-frequency = <26000000>; 190279377Simp }; 191279377Simp 192279377Simp tclkin_ck: tclkin_ck { 193279377Simp #clock-cells = <0>; 194279377Simp compatible = "fixed-clock"; 195279377Simp clock-frequency = <26000000>; 196279377Simp }; 197279377Simp 198279377Simp dpll_core_ck: dpll_core_ck { 199279377Simp #clock-cells = <0>; 200279377Simp compatible = "ti,am3-dpll-core-clock"; 201279377Simp clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 202279377Simp reg = <0x2d20>, <0x2d24>, <0x2d2c>; 203279377Simp }; 204279377Simp 205279377Simp dpll_core_x2_ck: dpll_core_x2_ck { 206279377Simp #clock-cells = <0>; 207279377Simp compatible = "ti,am3-dpll-x2-clock"; 208279377Simp clocks = <&dpll_core_ck>; 209279377Simp }; 210279377Simp 211279377Simp dpll_core_m4_ck: dpll_core_m4_ck { 212279377Simp #clock-cells = <0>; 213279377Simp compatible = "ti,divider-clock"; 214279377Simp clocks = <&dpll_core_x2_ck>; 215279377Simp ti,max-div = <31>; 216279377Simp ti,autoidle-shift = <8>; 217279377Simp reg = <0x2d38>; 218279377Simp ti,index-starts-at-one; 219279377Simp ti,invert-autoidle-bit; 220279377Simp }; 221279377Simp 222279377Simp dpll_core_m5_ck: dpll_core_m5_ck { 223279377Simp #clock-cells = <0>; 224279377Simp compatible = "ti,divider-clock"; 225279377Simp clocks = <&dpll_core_x2_ck>; 226279377Simp ti,max-div = <31>; 227279377Simp ti,autoidle-shift = <8>; 228279377Simp reg = <0x2d3c>; 229279377Simp ti,index-starts-at-one; 230279377Simp ti,invert-autoidle-bit; 231279377Simp }; 232279377Simp 233279377Simp dpll_core_m6_ck: dpll_core_m6_ck { 234279377Simp #clock-cells = <0>; 235279377Simp compatible = "ti,divider-clock"; 236279377Simp clocks = <&dpll_core_x2_ck>; 237279377Simp ti,max-div = <31>; 238279377Simp ti,autoidle-shift = <8>; 239279377Simp reg = <0x2d40>; 240279377Simp ti,index-starts-at-one; 241279377Simp ti,invert-autoidle-bit; 242279377Simp }; 243279377Simp 244279377Simp dpll_mpu_ck: dpll_mpu_ck { 245279377Simp #clock-cells = <0>; 246279377Simp compatible = "ti,am3-dpll-clock"; 247279377Simp clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 248279377Simp reg = <0x2d60>, <0x2d64>, <0x2d6c>; 249279377Simp }; 250279377Simp 251279377Simp dpll_mpu_m2_ck: dpll_mpu_m2_ck { 252279377Simp #clock-cells = <0>; 253279377Simp compatible = "ti,divider-clock"; 254279377Simp clocks = <&dpll_mpu_ck>; 255279377Simp ti,max-div = <31>; 256279377Simp ti,autoidle-shift = <8>; 257279377Simp reg = <0x2d70>; 258279377Simp ti,index-starts-at-one; 259279377Simp ti,invert-autoidle-bit; 260279377Simp }; 261279377Simp 262295436Sandrew mpu_periphclk: mpu_periphclk { 263295436Sandrew #clock-cells = <0>; 264295436Sandrew compatible = "fixed-factor-clock"; 265295436Sandrew clocks = <&dpll_mpu_m2_ck>; 266295436Sandrew clock-mult = <1>; 267295436Sandrew clock-div = <2>; 268295436Sandrew }; 269295436Sandrew 270279377Simp dpll_ddr_ck: dpll_ddr_ck { 271279377Simp #clock-cells = <0>; 272279377Simp compatible = "ti,am3-dpll-clock"; 273279377Simp clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 274279377Simp reg = <0x2da0>, <0x2da4>, <0x2dac>; 275279377Simp }; 276279377Simp 277279377Simp dpll_ddr_m2_ck: dpll_ddr_m2_ck { 278279377Simp #clock-cells = <0>; 279279377Simp compatible = "ti,divider-clock"; 280279377Simp clocks = <&dpll_ddr_ck>; 281279377Simp ti,max-div = <31>; 282279377Simp ti,autoidle-shift = <8>; 283279377Simp reg = <0x2db0>; 284279377Simp ti,index-starts-at-one; 285279377Simp ti,invert-autoidle-bit; 286279377Simp }; 287279377Simp 288279377Simp dpll_disp_ck: dpll_disp_ck { 289279377Simp #clock-cells = <0>; 290279377Simp compatible = "ti,am3-dpll-clock"; 291279377Simp clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 292279377Simp reg = <0x2e20>, <0x2e24>, <0x2e2c>; 293279377Simp }; 294279377Simp 295279377Simp dpll_disp_m2_ck: dpll_disp_m2_ck { 296279377Simp #clock-cells = <0>; 297279377Simp compatible = "ti,divider-clock"; 298279377Simp clocks = <&dpll_disp_ck>; 299279377Simp ti,max-div = <31>; 300279377Simp ti,autoidle-shift = <8>; 301279377Simp reg = <0x2e30>; 302279377Simp ti,index-starts-at-one; 303279377Simp ti,invert-autoidle-bit; 304279377Simp ti,set-rate-parent; 305279377Simp }; 306279377Simp 307279377Simp dpll_per_ck: dpll_per_ck { 308279377Simp #clock-cells = <0>; 309279377Simp compatible = "ti,am3-dpll-j-type-clock"; 310279377Simp clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 311279377Simp reg = <0x2de0>, <0x2de4>, <0x2dec>; 312279377Simp }; 313279377Simp 314279377Simp dpll_per_m2_ck: dpll_per_m2_ck { 315279377Simp #clock-cells = <0>; 316279377Simp compatible = "ti,divider-clock"; 317279377Simp clocks = <&dpll_per_ck>; 318279377Simp ti,max-div = <127>; 319279377Simp ti,autoidle-shift = <8>; 320279377Simp reg = <0x2df0>; 321279377Simp ti,index-starts-at-one; 322279377Simp ti,invert-autoidle-bit; 323279377Simp }; 324279377Simp 325279377Simp dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { 326279377Simp #clock-cells = <0>; 327279377Simp compatible = "fixed-factor-clock"; 328279377Simp clocks = <&dpll_per_m2_ck>; 329279377Simp clock-mult = <1>; 330279377Simp clock-div = <4>; 331279377Simp }; 332279377Simp 333279377Simp dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { 334279377Simp #clock-cells = <0>; 335279377Simp compatible = "fixed-factor-clock"; 336279377Simp clocks = <&dpll_per_m2_ck>; 337279377Simp clock-mult = <1>; 338279377Simp clock-div = <4>; 339279377Simp }; 340279377Simp 341279377Simp clk_24mhz: clk_24mhz { 342279377Simp #clock-cells = <0>; 343279377Simp compatible = "fixed-factor-clock"; 344279377Simp clocks = <&dpll_per_m2_ck>; 345279377Simp clock-mult = <1>; 346279377Simp clock-div = <8>; 347279377Simp }; 348279377Simp 349279377Simp clkdiv32k_ck: clkdiv32k_ck { 350279377Simp #clock-cells = <0>; 351279377Simp compatible = "fixed-factor-clock"; 352279377Simp clocks = <&clk_24mhz>; 353279377Simp clock-mult = <1>; 354279377Simp clock-div = <732>; 355279377Simp }; 356279377Simp 357279377Simp clkdiv32k_ick: clkdiv32k_ick { 358279377Simp #clock-cells = <0>; 359279377Simp compatible = "ti,gate-clock"; 360279377Simp clocks = <&clkdiv32k_ck>; 361279377Simp ti,bit-shift = <8>; 362279377Simp reg = <0x2a38>; 363279377Simp }; 364279377Simp 365279377Simp sysclk_div: sysclk_div { 366279377Simp #clock-cells = <0>; 367279377Simp compatible = "fixed-factor-clock"; 368279377Simp clocks = <&dpll_core_m4_ck>; 369279377Simp clock-mult = <1>; 370279377Simp clock-div = <1>; 371279377Simp }; 372279377Simp 373279377Simp pruss_ocp_gclk: pruss_ocp_gclk { 374279377Simp #clock-cells = <0>; 375279377Simp compatible = "ti,mux-clock"; 376279377Simp clocks = <&sysclk_div>, <&dpll_disp_m2_ck>; 377279377Simp reg = <0x4248>; 378279377Simp }; 379279377Simp 380279377Simp clk_32k_tpm_ck: clk_32k_tpm_ck { 381279377Simp #clock-cells = <0>; 382279377Simp compatible = "fixed-clock"; 383279377Simp clock-frequency = <32768>; 384279377Simp }; 385279377Simp 386279377Simp timer1_fck: timer1_fck { 387279377Simp #clock-cells = <0>; 388279377Simp compatible = "ti,mux-clock"; 389279377Simp clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>; 390279377Simp reg = <0x4200>; 391279377Simp }; 392279377Simp 393279377Simp timer2_fck: timer2_fck { 394279377Simp #clock-cells = <0>; 395279377Simp compatible = "ti,mux-clock"; 396279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 397279377Simp reg = <0x4204>; 398279377Simp }; 399279377Simp 400279377Simp timer3_fck: timer3_fck { 401279377Simp #clock-cells = <0>; 402279377Simp compatible = "ti,mux-clock"; 403279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 404279377Simp reg = <0x4208>; 405279377Simp }; 406279377Simp 407279377Simp timer4_fck: timer4_fck { 408279377Simp #clock-cells = <0>; 409279377Simp compatible = "ti,mux-clock"; 410279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 411279377Simp reg = <0x420c>; 412279377Simp }; 413279377Simp 414279377Simp timer5_fck: timer5_fck { 415279377Simp #clock-cells = <0>; 416279377Simp compatible = "ti,mux-clock"; 417279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 418279377Simp reg = <0x4210>; 419279377Simp }; 420279377Simp 421279377Simp timer6_fck: timer6_fck { 422279377Simp #clock-cells = <0>; 423279377Simp compatible = "ti,mux-clock"; 424279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 425279377Simp reg = <0x4214>; 426279377Simp }; 427279377Simp 428279377Simp timer7_fck: timer7_fck { 429279377Simp #clock-cells = <0>; 430279377Simp compatible = "ti,mux-clock"; 431279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 432279377Simp reg = <0x4218>; 433279377Simp }; 434279377Simp 435279377Simp wdt1_fck: wdt1_fck { 436279377Simp #clock-cells = <0>; 437279377Simp compatible = "ti,mux-clock"; 438279377Simp clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; 439279377Simp reg = <0x422c>; 440279377Simp }; 441279377Simp 442279377Simp l3_gclk: l3_gclk { 443279377Simp #clock-cells = <0>; 444279377Simp compatible = "fixed-factor-clock"; 445279377Simp clocks = <&dpll_core_m4_ck>; 446279377Simp clock-mult = <1>; 447279377Simp clock-div = <1>; 448279377Simp }; 449279377Simp 450279377Simp dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { 451279377Simp #clock-cells = <0>; 452279377Simp compatible = "fixed-factor-clock"; 453279377Simp clocks = <&sysclk_div>; 454279377Simp clock-mult = <1>; 455279377Simp clock-div = <2>; 456279377Simp }; 457279377Simp 458279377Simp l4hs_gclk: l4hs_gclk { 459279377Simp #clock-cells = <0>; 460279377Simp compatible = "fixed-factor-clock"; 461279377Simp clocks = <&dpll_core_m4_ck>; 462279377Simp clock-mult = <1>; 463279377Simp clock-div = <1>; 464279377Simp }; 465279377Simp 466279377Simp l3s_gclk: l3s_gclk { 467279377Simp #clock-cells = <0>; 468279377Simp compatible = "fixed-factor-clock"; 469279377Simp clocks = <&dpll_core_m4_div2_ck>; 470279377Simp clock-mult = <1>; 471279377Simp clock-div = <1>; 472279377Simp }; 473279377Simp 474279377Simp l4ls_gclk: l4ls_gclk { 475279377Simp #clock-cells = <0>; 476279377Simp compatible = "fixed-factor-clock"; 477279377Simp clocks = <&dpll_core_m4_div2_ck>; 478279377Simp clock-mult = <1>; 479279377Simp clock-div = <1>; 480279377Simp }; 481279377Simp 482279377Simp cpsw_125mhz_gclk: cpsw_125mhz_gclk { 483279377Simp #clock-cells = <0>; 484279377Simp compatible = "fixed-factor-clock"; 485279377Simp clocks = <&dpll_core_m5_ck>; 486279377Simp clock-mult = <1>; 487279377Simp clock-div = <2>; 488279377Simp }; 489279377Simp 490279377Simp cpsw_cpts_rft_clk: cpsw_cpts_rft_clk { 491279377Simp #clock-cells = <0>; 492279377Simp compatible = "ti,mux-clock"; 493279377Simp clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>; 494279377Simp reg = <0x4238>; 495279377Simp }; 496279377Simp 497295436Sandrew dpll_clksel_mac_clk: dpll_clksel_mac_clk { 498295436Sandrew #clock-cells = <0>; 499295436Sandrew compatible = "ti,divider-clock"; 500295436Sandrew clocks = <&dpll_core_m5_ck>; 501295436Sandrew reg = <0x4234>; 502295436Sandrew ti,bit-shift = <2>; 503295436Sandrew ti,dividers = <2>, <5>; 504295436Sandrew }; 505295436Sandrew 506279377Simp clk_32k_mosc_ck: clk_32k_mosc_ck { 507279377Simp #clock-cells = <0>; 508279377Simp compatible = "fixed-clock"; 509279377Simp clock-frequency = <32768>; 510279377Simp }; 511279377Simp 512279377Simp gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck { 513279377Simp #clock-cells = <0>; 514279377Simp compatible = "ti,mux-clock"; 515279377Simp clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>; 516279377Simp reg = <0x4240>; 517279377Simp }; 518279377Simp 519279377Simp gpio0_dbclk: gpio0_dbclk { 520279377Simp #clock-cells = <0>; 521279377Simp compatible = "ti,gate-clock"; 522279377Simp clocks = <&gpio0_dbclk_mux_ck>; 523279377Simp ti,bit-shift = <8>; 524279377Simp reg = <0x2b68>; 525279377Simp }; 526279377Simp 527279377Simp gpio1_dbclk: gpio1_dbclk { 528279377Simp #clock-cells = <0>; 529279377Simp compatible = "ti,gate-clock"; 530279377Simp clocks = <&clkdiv32k_ick>; 531279377Simp ti,bit-shift = <8>; 532279377Simp reg = <0x8c78>; 533279377Simp }; 534279377Simp 535279377Simp gpio2_dbclk: gpio2_dbclk { 536279377Simp #clock-cells = <0>; 537279377Simp compatible = "ti,gate-clock"; 538279377Simp clocks = <&clkdiv32k_ick>; 539279377Simp ti,bit-shift = <8>; 540279377Simp reg = <0x8c80>; 541279377Simp }; 542279377Simp 543279377Simp gpio3_dbclk: gpio3_dbclk { 544279377Simp #clock-cells = <0>; 545279377Simp compatible = "ti,gate-clock"; 546279377Simp clocks = <&clkdiv32k_ick>; 547279377Simp ti,bit-shift = <8>; 548279377Simp reg = <0x8c88>; 549279377Simp }; 550279377Simp 551279377Simp gpio4_dbclk: gpio4_dbclk { 552279377Simp #clock-cells = <0>; 553279377Simp compatible = "ti,gate-clock"; 554279377Simp clocks = <&clkdiv32k_ick>; 555279377Simp ti,bit-shift = <8>; 556279377Simp reg = <0x8c90>; 557279377Simp }; 558279377Simp 559279377Simp gpio5_dbclk: gpio5_dbclk { 560279377Simp #clock-cells = <0>; 561279377Simp compatible = "ti,gate-clock"; 562279377Simp clocks = <&clkdiv32k_ick>; 563279377Simp ti,bit-shift = <8>; 564279377Simp reg = <0x8c98>; 565279377Simp }; 566279377Simp 567279377Simp mmc_clk: mmc_clk { 568279377Simp #clock-cells = <0>; 569279377Simp compatible = "fixed-factor-clock"; 570279377Simp clocks = <&dpll_per_m2_ck>; 571279377Simp clock-mult = <1>; 572279377Simp clock-div = <2>; 573279377Simp }; 574279377Simp 575279377Simp gfx_fclk_clksel_ck: gfx_fclk_clksel_ck { 576279377Simp #clock-cells = <0>; 577279377Simp compatible = "ti,mux-clock"; 578279377Simp clocks = <&sysclk_div>, <&dpll_per_m2_ck>; 579279377Simp ti,bit-shift = <1>; 580279377Simp reg = <0x423c>; 581279377Simp }; 582279377Simp 583279377Simp gfx_fck_div_ck: gfx_fck_div_ck { 584279377Simp #clock-cells = <0>; 585279377Simp compatible = "ti,divider-clock"; 586279377Simp clocks = <&gfx_fclk_clksel_ck>; 587279377Simp reg = <0x423c>; 588279377Simp ti,max-div = <2>; 589279377Simp }; 590279377Simp 591279377Simp disp_clk: disp_clk { 592279377Simp #clock-cells = <0>; 593279377Simp compatible = "ti,mux-clock"; 594279377Simp clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; 595279377Simp reg = <0x4244>; 596279377Simp ti,set-rate-parent; 597279377Simp }; 598279377Simp 599279377Simp dpll_extdev_ck: dpll_extdev_ck { 600279377Simp #clock-cells = <0>; 601279377Simp compatible = "ti,am3-dpll-clock"; 602279377Simp clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 603279377Simp reg = <0x2e60>, <0x2e64>, <0x2e6c>; 604279377Simp }; 605279377Simp 606279377Simp dpll_extdev_m2_ck: dpll_extdev_m2_ck { 607279377Simp #clock-cells = <0>; 608279377Simp compatible = "ti,divider-clock"; 609279377Simp clocks = <&dpll_extdev_ck>; 610279377Simp ti,max-div = <127>; 611279377Simp ti,autoidle-shift = <8>; 612279377Simp reg = <0x2e70>; 613279377Simp ti,index-starts-at-one; 614279377Simp ti,invert-autoidle-bit; 615279377Simp }; 616279377Simp 617279377Simp mux_synctimer32k_ck: mux_synctimer32k_ck { 618279377Simp #clock-cells = <0>; 619279377Simp compatible = "ti,mux-clock"; 620279377Simp clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>; 621279377Simp reg = <0x4230>; 622279377Simp }; 623279377Simp 624279377Simp synctimer_32kclk: synctimer_32kclk { 625279377Simp #clock-cells = <0>; 626279377Simp compatible = "ti,gate-clock"; 627279377Simp clocks = <&mux_synctimer32k_ck>; 628279377Simp ti,bit-shift = <8>; 629279377Simp reg = <0x2a30>; 630279377Simp }; 631279377Simp 632279377Simp timer8_fck: timer8_fck { 633279377Simp #clock-cells = <0>; 634279377Simp compatible = "ti,mux-clock"; 635279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; 636279377Simp reg = <0x421c>; 637279377Simp }; 638279377Simp 639279377Simp timer9_fck: timer9_fck { 640279377Simp #clock-cells = <0>; 641279377Simp compatible = "ti,mux-clock"; 642279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; 643279377Simp reg = <0x4220>; 644279377Simp }; 645279377Simp 646279377Simp timer10_fck: timer10_fck { 647279377Simp #clock-cells = <0>; 648279377Simp compatible = "ti,mux-clock"; 649279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; 650279377Simp reg = <0x4224>; 651279377Simp }; 652279377Simp 653279377Simp timer11_fck: timer11_fck { 654279377Simp #clock-cells = <0>; 655279377Simp compatible = "ti,mux-clock"; 656279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; 657279377Simp reg = <0x4228>; 658279377Simp }; 659279377Simp 660279377Simp cpsw_50m_clkdiv: cpsw_50m_clkdiv { 661279377Simp #clock-cells = <0>; 662279377Simp compatible = "fixed-factor-clock"; 663279377Simp clocks = <&dpll_core_m5_ck>; 664279377Simp clock-mult = <1>; 665279377Simp clock-div = <1>; 666279377Simp }; 667279377Simp 668279377Simp cpsw_5m_clkdiv: cpsw_5m_clkdiv { 669279377Simp #clock-cells = <0>; 670279377Simp compatible = "fixed-factor-clock"; 671279377Simp clocks = <&cpsw_50m_clkdiv>; 672279377Simp clock-mult = <1>; 673279377Simp clock-div = <10>; 674279377Simp }; 675279377Simp 676279377Simp dpll_ddr_x2_ck: dpll_ddr_x2_ck { 677279377Simp #clock-cells = <0>; 678279377Simp compatible = "ti,am3-dpll-x2-clock"; 679279377Simp clocks = <&dpll_ddr_ck>; 680279377Simp }; 681279377Simp 682279377Simp dpll_ddr_m4_ck: dpll_ddr_m4_ck { 683279377Simp #clock-cells = <0>; 684279377Simp compatible = "ti,divider-clock"; 685279377Simp clocks = <&dpll_ddr_x2_ck>; 686279377Simp ti,max-div = <31>; 687279377Simp ti,autoidle-shift = <8>; 688279377Simp reg = <0x2db8>; 689279377Simp ti,index-starts-at-one; 690279377Simp ti,invert-autoidle-bit; 691279377Simp }; 692279377Simp 693279377Simp dpll_per_clkdcoldo: dpll_per_clkdcoldo { 694279377Simp #clock-cells = <0>; 695279377Simp compatible = "ti,fixed-factor-clock"; 696279377Simp clocks = <&dpll_per_ck>; 697279377Simp ti,clock-mult = <1>; 698279377Simp ti,clock-div = <1>; 699279377Simp ti,autoidle-shift = <8>; 700279377Simp reg = <0x2e14>; 701279377Simp ti,invert-autoidle-bit; 702279377Simp }; 703279377Simp 704279377Simp dll_aging_clk_div: dll_aging_clk_div { 705279377Simp #clock-cells = <0>; 706279377Simp compatible = "ti,divider-clock"; 707279377Simp clocks = <&sys_clkin_ck>; 708279377Simp reg = <0x4250>; 709279377Simp ti,dividers = <8>, <16>, <32>; 710279377Simp }; 711279377Simp 712279377Simp div_core_25m_ck: div_core_25m_ck { 713279377Simp #clock-cells = <0>; 714279377Simp compatible = "fixed-factor-clock"; 715279377Simp clocks = <&sysclk_div>; 716279377Simp clock-mult = <1>; 717279377Simp clock-div = <8>; 718279377Simp }; 719279377Simp 720279377Simp func_12m_clk: func_12m_clk { 721279377Simp #clock-cells = <0>; 722279377Simp compatible = "fixed-factor-clock"; 723279377Simp clocks = <&dpll_per_m2_ck>; 724279377Simp clock-mult = <1>; 725279377Simp clock-div = <16>; 726279377Simp }; 727279377Simp 728279377Simp vtp_clk_div: vtp_clk_div { 729279377Simp #clock-cells = <0>; 730279377Simp compatible = "fixed-factor-clock"; 731279377Simp clocks = <&sys_clkin_ck>; 732279377Simp clock-mult = <1>; 733279377Simp clock-div = <2>; 734279377Simp }; 735279377Simp 736279377Simp usbphy_32khz_clkmux: usbphy_32khz_clkmux { 737279377Simp #clock-cells = <0>; 738279377Simp compatible = "ti,mux-clock"; 739279377Simp clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; 740279377Simp reg = <0x4260>; 741279377Simp }; 742279377Simp 743279377Simp usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k { 744279377Simp #clock-cells = <0>; 745279377Simp compatible = "ti,gate-clock"; 746279377Simp clocks = <&usbphy_32khz_clkmux>; 747279377Simp ti,bit-shift = <8>; 748279377Simp reg = <0x2a40>; 749279377Simp }; 750279377Simp 751279377Simp usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k { 752279377Simp #clock-cells = <0>; 753279377Simp compatible = "ti,gate-clock"; 754279377Simp clocks = <&usbphy_32khz_clkmux>; 755279377Simp ti,bit-shift = <8>; 756279377Simp reg = <0x2a48>; 757279377Simp }; 758279377Simp 759279377Simp usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m { 760279377Simp #clock-cells = <0>; 761279377Simp compatible = "ti,gate-clock"; 762279377Simp clocks = <&dpll_per_clkdcoldo>; 763279377Simp ti,bit-shift = <8>; 764279377Simp reg = <0x8a60>; 765279377Simp }; 766279377Simp 767279377Simp usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m { 768279377Simp #clock-cells = <0>; 769279377Simp compatible = "ti,gate-clock"; 770279377Simp clocks = <&dpll_per_clkdcoldo>; 771279377Simp ti,bit-shift = <8>; 772279377Simp reg = <0x8a68>; 773279377Simp }; 774279377Simp}; 775