alpine.dtsi revision 295011
1295011Sandrew/* 2295011Sandrew * Copyright 2015 Annapurna Labs Ltd. 3295011Sandrew * 4295011Sandrew * This program is free software; you can redistribute it and/or modify it 5295011Sandrew * under the terms and conditions of the GNU General Public License, 6295011Sandrew * version 2, as published by the Free Software Foundation. 7295011Sandrew * 8295011Sandrew * Alternatively, redistribution and use in source and binary forms, with or 9295011Sandrew * without modification, are permitted provided that the following conditions 10295011Sandrew * are met: 11295011Sandrew * 12295011Sandrew * * Redistributions of source code must retain the above copyright notice, 13295011Sandrew * this list of conditions and the following disclaimer. 14295011Sandrew * 15295011Sandrew * * Redistributions in binary form must reproduce the above copyright 16295011Sandrew * notice, this list of conditions and the following disclaimer in 17295011Sandrew * the documentation and/or other materials provided with the 18295011Sandrew * distribution. 19295011Sandrew * 20295011Sandrew * This program is distributed in the hope it will be useful, but WITHOUT 21295011Sandrew * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 22295011Sandrew * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 23295011Sandrew * more details. 24295011Sandrew * 25295011Sandrew */ 26295011Sandrew 27295011Sandrew#include <dt-bindings/interrupt-controller/arm-gic.h> 28295011Sandrew#include "skeleton64.dtsi" 29295011Sandrew 30295011Sandrew/ { 31295011Sandrew /* SOC compatibility */ 32295011Sandrew compatible = "al,alpine"; 33295011Sandrew 34295011Sandrew /* CPU Configuration */ 35295011Sandrew cpus { 36295011Sandrew #address-cells = <1>; 37295011Sandrew #size-cells = <0>; 38295011Sandrew enable-method = "al,alpine-smp"; 39295011Sandrew 40295011Sandrew cpu@0 { 41295011Sandrew compatible = "arm,cortex-a15"; 42295011Sandrew device_type = "cpu"; 43295011Sandrew reg = <0>; 44295011Sandrew clock-frequency = <0>; /* Filled by loader */ 45295011Sandrew }; 46295011Sandrew 47295011Sandrew cpu@1 { 48295011Sandrew compatible = "arm,cortex-a15"; 49295011Sandrew device_type = "cpu"; 50295011Sandrew reg = <1>; 51295011Sandrew clock-frequency = <0>; /* Filled by loader */ 52295011Sandrew }; 53295011Sandrew 54295011Sandrew cpu@2 { 55295011Sandrew compatible = "arm,cortex-a15"; 56295011Sandrew device_type = "cpu"; 57295011Sandrew reg = <2>; 58295011Sandrew clock-frequency = <0>; /* Filled by loader */ 59295011Sandrew }; 60295011Sandrew 61295011Sandrew cpu@3 { 62295011Sandrew compatible = "arm,cortex-a15"; 63295011Sandrew device_type = "cpu"; 64295011Sandrew reg = <3>; 65295011Sandrew clock-frequency = <0>; /* Filled by loader */ 66295011Sandrew }; 67295011Sandrew }; 68295011Sandrew 69295011Sandrew soc { 70295011Sandrew #address-cells = <2>; 71295011Sandrew #size-cells = <2>; 72295011Sandrew compatible = "simple-bus"; 73295011Sandrew interrupt-parent = <&gic>; 74295011Sandrew ranges; 75295011Sandrew 76295011Sandrew arch-timer { 77295011Sandrew compatible = "arm,cortex-a15-timer", 78295011Sandrew "arm,armv7-timer"; 79295011Sandrew interrupts = 80295011Sandrew <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 81295011Sandrew <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 82295011Sandrew <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 83295011Sandrew <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 84295011Sandrew clock-frequency = <0>; /* Filled by loader */ 85295011Sandrew }; 86295011Sandrew 87295011Sandrew /* Interrupt Controller */ 88295011Sandrew gic: gic@fb001000 { 89295011Sandrew compatible = "arm,cortex-a15-gic"; 90295011Sandrew #interrupt-cells = <3>; 91295011Sandrew #size-cells = <0>; 92295011Sandrew #address-cells = <0>; 93295011Sandrew interrupt-controller; 94295011Sandrew reg = <0x0 0xfb001000 0x0 0x1000>, 95295011Sandrew <0x0 0xfb002000 0x0 0x2000>, 96295011Sandrew <0x0 0xfb004000 0x0 0x1000>, 97295011Sandrew <0x0 0xfb006000 0x0 0x2000>; 98295011Sandrew interrupts = 99295011Sandrew <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 100295011Sandrew }; 101295011Sandrew 102295011Sandrew /* CPU Resume registers */ 103295011Sandrew cpu-resume@fbff5ec0 { 104295011Sandrew compatible = "al,alpine-cpu-resume"; 105295011Sandrew reg = <0x0 0xfbff5ec0 0x0 0x30>; 106295011Sandrew }; 107295011Sandrew 108295011Sandrew /* North Bridge Service Registers */ 109295011Sandrew sysfabric-service@fb070000 { 110295011Sandrew compatible = "al,alpine-sysfabric-service", "syscon"; 111295011Sandrew reg = <0x0 0xfb070000 0x0 0x10000>; 112295011Sandrew }; 113295011Sandrew 114295011Sandrew /* Performance Monitor Unit */ 115295011Sandrew pmu { 116295011Sandrew compatible = "arm,cortex-a15-pmu"; 117295011Sandrew interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 118295011Sandrew <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 119295011Sandrew <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 120295011Sandrew <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 121295011Sandrew }; 122295011Sandrew 123295011Sandrew uart0:uart@fd883000 { 124295011Sandrew compatible = "ns16550a"; 125295011Sandrew reg = <0x0 0xfd883000 0x0 0x1000>; 126295011Sandrew clock-frequency = <0>; /* Filled by loader */ 127295011Sandrew interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 128295011Sandrew reg-shift = <2>; 129295011Sandrew reg-io-width = <4>; 130295011Sandrew }; 131295011Sandrew 132295011Sandrew uart1:uart@0xfd884000 { 133295011Sandrew compatible = "ns16550a"; 134295011Sandrew reg = <0x0 0xfd884000 0x0 0x1000>; 135295011Sandrew clock-frequency = <0>; /* Filled by loader */ 136295011Sandrew interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 137295011Sandrew reg-shift = <2>; 138295011Sandrew reg-io-width = <4>; 139295011Sandrew }; 140295011Sandrew 141295011Sandrew /* Internal PCIe Controller */ 142295011Sandrew pcie-internal@0xfbc00000 { 143295011Sandrew compatible = "pci-host-ecam-generic"; 144295011Sandrew device_type = "pci"; 145295011Sandrew #size-cells = <2>; 146295011Sandrew #address-cells = <3>; 147295011Sandrew #interrupt-cells = <1>; 148295011Sandrew reg = <0x0 0xfbc00000 0x0 0x100000>; 149295011Sandrew interrupt-map-mask = <0xf800 0 0 7>; 150295011Sandrew /* Add legacy interrupts for SATA devices only */ 151295011Sandrew interrupt-map = <0x4000 0 0 1 &gic 0 43 4>, 152295011Sandrew <0x4800 0 0 1 &gic 0 44 4>; 153295011Sandrew 154295011Sandrew /* 32 bit non prefetchable memory space */ 155295011Sandrew ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>; 156295011Sandrew 157295011Sandrew bus-range = <0x00 0x00>; 158295011Sandrew }; 159295011Sandrew }; 160295011Sandrew}; 161