if_xlreg.h revision 47627
1139731Simp/* 24Srgrimes * Copyright (c) 1997, 1998 34Srgrimes * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 44Srgrimes * 58876Srgrimes * Redistribution and use in source and binary forms, with or without 64Srgrimes * modification, are permitted provided that the following conditions 74Srgrimes * are met: 84Srgrimes * 1. Redistributions of source code must retain the above copyright 94Srgrimes * notice, this list of conditions and the following disclaimer. 104Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 118876Srgrimes * notice, this list of conditions and the following disclaimer in the 128876Srgrimes * documentation and/or other materials provided with the distribution. 134Srgrimes * 3. All advertising materials mentioning features or use of this software 144Srgrimes * must display the following acknowledgement: 158876Srgrimes * This product includes software developed by Bill Paul. 164Srgrimes * 4. Neither the name of the author nor the names of any co-contributors 178876Srgrimes * may be used to endorse or promote products derived from this software 184Srgrimes * without specific prior written permission. 194Srgrimes * 204Srgrimes * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 214Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 228876Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 234Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 244Srgrimes * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 254Srgrimes * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 264Srgrimes * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27118031Sobrien * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28118031Sobrien * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29118031Sobrien * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 304Srgrimes * THE POSSIBILITY OF SUCH DAMAGE. 314Srgrimes * 324Srgrimes * $Id: if_xlreg.h,v 1.16 1999/05/26 23:01:52 gallatin Exp $ 332056Swollman */ 34238166Sjhb 3524494Sbde#define XL_EE_READ 0x0080 /* read, 5 bit address */ 362056Swollman#define XL_EE_WRITE 0x0040 /* write, 5 bit address */ 374Srgrimes#define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */ 384Srgrimes#define XL_EE_EWEN 0x0030 /* erase, no data needed */ 394Srgrimes#define XL_EE_BUSY 0x8000 404Srgrimes 414Srgrimes#define XL_EE_EADDR0 0x00 /* station address, first word */ 424Srgrimes#define XL_EE_EADDR1 0x01 /* station address, next word, */ 434Srgrimes#define XL_EE_EADDR2 0x02 /* station address, last word */ 444Srgrimes#define XL_EE_PRODID 0x03 /* product ID code */ 454Srgrimes#define XL_EE_MDATA_DATE 0x04 /* manufacturing data, date */ 464Srgrimes#define XL_EE_MDATA_DIV 0x05 /* manufacturing data, division */ 474Srgrimes#define XL_EE_MDATA_PCODE 0x06 /* manufacturing data, product code */ 484Srgrimes#define XL_EE_MFG_ID 0x07 494Srgrimes#define XL_EE_PCI_PARM 0x08 504Srgrimes#define XL_EE_ROM_ONFO 0x09 51238166Sjhb#define XL_EE_OEM_ADR0 0x0A 52238166Sjhb#define XL_EE_OEM_ADR1 0x0B 53238166Sjhb#define XL_EE_OEM_ADR2 0x0C 544Srgrimes#define XL_EE_SOFTINFO1 0x0D 554Srgrimes#define XL_EE_COMPAT 0x0E 56144353Speter#define XL_EE_SOFTINFO2 0x0F 57144353Speter#define XL_EE_CAPS 0x10 /* capabilities word */ 58144353Speter#define XL_EE_RSVD0 0x11 59144353Speter#define XL_EE_ICFG_0 0x12 60144353Speter#define XL_EE_ICFG_1 0x13 61144353Speter#define XL_EE_RSVD1 0x14 62144353Speter#define XL_EE_SOFTINFO3 0x15 63144353Speter#define XL_EE_RSVD_2 0x16 64144353Speter 654Srgrimes/* 664Srgrimes * Bits in the capabilities word 674Srgrimes */ 684Srgrimes#define XL_CAPS_PNP 0x0001 694Srgrimes#define XL_CAPS_FULL_DUPLEX 0x0002 704Srgrimes#define XL_CAPS_LARGE_PKTS 0x0004 714Srgrimes#define XL_CAPS_SLAVE_DMA 0x0008 724Srgrimes#define XL_CAPS_SECOND_DMA 0x0010 73238166Sjhb#define XL_CAPS_FULL_BM 0x0020 744Srgrimes#define XL_CAPS_FRAG_BM 0x0040 754Srgrimes#define XL_CAPS_CRC_PASSTHRU 0x0080 764Srgrimes#define XL_CAPS_TXDONE 0x0100 774Srgrimes#define XL_CAPS_NO_TXLENGTH 0x0200 784Srgrimes#define XL_CAPS_RX_REPEAT 0x0400 794Srgrimes#define XL_CAPS_SNOOPING 0x0800 804Srgrimes#define XL_CAPS_100MBPS 0x1000 814Srgrimes#define XL_CAPS_PWRMGMT 0x2000 824Srgrimes 834Srgrimes#define XL_PACKET_SIZE 1536 844Srgrimes 854Srgrimes/* 864Srgrimes * Register layouts. 874Srgrimes */ 884Srgrimes#define XL_COMMAND 0x0E 894Srgrimes#define XL_STATUS 0x0E 904Srgrimes 91164263Sjhb#define XL_TX_STATUS 0x1B 924Srgrimes#define XL_TX_FREE 0x1C 934Srgrimes#define XL_DMACTL 0x20 944Srgrimes#define XL_DOWNLIST_PTR 0x24 954Srgrimes#define XL_TX_FREETHRESH 0x2F 964Srgrimes#define XL_UPLIST_PTR 0x38 974Srgrimes#define XL_UPLIST_STATUS 0x30 984Srgrimes 994Srgrimes#define XL_PKTSTAT_UP_STALLED 0x00002000 1004Srgrimes#define XL_PKTSTAT_UP_ERROR 0x00004000 1014Srgrimes#define XL_PKTSTAT_UP_CMPLT 0x00008000 102144354Speter 10321277Sbde#define XL_DMACTL_DN_CMPLT_REQ 0x00000002 10421277Sbde#define XL_DMACTL_DOWN_STALLED 0x00000004 105144354Speter#define XL_DMACTL_UP_CMPLT 0x00000008 1064Srgrimes#define XL_DMACTL_DOWN_CMPLT 0x00000010 10711940Sbde#define XL_DMACTL_UP_RX_EARLY 0x00000020 10814887Swollman#define XL_DMACTL_ARM_COUNTDOWN 0x00000040 1094Srgrimes#define XL_DMACTL_DOWN_INPROG 0x00000080 1104Srgrimes#define XL_DMACTL_COUNTER_SPEED 0x00000100 1114Srgrimes#define XL_DMACTL_DOWNDOWN_MODE 0x00000200 11217109Sbde#define XL_DMACTL_TARGET_ABORT 0x40000000 1134Srgrimes#define XL_DMACTL_MASTER_ABORT 0x80000000 1144Srgrimes 1154Srgrimes/* 1164Srgrimes * Command codes. Some command codes require that we wait for 1174Srgrimes * the CMD_BUSY flag to clear. Those codes are marked as 'mustwait.' 1184Srgrimes */ 11911940Sbde#define XL_CMD_RESET 0x0000 /* mustwait */ 12014887Swollman#define XL_CMD_WINSEL 0x0800 1214Srgrimes#define XL_CMD_COAX_START 0x1000 1224Srgrimes#define XL_CMD_RX_DISABLE 0x1800 12317109Sbde#define XL_CMD_RX_ENABLE 0x2000 1244Srgrimes#define XL_CMD_RX_RESET 0x2800 /* mustwait */ 1254Srgrimes#define XL_CMD_UP_STALL 0x3000 /* mustwait */ 1264Srgrimes#define XL_CMD_UP_UNSTALL 0x3001 127238166Sjhb#define XL_CMD_DOWN_STALL 0x3002 /* mustwait */ 128238166Sjhb#define XL_CMD_DOWN_UNSTALL 0x3003 129238166Sjhb#define XL_CMD_RX_DISCARD 0x4000 130255192Sjhb#define XL_CMD_TX_ENABLE 0x4800 131238166Sjhb#define XL_CMD_TX_DISABLE 0x5000 132238166Sjhb#define XL_CMD_TX_RESET 0x5800 /* mustwait */ 133238166Sjhb#define XL_CMD_INTR_FAKE 0x6000 134238166Sjhb#define XL_CMD_INTR_ACK 0x6800 135238166Sjhb#define XL_CMD_INTR_ENB 0x7000 136238166Sjhb#define XL_CMD_STAT_ENB 0x7800 137238166Sjhb#define XL_CMD_RX_SET_FILT 0x8000 138238166Sjhb#define XL_CMD_RX_SET_THRESH 0x8800 139238166Sjhb#define XL_CMD_TX_SET_THRESH 0x9000 140238166Sjhb#define XL_CMD_TX_SET_START 0x9800 141238166Sjhb#define XL_CMD_DMA_UP 0xA000 142238166Sjhb#define XL_CMD_DMA_STOP 0xA001 143238166Sjhb#define XL_CMD_STATS_ENABLE 0xA800 144238166Sjhb#define XL_CMD_STATS_DISABLE 0xB000 145238166Sjhb#define XL_CMD_COAX_STOP 0xB800 146238166Sjhb 147238166Sjhb#define XL_CMD_SET_TX_RECLAIM 0xC000 /* 3c905B only */ 148238166Sjhb#define XL_CMD_RX_SET_HASH 0xC800 /* 3c905B only */ 149238166Sjhb 150238166Sjhb#define XL_HASH_SET 0x0400 151238166Sjhb#define XL_HASHFILT_SIZE 256 152238166Sjhb 153238166Sjhb/* 154238166Sjhb * status codes 155238166Sjhb * Note that bits 15 to 13 indicate the currently visible register window 156238166Sjhb * which may be anything from 0 to 7. 157238166Sjhb */ 158238166Sjhb#define XL_STAT_INTLATCH 0x0001 /* 0 */ 159238166Sjhb#define XL_STAT_ADFAIL 0x0002 /* 1 */ 160238166Sjhb#define XL_STAT_TX_COMPLETE 0x0004 /* 2 */ 161238166Sjhb#define XL_STAT_TX_AVAIL 0x0008 /* 3 first generation */ 162238166Sjhb#define XL_STAT_RX_COMPLETE 0x0010 /* 4 */ 163238166Sjhb#define XL_STAT_RX_EARLY 0x0020 /* 5 */ 164238166Sjhb#define XL_STAT_INTREQ 0x0040 /* 6 */ 165238166Sjhb#define XL_STAT_STATSOFLOW 0x0080 /* 7 */ 16614887Swollman#define XL_STAT_DMADONE 0x0100 /* 8 first generation */ 1674Srgrimes#define XL_STAT_LINKSTAT 0x0100 /* 8 3c509B */ 1684Srgrimes#define XL_STAT_DOWN_COMPLETE 0x0200 /* 9 */ 1694Srgrimes#define XL_STAT_UP_COMPLETE 0x0400 /* 10 */ 1704Srgrimes#define XL_STAT_DMABUSY 0x0800 /* 11 first generation */ 1714Srgrimes#define XL_STAT_CMDBUSY 0x1000 /* 12 */ 1724Srgrimes 1734Srgrimes/* 1744Srgrimes * Interrupts we normally want enabled. 1754Srgrimes */ 1764Srgrimes#define XL_INTRS \ 17714887Swollman (XL_STAT_UP_COMPLETE|XL_STAT_STATSOFLOW|XL_STAT_ADFAIL| \ 1784Srgrimes XL_STAT_DOWN_COMPLETE|XL_STAT_TX_COMPLETE|XL_STAT_INTLATCH) 1794Srgrimes 1804Srgrimes/* 1814Srgrimes * Window 0 registers 1824Srgrimes */ 1834Srgrimes#define XL_W0_EE_DATA 0x0C 1844Srgrimes#define XL_W0_EE_CMD 0x0A 1854Srgrimes#define XL_W0_RSRC_CFG 0x08 1864Srgrimes#define XL_W0_ADDR_CFG 0x06 1874Srgrimes#define XL_W0_CFG_CTRL 0x04 18814887Swollman 1894Srgrimes#define XL_W0_PROD_ID 0x02 1904Srgrimes#define XL_W0_MFG_ID 0x00 1914Srgrimes 1924Srgrimes/* 1934Srgrimes * Window 1 1944Srgrimes */ 1954Srgrimes 1964Srgrimes#define XL_W1_TX_FIFO 0x10 1974Srgrimes 1984Srgrimes#define XL_W1_FREE_TX 0x0C 19921277Sbde#define XL_W1_TX_STATUS 0x0B 20021277Sbde#define XL_W1_TX_TIMER 0x0A 20121277Sbde#define XL_W1_RX_STATUS 0x08 20221277Sbde#define XL_W1_RX_FIFO 0x00 20321277Sbde 20421277Sbde/* 20521277Sbde * RX status codes 206238166Sjhb */ 207238166Sjhb#define XL_RXSTATUS_OVERRUN 0x01 20821277Sbde#define XL_RXSTATUS_RUNT 0x02 20921277Sbde#define XL_RXSTATUS_ALIGN 0x04 210181606Sjhb#define XL_RXSTATUS_CRC 0x08 211181606Sjhb#define XL_RXSTATUS_OVERSIZE 0x10 212181606Sjhb#define XL_RXSTATUS_DRIBBLE 0x20 213181606Sjhb 214181606Sjhb/* 215238109Sjhb * TX status codes 216238109Sjhb */ 217238109Sjhb#define XL_TXSTATUS_RECLAIM 0x02 /* 3c905B only */ 218181606Sjhb#define XL_TXSTATUS_OVERFLOW 0x04 219181606Sjhb#define XL_TXSTATUS_MAXCOLS 0x08 220181606Sjhb#define XL_TXSTATUS_UNDERRUN 0x10 221181606Sjhb#define XL_TXSTATUS_JABBER 0x20 222181606Sjhb#define XL_TXSTATUS_INTREQ 0x40 223181606Sjhb#define XL_TXSTATUS_COMPLETE 0x80 224181606Sjhb 225181606Sjhb/* 226181606Sjhb * Window 2 227181606Sjhb */ 228181606Sjhb#define XL_W2_RESET_OPTIONS 0x0C /* 3c905B only */ 229181606Sjhb#define XL_W2_STATION_MASK_HI 0x0A 230181606Sjhb#define XL_W2_STATION_MASK_MID 0x08 231181606Sjhb#define XL_W2_STATION_MASK_LO 0x06 23214887Swollman#define XL_W2_STATION_ADDR_HI 0x04 23317109Sbde#define XL_W2_STATION_ADDR_MID 0x02 23417109Sbde#define XL_W2_STATION_ADDR_LO 0x00 2354Srgrimes 2364Srgrimes#define XL_RESETOPT_FEATUREMASK 0x0001|0x0002|0x004 2374Srgrimes#define XL_RESETOPT_D3RESETDIS 0x0008 238181606Sjhb#define XL_RESETOPT_DISADVFD 0x0010 2394Srgrimes#define XL_RESETOPT_DISADV100 0x0020 240181606Sjhb#define XL_RESETOPT_DISAUTONEG 0x0040 2414Srgrimes#define XL_RESETOPT_DEBUGMODE 0x0080 2424Srgrimes#define XL_RESETOPT_FASTAUTO 0x0100 2434Srgrimes#define XL_RESETOPT_FASTEE 0x0200 2444Srgrimes#define XL_RESETOPT_FORCEDCONF 0x0400 2454Srgrimes#define XL_RESETOPT_TESTPDTPDR 0x0800 2464Srgrimes#define XL_RESETOPT_TEST100TX 0x1000 2474Srgrimes#define XL_RESETOPT_TEST100RX 0x2000 2484Srgrimes 2494Srgrimes/* 2504Srgrimes * Window 3 (fifo management) 2514Srgrimes */ 25217109Sbde#define XL_W3_INTERNAL_CFG 0x00 25321277Sbde#define XL_W3_RESET_OPT 0x08 25421277Sbde#define XL_W3_FREE_TX 0x0C 25521277Sbde#define XL_W3_FREE_RX 0x0A 25621277Sbde#define XL_W3_MAC_CTRL 0x06 25721277Sbde 2584Srgrimes#define XL_ICFG_CONNECTOR_MASK 0x00F00000 25921277Sbde#define XL_ICFG_CONNECTOR_BITS 20 2604Srgrimes 2614Srgrimes#define XL_ICFG_RAMSIZE_MASK 0x00000007 2624Srgrimes#define XL_ICFG_RAMWIDTH 0x00000008 2634Srgrimes#define XL_ICFG_ROMSIZE_MASK (0x00000040|0x00000080) 2644Srgrimes#define XL_ICFG_DISABLE_BASSD 0x00000100 2654Srgrimes#define XL_ICFG_RAMLOC 0x00000200 2664Srgrimes#define XL_ICFG_RAMPART (0x00010000|0x00020000) 2674Srgrimes#define XL_ICFG_XCVRSEL (0x00100000|0x00200000|0x00400000) 2684Srgrimes#define XL_ICFG_AUTOSEL 0x01000000 2694Srgrimes 2704Srgrimes#define XL_XCVR_10BT 0x00 2714Srgrimes#define XL_XCVR_AUI 0x01 27214887Swollman#define XL_XCVR_RSVD_0 0x02 27314887Swollman#define XL_XCVR_COAX 0x03 27414887Swollman#define XL_XCVR_100BTX 0x04 27514887Swollman#define XL_XCVR_100BFX 0x05 27614887Swollman#define XL_XCVR_MII 0x06 277181606Sjhb#define XL_XCVR_RSVD_1 0x07 278181606Sjhb#define XL_XCVR_AUTO 0x08 /* 3c905B only */ 27914887Swollman 280181606Sjhb#define XL_MACCTRL_DEFER_EXT_END 0x0001 28114887Swollman#define XL_MACCTRL_DEFER_0 0x0002 282238166Sjhb#define XL_MACCTRL_DEFER_1 0x0004 28314887Swollman#define XL_MACCTRL_DEFER_2 0x0008 28414887Swollman#define XL_MACCTRL_DEFER_3 0x0010 28514887Swollman#define XL_MACCTRL_DUPLEX 0x0020 28614887Swollman#define XL_MACCTRL_ALLOW_LARGE_PACK 0x0040 28714887Swollman#define XL_MACCTRL_EXTEND_AFTER_COL 0x0080 (3c905B only) 28814887Swollman#define XL_MACCTRL_FLOW_CONTROL_ENB 0x0100 (3c905B only) 28914887Swollman#define XL_MACCTRL_VLT_END 0x0200 (3c905B only) 29014887Swollman 29114887Swollman/* 292144354Speter * The 'reset options' register contains power-on reset values 293144354Speter * loaded from the EEPROM. This includes the supported media 294144354Speter * types on the card. It is also known as the media options register. 295144354Speter */ 296144354Speter#define XL_W3_MEDIA_OPT 0x08 297144354Speter 298144354Speter#define XL_MEDIAOPT_BT4 0x0001 /* MII */ 299144354Speter#define XL_MEDIAOPT_BTX 0x0002 /* on-chip */ 300144354Speter#define XL_MEDIAOPT_BFX 0x0004 /* on-chip */ 301144354Speter#define XL_MEDIAOPT_BT 0x0008 /* on-chip */ 302144354Speter#define XL_MEDIAOPT_BNC 0x0010 /* on-chip */ 303144354Speter#define XL_MEDIAOPT_AUI 0x0020 /* on-chip */ 304144354Speter#define XL_MEDIAOPT_MII 0x0040 /* MII */ 305144354Speter#define XL_MEDIAOPT_VCO 0x0100 /* 1st gen chip only */ 306144354Speter 307144354Speter#define XL_MEDIAOPT_10FL 0x0100 /* 3x905B only, on-chip */ 308144354Speter#define XL_MEDIAOPT_MASK 0x01FF 309144354Speter 310144354Speter/* 311144354Speter * Window 4 (diagnostics) 312238166Sjhb */ 313238166Sjhb#define XL_W4_UPPERBYTESOK 0x0D 314238166Sjhb#define XL_W4_BADSSD 0x0C 315238166Sjhb#define XL_W4_MEDIA_STATUS 0x0A 316238166Sjhb#define XL_W4_PHY_MGMT 0x08 317238166Sjhb#define XL_W4_NET_DIAG 0x06 318238166Sjhb#define XL_W4_FIFO_DIAG 0x04 319238166Sjhb#define XL_W4_VCO_DIAG 0x02 320238166Sjhb 321238166Sjhb#define XL_W4_CTRLR_STAT 0x08 322238166Sjhb#define XL_W4_TX_DIAG 0x00 323238166Sjhb 324238166Sjhb#define XL_MII_CLK 0x01 325238166Sjhb#define XL_MII_DATA 0x02 326238166Sjhb#define XL_MII_DIR 0x04 327238166Sjhb 328238166Sjhb#define XL_MEDIA_SQE 0x0008 329238166Sjhb#define XL_MEDIA_10TP 0x00C0 330238166Sjhb#define XL_MEDIA_LNK 0x0080 331238166Sjhb#define XL_MEDIA_LNKBEAT 0x0800 33217109Sbde 3334Srgrimes#define XL_MEDIASTAT_CRCSTRIP 0x0004 3344Srgrimes#define XL_MEDIASTAT_SQEENB 0x0008 3354Srgrimes#define XL_MEDIASTAT_COLDET 0x0010 3364Srgrimes#define XL_MEDIASTAT_CARRIER 0x0020 3374Srgrimes#define XL_MEDIASTAT_JABGUARD 0x0040 3384Srgrimes#define XL_MEDIASTAT_LINKBEAT 0x0080 3394Srgrimes#define XL_MEDIASTAT_JABDETECT 0x0200 3404Srgrimes#define XL_MEDIASTAT_POLREVERS 0x0400 3414Srgrimes#define XL_MEDIASTAT_LINKDETECT 0x0800 3424Srgrimes#define XL_MEDIASTAT_TXINPROG 0x1000 3434Srgrimes#define XL_MEDIASTAT_DCENB 0x4000 3444Srgrimes#define XL_MEDIASTAT_AUIDIS 0x8000 3454Srgrimes 3464Srgrimes#define XL_NETDIAG_TEST_LOWVOLT 0x0001 3474Srgrimes#define XL_NETDIAG_ASIC_REVMASK (0x0002|0x0004|0x0008|0x0010|0x0020) 3484Srgrimes#define XL_NETDIAG_UPPER_BYTES_ENABLE 0x0040 3494Srgrimes#define XL_NETDIAG_STATS_ENABLED 0x0080 3504Srgrimes#define XL_NETDIAG_TX_FATALERR 0x0100 3514Srgrimes#define XL_NETDIAG_TRANSMITTING 0x0200 35217109Sbde#define XL_NETDIAG_RX_ENABLED 0x0400 3534Srgrimes#define XL_NETDIAG_TX_ENABLED 0x0800 3544Srgrimes#define XL_NETDIAG_FIFO_LOOPBACK 0x1000 3554Srgrimes#define XL_NETDIAG_MAC_LOOPBACK 0x2000 3564Srgrimes#define XL_NETDIAG_ENDEC_LOOPBACK 0x4000 3574Srgrimes#define XL_NETDIAG_EXTERNAL_LOOP 0x8000 3584Srgrimes 3594Srgrimes/* 3604Srgrimes * Window 5 3614Srgrimes */ 3624Srgrimes#define XL_W5_STAT_ENB 0x0C 3634Srgrimes#define XL_W5_INTR_ENB 0x0A 3644Srgrimes#define XL_W5_RECLAIM_THRESH 0x09 /* 3c905B only */ 3654Srgrimes#define XL_W5_RX_FILTER 0x08 3664Srgrimes#define XL_W5_RX_EARLYTHRESH 0x06 3674Srgrimes#define XL_W5_TX_AVAILTHRESH 0x02 3684Srgrimes#define XL_W5_TX_STARTTHRESH 0x00 3694Srgrimes 3704Srgrimes/* 3714Srgrimes * RX filter bits 37217109Sbde */ 3734Srgrimes#define XL_RXFILTER_INDIVIDUAL 0x01 3744Srgrimes#define XL_RXFILTER_ALLMULTI 0x02 37521277Sbde#define XL_RXFILTER_BROADCAST 0x04 37621277Sbde#define XL_RXFILTER_ALLFRAMES 0x08 37717109Sbde#define XL_RXFILTER_MULTIHASH 0x10 /* 3c905B only */ 37817109Sbde 3794Srgrimes/* 3804Srgrimes * Window 6 (stats) 3814Srgrimes */ 3824Srgrimes#define XL_W6_TX_BYTES_OK 0x0C 3834Srgrimes#define XL_W6_RX_BYTES_OK 0x0A 38421277Sbde#define XL_W6_UPPER_FRAMES_OK 0x09 38521277Sbde#define XL_W6_DEFERRED 0x08 38617109Sbde#define XL_W6_RX_OK 0x07 38717109Sbde#define XL_W6_TX_OK 0x06 388181606Sjhb#define XL_W6_RX_OVERRUN 0x05 389181606Sjhb#define XL_W6_COL_LATE 0x04 3904Srgrimes#define XL_W6_COL_SINGLE 0x03 3914Srgrimes#define XL_W6_COL_MULTIPLE 0x02 39217109Sbde#define XL_W6_SQE_ERRORS 0x01 39321277Sbde#define XL_W6_CARRIER_LOST 0x00 39421277Sbde 3954Srgrimes/* 39621277Sbde * Window 7 (bus master control) 3974Srgrimes */ 3984Srgrimes#define XL_W7_BM_ADDR 0x00 39921277Sbde#define XL_W7_BM_LEN 0x06 40021277Sbde#define XL_W7_BM_STATUS 0x0B 4014Srgrimes#define XL_W7_BM_TIMEr 0x0A 4024Srgrimes 4034Srgrimes/* 40417109Sbde * bus master control registers 4054Srgrimes */ 4064Srgrimes#define XL_BM_PKTSTAT 0x20 4074Srgrimes#define XL_BM_DOWNLISTPTR 0x24 40821277Sbde#define XL_BM_FRAGADDR 0x28 40921277Sbde#define XL_BM_FRAGLEN 0x2C 4104Srgrimes#define XL_BM_TXFREETHRESH 0x2F 4114Srgrimes#define XL_BM_UPPKTSTAT 0x30 41217109Sbde#define XL_BM_UPLISTPTR 0x38 4134Srgrimes 4144Srgrimes#define XL_LAST_FRAG 0x80000000 4154Srgrimes 4164Srgrimes/* 4174Srgrimes * Boomerang/Cyclone TX/RX list structure. 4184Srgrimes * For the TX lists, bits 0 to 12 of the status word indicate 4194Srgrimes * length. 42021277Sbde * This looks suspiciously like the ThunderLAN, doesn't it. 42121277Sbde */ 42221277Sbdestruct xl_frag { 42321277Sbde u_int32_t xl_addr; /* 63 addr/len pairs */ 42421277Sbde u_int32_t xl_len; 42521277Sbde}; 42621277Sbde 42721277Sbdestruct xl_list { 42821277Sbde u_int32_t xl_next; /* final entry has 0 nextptr */ 4294Srgrimes u_int32_t xl_status; 4304Srgrimes struct xl_frag xl_frag[63]; 43114887Swollman}; 4324Srgrimes 4334Srgrimesstruct xl_list_onefrag { 4344Srgrimes u_int32_t xl_next; /* final entry has 0 nextptr */ 43514887Swollman u_int32_t xl_status; 436144354Speter struct xl_frag xl_frag; 4374Srgrimes}; 4384Srgrimes 439238166Sjhb#define XL_MAXFRAGS 63 4404Srgrimes#define XL_RX_LIST_CNT 128 4414Srgrimes#define XL_TX_LIST_CNT 256 4424Srgrimes#define XL_MIN_FRAMELEN 60 4434Srgrimes 4444Srgrimesstruct xl_list_data { 4454Srgrimes struct xl_list_onefrag xl_rx_list[XL_RX_LIST_CNT]; 44621277Sbde struct xl_list xl_tx_list[XL_TX_LIST_CNT]; 4474Srgrimes unsigned char xl_pad[XL_MIN_FRAMELEN]; 4484Srgrimes}; 4494Srgrimes 45014887Swollmanstruct xl_chain { 4514Srgrimes struct xl_list *xl_ptr; 4524Srgrimes struct mbuf *xl_mbuf; 45314887Swollman struct xl_chain *xl_next; 4544Srgrimes}; 4554Srgrimes 45617109Sbdestruct xl_chain_onefrag { 4574Srgrimes struct xl_list_onefrag *xl_ptr; 4584Srgrimes struct mbuf *xl_mbuf; 45917109Sbde struct xl_chain_onefrag *xl_next; 4604Srgrimes}; 4614Srgrimes 4624Srgrimesstruct xl_chain_data { 46314887Swollman struct xl_chain_onefrag xl_rx_chain[XL_RX_LIST_CNT]; 4644Srgrimes struct xl_chain xl_tx_chain[XL_TX_LIST_CNT]; 4654Srgrimes 4664Srgrimes struct xl_chain_onefrag *xl_rx_head; 46721277Sbde 4684Srgrimes struct xl_chain *xl_tx_head; 4694Srgrimes struct xl_chain *xl_tx_tail; 4704Srgrimes struct xl_chain *xl_tx_free; 47117109Sbde}; 47221277Sbde 4734Srgrimes#define XL_RXSTAT_LENMASK 0x00001FFF 4744Srgrimes#define XL_RXSTAT_UP_ERROR 0x00004000 47514887Swollman#define XL_RXSTAT_UP_CMPLT 0x00008000 4764Srgrimes#define XL_RXSTAT_UP_OVERRUN 0x00010000 4774Srgrimes#define XL_RXSTAT_RUNT 0x00020000 4784Srgrimes#define XL_RXSTAT_ALIGN 0x00040000 47917109Sbde#define XL_RXSTAT_CRC 0x00080000 4804Srgrimes#define XL_RXSTAT_OVERSIZE 0x00100000 4814Srgrimes#define XL_RXSTAT_DRIBBLE 0x00800000 4824Srgrimes#define XL_RXSTAT_UP_OFLOW 0x01000000 48314887Swollman#define XL_RXSTAT_IPCKERR 0x02000000 /* 3c905B only */ 4844Srgrimes#define XL_RXSTAT_TCPCKERR 0x04000000 /* 3c905B only */ 4854Srgrimes#define XL_RXSTAT_UDPCKERR 0x08000000 /* 3c905B only */ 4864Srgrimes#define XL_RXSTAT_BUFEN 0x10000000 /* 3c905B only */ 4874Srgrimes#define XL_RXSTAT_IPCKOK 0x20000000 /* 3c905B only */ 4884Srgrimes#define XL_RXSTAT_TCPCOK 0x40000000 /* 3c905B only */ 4894Srgrimes#define XL_RXSTAT_UDPCKOK 0x80000000 /* 3c905B only */ 4904Srgrimes 4914Srgrimes#define XL_TXSTAT_LENMASK 0x00001FFF 4924Srgrimes#define XL_TXSTAT_CRCDIS 0x00002000 4934Srgrimes#define XL_TXSTAT_TX_INTR 0x00008000 49414887Swollman#define XL_TXSTAT_DL_COMPLETE 0x00010000 4954Srgrimes#define XL_TXSTAT_IPCKSUM 0x02000000 /* 3c905B only */ 4964Srgrimes#define XL_TXSTAT_TCPCKSUM 0x04000000 /* 3c905B only */ 49717109Sbde#define XL_TXSTAT_UDPCKSUM 0x08000000 /* 3c905B only */ 49821277Sbde#define XL_TXSTAT_DL_INTR 0x80000000 49917109Sbde 50017109Sbde#define XL_CAPABILITY_BM 0x20 50117109Sbde 50217109Sbde 5034Srgrimesstruct xl_type { 5044Srgrimes u_int16_t xl_vid; 50514887Swollman u_int16_t xl_did; 50621277Sbde char *xl_name; 50721277Sbde}; 50821277Sbde 50921277Sbdestruct xl_mii_frame { 51021277Sbde u_int8_t mii_stdelim; 51121277Sbde u_int8_t mii_opcode; 51221277Sbde u_int8_t mii_phyaddr; 51321277Sbde u_int8_t mii_regaddr; 5144Srgrimes u_int8_t mii_turnaround; 5154Srgrimes u_int16_t mii_data; 51614887Swollman}; 51721277Sbde 5184Srgrimes/* 51921277Sbde * MII constants 52021277Sbde */ 52117109Sbde#define XL_MII_STARTDELIM 0x01 5224Srgrimes#define XL_MII_READOP 0x02 5234Srgrimes#define XL_MII_WRITEOP 0x01 5244Srgrimes#define XL_MII_TURNAROUND 0x02 5254Srgrimes 5264Srgrimes/* 52714887Swollman * The 3C905B adapters implement a few features that we want to 5284Srgrimes * take advantage of, namely the multicast hash filter. With older 5294Srgrimes * chips, you only have the option of turning on reception of all 53021277Sbde * multicast frames, which is kind of lame. 53121277Sbde */ 5324Srgrimes#define XL_TYPE_905B 1 5334Srgrimes#define XL_TYPE_90X 2 5344Srgrimes 5354Srgrimes#define XL_FLAG_FORCEDELAY 1 5364Srgrimes#define XL_FLAG_SCHEDDELAY 2 5374Srgrimes#define XL_FLAG_DELAYTIMEO 3 53814887Swollman 5394Srgrimesstruct xl_softc { 5404Srgrimes struct arpcom arpcom; /* interface info */ 5414Srgrimes struct ifmedia ifmedia; /* media info */ 5424Srgrimes bus_space_handle_t xl_bhandle; 5434Srgrimes bus_space_tag_t xl_btag; 5444Srgrimes struct xl_type *xl_info; /* 3Com adapter info */ 5454Srgrimes struct xl_type *xl_pinfo; /* phy info */ 5464Srgrimes u_int8_t xl_unit; /* interface number */ 5474Srgrimes u_int8_t xl_type; 5484Srgrimes u_int8_t xl_phy_addr; /* PHY address */ 54914887Swollman u_int32_t xl_xcvr; 55021277Sbde u_int16_t xl_media; 55121277Sbde u_int16_t xl_caps; 55221277Sbde u_int8_t xl_tx_pend; /* TX pending */ 55321277Sbde u_int8_t xl_want_auto; 55421277Sbde u_int8_t xl_autoneg; 55521277Sbde u_int8_t xl_stats_no_timeout; 55621277Sbde u_int16_t xl_tx_thresh; 55721277Sbde caddr_t xl_ldata_ptr; 5584Srgrimes struct xl_list_data *xl_ldata; 5594Srgrimes struct xl_chain_data xl_cdata; 56014887Swollman struct callout_handle xl_stat_ch; 56121277Sbde}; 56221277Sbde 56321277Sbde#define xl_rx_goodframes(x) \ 56421277Sbde ((x.xl_upper_frames_ok & 0x03) << 8) | x.xl_rx_frames_ok 56517109Sbde 56621277Sbde#define xl_tx_goodframes(x) \ 5674Srgrimes ((x.xl_upper_frames_ok & 0x30) << 4) | x.xl_tx_frames_ok 56821277Sbde 5694Srgrimesstruct xl_stats { 5704Srgrimes u_int8_t xl_carrier_lost; 57117109Sbde u_int8_t xl_sqe_errs; 5724Srgrimes u_int8_t xl_tx_multi_collision; 5734Srgrimes u_int8_t xl_tx_single_collision; 5744Srgrimes u_int8_t xl_tx_late_collision; 5754Srgrimes u_int8_t xl_rx_overrun; 57614887Swollman u_int8_t xl_tx_frames_ok; 5774Srgrimes u_int8_t xl_rx_frames_ok; 5784Srgrimes u_int8_t xl_tx_deferred; 5794Srgrimes u_int8_t xl_upper_frames_ok; 5804Srgrimes u_int16_t xl_rx_bytes_ok; 5814Srgrimes u_int16_t xl_tx_bytes_ok; 5824Srgrimes u_int16_t status; 5834Srgrimes}; 5844Srgrimes 5854Srgrimes/* 5864Srgrimes * register space access macros 58714887Swollman */ 5884Srgrimes#define CSR_WRITE_4(sc, reg, val) \ 5894Srgrimes bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val) 5904Srgrimes#define CSR_WRITE_2(sc, reg, val) \ 5914Srgrimes bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val) 5924Srgrimes#define CSR_WRITE_1(sc, reg, val) \ 5934Srgrimes bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val) 5944Srgrimes 5954Srgrimes#define CSR_READ_4(sc, reg) \ 5964Srgrimes bus_space_read_4(sc->xl_btag, sc->xl_bhandle, reg) 5974Srgrimes#define CSR_READ_2(sc, reg) \ 59814887Swollman bus_space_read_2(sc->xl_btag, sc->xl_bhandle, reg) 5994Srgrimes#define CSR_READ_1(sc, reg) \ 6004Srgrimes bus_space_read_1(sc->xl_btag, sc->xl_bhandle, reg) 6014Srgrimes 6024Srgrimes#define XL_SEL_WIN(x) \ 6034Srgrimes CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x) 6044Srgrimes#define XL_TIMEOUT 1000 6054Srgrimes 6064Srgrimes/* 6074Srgrimes * General constants that are fun to know. 6084Srgrimes * 60917109Sbde * 3Com PCI vendor ID 6104Srgrimes */ 6114Srgrimes#define TC_VENDORID 0x10B7 6124Srgrimes 6134Srgrimes/* 6144Srgrimes * 3Com chip device IDs. 6154Srgrimes */ 6164Srgrimes#define TC_DEVICEID_BOOMERANG_10BT 0x9000 6174Srgrimes#define TC_DEVICEID_BOOMERANG_10BT_COMBO 0x9001 6184Srgrimes#define TC_DEVICEID_BOOMERANG_10_100BT 0x9050 6194Srgrimes#define TC_DEVICEID_BOOMERANG_100BT4 0x9051 62017109Sbde#define TC_DEVICEID_KRAKATOA_10BT 0x9004 6214Srgrimes#define TC_DEVICEID_KRAKATOA_10BT_COMBO 0x9005 6224Srgrimes#define TC_DEVICEID_KRAKATOA_10BT_TPC 0x9006 62321277Sbde#define TC_DEVICEID_CYCLONE_10FL 0x900A 62421277Sbde#define TC_DEVICEID_HURRICANE_10_100BT 0x9055 62521277Sbde#define TC_DEVICEID_CYCLONE_10_100BT4 0x9056 62621277Sbde#define TC_DEVICEID_CYCLONE_10_100_COMBO 0x9058 6274Srgrimes#define TC_DEVICEID_CYCLONE_10_100FX 0x905A 6284Srgrimes#define TC_DEVICEID_TORNADO_10_100BT 0x9200 6294Srgrimes#define TC_DEVICEID_HURRICANE_10_100BT_SERV 0x9800 6304Srgrimes#define TC_DEVICEID_HURRICANE_SOHO100TX 0x7646 63114887Swollman 6324Srgrimes/* 6334Srgrimes * Texas Instruments PHY identifiers 6344Srgrimes * 6354Srgrimes * The ThunderLAN manual has a curious and confusing error in it. 63621277Sbde * In chapter 7, which describes PHYs, it says that TI PHYs have 6374Srgrimes * the following ID codes, where xx denotes a revision: 6384Srgrimes * 6394Srgrimes * 0x4000501xx internal 10baseT PHY 6404Srgrimes * 0x4000502xx TNETE211 100VG-AnyLan PMI 6414Srgrimes * 6424Srgrimes * The problem here is that these are not valid 32-bit hex numbers: 6434Srgrimes * there's one digit too many. My guess is that they mean the internal 6444Srgrimes * 10baseT PHY is 0x4000501x and the TNETE211 is 0x4000502x since these 6454Srgrimes * are the only numbers that make sense. 6464Srgrimes */ 6474Srgrimes#define TI_PHY_VENDORID 0x4000 648238166Sjhb#define TI_PHY_10BT 0x501F 6494Srgrimes#define TI_PHY_100VGPMI 0x502F 6504Srgrimes 6514Srgrimes/* 6524Srgrimes * These ID values are for the NS DP83840A 10/100 PHY 6534Srgrimes */ 65421277Sbde#define NS_PHY_VENDORID 0x2000 6554Srgrimes#define NS_PHY_83840A 0x5C0F 6564Srgrimes 6574Srgrimes/* 6584Srgrimes * Level 1 10/100 PHY 6594Srgrimes */ 6604Srgrimes#define LEVEL1_PHY_VENDORID 0x7810 6614Srgrimes#define LEVEL1_PHY_LXT970 0x000F 6624Srgrimes 66321277Sbde/* 6644Srgrimes * Intel 82555 10/100 PHY 6654Srgrimes */ 6664Srgrimes#define INTEL_PHY_VENDORID 0x0A28 6674Srgrimes#define INTEL_PHY_82555 0x015F 6684Srgrimes 6694Srgrimes/* 6704Srgrimes * SEEQ 80220 10/100 PHY 6714Srgrimes */ 6724Srgrimes#define SEEQ_PHY_VENDORID 0x0016 6734Srgrimes#define SEEQ_PHY_80220 0xF83F 6744Srgrimes 67521277Sbde 6764Srgrimes/* 6774Srgrimes * PCI low memory base and low I/O base register, and 6784Srgrimes * other PCI registers. Note: some are only available on 6794Srgrimes * the 3c905B, in particular those that related to power management. 6804Srgrimes */ 68121277Sbde 6824Srgrimes#define XL_PCI_VENDOR_ID 0x00 6834Srgrimes#define XL_PCI_DEVICE_ID 0x02 6844Srgrimes#define XL_PCI_COMMAND 0x04 6854Srgrimes#define XL_PCI_STATUS 0x06 6864Srgrimes#define XL_PCI_CLASSCODE 0x09 6874Srgrimes#define XL_PCI_LATENCY_TIMER 0x0D 6884Srgrimes#define XL_PCI_HEADER_TYPE 0x0E 6894Srgrimes#define XL_PCI_LOIO 0x10 6904Srgrimes#define XL_PCI_LOMEM 0x14 6914Srgrimes#define XL_PCI_BIOSROM 0x30 6924Srgrimes#define XL_PCI_INTLINE 0x3C 69321277Sbde#define XL_PCI_INTPIN 0x3D 6944Srgrimes#define XL_PCI_MINGNT 0x3E 6954Srgrimes#define XL_PCI_MINLAT 0x0F 6964Srgrimes#define XL_PCI_RESETOPT 0x48 6974Srgrimes#define XL_PCI_EEPROM_DATA 0x4C 6984Srgrimes 69921277Sbde/* 3c905B-only registers */ 7004Srgrimes#define XL_PCI_CAPID 0xDC /* 8 bits */ 7014Srgrimes#define XL_PCI_NEXTPTR 0xDD /* 8 bits */ 7024Srgrimes#define XL_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 7034Srgrimes#define XL_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 704144353Speter 705144353Speter#define XL_PSTATE_MASK 0x0003 706144353Speter#define XL_PSTATE_D0 0x0000 707144353Speter#define XL_PSTATE_D1 0x0002 708144353Speter#define XL_PSTATE_D2 0x0002 709144353Speter#define XL_PSTATE_D3 0x0003 710144353Speter#define XL_PME_EN 0x0010 711144353Speter#define XL_PME_STATUS 0x8000 7124Srgrimes 713144353Speter#define PHY_UNKNOWN 6 714144353Speter 715144353Speter#define XL_PHYADDR_MIN 0x00 716144353Speter#define XL_PHYADDR_MAX 0x1F 717144353Speter 718144353Speter#define XL_PHY_GENCTL 0x00 719144353Speter#define XL_PHY_GENSTS 0x01 720144353Speter#define XL_PHY_VENID 0x02 7214Srgrimes#define XL_PHY_DEVID 0x03 7224Srgrimes#define XL_PHY_ANAR 0x04 7234Srgrimes#define XL_PHY_LPAR 0x05 7244Srgrimes#define XL_PHY_ANEXP 0x06 7254Srgrimes 7264Srgrimes#define PHY_ANAR_NEXTPAGE 0x8000 7274Srgrimes#define PHY_ANAR_RSVD0 0x4000 7284Srgrimes#define PHY_ANAR_TLRFLT 0x2000 7294Srgrimes#define PHY_ANAR_RSVD1 0x1000 7304Srgrimes#define PHY_ANAR_RSVD2 0x0800 7314Srgrimes#define PHY_ANAR_RSVD3 0x0400 7324Srgrimes#define PHY_ANAR_100BT4 0x0200 7334Srgrimes#define PHY_ANAR_100BTXFULL 0x0100 7344Srgrimes#define PHY_ANAR_100BTXHALF 0x0080 7354Srgrimes#define PHY_ANAR_10BTFULL 0x0040 7364Srgrimes#define PHY_ANAR_10BTHALF 0x0020 7374Srgrimes#define PHY_ANAR_PROTO4 0x0010 7384Srgrimes#define PHY_ANAR_PROTO3 0x0008 7394Srgrimes#define PHY_ANAR_PROTO2 0x0004 7404Srgrimes#define PHY_ANAR_PROTO1 0x0002 7414Srgrimes#define PHY_ANAR_PROTO0 0x0001 7424Srgrimes 743144354Speter/* 7444Srgrimes * These are the register definitions for the PHY (physical layer 7454Srgrimes * interface chip). 7464Srgrimes */ 7474Srgrimes/* 7484Srgrimes * PHY BMCR Basic Mode Control Register 7494Srgrimes */ 7504Srgrimes#define PHY_BMCR 0x00 7514Srgrimes#define PHY_BMCR_RESET 0x8000 75221277Sbde#define PHY_BMCR_LOOPBK 0x4000 7534Srgrimes#define PHY_BMCR_SPEEDSEL 0x2000 7544Srgrimes#define PHY_BMCR_AUTONEGENBL 0x1000 7554Srgrimes#define PHY_BMCR_RSVD0 0x0800 /* write as zero */ 7564Srgrimes#define PHY_BMCR_ISOLATE 0x0400 7574Srgrimes#define PHY_BMCR_AUTONEGRSTR 0x0200 7584Srgrimes#define PHY_BMCR_DUPLEX 0x0100 7594Srgrimes#define PHY_BMCR_COLLTEST 0x0080 7604Srgrimes#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */ 7614Srgrimes#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */ 7624Srgrimes#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */ 7634Srgrimes#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */ 7644Srgrimes#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */ 7654Srgrimes#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */ 7664Srgrimes#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */ 7674Srgrimes/* 7684Srgrimes * RESET: 1 == software reset, 0 == normal operation 7694Srgrimes * Resets status and control registers to default values. 7704Srgrimes * Relatches all hardware config values. 7714Srgrimes * 7724Srgrimes * LOOPBK: 1 == loopback operation enabled, 0 == normal operation 7734Srgrimes * 7744Srgrimes * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s 7754Srgrimes * Link speed is selected byt his bit or if auto-negotiation if bit 7764Srgrimes * 12 (AUTONEGENBL) is set (in which case the value of this register 77717109Sbde * is ignored). 77817109Sbde * 77921277Sbde * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled 78017109Sbde * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13 7814Srgrimes * determine speed and mode. Should be cleared and then set if PHY configured 7824Srgrimes * for no autoneg on startup. 7834Srgrimes * 7844Srgrimes * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation 7854Srgrimes * 7864Srgrimes * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation 7874Srgrimes * 7884Srgrimes * DUPLEX: 1 == full duplex mode, 0 == half duplex mode 7894Srgrimes * 7904Srgrimes * COLLTEST: 1 == collision test enabled, 0 == normal operation 7914Srgrimes */ 7924Srgrimes 7934Srgrimes/* 7944Srgrimes * PHY, BMSR Basic Mode Status Register 7954Srgrimes */ 7964Srgrimes#define PHY_BMSR 0x01 7974Srgrimes#define PHY_BMSR_100BT4 0x8000 7984Srgrimes#define PHY_BMSR_100BTXFULL 0x4000 7994Srgrimes#define PHY_BMSR_100BTXHALF 0x2000 8004Srgrimes#define PHY_BMSR_10BTFULL 0x1000 8014Srgrimes#define PHY_BMSR_10BTHALF 0x0800 8024Srgrimes#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */ 8034Srgrimes#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */ 804238166Sjhb#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */ 805238166Sjhb#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ 8064Srgrimes#define PHY_BMSR_MFPRESUP 0x0040 8074Srgrimes#define PHY_BMSR_AUTONEGCOMP 0x0020 8084Srgrimes#define PHY_BMSR_REMFAULT 0x0010 8094Srgrimes#define PHY_BMSR_CANAUTONEG 0x0008 8104Srgrimes#define PHY_BMSR_LINKSTAT 0x0004 8114Srgrimes#define PHY_BMSR_JABBER 0x0002 8124Srgrimes#define PHY_BMSR_EXTENDED 0x0001 8134Srgrimes 8144Srgrimes#ifdef __alpha__ 8154Srgrimes#undef vtophys 8164Srgrimes#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 8174Srgrimes 8184Srgrimes#endif 8194Srgrimes 8204Srgrimes#ifndef IFM_10_FL 8214Srgrimes#define IFM_10_FL 13 /* 10baseFL - Fiber */ 8224Srgrimes#endif 8234Srgrimes