if_xereg.h revision 55723
147133Sobrien/*- 247133Sobrien * Copyright (c) 1998, 1999 Scott Mitchell 347133Sobrien * All rights reserved. 447133Sobrien * 547133Sobrien * Redistribution and use in source and binary forms, with or without 647133Sobrien * modification, are permitted provided that the following conditions 747133Sobrien * are met: 847133Sobrien * 1. Redistributions of source code must retain the above copyright 947133Sobrien * notice, this list of conditions and the following disclaimer. 1047133Sobrien * 2. Redistributions in binary form must reproduce the above copyright 1147133Sobrien * notice, this list of conditions and the following disclaimer in the 1247133Sobrien * documentation and/or other materials provided with the distribution. 1347133Sobrien * 1447133Sobrien * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1547133Sobrien * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1647133Sobrien * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1747133Sobrien * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1847133Sobrien * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1947133Sobrien * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2047133Sobrien * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2147133Sobrien * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2247133Sobrien * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2347133Sobrien * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2447133Sobrien * SUCH DAMAGE. 2547133Sobrien * 2651594Speter * $Id: if_xereg.h,v 1.5 1999/05/20 21:53:58 scott Exp $ 2750477Speter * $FreeBSD: head/sys/dev/xe/if_xereg.h 55723 2000-01-10 08:05:53Z imp $ 2847133Sobrien */ 2955723Simp#ifndef DEV_XE_IF_XEREG_H 3055723Simp#define DEV_XE_IF_XEREG_H 3147133Sobrien 3247133Sobrien/* 3348114Sobrien * Register definitions for Xircom PCMCIA Ethernet controllers, based on 3448114Sobrien * Rev. B of the "Dingo" 10/100 controller used in Xircom CEM56 and RealPort 3548114Sobrien * Ethernet/modem cards. The Dingo can be configured to be register 3648114Sobrien * compatible with the "Mohawk" 10/100 controller used in Xircom CE3 cards 3748114Sobrien * (also some Intel and Compaq OEM versions of the CE3). The older 10Mbps CE2 3848114Sobrien * cards seem to use earlier revisions of the same device. Some registers and 3948114Sobrien * bits below are marked 'CE2 only'; these are used by Werner Koch's xirc2ps 4048114Sobrien * driver that was originally for the CE2 but, according to the spec, aren't 4148114Sobrien * present on the Dingo. They often seem to relate to operation on coax 4248114Sobrien * cables, which Mohawk can do in theory (it has the SSI interface) so they 4348114Sobrien * _might_ also work on Mohawk. I've also noted the few registers that are 4448114Sobrien * specific to Dingo. 4548114Sobrien * 4648114Sobrien * As far as I can tell, the Dingo is basically a Mohawk device with a few 4748114Sobrien * registers and support for a second PCMCIA function (the modem) added. In 4848114Sobrien * Dingo mode the SSI (non-MII) PHY interface of the Mohawk is not available. 4948114Sobrien * The CE2 chip is most likely a Mohawk without the MII and definitely with a 5048114Sobrien * slightly different register set. 5148114Sobrien * 5248114Sobrien * In all cases, the controller uses a paged model of register access. The 5348114Sobrien * first eight registers are always the same, the function of the second eight 5448114Sobrien * is selected by the value in the Page Register (reg 0x01). 5548114Sobrien * 5648114Sobrien * References: 5748114Sobrien * 1. Dingo External Reference Specification, Revision B. Xircom Inc., 5848114Sobrien * Thousand Oaks, California. August 1998. Available under licence from 5948114Sobrien * Xircom, http://www.xircom.com/ 6048114Sobrien * 2. ML6692 100BASE-TX Physical Layer with MII specification. MicroLinear 6148114Sobrien * Corp, San Jose, California. May 1997. Available for download from 6248114Sobrien * http://www.microlinear.com/ 6348114Sobrien * 3. DP83840 10/100 Mb/s Ethernet Physical Layer specification. National 6448114Sobrien * Semiconductor Corp., Arlington, Texas. March 1997. Available for 6548114Sobrien * download from http://www.ns.com/ 6648114Sobrien * 4. Werner Koch's xirc2ps driver for Linux, for all the CE2 and CE3 frobs 6748114Sobrien * that aren't documented in the Xircom spec. Available for download from 6848114Sobrien * http://www.d.shuttle.de/isil/xircom/xirc2ps.html 6947133Sobrien */ 7047133Sobrien 7148114Sobrien/******************* 7248114Sobrien * PCMCIA registers 7348114Sobrien *******************/ 7448114Sobrien 7547133Sobrien/* 7648114Sobrien * These are probably Dingo-specific, but you won't need them unless you have 7748114Sobrien * a CEM card that needs a bit of hackery to get the Ethernet function to 7848114Sobrien * operate. All addresses are in card attribute space. 7947133Sobrien */ 8048114Sobrien#define DINGO_CIS 0x0000 /* Start of CIS tuples */ 8148114Sobrien#define DINGO_ETH 0x0800 /* Ethernet configuration registers */ 8248114Sobrien#define DINGO_COR 0x0820 /* Dingo configuration option registers */ 8348114Sobrien#define DINGO_2ND 0x0840 /* 2nd function configuration registers */ 8447133Sobrien 8548114Sobrien 8647133Sobrien/* 8748114Sobrien * Ethernet configuration registers 8847133Sobrien */ 8948114Sobrien#define DINGO_ECOR (DINGO_ETH+0) /* Ethernet Configuration Option Register */ 9048114Sobrien#define DINGO_ECSR (DINGO_ETH+2) /* Ethernet Configuration Status Register */ 9148114Sobrien#define DINGO_EBAR0 (DINGO_ETH+10) /* Ethernet Base Address Register bits 7:4 (3:0 always 0) */ 9248114Sobrien#define DINGO_EBAR1 (DINGO_ETH+12) /* Ethernet Base Address Register bits 15:8 */ 9347133Sobrien 9448114Sobrien/* DINGO_ECOR bits */ 9548114Sobrien#define DINGO_ECOR_ETH_ENABLE 0x01 /* 1 = Enable Ethernet part of adapter */ 9648114Sobrien#define DINGO_ECOR_IOB_ENABLE 0x02 /* 1 = Enable EBAR, else use INDEX bits */ 9748114Sobrien#define DINGO_ECOR_INT_ENABLE 0x04 /* 1 = Enable Ethernet interrupts */ 9848114Sobrien#define DINGO_ECOR_IOB_INDEX 0x18 /* 00 = 0x300; 01 = 0x310; 10 = 0x320; 11 = no IO base */ 9948114Sobrien#define DINGO_ECOR_IOB_SHIFT 0x03 10048114Sobrien#define DINGO_ECOR_IRQ_STSCHG 0x20 /* 1 = Route interrupts to -STSCHG pin, else use -INT pin */ 10148114Sobrien#define DINGO_ECOR_IRQ_LEVEL 0x40 /* 1 = Level-triggered interrupts, else edge-triggered */ 10248114Sobrien#define DINGO_ECOR_SRESET 0x80 /* 1 = Soft reset Ethernet adpater. Must write to 0 */ 10348114Sobrien 10448114Sobrien/* DINGO_ECSR bits */ 10548114Sobrien#define DINGO_ECSR_INT_ACK 0x01 /* 1 = Host must acknowledge interrupts (Clear ECSR_INT bit) */ 10648114Sobrien#define DINGO_ECSR_INT 0x02 /* 1 = Interrupt service requested */ 10748114Sobrien#define DINGO_ECSR_POWER_DOWN 0x04 /* 1 = Power down Ethernet adapter */ 10848114Sobrien 10947133Sobrien/* 11048114Sobrien * EBAR0/EBAR1 set the I/O base address of the Ethernet adapter when 11148114Sobrien * ECOR_IOB_ENABLE is set. 12 significant bits. 11247133Sobrien */ 11347133Sobrien 11448114Sobrien 11547133Sobrien/* 11648114Sobrien * Dingo configuration registers 11747133Sobrien */ 11848114Sobrien#define DINGO_DCOR0 (DINGO_COR+0) /* Dingo Configuration Options Register 0 */ 11948114Sobrien#define DINGO_DCOR1 (DINGO_COR+2) /* Dingo Configuration Options Register 1 */ 12048114Sobrien#define DINGO_DCOR2 (DINGO_COR+4) /* Dingo Configuration Options Register 2 */ 12148114Sobrien#define DINGO_DCOR3 (DINGO_COR+6) /* Dingo Configuration Options Register 3 */ 12248114Sobrien#define DINGO_DCOR4 (DINGO_COR+8) /* Dingo Configuration Options Register 4 */ 12347133Sobrien 12448114Sobrien/* DINGO_DCOR0 bits */ 12548114Sobrien#define DINGO_DCOR0_SF_INT 0x01 /* 1 = Enable 2ndF interrupts (alternate to SFCOR:2) */ 12648114Sobrien#define DINGO_DCOR0_DECODE 0x04 /* 1 = Decode 2ndF interrupts in Dingo, else in 2ndF */ 12748114Sobrien#define DINGO_DCOR0_BUS 0x08 /* 1 = 2ndF bus is ISA, else PCMCIA */ 12848114Sobrien#define DINGO_DCOR0_LED3_POWER 0x10 /* 1 = Drive LED3 line from SFCSR:2 */ 12948114Sobrien#define DINGO_DCOR0_LED3_RESET 0x20 /* 1 = Drive LED3 line from SFCOR:7 */ 13048114Sobrien#define DINGO_DCOR0_MR_POWER 0x40 /* 1 = Drive MRESET line from SFCSR:2 */ 13148114Sobrien#define DINGO_DCOR0_MR_RESET 0x80 /* 1 = Drive MRESET line from SFCOR:7 */ 13247133Sobrien 13348114Sobrien/* DINGO_DCOR1 bits */ 13448114Sobrien#define DINGO_DCOR1_INT_STSCHG 0x01 /* 1 = Route 2ndF interrupts to -STSCHG (alternate to SFCOR:5) */ 13548114Sobrien#define DINGO_DCOR1_MSTSCHG 0x02 /* 1 = Route 2ndF -MSTSCHG line to -STSCHG */ 13648114Sobrien#define DINGO_DCOR1_EEDIO 0x04 /* 1 = Use EEDIO pin as data line 6 to 2ndF */ 13748114Sobrien#define DINGO_DCOR1_INT_LEVEL 0x08 /* 1 = Force level-triggered interrupts from 2ndF */ 13848114Sobrien#define DINGO_DCOR1_SHADOW_CSR 0x10 /* Reserved, always write 0 */ 13948114Sobrien#define DINGO_DCOR1_SHADOW_IOB 0x20 /* Reserved, always write 0 */ 14048114Sobrien#define DINGO_DCOR1_CSR_WAIT 0xC0 /* Reserved, always write 0 */ 14148114Sobrien#define DINGO_DCOR1_CSR_SHIFT 0x06 14248114Sobrien 14348114Sobrien/* DINGO_DCOR2 bits */ 14448114Sobrien#define DINGO_DCOR2_SHM_BASE 0x0f /* Bits 15-12 of Ethernet shared memory window */ 14548114Sobrien#define DINGO_DCOR2_SHM_SHIFT 0x00 14648114Sobrien#define DINGO_DCOR2_SHADOW_COR 0x10 /* Reserved, always write 0 */ 14748114Sobrien 14847133Sobrien/* 14948114Sobrien * DCOR3/DCOR4 configure Dingo to assert -IOIS16 on any access to each pair of 15048114Sobrien * ports in the range SFIOB+0 .. SFIOB+31. Each pair can be set individually, 15148114Sobrien * eg. DCOR3:0 enables this function on ports SFIOB+0 and SFIOB+1. 15247133Sobrien */ 15347133Sobrien 15448114Sobrien 15547133Sobrien/* 15648114Sobrien * Second function configuration registers 15747133Sobrien */ 15848114Sobrien#define DINGO_SFCOR (DINGO_2ND+0) /* 2nd Function Configuration Option Register */ 15948114Sobrien#define DINGO_SFCSR (DINGO_2ND+2) /* 2nd Function Configuration Status Register */ 16048114Sobrien#define DINGO_SFBAR0 (DINGO_2ND+10) /* 2nd Function Base Address Register bits 7:0 */ 16148114Sobrien#define DINGO_SFBAR1 (DINGO_2ND+12) /* 2nd Function Base Address Register bits 15:8 */ 16248114Sobrien#define DINGO_SFILR (DINGO_2ND+18) /* 2nd Function I/O Limit Register */ 16347133Sobrien 16448114Sobrien/* DINGO_SFCOR bits */ 16548114Sobrien#define DINGO_SFCOR_SF_ENABLE 0x01 /* 1 = Enable second fuction */ 16648114Sobrien#define DINGO_SFCOR_IOB_ENABLE 0x02 /* 1 = Enable SFBAR, else use COM_SELECT bits */ 16748114Sobrien#define DINGO_SFCOR_INT_ENABLE 0x04 /* 1 = Enable second function interrupts */ 16848114Sobrien#define DINGO_SFCOR_COM_SELECT 0x18 /* 00 = 0x3f8; 01 = 0x2f8; 10 = 0x3e8; 11 = 0x2e8 */ 16948114Sobrien#define DINGO_SFCOR_COM_SHIFT 0x03 17048114Sobrien#define DINGO_SFCOR_IRQ_STSCHG 0x20 /* 1 = Route interrupts to -STSCHG pin, else use -INT pin */ 17148114Sobrien#define DINGO_SFCOR_IRQ_LEVEL 0x40 /* 1 = Level-triggered interrupts, else edge-triggered */ 17248114Sobrien#define DINGO_SFCOR_SRESET 0x80 /* 1 = Soft reset second function. Must write to 0 */ 17347133Sobrien 17448114Sobrien/* DINGO_SFCSR bits */ 17548114Sobrien#define DINGO_SFCSR_INT_ACK 0x01 /* 1 = Host must acknowledge interrupts (Clear SFCSR_INT bit) */ 17648114Sobrien#define DINGO_SFCSR_INT 0x02 /* 1 = Interrupt service requested */ 17748114Sobrien#define DINGO_SFCSR_POWER_DOWN 0x04 /* 1 = Power down second function */ 17848114Sobrien 17947133Sobrien/* 18048114Sobrien * SFBAR0/SFBAR1 set the I/O base address of the second function when 18148114Sobrien * SFCOR_IOB_ENABLE is set. 16 significant bits. 18247133Sobrien */ 18347133Sobrien 18447133Sobrien/* 18548114Sobrien * SFILR is a bitmap of address lines 7:0 decoded by the second function 18648114Sobrien * device. Eg. a device with 16 ports should write 0x0f to this register. 18747133Sobrien */ 18847133Sobrien 18947133Sobrien 19048114Sobrien 19148114Sobrien/******************************** 19248114Sobrien * Ethernet controller registers 19348114Sobrien ********************************/ 19448114Sobrien 19547133Sobrien/* 19648114Sobrien * Common registers (available from any register page) 19748114Sobrien * 19848114Sobrien * Note: The EDP is actually 32 bits wide, occupying registers 2-5. In PCMCIA 19948114Sobrien * operation we can only access 16 bits at once, through registers 4 & 5. 20048114Sobrien */ 20148114Sobrien#define XE_CR 0x00 /* Command register (write) */ 20248114Sobrien#define XE_ESR 0x00 /* Ethernet status register (read) */ 20348114Sobrien#define XE_PR 0x01 /* Page select register */ 20448114Sobrien#define XE_EDP 0x04 /* Ethernet data port */ 20548114Sobrien#define XE_ISR 0x06 /* Ethernet interrupt status register (read) */ 20648114Sobrien#define XE_GIR 0x07 /* Global interrupt register (Dingo only) */ 20748114Sobrien 20848114Sobrien/* XE_CR bits */ 20948114Sobrien#define XE_CR_TX_PACKET 0x01 /* Transmit packet */ 21048114Sobrien#define XE_CR_SOFT_RESET 0x02 /* Software reset */ 21148114Sobrien#define XE_CR_ENABLE_INTR 0x04 /* Enable interrupts */ 21248114Sobrien#define XE_CR_FORCE_INTR 0x08 /* Force an interrupt */ 21348114Sobrien#define XE_CR_CLEAR_FIFO 0x10 /* Clear FIFO after transmit overrun */ 21448114Sobrien#define XE_CR_CLEAR_OVERRUN 0x20 /* Clear receive overrun condition */ 21548114Sobrien#define XE_CR_RESTART_TX 0x40 /* Restart TX after 16 collisions or TX underrun */ 21648114Sobrien 21748114Sobrien/* XE_ESR bits */ 21848114Sobrien#define XE_ESR_FULL_PACKET_RX 0x01 /* At least one full packet received */ 21948114Sobrien#define XE_ESR_PART_PACKET_RX 0x02 /* At least 64 bytes of packet received */ 22048114Sobrien#define XE_ESR_REJECT_PACKET 0x04 /* Partial packet rejected */ 22148114Sobrien#define XE_ESR_TX_PENDING 0x08 /* At least one packet waiting to transmit */ 22248114Sobrien#define XE_ESR_BAD_POLARITY 0x10 /* Bad cable polarity? (CE2 only) */ 22348114Sobrien#define XE_ESR_MEDIA_SELECT 0x20 /* SSI(?) media select: 1 = Twisted pair; 0 = AUI */ 22448114Sobrien 22548114Sobrien/* XE_ISR bits */ 22648114Sobrien#define XE_ISR_TX_OVERFLOW 0x01 /* No space in transmit buffer */ 22748114Sobrien#define XE_ISR_TX_PACKET 0x02 /* Packet sent successfully */ 22848114Sobrien#define XE_ISR_MAC_INTR 0x04 /* Some kind of MAC interrupt happened */ 22948114Sobrien#define XE_ISR_RX_EARLY 0x10 /* Incoming packet in early receive mode */ 23048114Sobrien#define XE_ISR_RX_PACKET 0x20 /* Complete packet received successfully */ 23148114Sobrien#define XE_ISR_RX_REJECT 0x40 /* Partial incoming packet rejected by MAC */ 23248114Sobrien#define XE_ISR_FORCE_INTR 0x80 /* Interrupt forced */ 23348114Sobrien 23448114Sobrien/* XE_GIR bits */ 23548114Sobrien#define XE_GIR_ETH_IRQ 0x01 /* Ethernet IRQ pending */ 23648114Sobrien#define XE_GIR_ETH_MASK 0x02 /* 1 = Mask Ethernet interrupts to host */ 23748114Sobrien#define XE_GIR_SF_IRQ 0x04 /* Second function IRQ pending */ 23848114Sobrien#define XE_GIR_SF_MASK 0x08 /* 1 = Mask second function interrupts to host */ 23948114Sobrien 24048114Sobrien 24148114Sobrien/* 24248114Sobrien * Page 0 registers 24348114Sobrien */ 24448114Sobrien#define XE_TSO 0x08 /* Transmit space open (17 bits) */ 24548114Sobrien#define XE_TRS 0x0a /* Transmit reservation size (CE2 only, removed in rev. 1) */ 24648114Sobrien#define XE_DO 0x0c /* Data offset register (13 bits/3 flags, write) */ 24748114Sobrien#define XE_RSR 0x0c /* Receive status register (read) */ 24848114Sobrien#define XE_TPR 0x0d /* Packets transmitted register (read) */ 24948114Sobrien#define XE_RBC 0x0e /* Received byte count (13 bits/3 flags, read) */ 25048114Sobrien 25148114Sobrien/* XE_DO bits */ 25248114Sobrien#define XE_DO_OFFSET 0x1fff /* First byte fetched when CHANGE_OFFSET issued */ 25348114Sobrien#define XE_DO_OFFSET_SHIFT 0x00 25448114Sobrien#define XE_DO_CHANGE_OFFSET 0x2000 /* Flush RX FIFO, start fetching from OFFSET */ 25548114Sobrien#define XE_DO_SHARED_MEM 0x4000 /* Enable shared memory mode */ 25648114Sobrien#define XE_DO_SKIP_RX_PACKET 0x8000 /* Skip to next packet in buffer memory */ 25748114Sobrien 25848114Sobrien/* XE_RSR bits */ 25948114Sobrien#define XE_RSR_PHYS_PACKET 0x01 /* 1 = Physical packet, 0 = Multicast packet */ 26048114Sobrien#define XE_RSR_BCAST_PACKET 0x02 /* Broadcast packet */ 26148114Sobrien#define XE_RSR_LONG_PACKET 0x04 /* Packet >1518 bytes */ 26248114Sobrien#define XE_RSR_ADDR_MATCH 0x08 /* Packet matched one of our node addresses */ 26348114Sobrien#define XE_RSR_ALIGN_ERROR 0x10 /* Bad alignment? (CE2 only) */ 26448114Sobrien#define XE_RSR_CRC_ERROR 0x20 /* Incorrect CRC */ 26548114Sobrien#define XE_RSR_RX_OK 0x80 /* No errors on received packet */ 26648114Sobrien 26748114Sobrien/* XE_RBC bits */ 26848114Sobrien#define XE_RBC_BYTE_COUNT 0x1fff /* Bytes received for current packet */ 26948114Sobrien#define XE_RBC_COUNT_SHIFT 0x00 27048114Sobrien#define XE_RBC_FULL_PACKET_RX 0x2000 /* These mirror bits 2:0 of ESR, if ECR:7 is set */ 27148114Sobrien#define XE_RBC_PART_PACKET_RX 0x4000 27248114Sobrien#define XE_RBC_REJECT_PACKET 0x8000 27348114Sobrien 27448114Sobrien 27548114Sobrien/* 27648114Sobrien * Page 1 registers 27748114Sobrien */ 27848114Sobrien#define XE_IMR0 0x0c /* Interrupt mask register 0 */ 27948114Sobrien#define XE_IMR1 0x0d /* Interrupt mask register 1 (CE2 only) */ 28048114Sobrien#define XE_ECR 0x0e /* Ethernet configuration register */ 28148114Sobrien 28248114Sobrien/* XE_IMR0 bits */ 28348114Sobrien#define XE_IMR0_TX_OVERFLOW 0x01 /* Masks for bits in ISR */ 28448114Sobrien#define XE_IMR0_TX_PACKET 0x02 28548114Sobrien#define XE_IMR0_MAC_INTR 0x04 28648114Sobrien#define XE_IMR0_RX_EARLY 0x10 28748114Sobrien#define XE_IMR0_RX_PACKET 0x20 28848114Sobrien#define XE_IMR0_RX_REJECT 0x40 28948114Sobrien#define XE_IMR0_FORCE_INTR 0x80 29048114Sobrien 29148114Sobrien/* XE_ECR bits */ 29248114Sobrien#define XE_ECR_EARLY_TX 0x01 /* Enable early transmit mode */ 29348114Sobrien#define XE_ECR_EARLY_RX 0x02 /* Enable early receive mode */ 29448114Sobrien#define XE_ECR_FULL_DUPLEX 0x04 /* Enable full-duplex (disable collision detection) */ 29548114Sobrien#define XE_ECR_LONG_TPCABLE 0x08 /* CE2 only */ 29648114Sobrien#define XE_ECR_NO_POL_COL 0x10 /* CE2 only */ 29748114Sobrien#define XE_ECR_NO_LINK_PULSE 0x20 /* Don't check/send link pulses (not 10BT compliant) */ 29848114Sobrien#define XE_ECR_NO_AUTO_TX 0x40 /* CE2 only */ 29948114Sobrien#define XE_ECR_SOFT_COMPAT 0x80 /* Map ESR bits 2:0 to RBC bits 15:13 */ 30048114Sobrien 30148114Sobrien 30248114Sobrien/* 30347133Sobrien * Page 2 registers 30447133Sobrien */ 30548114Sobrien#define XE_RBS 0x08 /* Receive buffer start (16 bits) */ 30648114Sobrien#define XE_LED 0x0a /* LED control register */ 30748114Sobrien#define XE_LED3 0x0b /* LED3 control register */ 30848114Sobrien#define XE_MSR 0x0c /* Misc. setup register (Mohawk specific register?) */ 30948114Sobrien#define XE_GPR2 0x0d /* General purpose register 2 */ 31047133Sobrien 31148114Sobrien/* 31248114Sobrien * LED function selection: 31348114Sobrien * 000 - Disabled 31448114Sobrien * 001 - Collision activity 31548114Sobrien * 010 - !Collision activity 31648114Sobrien * 011 - 10Mbit link detected 31748114Sobrien * 100 - 100Mbit link detected 31848114Sobrien * 101 - 10/100Mbit link detected 31948114Sobrien * 110 - Automatic assertion 32048114Sobrien * 111 - Transmit activity 32148114Sobrien */ 32247133Sobrien 32348114Sobrien/* XE_LED bits */ 32448114Sobrien#define XE_LED_LED0_MASK 0x07 /* LED0 function selection */ 32548114Sobrien#define XE_LED_LED0_SHIFT 0x00 32648114Sobrien#define XE_LED_LED1_MASK 0x38 /* LED1 function selection */ 32748114Sobrien#define XE_LED_LED1_SHIFT 0x03 32848114Sobrien#define XE_LED_LED0_RX 0x40 /* Add receive activity to LED0 */ 32948114Sobrien#define XE_LED_LED1_RX 0x80 /* Add receive activity to LED1 */ 33048114Sobrien 33148114Sobrien/* XE_LED3 bits */ 33248114Sobrien#define XE_LED3_MASK 0x07 /* LED3 function selection */ 33348114Sobrien#define XE_LED3_SHIFT 0x00 33448114Sobrien#define XE_LED3_RX 0x40 /* Add receive activity to LED3 */ 33548114Sobrien 33648114Sobrien/* XE_MSR bits */ 33748114Sobrien#define XE_MSR_128K_SRAM 0x01 /* Select 128K SRAM */ 33848114Sobrien#define XE_MSR_RBS_BIT16 0x02 /* Bit 16 of RBS (only useful with big SRAM) */ 33948114Sobrien#define XE_MSR_MII_SELECT 0x08 /* Select MII instead of SSI interface */ 34048114Sobrien#define XE_MSR_HASH_TABLE 0x20 /* Enable hash table filtering */ 34148114Sobrien 34248114Sobrien/* XE_GPR2 bits */ 34348114Sobrien#define XE_GPR2_GP3_OUT 0x01 /* Value written to GP3 line */ 34448114Sobrien#define XE_GPR2_GP4_OUT 0x02 /* Value written to GP4 line */ 34548114Sobrien#define XE_GPR2_GP3_SELECT 0x04 /* 1 = GP3 is output, 0 = GP3 is input */ 34648114Sobrien#define XE_GPR2_GP4_SELECT 0x08 /* 1 = GP4 is output, 0 = GP3 is input */ 34748114Sobrien#define XE_GPR2_GP3_IN 0x10 /* Value read from GP3 line */ 34848114Sobrien#define XE_GPR2_GP4_IN 0x20 /* Value read from GP4 line */ 34948114Sobrien 35048114Sobrien 35147133Sobrien/* 35248114Sobrien * Page 3 registers 35348114Sobrien */ 35448114Sobrien#define XE_TPT 0x0a /* Transmit packet threshold (13 bits) */ 35548114Sobrien 35648114Sobrien 35748114Sobrien/* 35847133Sobrien * Page 4 registers 35947133Sobrien */ 36048114Sobrien#define XE_GPR0 0x08 /* General purpose register 0 */ 36148114Sobrien#define XE_GPR1 0x09 /* General purpose register 1 */ 36248114Sobrien#define XE_BOV 0x0a /* Bonding version register (read) */ 36348114Sobrien#define XE_EES 0x0b /* EEPROM control register */ 36448114Sobrien#define XE_LMA 0x0c /* Local memory address (CE2 only) */ 36548114Sobrien#define XE_LMD 0x0e /* Local memory data (CE2 only) */ 36647133Sobrien 36748114Sobrien/* XE_GPR0 bits */ 36848114Sobrien#define XE_GPR0_GP1_OUT 0x01 /* Value written to GP1 line */ 36948114Sobrien#define XE_GPR0_GP2_OUT 0x02 /* Value wirtten to GP2 line */ 37048114Sobrien#define XE_GPR0_GP1_SELECT 0x04 /* 1 = GP1 is output, 0 = GP1 is input */ 37148114Sobrien#define XE_GPR0_GP2_SELECT 0x08 /* 1 = GP2 is output, 0 = GP2 is input */ 37248114Sobrien#define XE_GPR0_GP1_IN 0x10 /* Value read from GP1 line */ 37348114Sobrien#define XE_GPR0_GP2_IN 0x20 /* Value read from GP2 line */ 37447133Sobrien 37548114Sobrien/* XE_GPR1 bits */ 37648114Sobrien#define XE_GPR1_POWER_DOWN 0x01 /* Power down analog section (down to 20mA load) */ 37748114Sobrien 37848114Sobrien/* XE_BOV values */ 37948114Sobrien#define XE_BOV_DINGO 0x55 /* Dingo in Dingo mode */ 38048114Sobrien#define XE_BOV_MOHAWK 0x41 /* Original Mohawk */ 38148114Sobrien#define XE_BOV_MOHAWK_REV1 0x45 /* Rev. 1 Mohawk, or Dingo in Mohawk mode */ 38248114Sobrien#define XE_BOV_CEM28 0x11 /* CEM28 */ 38348114Sobrien 38448114Sobrien/* XE_EES bits */ 38548114Sobrien#define XE_EES_SCL_OUTPUT 0x01 /* Value written to SCL line, when MANUAL_ROM set */ 38648114Sobrien#define XE_EES_SDA_OUTPUT 0x02 /* Value written to SDA line, when MANUAL_ROM set */ 38748114Sobrien#define XE_EES_SDA_INPUT 0x04 /* Value read from SDA line */ 38848114Sobrien#define XE_EES_SDA_TRISTATE 0x08 /* 1 = SDA is output, 0 = SDA is input */ 38948114Sobrien#define XE_EES_MANUAL_ROM 0x20 /* Enable manual contro of serial EEPROM */ 39048114Sobrien 39148114Sobrien 39247133Sobrien/* 39348114Sobrien * Page 5 registers (all read only) 39447133Sobrien */ 39548114Sobrien#define XE_CRHA 0x08 /* Current Rx host address (16 bits) */ 39648114Sobrien#define XE_RHSA 0x0a /* Rx host start address (16 bits) */ 39748114Sobrien#define XE_RNSA 0x0c /* Rx network start address (16 bits) */ 39848114Sobrien#define XE_CRNA 0x0e /* Current Rx network address (16 bits) */ 39947133Sobrien 40047133Sobrien 40147133Sobrien/* 40248114Sobrien * Page 6 registers (all read only) 40347133Sobrien */ 40448114Sobrien#define XE_CTHA 0x08 /* Current Tx host address (16 bits) */ 40548114Sobrien#define XE_THSA 0x0a /* Tx host start address (16 bits) */ 40648114Sobrien#define XE_TNSA 0x0c /* Tx network statr address (16 bits) */ 40748114Sobrien#define XE_CTNA 0x0e /* Current Tx network address (16 bits) */ 40847133Sobrien 40948114Sobrien 41047133Sobrien/* 41148114Sobrien * Page 8 registers (all read only) 41247133Sobrien */ 41348114Sobrien#define XE_THBC 0x08 /* Tx host byte count (16 bits) */ 41448114Sobrien#define XE_THPS 0x0a /* Tx host packet size (16 bits) */ 41548114Sobrien#define XE_TNBC 0x0c /* Tx network byte count (16 bits) */ 41648114Sobrien#define XE_TNPS 0x0e /* Tx network packet size (16 bits) */ 41747133Sobrien 41847133Sobrien 41947133Sobrien/* 42048114Sobrien * Page 0x10 registers (all read only) 42147133Sobrien */ 42248114Sobrien#define XE_DINGOID 0x08 /* Dingo ID register (16 bits) (Dingo only) */ 42348114Sobrien#define XE_RevID 0x0a /* Dingo revision ID (16 bits) (Dingo only) */ 42448114Sobrien#define XE_VendorID 0x0c /* Dingo vendor ID (16 bits) (Dingo only) */ 42547133Sobrien 42648114Sobrien/* Values for the above registers */ 42748114Sobrien#define XE_DINGOID_DINGO3 0x444b /* In both Dingo and Mohawk modes */ 42848114Sobrien#define XE_RevID_DINGO3 0x0001 42948114Sobrien#define XE_VendorID_DINGO3 0x0041 43047133Sobrien 43148114Sobrien 43247133Sobrien/* 43348114Sobrien * Page 0x40 registers 43447133Sobrien */ 43548114Sobrien#define XE_CMD0 0x08 /* MAC Command register (write) */ 43648114Sobrien#define XE_RST0 0x09 /* Receive status register */ 43748114Sobrien#define XE_TXST0 0x0b /* Transmit status register 0 */ 43848114Sobrien#define XE_TXST1 0x0c /* Transmit status register 1 */ 43948114Sobrien#define XE_RX0Msk 0x0d /* Receive status mask register */ 44048114Sobrien#define XE_TX0Msk 0x0e /* Transmit status 0 mask register */ 44148114Sobrien#define XE_TX1Msk 0x0f /* Transmit status 1 mask register */ 44247133Sobrien 44348114Sobrien/* CMD0 bits */ 44448114Sobrien#define XE_CMD0_TX 0x01 /* CE2 only */ 44548114Sobrien#define XE_CMD0_RX_ENABLE 0x04 /* Enable receiver */ 44648114Sobrien#define XE_CMD0_RX_DISABLE 0x08 /* Disable receiver */ 44748114Sobrien#define XE_CMD0_ABORT 0x10 /* CE2 only */ 44848114Sobrien#define XE_CMD0_ONLINE 0x20 /* Take MAC online */ 44948114Sobrien#define XE_CMD0_ACK_INTR 0x40 /* CE2 only */ 45048114Sobrien#define XE_CMD0_OFFLINE 0x80 /* Take MAC offline */ 45147133Sobrien 45248114Sobrien/* RST0 bits */ 45348114Sobrien#define XE_RST0_LONG_PACKET 0x02 /* Packet received with >1518 and <8184 bytes */ 45448114Sobrien#define XE_RST0_CRC_ERROR 0x08 /* Packet received with incorrect CRC */ 45548114Sobrien#define XE_RST0_RX_OVERRUN 0x10 /* Receiver overrun, byte(s) dropped */ 45648114Sobrien#define XE_RST0_RX_ENABLE 0x20 /* Receiver enabled */ 45748114Sobrien#define XE_RST0_RX_ABORT 0x40 /* Receive aborted: CRC, FIFO overrun or addr mismatch */ 45848114Sobrien#define XE_RST0_RX_OK 0x80 /* Complete packet received OK */ 45948114Sobrien 46048114Sobrien/* TXST0 bits */ 46148114Sobrien#define XE_TXST0_NO_CARRIER 0x01 /* Lost carrier. Only valid in 10Mbit half-duplex */ 46248114Sobrien#define XE_TXST0_16_COLLISIONS 0x02 /* Packet aborted after 16 collisions */ 46348114Sobrien#define XE_TXST0_TX_UNDERRUN 0x08 /* MAC ran out of data to send */ 46448114Sobrien#define XE_TXST0_LATE_COLLISION 0x10 /* Collision later than 512 bits */ 46548114Sobrien#define XE_TXST0_SQE_FAIL 0x20 /* SQE test failed. */ 46648114Sobrien#define XE_TXST0_TX_ABORT 0x40 /* Transmit aborted: collisions, underrun or overrun */ 46748114Sobrien#define XE_TXST0_TX_OK 0x80 /* Complete packet sent OK */ 46848114Sobrien 46948114Sobrien/* TXST1 bits */ 47048114Sobrien#define XE_TXST1_RETRY_COUNT 0x0f /* Collision counter for current packet */ 47148114Sobrien#define XE_TXST1_LINK_STATUS 0x10 /* Valid link status */ 47248114Sobrien 47348114Sobrien/* RX0Msk bits */ 47448114Sobrien#define XE_RX0M_LONG_PACKET 0x02 /* Masks for bits in RXST0 */ 47548114Sobrien#define XE_RX0M_ALIGN_ERROR 0x04 /* Alignment error (CE2 only) */ 47648114Sobrien#define XE_RX0M_CRC_ERROR 0x08 47748114Sobrien#define XE_RX0M_RX_OVERRUN 0x10 47848114Sobrien#define XE_RX0M_RX_ABORT 0x40 47948114Sobrien#define XE_RX0M_RX_OK 0x80 48048114Sobrien 48148114Sobrien/* TX0Msk bits */ 48248114Sobrien#define XE_TX0M_NO_CARRIER 0x01 /* Masks for bits in TXST0 */ 48348114Sobrien#define XE_TX0M_16_COLLISIONS 0x02 48448114Sobrien#define XE_TX0M_TX_UNDERRUN 0x08 48548114Sobrien#define XE_TX0M_LATE_COLLISION 0x10 48648114Sobrien#define XE_TX0M_SQE_FAIL 0x20 48748114Sobrien#define XE_TX0M_TX_ABORT 0x40 48848114Sobrien#define XE_TX0M_TX_OK 0x80 48948114Sobrien 49048114Sobrien/* TX1Msk bits */ 49148114Sobrien#define XE_TX1M_PKTDEF 0x20 49248114Sobrien 49348114Sobrien 49447133Sobrien/* 49548114Sobrien * Page 0x42 registers 49647133Sobrien */ 49748114Sobrien#define XE_SWC0 0x08 /* Software configuration 0 */ 49848114Sobrien#define XE_SWC1 0x09 /* Software configuration 1 */ 49948114Sobrien#define XE_BOC 0x0a /* Back-off configuration */ 50048114Sobrien#define XE_TCD 0x0b /* Transmit collision deferral */ 50147133Sobrien 50248114Sobrien/* SWC0 bits */ 50348114Sobrien#define XE_SWC0_LOOPBACK_ENABLE 0x01 /* Enable loopback operation */ 50448114Sobrien#define XE_SWC0_LOOPBACK_SOURCE 0x02 /* 1 = Transceiver, 0 = MAC */ 50548114Sobrien#define XE_SWC0_ACCEPT_ERROR 0x04 /* Accept otherwise OK packets with CRC errors */ 50648114Sobrien#define XE_SWC0_ACCEPT_SHORT 0x08 /* Accept otherwise OK packets that are too short */ 50748114Sobrien#define XE_SWC0_NO_CRC_INSERT 0x40 /* Don't add CRC to outgoing packets */ 50847133Sobrien 50948114Sobrien/* SWC1 bits */ 51048114Sobrien#define XE_SWC1_IA_ENABLE 0x01 /* Enable individual address filters */ 51148114Sobrien#define XE_SWC1_ALLMULTI 0x02 /* Accept all multicast packets */ 51248114Sobrien#define XE_SWC1_PROMISCUOUS 0x04 /* Accept all non-multicast packets */ 51348114Sobrien#define XE_SWC1_BCAST_DISABLE 0x08 /* Reject broadcast packets */ 51448114Sobrien#define XE_SWC1_MEDIA_SELECT 0x40 /* AUI media select (Mohawk only) */ 51548114Sobrien#define XE_SWC1_AUTO_MEDIA 0x80 /* Auto media select (Mohawk only) */ 51648114Sobrien 51748114Sobrien 51847133Sobrien/* 51948114Sobrien * Page 0x44 registers (CE2 only) 52047133Sobrien */ 52148114Sobrien#define XE_TDR0 0x08 /* Time domain reflectometry register 0 */ 52248114Sobrien#define XE_TDR1 0x09 /* Time domain reflectometry register 1 */ 52348114Sobrien#define XE_RXC0 0x0a /* Receive byte count low */ 52448114Sobrien#define XE_RXC1 0x0b /* Receive byte count high */ 52547133Sobrien 52647133Sobrien 52747133Sobrien/* 52848114Sobrien * Page 0x45 registers (CE2 only) 52947133Sobrien */ 53048114Sobrien#define XE_REV 0x0f /* Revision (read) */ 53147133Sobrien 53247133Sobrien 53348114Sobrien/* 53448114Sobrien * Page 0x50-0x57: Individual address 0-9 53548114Sobrien * 53648114Sobrien * Used to filter incoming packets by matching against individual node 53748114Sobrien * addresses. If IA matching is enabled (SWC1, bit0) any incoming packet with 53848114Sobrien * a destination matching one of these 10 addresses will be received. IA0 is 53948114Sobrien * always enabled and usually matches the card's unique address. 54048114Sobrien * 54148114Sobrien * Addresses are stored LSB first, ie. IA00 (reg. 8 on page 0x50) contains the 54248114Sobrien * LSB of IA0, and so on. The data is stored contiguously, in that addresses 54348114Sobrien * can be broken across page boundaries. That is: 54448114Sobrien * 54548114Sobrien * Reg: 50/8 50/9 50/a 50/b 50/c 50/d 50/e 50/f 51/8 51/9 ... 57/a 57/b 54648114Sobrien * IA00 IA01 IA02 IA03 IA04 IA05 IA10 IA11 IA12 IA13 ... IA94 IA95 54748114Sobrien */ 54847136Sobrien 54947133Sobrien/* 55048114Sobrien * Page 0x58: Multicast hash table filter 55147136Sobrien * 55248114Sobrien * In case the 10 individual addresses aren't enough, we also have a multicast 55348114Sobrien * hash filter, enabled through MSR:5. The most significant six bits of the 55448114Sobrien * CRC on each incoming packet are reversed and used as an index into the 64 55548114Sobrien * bits of the hash table. If the appropriate bit is set the packet it 55648114Sobrien * received, although higher layers may still need to filter it out. The CRC 55748114Sobrien * calculation is as follows: 55847136Sobrien * 55948114Sobrien * crc = 0xffffffff; 56048114Sobrien * poly = 0x04c11db6; 56148114Sobrien * for (i = 0; i < 6; i++) { 56248114Sobrien * current = mcast_addr[i]; 56348114Sobrien * for (k = 1; k <= 8; k++) { 56448114Sobrien * if (crc & 0x80000000); 56548114Sobrien * crc31 = 0x01; 56648114Sobrien * else 56748114Sobrien * crc31 = 0; 56848114Sobrien * bit = crc31 ^ (current & 0x01); 56948114Sobrien * crc <<= 1; 57048114Sobrien * current >>= 1; 57148114Sobrien * if (bit) 57248114Sobrien * crc = (crc ^ poly)|1 57348114Sobrien * } 57448114Sobrien * } 57547133Sobrien */ 57647136Sobrien 57748114Sobrien 57848114Sobrien 57948114Sobrien/**************** 58048114Sobrien * MII registers 58148114Sobrien ****************/ 58248114Sobrien 58347136Sobrien/* 58448114Sobrien * Basic MII-compliant PHY register definitions. According to the Dingo spec, 58548114Sobrien * PHYs from (at least) MicroLinear, National Semiconductor, ICS, TDK and 58648114Sobrien * Quality Semiconductor have been used. These apparently all come up with 58748114Sobrien * PHY ID 0x00 unless the "interceptor module" on the Dingo 3 is in use. With 58848114Sobrien * the interceptor enabled, the PHY is faked up to look like an ICS unit with 58948114Sobrien * ID 0x16. The interceptor can be enabled/disabled in software. 59048114Sobrien * 59148114Sobrien * The ML6692 (and maybe others) doesn't have a 10Mbps mode -- this is handled 59248114Sobrien * by an internal 10Mbps transceiver that we know nothing about... some cards 59348114Sobrien * seem to work with the MII in 10Mbps mode, so I guess some PHYs must support 59448114Sobrien * it. The question is, how can you figure out which one you have? Just to 59548114Sobrien * add to the fun there are also 10Mbps _only_ Mohawk/Dingo cards. Aaargh! 59647136Sobrien */ 59747136Sobrien 59847136Sobrien/* 59948114Sobrien * Masks for the MII-related bits in GPR2 60048114Sobrien */ 60148114Sobrien#define XE_MII_CLK XE_GPR2_GP3_OUT 60248114Sobrien#define XE_MII_DIR XE_GPR2_GP4_SELECT 60348114Sobrien#define XE_MII_WRD XE_GPR2_GP4_OUT 60448114Sobrien#define XE_MII_RDD XE_GPR2_GP4_IN 60548114Sobrien 60648114Sobrien/* 60748114Sobrien * MII PHY ID register values 60848114Sobrien */ 60948114Sobrien#define PHY_ID_ML6692 0x0000 /* MicroLinear ML6692? Or unknown */ 61048114Sobrien#define PHY_ID_ICS1890 0x0015 /* ICS1890 */ 61148114Sobrien#define PHY_ID_QS6612 0x0181 /* Quality QS6612 */ 61248114Sobrien#define PHY_ID_DP83840 0x2000 /* National DP83840 */ 61348114Sobrien 61448114Sobrien/* 61547136Sobrien * MII command (etc) bit strings. 61647136Sobrien */ 61747133Sobrien#define XE_MII_STARTDELIM 0x01 61847133Sobrien#define XE_MII_READOP 0x02 61947133Sobrien#define XE_MII_WRITEOP 0x01 62047133Sobrien#define XE_MII_TURNAROUND 0x02 62147133Sobrien 62247136Sobrien/* 62347136Sobrien * PHY registers. 62447136Sobrien */ 62547136Sobrien#define PHY_BMCR 0x00 /* Basic Mode Control Register */ 62647136Sobrien#define PHY_BMSR 0x01 /* Basic Mode Status Register */ 62748114Sobrien#define PHY_ID1 0x02 /* PHY ID 1 */ 62848114Sobrien#define PHY_ID2 0x03 /* PHY ID 2 */ 62947136Sobrien#define PHY_ANAR 0x04 /* Auto-Negotiation Advertisment Register */ 63047136Sobrien#define PHY_LPAR 0x05 /* Auto-Negotiation Link Partner Ability Register */ 63147136Sobrien#define PHY_ANER 0x06 /* Auto-Negotiation Expansion Register */ 63247133Sobrien 63348114Sobrien/* BMCR bits */ 63447136Sobrien#define PHY_BMCR_RESET 0x8000 /* Soft reset PHY. Self-clearing */ 63547136Sobrien#define PHY_BMCR_LOOPBK 0x4000 /* Enable loopback */ 63647136Sobrien#define PHY_BMCR_SPEEDSEL 0x2000 /* 1=100Mbps, 0=10Mbps */ 63747136Sobrien#define PHY_BMCR_AUTONEGENBL 0x1000 /* Auto-negotiation enabled */ 63847136Sobrien#define PHY_BMCR_ISOLATE 0x0400 /* Isolate ML6692 from MII */ 63947136Sobrien#define PHY_BMCR_AUTONEGRSTR 0x0200 /* Restart auto-negotiation. Self-clearing */ 64047136Sobrien#define PHY_BMCR_DUPLEX 0x0100 /* Full duplex operation */ 64147136Sobrien#define PHY_BMCR_COLLTEST 0x0080 /* Enable collision test */ 64247133Sobrien 64348114Sobrien/* BMSR bits */ 64447136Sobrien#define PHY_BMSR_100BT4 0x8000 /* 100Base-T4 capable */ 64547136Sobrien#define PHY_BMSR_100BTXFULL 0x4000 /* 100Base-TX full duplex capable */ 64647136Sobrien#define PHY_BMSR_100BTXHALF 0x2000 /* 100Base-TX half duplex capable */ 64747136Sobrien#define PHY_BMSR_10BTFULL 0x1000 /* 10Base-T full duplex capable */ 64847136Sobrien#define PHY_BMSR_10BTHALF 0x0800 /* 10Base-T half duplex capable */ 64947136Sobrien#define PHY_BMSR_AUTONEGCOMP 0x0020 /* Auto-negotiation complete */ 65047136Sobrien#define PHY_BMSR_CANAUTONEG 0x0008 /* Auto-negotiation supported */ 65147136Sobrien#define PHY_BMSR_LINKSTAT 0x0004 /* Link is up */ 65247136Sobrien#define PHY_BMSR_EXTENDED 0x0001 /* Extended register capabilities */ 65347136Sobrien 65448114Sobrien/* ANAR bits */ 65547136Sobrien#define PHY_ANAR_NEXTPAGE 0x8000 /* Additional link code word pages */ 65647136Sobrien#define PHY_ANAR_TLRFLT 0x2000 /* Remote wire fault detected */ 65747136Sobrien#define PHY_ANAR_100BT4 0x0200 /* 100Base-T4 capable */ 65847136Sobrien#define PHY_ANAR_100BTXFULL 0x0100 /* 100Base-TX full duplex capable */ 65947136Sobrien#define PHY_ANAR_100BTXHALF 0x0080 /* 100Base-TX half duplex capable */ 66047136Sobrien#define PHY_ANAR_10BTFULL 0x0040 /* 10Base-T full duplex capable */ 66147136Sobrien#define PHY_ANAR_10BTHALF 0x0020 /* 10Base-T half duplex capable */ 66247136Sobrien#define PHY_ANAR_PROTO4 0x0010 /* Protocol selection (00001 = 802.3) */ 66347133Sobrien#define PHY_ANAR_PROTO3 0x0008 66447133Sobrien#define PHY_ANAR_PROTO2 0x0004 66547133Sobrien#define PHY_ANAR_PROTO1 0x0002 66647133Sobrien#define PHY_ANAR_PROTO0 0x0001 66748114Sobrien#define PHY_ANAR_8023 PHY_ANAR_PROTO0 66848114Sobrien#define PHY_ANAR_DINGO PHY_ANAR_100BT+PHY_ANAR_10BT_FD+PHY_ANAR_10BT+PHY_ANAR_8023 66948114Sobrien#define PHY_ANAR_MOHAWK PHY_ANAR_100BT+PHY_ANAR_10BT_FD+PHY_ANAR_10BT+PHY_ANAR_8023 67047133Sobrien 67148114Sobrien/* LPAR bits */ 67247136Sobrien#define PHY_LPAR_NEXTPAGE 0x8000 /* Additional link code word pages */ 67347136Sobrien#define PHY_LPAR_LPACK 0x4000 /* Link partner acknowledged receipt */ 67447136Sobrien#define PHY_LPAR_TLRFLT 0x2000 /* Remote wire fault detected */ 67547136Sobrien#define PHY_LPAR_100BT4 0x0200 /* 100Base-T4 capable */ 67647136Sobrien#define PHY_LPAR_100BTXFULL 0x0100 /* 100Base-TX full duplex capable */ 67747136Sobrien#define PHY_LPAR_100BTXHALF 0x0080 /* 100Base-TX half duplex capable */ 67847136Sobrien#define PHY_LPAR_10BTFULL 0x0040 /* 10Base-T full duplex capable */ 67947136Sobrien#define PHY_LPAR_10BTHALF 0x0020 /* 10Base-T half duplex capable */ 68047136Sobrien#define PHY_LPAR_PROTO4 0x0010 /* Protocol selection (00001 = 802.3) */ 68147136Sobrien#define PHY_LPAR_PROTO3 0x0008 68247136Sobrien#define PHY_LPAR_PROTO2 0x0004 68347136Sobrien#define PHY_LPAR_PROTO1 0x0002 68447136Sobrien#define PHY_LPAR_PROTO0 0x0001 68547133Sobrien 68648114Sobrien/* ANER bits */ 68747136Sobrien#define PHY_ANER_MLFAULT 0x0010 /* More than one link is up! */ 68847136Sobrien#define PHY_ANER_LPNPABLE 0x0008 /* Link partner supports next page */ 68947136Sobrien#define PHY_ANER_NPABLE 0x0004 /* Local port supports next page */ 69047136Sobrien#define PHY_ANER_PAGERX 0x0002 /* Page received */ 69147136Sobrien#define PHY_ANER_LPAUTONEG 0x0001 /* Link partner can auto-negotiate */ 69247133Sobrien 69355723Simp#endif /* DEV_XE_IF_XEREG_H */ 694