if_xereg.h revision 47136
199461Sobrien/*- 2218822Sdim * Copyright (c) 1998, 1999 Scott Mitchell 3218822Sdim * All rights reserved. 499461Sobrien * 599461Sobrien * Redistribution and use in source and binary forms, with or without 699461Sobrien * modification, are permitted provided that the following conditions 799461Sobrien * are met: 899461Sobrien * 1. Redistributions of source code must retain the above copyright 999461Sobrien * notice, this list of conditions and the following disclaimer. 1099461Sobrien * 2. Redistributions in binary form must reproduce the above copyright 1199461Sobrien * notice, this list of conditions and the following disclaimer in the 1299461Sobrien * documentation and/or other materials provided with the distribution. 1399461Sobrien * 1499461Sobrien * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1599461Sobrien * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1699461Sobrien * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1799461Sobrien * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1899461Sobrien * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1999461Sobrien * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20218822Sdim * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21218822Sdim * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2299461Sobrien * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23218822Sdim * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2499461Sobrien * SUCH DAMAGE. 2599461Sobrien * 2699461Sobrien * $Id: if_xereg.h,v 1.3 1999/02/22 14:00:53 root Exp $ 2799461Sobrien */ 2899461Sobrien 2999461Sobrien/* 3099461Sobrien * Register definitions for Xircom CreditCard Ethernet adapters. See if_xe.c 3199461Sobrien * for details of supported hardware. Adapted from Werner Koch's 'xirc2ps' 3299461Sobrien * driver for Linux and the FreeBSD 'xl' driver (for the MII support). 33130561Sobrien */ 3499461Sobrien 3599461Sobrien#include "xe.h" 3699461Sobrien#if NXE > 0 3799461Sobrien 3899461Sobrien 39130561Sobrien/* 4099461Sobrien * Common registers 41130561Sobrien */ 4299461Sobrien#define XE_CR 0 /* Command register (write) */ 4399461Sobrien#define XE_ESR 0 /* Ethernet status register (read) */ 44218822Sdim#define XE_PSR 1 /* Page select register */ 45107492Sobrien#define XE_EDP 4 /* Ethernet data port */ 46130561Sobrien#define XE_ISR 6 /* Interrupt status register */ 4799461Sobrien 4899461Sobrien/* 49130561Sobrien * Command register values 50130561Sobrien */ 51130561Sobrien#define XE_CR_TX_PACKET 0x01 52130561Sobrien#define XE_CR_SOFT_RESET 0x02 5399461Sobrien#define XE_CR_ENABLE_INTR 0x04 54130561Sobrien#define XE_CR_FORCE_INTR 0x08 5599461Sobrien#define XE_CR_CLEAR_FIFO 0x10 56130561Sobrien#define XE_CR_CLEAR_OVERRUN 0x20 5799461Sobrien#define XE_CR_RESTART_TX 0x40 58130561Sobrien 5999461Sobrien/* 60130561Sobrien * Status register values 6199461Sobrien */ 6299461Sobrien#define XE_ESR_FULL_PKT_RX 0x01 63130561Sobrien#define XE_ESR_PKT_REJECT 0x04 6499461Sobrien#define XE_ESR_TX_PENDING 0x08 6599461Sobrien#define XE_ESR_BAD_POLARITY 0x10 6699461Sobrien#define XE_ESR_MEDIA_SELECT 0x20 6799461Sobrien 68130561Sobrien/* 6999461Sobrien * Interrupt register values 70130561Sobrien */ 71130561Sobrien#define XE_ISR_TX_OVERFLOW 0x01 72130561Sobrien#define XE_ISR_TX_PACKET 0x02 73130561Sobrien#define XE_ISR_MAC_INTR 0x04 74130561Sobrien#define XE_ISR_TX_RES 0x08 75130561Sobrien#define XE_ISR_RX_PACKET 0x20 76130561Sobrien#define XE_ISR_RX_REJECT 0x40 77130561Sobrien#define XE_ISR_FORCE_INTR 0x80 78130561Sobrien 79130561Sobrien 80130561Sobrien/* 81130561Sobrien * Page 0 registers 82130561Sobrien */ 83130561Sobrien#define XE_TSO 8 /* Transmit space open */ 84130561Sobrien#define XE_TRS 10 /* Transmit reservation size */ 85130561Sobrien#define XE_DOR 12 /* Data offset register (write) */ 8699461Sobrien#define XE_RSR 12 /* Receive status register (read) */ 8799461Sobrien#define XE_PTR 13 /* Packets transmitted register (read) */ 8899461Sobrien#define XE_RBC 14 /* Received byte count (read) */ 8999461Sobrien 9099461Sobrien/* 9199461Sobrien * RSR values 9299461Sobrien */ 9399461Sobrien#define XE_RSR_PHYS_PKT 0x01 9499461Sobrien#define XE_RSR_BCAST_PKT 0x02 9599461Sobrien#define XE_RSR_LONG_PKT 0x04 9699461Sobrien#define XE_RSR_ALIGN_ERR 0x10 97130561Sobrien#define XE_RSR_CRC_ERR 0x20 9899461Sobrien#define XE_RSR_RX_OK 0x80 9999461Sobrien 10099461Sobrien 10199461Sobrien/* 102130561Sobrien * Page 1 registers 10399461Sobrien */ 10499461Sobrien#define XE_IMR0 12 /* Interrupt mask register, part 1 */ 105130561Sobrien#define XE_IMR1 13 /* Interrupt mask register, part 2 */ 10699461Sobrien#define XE_ECR 14 /* Ethernet configuration register */ 107130561Sobrien 108130561Sobrien/* 109130561Sobrien * ECR values 110130561Sobrien */ 111130561Sobrien#define XE_ECR_FULL_DUPLEX 0x04 112130561Sobrien#define XE_ECR_LONG_TPCABLE 0x08 113130561Sobrien#define XE_ECR_NO_POLCOL 0x10 114130561Sobrien#define XE_ECR_NO_LINKPULSE 0x20 115130561Sobrien#define XE_ECR_NO_AUTOTX 0x40 116130561Sobrien 117130561Sobrien 118130561Sobrien/* 119130561Sobrien * Page 2 registers 120130561Sobrien */ 121130561Sobrien#define XE_RBS 8 /* Receive buffer start */ 122130561Sobrien#define XE_LED 10 /* LED configuration register */ 123130561Sobrien#define XE_MSR 12 /* Mohawk specfic register (Mohawk = CE3) */ 124130561Sobrien#define XE_GPR2 13 /* General purpose register 2 */ 125130561Sobrien 126130561Sobrien 127130561Sobrien/* 128130561Sobrien * Page 4 registers 129130561Sobrien */ 130130561Sobrien#define XE_GPR0 8 /* General purpose register 0 */ 131130561Sobrien#define XE_GPR1 9 /* General purpose register 1 */ 132130561Sobrien#define XE_BOV 10 /* Bonding version register */ 133130561Sobrien#define XE_LMA 12 /* Local memory address */ 134130561Sobrien#define XE_LMD 14 /* Local memory data */ 135130561Sobrien 136130561Sobrien 137130561Sobrien/* 138130561Sobrien * Page 5 registers 139130561Sobrien */ 140130561Sobrien#define XE_RHS 10 /* Receive host start address */ 141130561Sobrien 142130561Sobrien 143130561Sobrien/* 144130561Sobrien * Page 0x40 registers 145130561Sobrien */ 146130561Sobrien#define XE_OCR 8 /* The Other command register */ 147130561Sobrien#define XE_RXS0 9 /* Receive status 0 */ 148130561Sobrien#define XE_TXS0 11 /* Transmit status 0 */ 149130561Sobrien#define XE_TXS1 12 /* Transmit status 1 */ 150130561Sobrien#define XE_RXM0 13 /* Receive mask register 0 */ 151130561Sobrien#define XE_TXM0 14 /* Transmit mask register 0 */ 152130561Sobrien#define XE_TXM1 15 /* Transmit mask register 1 */ 153130561Sobrien 154130561Sobrien/* 155130561Sobrien * OCR values 156130561Sobrien */ 157130561Sobrien#define XE_OCR_TX 0x01 158130561Sobrien#define XE_OCR_RX_ENABLE 0x04 159130561Sobrien#define XE_OCR_RX_DISABLE 0x08 160130561Sobrien#define XE_OCR_ABORT 0x10 161130561Sobrien#define XE_OCR_ONLINE 0x20 162130561Sobrien#define XE_OCR_ACK_INTR 0x40 163130561Sobrien#define XE_OCR_OFFLINE 0x80 164130561Sobrien 165130561Sobrien 166130561Sobrien/* 167130561Sobrien * Page 0x42 registers 168130561Sobrien */ 169130561Sobrien#define XE_SWC0 8 /* Software configuration register 0 */ 170130561Sobrien#define XE_SWC1 9 /* Software configuration register 1 */ 171130561Sobrien#define XE_BOC 10 /* Back-off configuration */ 172130561Sobrien 173130561Sobrien 174130561Sobrien/* 175130561Sobrien * Page 0x44 registers 176130561Sobrien */ 177130561Sobrien#define XE_TDR0 8 /* Time domain reflectometry register 0 */ 178130561Sobrien#define XE_TDR1 9 /* Time domain reflectometry register 1 */ 179130561Sobrien#define XE_RXC0 10 /* Receive byte count low */ 180130561Sobrien#define XE_RXC1 11 /* Receive byte count high */ 181130561Sobrien 182130561Sobrien 183130561Sobrien/* 184130561Sobrien * Page 0x45 registers 185130561Sobrien */ 186130561Sobrien#define XE_REV 15 /* Revision (read) */ 187130561Sobrien 188130561Sobrien 189130561Sobrien/* 190130561Sobrien * Page 0x50 registers 191130561Sobrien */ 192130561Sobrien#define XE_IAR 8 /* Individual address register */ 193130561Sobrien 194130561Sobrien 195130561Sobrien/* 196130561Sobrien * Pages 0x43, 0x46-0x4f and 0x51-0x5e apparently don't exist. 197130561Sobrien * The remainder of 0x0-0x8 and 0x40-0x5f exist, but I have no 198130561Sobrien * idea what's on most of them. 199130561Sobrien */ 200130561Sobrien 201130561Sobrien 202130561Sobrien 203130561Sobrien/* 204130561Sobrien * Definitions for the Micro Linear ML6692 100Base-TX PHY, which handles the 205130561Sobrien * 100Mbit functionality of CE3 type cards, including media autonegotiation. 206130561Sobrien * It appears to be mostly compatible with the National Semiconductor 207130561Sobrien * DP83840A, but with a much smaller register set. Please refer to the data 208130561Sobrien * sheets for these devices for the definitive word on what all this stuff 209130561Sobrien * means :) 210130561Sobrien * 211130561Sobrien * Note that the ML6692 has no 10Mbit capability -- that is handled by another 212130561Sobrien * chip that we don't know anything about. 213130561Sobrien * 21499461Sobrien * Most of these definitions were adapted from the xl driver. 21599461Sobrien */ 21699461Sobrien 21799461Sobrien/* 218130561Sobrien * Masks for the MII-related bits in GPR2. For some reason read and write 21999461Sobrien * data are on separate bits. 220130561Sobrien */ 22199461Sobrien#define XE_MII_CLK 0x01 22299461Sobrien#define XE_MII_DIR 0x08 22399461Sobrien#define XE_MII_WRD 0x02 22499461Sobrien#define XE_MII_RDD 0x20 22599461Sobrien 22699461Sobrien/* 22799461Sobrien * MII command (etc) bit strings. 22899461Sobrien */ 22999461Sobrien#define XE_MII_STARTDELIM 0x01 23099461Sobrien#define XE_MII_READOP 0x02 23199461Sobrien#define XE_MII_WRITEOP 0x01 23299461Sobrien#define XE_MII_TURNAROUND 0x02 23399461Sobrien 23499461Sobrien/* 23599461Sobrien * PHY registers. 23699461Sobrien */ 23799461Sobrien#define PHY_BMCR 0x00 /* Basic Mode Control Register */ 23899461Sobrien#define PHY_BMSR 0x01 /* Basic Mode Status Register */ 23999461Sobrien#define PHY_ANAR 0x04 /* Auto-Negotiation Advertisment Register */ 24099461Sobrien#define PHY_LPAR 0x05 /* Auto-Negotiation Link Partner Ability Register */ 24199461Sobrien#define PHY_ANER 0x06 /* Auto-Negotiation Expansion Register */ 24299461Sobrien 24399461Sobrien#define PHY_BMCR_RESET 0x8000 /* Soft reset PHY. Self-clearing */ 24499461Sobrien#define PHY_BMCR_LOOPBK 0x4000 /* Enable loopback */ 24599461Sobrien#define PHY_BMCR_SPEEDSEL 0x2000 /* 1=100Mbps, 0=10Mbps */ 24699461Sobrien#define PHY_BMCR_AUTONEGENBL 0x1000 /* Auto-negotiation enabled */ 24799461Sobrien#define PHY_BMCR_ISOLATE 0x0400 /* Isolate ML6692 from MII */ 24899461Sobrien#define PHY_BMCR_AUTONEGRSTR 0x0200 /* Restart auto-negotiation. Self-clearing */ 24999461Sobrien#define PHY_BMCR_DUPLEX 0x0100 /* Full duplex operation */ 25099461Sobrien#define PHY_BMCR_COLLTEST 0x0080 /* Enable collision test */ 25199461Sobrien 25299461Sobrien#define PHY_BMSR_100BT4 0x8000 /* 100Base-T4 capable */ 25399461Sobrien#define PHY_BMSR_100BTXFULL 0x4000 /* 100Base-TX full duplex capable */ 25499461Sobrien#define PHY_BMSR_100BTXHALF 0x2000 /* 100Base-TX half duplex capable */ 25599461Sobrien#define PHY_BMSR_10BTFULL 0x1000 /* 10Base-T full duplex capable */ 25699461Sobrien#define PHY_BMSR_10BTHALF 0x0800 /* 10Base-T half duplex capable */ 25799461Sobrien#define PHY_BMSR_AUTONEGCOMP 0x0020 /* Auto-negotiation complete */ 258130561Sobrien#define PHY_BMSR_CANAUTONEG 0x0008 /* Auto-negotiation supported */ 25999461Sobrien#define PHY_BMSR_LINKSTAT 0x0004 /* Link is up */ 26099461Sobrien#define PHY_BMSR_EXTENDED 0x0001 /* Extended register capabilities */ 26199461Sobrien 26299461Sobrien#define PHY_ANAR_NEXTPAGE 0x8000 /* Additional link code word pages */ 26399461Sobrien#define PHY_ANAR_TLRFLT 0x2000 /* Remote wire fault detected */ 26499461Sobrien#define PHY_ANAR_100BT4 0x0200 /* 100Base-T4 capable */ 26599461Sobrien#define PHY_ANAR_100BTXFULL 0x0100 /* 100Base-TX full duplex capable */ 26699461Sobrien#define PHY_ANAR_100BTXHALF 0x0080 /* 100Base-TX half duplex capable */ 26799461Sobrien#define PHY_ANAR_10BTFULL 0x0040 /* 10Base-T full duplex capable */ 26899461Sobrien#define PHY_ANAR_10BTHALF 0x0020 /* 10Base-T half duplex capable */ 26999461Sobrien#define PHY_ANAR_PROTO4 0x0010 /* Protocol selection (00001 = 802.3) */ 27099461Sobrien#define PHY_ANAR_PROTO3 0x0008 27199461Sobrien#define PHY_ANAR_PROTO2 0x0004 27299461Sobrien#define PHY_ANAR_PROTO1 0x0002 27399461Sobrien#define PHY_ANAR_PROTO0 0x0001 27499461Sobrien 27599461Sobrien#define PHY_LPAR_NEXTPAGE 0x8000 /* Additional link code word pages */ 27699461Sobrien#define PHY_LPAR_LPACK 0x4000 /* Link partner acknowledged receipt */ 277130561Sobrien#define PHY_LPAR_TLRFLT 0x2000 /* Remote wire fault detected */ 278130561Sobrien#define PHY_LPAR_100BT4 0x0200 /* 100Base-T4 capable */ 279130561Sobrien#define PHY_LPAR_100BTXFULL 0x0100 /* 100Base-TX full duplex capable */ 280130561Sobrien#define PHY_LPAR_100BTXHALF 0x0080 /* 100Base-TX half duplex capable */ 281130561Sobrien#define PHY_LPAR_10BTFULL 0x0040 /* 10Base-T full duplex capable */ 282130561Sobrien#define PHY_LPAR_10BTHALF 0x0020 /* 10Base-T half duplex capable */ 283130561Sobrien#define PHY_LPAR_PROTO4 0x0010 /* Protocol selection (00001 = 802.3) */ 284130561Sobrien#define PHY_LPAR_PROTO3 0x0008 285130561Sobrien#define PHY_LPAR_PROTO2 0x0004 286130561Sobrien#define PHY_LPAR_PROTO1 0x0002 287130561Sobrien#define PHY_LPAR_PROTO0 0x0001 288130561Sobrien 289130561Sobrien#define PHY_ANER_MLFAULT 0x0010 /* More than one link is up! */ 290130561Sobrien#define PHY_ANER_LPNPABLE 0x0008 /* Link partner supports next page */ 291130561Sobrien#define PHY_ANER_NPABLE 0x0004 /* Local port supports next page */ 292130561Sobrien#define PHY_ANER_PAGERX 0x0002 /* Page received */ 293130561Sobrien#define PHY_ANER_LPAUTONEG 0x0001 /* Link partner can auto-negotiate */ 294130561Sobrien 295130561Sobrien 296130561Sobrien#endif /* NXE > 0 */ 297130561Sobrien