1221167Sgnn/*- 2221167Sgnn * Copyright(c) 2002-2011 Exar Corp. 3221167Sgnn * All rights reserved. 4221167Sgnn * 5221167Sgnn * Redistribution and use in source and binary forms, with or without 6221167Sgnn * modification are permitted provided the following conditions are met: 7221167Sgnn * 8221167Sgnn * 1. Redistributions of source code must retain the above copyright notice, 9221167Sgnn * this list of conditions and the following disclaimer. 10221167Sgnn * 11221167Sgnn * 2. Redistributions in binary form must reproduce the above copyright 12221167Sgnn * notice, this list of conditions and the following disclaimer in the 13221167Sgnn * documentation and/or other materials provided with the distribution. 14221167Sgnn * 15221167Sgnn * 3. Neither the name of the Exar Corporation nor the names of its 16221167Sgnn * contributors may be used to endorse or promote products derived from 17221167Sgnn * this software without specific prior written permission. 18221167Sgnn * 19221167Sgnn * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20221167Sgnn * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21221167Sgnn * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22221167Sgnn * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23221167Sgnn * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24221167Sgnn * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25221167Sgnn * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26221167Sgnn * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27221167Sgnn * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28221167Sgnn * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29221167Sgnn * POSSIBILITY OF SUCH DAMAGE. 30221167Sgnn */ 31221167Sgnn/*$FreeBSD: releng/11.0/sys/dev/vxge/include/vxgehal-config.h 226436 2011-10-16 14:30:28Z eadler $*/ 32221167Sgnn 33221167Sgnn#ifndef VXGE_HAL_CONFIG_H 34221167Sgnn#define VXGE_HAL_CONFIG_H 35221167Sgnn 36221167Sgnn__EXTERN_BEGIN_DECLS 37221167Sgnn 38221167Sgnn#define VXGE_HAL_USE_FLASH_DEFAULT VXGE_HAL_DEFAULT_32 39221167Sgnn 40221167Sgnn#define VXGE_HAL_MAX_INTR_PER_VP 4 41221167Sgnn 42221167Sgnn#define VXGE_HAL_VPATH_MSIX_MAX 4 43221167Sgnn 44221167Sgnn#define VXGE_HAL_VPATH_INTR_TX 0 45221167Sgnn 46221167Sgnn#define VXGE_HAL_VPATH_INTR_RX 1 47221167Sgnn 48221167Sgnn#define VXGE_HAL_VPATH_INTR_EINTA 2 49221167Sgnn 50221167Sgnn#define VXGE_HAL_VPATH_INTR_BMAP 3 51221167Sgnn 52221167Sgnn#define WAIT_FACTOR 1 53221167Sgnn/* 54221167Sgnn * struct vxge_hal_driver_config_t - HAL driver object configuration. 55221167Sgnn * 56221167Sgnn * @level: Debug Level. See vxge_debug_level_e {} 57221167Sgnn * 58221167Sgnn * Currently this structure contains just a few basic values. 59221167Sgnn */ 60221167Sgnntypedef struct vxge_hal_driver_config_t { 61221167Sgnn vxge_debug_level_e level; 62221167Sgnn} vxge_hal_driver_config_t; 63221167Sgnn 64221167Sgnn/* 65221167Sgnn * struct vxge_hal_wire_port_config_t - Wire Port configuration (Physical ports) 66221167Sgnn * @port_id: Port number 67221167Sgnn * @media: Transponder type. 68221167Sgnn * @mtu: mtu size used on this port. 69221167Sgnn * @autoneg_mode: The device supports several mechanisms to auto-negotiate the 70221167Sgnn * port data rate. The Fixed mode essentially means no 71221167Sgnn * auto-negotiation and the data rate is determined by the RATE 72221167Sgnn * field of this register. The MDIO-based mode determines the data 73221167Sgnn * rate by reading MDIO registers in the external PHY chip. The 74221167Sgnn * Backplane Ethernet mode using parallel detect and/or 75221167Sgnn * DME-signaled exchange of page information with the PHY chip in 76221167Sgnn * order to figure out the proper rate. 77221167Sgnn * 00 - Fixed 78221167Sgnn * 01 - MDIO-based 79221167Sgnn * 10 - Backplane Ethernet 80221167Sgnn * 11 - Reserved 81221167Sgnn * @autoneg_rate: When MODE is set to Fixed, then this field determines the data 82221167Sgnn * rate of the port. 83221167Sgnn * 0 - 1G 84221167Sgnn * 1 - 10G 85221167Sgnn * @fixed_use_fsm: When MODE is set to Fixed, then this field determines whether 86221167Sgnn * a processor (i.e. F/W or host driver) or hardware-based state 87221167Sgnn * machine is used to run the auto-negotiation. 88221167Sgnn * 0 - Use processor. Either on-chip F/W or host-based driver used. 89221167Sgnn * 1 - Use H/W state machine 90221167Sgnn * @antp_use_fsm: When MODE is set to ANTP (Auto-Negotiation for Twisted Pair), 91221167Sgnn * this field determines whether a processor (F/W or host driver) 92221167Sgnn * or hardware-based state machine is used to talk to the PHY chip 93221167Sgnn * via the MDIO interface. 94221167Sgnn * 0 - Use processor. Either on-chip F/W or host-based driver used. 95221167Sgnn * 1 - Use H/W state machine 96221167Sgnn * @anbe_use_fsm: When MODE is set to ANBE-based, then this field determines 97221167Sgnn * whether a processor (i.e. F/W or host driver) or hardware-based 98221167Sgnn * state machine is used to talk to the Backplane Ethernet logic 99221167Sgnn * inside the device 100221167Sgnn * 0 - Use processor. Either on-chip F/W or host-based driver used. 101221167Sgnn * 1 - Use H/W state machine 102221167Sgnn * @link_stability_period: Timeout for the link stability 103221167Sgnn * @port_stability_period: Timeout for the port stability 104221167Sgnn * @tmac_en: TMAC enable. 0 - Disable; 1 - Enable 105221167Sgnn * @rmac_en: RMAC enable. 0 - Disable; 1 - Enable 106221167Sgnn * @tmac_pad: Determines whether padding is appended to transmitted frames. 107221167Sgnn * 0 - No padding appended 108221167Sgnn * 1 - Pad to 64 bytes (not including preamble/SFD) 109221167Sgnn * @tmac_pad_byte: The byte that is used to pad 110221167Sgnn * @tmac_util_period: The sampling period over which the transmit utilization 111221167Sgnn * is calculated. 112221167Sgnn * @rmac_strip_fcs: Determines whether FCS of received frames is removed by the 113221167Sgnn * MAC or sent to the host. 114221167Sgnn * 0 - Send FCS to host. 115221167Sgnn * 1 - FCS removed by MAC. 116221167Sgnn * @rmac_prom_en: Enable/Disable promiscuous mode. In promiscuous mode all 117221167Sgnn * received frames are passed to the host. PROM_EN overrules the 118221167Sgnn * configuration determined by the UCAST_ALL_ADDR_EN, 119221167Sgnn * MCAST_ALL_ADDR_EN and ALL_VID_EN fields of RXMAC_VCFG, as well 120221167Sgnn * as the configurable discard fields in RMAC_ERR_CFG_PORTn. 121221167Sgnn * Note: PROM_EN does not overrule DISCARD_PFRM (i.e. discard of 122221167Sgnn * pause frames by receive MAC is controlled solely by 123221167Sgnn * DISCARD_PFRM). 124221167Sgnn * 0 - Disable 125221167Sgnn * 1 - Enable 126221167Sgnn * @rmac_discard_pfrm: Determines whether received pause frames are discarded at 127221167Sgnn * the receive MAC or passed to the host. 128221167Sgnn * Note: Other MAC control frames are always passed to the host. 129221167Sgnn * 0 - Send to host. 130221167Sgnn * 1 - Pause frames discarded by MAC. 131221167Sgnn * @rmac_util_period: The sampling period over which the receive utilization 132221167Sgnn * is calculated. 133221167Sgnn * @rmac_strip_pad: Determines whether padding of received frames is removed by 134221167Sgnn * the MAC or sent to the host. 135221167Sgnn * @rmac_bcast_en: Enable frames containing broadcast address to be 136221167Sgnn * passed to the host. 137221167Sgnn * @rmac_pause_gen_en: Received pause generation enable. 138221167Sgnn * @rmac_pause_rcv_en: Receive pause enable. 139221167Sgnn * @rmac_pause_time: The value to be inserted in outgoing pause frames. 140221167Sgnn * Has units of pause quanta (one pause quanta = 512 bit times). 141221167Sgnn * @limiter_en: Enables logic that limits the contribution that any one receive 142221167Sgnn * queue can have on the transmission of pause frames. This avoids 143221167Sgnn * a situation where the adapter will permanently send pause frames 144221167Sgnn * due to a receive VPATH that is either undergoing a long reset or 145221167Sgnn * is in a dead state. 146221167Sgnn * 0 - Don't limit the contribution of any queue. If any queue's 147221167Sgnn * fill level sits above the high threshold, then a pause frame 148221167Sgnn * is sent. 149221167Sgnn * 1 - Place a cap on the number of pause frames that are sent 150221167Sgnn * because any one queue has crossed its high threshold. 151221167Sgnn * See MAX_LIMIT for more details. 152221167Sgnn * @max_limit: Contains the value that is loaded into the per-queue limiting 153221167Sgnn * counters that exist in the flow control logic. Essentially, 154221167Sgnn * this represents the maximum number of pause frames that are sent 155221167Sgnn * due to any one particular queue having crossed its high 156221167Sgnn * threshold. Each counter is set to this max limit the first time 157221167Sgnn * the corresponding queue's high threshold is crossed. The counter 158221167Sgnn * decrements each time the queue remains above the high threshold 159221167Sgnn * and the adapter requests pause frame transmission. Once the 160221167Sgnn * counter expires that queue no longer contributes to pause frame 161221167Sgnn * transmission requests. The queue's fill level must drop below 162221167Sgnn * the low pause threshold before it is once again allowed to 163221167Sgnn * contribute. Note: This field is only used when LIMITER_EN is set 164221167Sgnn * to 1. 165221167Sgnn * 166221167Sgnn * Wire Port Configuration 167221167Sgnn */ 168221167Sgnntypedef struct vxge_hal_wire_port_config_t { 169221167Sgnn 170221167Sgnn u32 port_id; 171221167Sgnn#define VXGE_HAL_WIRE_PORT_PORT0 0 172221167Sgnn#define VXGE_HAL_WIRE_PORT_PORT1 1 173221167Sgnn#define VXGE_HAL_WIRE_PORT_MAX_PORTS VXGE_HAL_MAC_MAX_WIRE_PORTS 174221167Sgnn 175221167Sgnn u32 media; 176221167Sgnn#define VXGE_HAL_WIRE_PORT_MIN_MEDIA 0 177221167Sgnn#define VXGE_HAL_WIRE_PORT_MEDIA_SR 0 178221167Sgnn#define VXGE_HAL_WIRE_PORT_MEDIA_SW 1 179221167Sgnn#define VXGE_HAL_WIRE_PORT_MEDIA_LR 2 180221167Sgnn#define VXGE_HAL_WIRE_PORT_MEDIA_LW 3 181221167Sgnn#define VXGE_HAL_WIRE_PORT_MEDIA_ER 4 182221167Sgnn#define VXGE_HAL_WIRE_PORT_MEDIA_EW 5 183221167Sgnn#define VXGE_HAL_WIRE_PORT_MAX_MEDIA 5 184221167Sgnn#define VXGE_HAL_WIRE_PORT_MEDIA_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 185221167Sgnn 186221167Sgnn u32 mtu; 187221167Sgnn#define VXGE_HAL_WIRE_PORT_MIN_INITIAL_MTU VXGE_HAL_MIN_MTU 188221167Sgnn#define VXGE_HAL_WIRE_PORT_MAX_INITIAL_MTU VXGE_HAL_MAX_MTU 189221167Sgnn#define VXGE_HAL_WIRE_PORT_DEF_INITIAL_MTU VXGE_HAL_USE_FLASH_DEFAULT 190221167Sgnn 191221167Sgnn u32 autoneg_mode; 192221167Sgnn#define VXGE_HAL_WIRE_PORT_AUTONEG_MODE_FIXED 0 193221167Sgnn#define VXGE_HAL_WIRE_PORT_AUTONEG_MODE_ANTP 1 194221167Sgnn#define VXGE_HAL_WIRE_PORT_AUTONEG_MODE_ANBE 2 195221167Sgnn#define VXGE_HAL_WIRE_PORT_AUTONEG_MODE_RESERVED 3 196221167Sgnn#define VXGE_HAL_WIRE_PORT_AUTONEG_MODE_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 197221167Sgnn 198221167Sgnn u32 autoneg_rate; 199221167Sgnn#define VXGE_HAL_WIRE_PORT_AUTONEG_RATE_1G 0 200221167Sgnn#define VXGE_HAL_WIRE_PORT_AUTONEG_RATE_10G 1 201221167Sgnn#define VXGE_HAL_WIRE_PORT_AUTONEG_RATE_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 202221167Sgnn 203221167Sgnn u32 fixed_use_fsm; 204221167Sgnn#define VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_PROCESSOR 0 205221167Sgnn#define VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_HW 1 206221167Sgnn#define VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 207221167Sgnn 208221167Sgnn u32 antp_use_fsm; 209221167Sgnn#define VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_PROCESSOR 0 210221167Sgnn#define VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_HW 1 211221167Sgnn#define VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 212221167Sgnn 213221167Sgnn u32 anbe_use_fsm; 214221167Sgnn#define VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_PROCESSOR 0 215221167Sgnn#define VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_HW 1 216221167Sgnn#define VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 217221167Sgnn 218221167Sgnn u32 link_stability_period; 219221167Sgnn#define VXGE_HAL_WIRE_PORT_MIN_LINK_STABILITY_PERIOD 0x0 /* 0s */ 220221167Sgnn#define VXGE_HAL_WIRE_PORT_MAX_LINK_STABILITY_PERIOD 0xF /* 2s */ 221221167Sgnn#define VXGE_HAL_WIRE_PORT_DEF_LINK_STABILITY_PERIOD \ 222221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 223221167Sgnn 224221167Sgnn u32 port_stability_period; 225221167Sgnn#define VXGE_HAL_WIRE_PORT_MIN_PORT_STABILITY_PERIOD 0x0 /* 0s */ 226221167Sgnn#define VXGE_HAL_WIRE_PORT_MAX_PORT_STABILITY_PERIOD 0xF /* 2s */ 227221167Sgnn#define VXGE_HAL_WIRE_PORT_DEF_PORT_STABILITY_PERIOD \ 228221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 229221167Sgnn 230221167Sgnn u32 tmac_en; 231221167Sgnn#define VXGE_HAL_WIRE_PORT_TMAC_ENABLE 1 232221167Sgnn#define VXGE_HAL_WIRE_PORT_TMAC_DISABLE 0 233221167Sgnn#define VXGE_HAL_WIRE_PORT_TMAC_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 234221167Sgnn 235221167Sgnn u32 rmac_en; 236221167Sgnn#define VXGE_HAL_WIRE_PORT_RMAC_ENABLE 1 237221167Sgnn#define VXGE_HAL_WIRE_PORT_RMAC_DISABLE 0 238221167Sgnn#define VXGE_HAL_WIRE_PORT_RMAC_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 239221167Sgnn 240221167Sgnn u32 tmac_pad; 241221167Sgnn#define VXGE_HAL_WIRE_PORT_TMAC_NO_PAD 0 242221167Sgnn#define VXGE_HAL_WIRE_PORT_TMAC_64B_PAD 1 243221167Sgnn#define VXGE_HAL_WIRE_PORT_TMAC_PAD_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 244221167Sgnn 245221167Sgnn u32 tmac_pad_byte; 246221167Sgnn#define VXGE_HAL_WIRE_PORT_MIN_TMAC_PAD_BYTE 0 247221167Sgnn#define VXGE_HAL_WIRE_PORT_MAX_TMAC_PAD_BYTE 255 248221167Sgnn#define VXGE_HAL_WIRE_PORT_DEF_TMAC_PAD_BYTE VXGE_HAL_USE_FLASH_DEFAULT 249221167Sgnn 250221167Sgnn u32 tmac_util_period; 251221167Sgnn#define VXGE_HAL_WIRE_PORT_MIN_TMAC_UTIL_PERIOD 0 252221167Sgnn#define VXGE_HAL_WIRE_PORT_MAX_TMAC_UTIL_PERIOD 15 253221167Sgnn#define VXGE_HAL_WIRE_PORT_DEF_TMAC_UTIL_PERIOD VXGE_HAL_USE_FLASH_DEFAULT 254221167Sgnn 255221167Sgnn u32 rmac_strip_fcs; 256221167Sgnn#define VXGE_HAL_WIRE_PORT_RMAC_STRIP_FCS 1 257221167Sgnn#define VXGE_HAL_WIRE_PORT_RMAC_SEND_FCS_TO_HOST 0 258221167Sgnn#define VXGE_HAL_WIRE_PORT_RMAC_STRIP_FCS_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 259221167Sgnn 260221167Sgnn u32 rmac_prom_en; 261221167Sgnn#define VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_ENABLE 1 262221167Sgnn#define VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_DISABLE 0 263221167Sgnn#define VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 264221167Sgnn 265221167Sgnn u32 rmac_discard_pfrm; 266221167Sgnn#define VXGE_HAL_WIRE_PORT_RMAC_DISCARD_PFRM 1 267221167Sgnn#define VXGE_HAL_WIRE_PORT_RMAC_SEND_PFRM_TO_HOST 0 268221167Sgnn#define VXGE_HAL_WIRE_PORT_RMAC_DISCARD_PFRM_DEFAULT \ 269221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 270221167Sgnn 271221167Sgnn u32 rmac_util_period; 272221167Sgnn#define VXGE_HAL_WIRE_PORT_MIN_RMAC_UTIL_PERIOD 0 273221167Sgnn#define VXGE_HAL_WIRE_PORT_MAX_RMAC_UTIL_PERIOD 15 274221167Sgnn#define VXGE_HAL_WIRE_PORT_DEF_RMAC_UTIL_PERIOD VXGE_HAL_USE_FLASH_DEFAULT 275221167Sgnn 276221167Sgnn u32 rmac_pause_gen_en; 277221167Sgnn#define VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_ENABLE 1 278221167Sgnn#define VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_DISABLE 0 279221167Sgnn#define VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_DEFAULT \ 280221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 281221167Sgnn 282221167Sgnn u32 rmac_pause_rcv_en; 283221167Sgnn#define VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_ENABLE 1 284221167Sgnn#define VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_DISABLE 0 285221167Sgnn#define VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_DEFAULT \ 286221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 287221167Sgnn 288221167Sgnn u32 rmac_pause_time; 289221167Sgnn#define VXGE_HAL_WIRE_PORT_MIN_RMAC_HIGH_PTIME 16 290221167Sgnn#define VXGE_HAL_WIRE_PORT_MAX_RMAC_HIGH_PTIME 65535 291221167Sgnn#define VXGE_HAL_WIRE_PORT_DEF_RMAC_HIGH_PTIME VXGE_HAL_USE_FLASH_DEFAULT 292221167Sgnn 293221167Sgnn u32 limiter_en; 294221167Sgnn#define VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_ENABLE 1 295221167Sgnn#define VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_DISABLE 0 296221167Sgnn#define VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_DEFAULT \ 297221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 298221167Sgnn 299221167Sgnn u32 max_limit; 300221167Sgnn#define VXGE_HAL_WIRE_PORT_MIN_RMAC_MAX_LIMIT 0 301221167Sgnn#define VXGE_HAL_WIRE_PORT_MAX_RMAC_MAX_LIMIT 255 302221167Sgnn#define VXGE_HAL_WIRE_PORT_DEF_RMAC_MAX_LIMIT VXGE_HAL_USE_FLASH_DEFAULT 303221167Sgnn 304221167Sgnn} vxge_hal_wire_port_config_t; 305221167Sgnn 306221167Sgnn/* 307221167Sgnn * struct vxge_hal_switch_port_config_t - Switch Port configuration(vm-vm port) 308221167Sgnn * @mtu: mtu size used on this port. 309221167Sgnn * @tmac_en: TMAC enable. 0 - Disable; 1 - Enable 310221167Sgnn * @rmac_en: RMAC enable. 0 - Disable; 1 - Enable 311221167Sgnn * @tmac_pad: Determines whether padding is appended to transmitted frames. 312221167Sgnn * 0 - No padding appended 313221167Sgnn * 1 - Pad to 64 bytes (not including preamble/SFD) 314221167Sgnn * @tmac_pad_byte: The byte that is used to pad 315221167Sgnn * @tmac_util_period: The sampling period over which the transmit utilization 316221167Sgnn * is calculated. 317221167Sgnn * @rmac_strip_fcs: Determines whether FCS of received frames is removed by the 318221167Sgnn * MAC or sent to the host. 319221167Sgnn * 0 - Send FCS to host. 320221167Sgnn * 1 - FCS removed by MAC. 321221167Sgnn * @rmac_prom_en: Enable/Disable promiscuous mode. In promiscuous mode all 322221167Sgnn * received frames are passed to the host. PROM_EN overrules the 323221167Sgnn * configuration determined by the UCAST_ALL_ADDR_EN, 324221167Sgnn * MCAST_ALL_ADDR_EN and ALL_VID_EN fields of RXMAC_VCFG, as well 325221167Sgnn * as the configurable discard fields in RMAC_ERR_CFG_PORTn. 326221167Sgnn * Note: PROM_EN does not overrule DISCARD_PFRM (i.e. discard of 327221167Sgnn * pause frames by receive MAC is controlled solely by 328221167Sgnn * DISCARD_PFRM). 329221167Sgnn * 0 - Disable 330221167Sgnn * 1 - Enable 331221167Sgnn * @rmac_discard_pfrm: Determines whether received pause frames are discarded at 332221167Sgnn * the receive MAC or passed to the host. 333221167Sgnn * Note: Other MAC control frames are always passed to the host. 334221167Sgnn * 0 - Send to host. 335221167Sgnn * 1 - Pause frames discarded by MAC. 336221167Sgnn * @rmac_util_period: The sampling period over which the receive utilization 337221167Sgnn * is calculated. 338221167Sgnn * @rmac_strip_pad: Determines whether padding of received frames is removed by 339221167Sgnn * the MAC or sent to the host. 340221167Sgnn * @rmac_bcast_en: Enable frames containing broadcast address to be 341221167Sgnn * passed to the host. 342221167Sgnn * @rmac_pause_gen_en: Received pause generation enable. 343221167Sgnn * @rmac_pause_rcv_en: Receive pause enable. 344221167Sgnn * @rmac_pause_time: The value to be inserted in outgoing pause frames. 345221167Sgnn * Has units of pause quanta (one pause quanta = 512 bit times). 346221167Sgnn * @limiter_en: Enables logic that limits the contribution that any one receive 347221167Sgnn * queue can have on the transmission of pause frames. This avoids 348221167Sgnn * a situation where the adapter will permanently send pause frames 349221167Sgnn * due to a receive VPATH that is either undergoing a long reset or 350221167Sgnn * is in a dead state. 351221167Sgnn * 0 - Don't limit the contribution of any queue. If any queue's 352221167Sgnn * fill level sits above the high threshold, then a pause frame 353221167Sgnn * is sent. 354221167Sgnn * 1 - Place a cap on the number of pause frames that are sent 355221167Sgnn * because any one queue has crossed its high threshold. 356221167Sgnn * See MAX_LIMIT for more details. 357221167Sgnn * @max_limit: Contains the value that is loaded into the per-queue limiting 358221167Sgnn * counters that exist in the flow control logic. Essentially, 359221167Sgnn * this represents the maximum number of pause frames that are sent 360221167Sgnn * due to any one particular queue having crossed its high 361221167Sgnn * threshold. Each counter is set to this max limit the first time 362221167Sgnn * the corresponding queue's high threshold is crossed. The counter 363221167Sgnn * decrements each time the queue remains above the high threshold 364221167Sgnn * and the adapter requests pause frame transmission. Once the 365221167Sgnn * counter expires that queue no longer contributes to pause frame 366221167Sgnn * transmission requests. The queue's fill level must drop below 367221167Sgnn * the low pause threshold before it is once again allowed to 368221167Sgnn * contribute. Note: This field is only used when LIMITER_EN is set 369221167Sgnn * to 1. 370221167Sgnn * 371221167Sgnn * Switch Port Configuration 372221167Sgnn */ 373221167Sgnntypedef struct vxge_hal_switch_port_config_t { 374221167Sgnn 375221167Sgnn u32 mtu; 376221167Sgnn#define VXGE_HAL_SWITCH_PORT_MIN_INITIAL_MTU VXGE_HAL_MIN_MTU 377221167Sgnn#define VXGE_HAL_SWITCH_PORT_MAX_INITIAL_MTU VXGE_HAL_MAX_MTU 378221167Sgnn#define VXGE_HAL_SWITCH_PORT_DEF_INITIAL_MTU VXGE_HAL_USE_FLASH_DEFAULT 379221167Sgnn 380221167Sgnn u32 tmac_en; 381221167Sgnn#define VXGE_HAL_SWITCH_PORT_TMAC_ENABLE 1 382221167Sgnn#define VXGE_HAL_SWITCH_PORT_TMAC_DISABLE 0 383221167Sgnn#define VXGE_HAL_SWITCH_PORT_TMAC_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 384221167Sgnn 385221167Sgnn u32 rmac_en; 386221167Sgnn#define VXGE_HAL_SWITCH_PORT_RMAC_ENABLE 1 387221167Sgnn#define VXGE_HAL_SWITCH_PORT_RMAC_DISABLE 0 388221167Sgnn#define VXGE_HAL_SWITCH_PORT_RMAC_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 389221167Sgnn 390221167Sgnn u32 tmac_pad; 391221167Sgnn#define VXGE_HAL_SWITCH_PORT_TMAC_NO_PAD 0 392221167Sgnn#define VXGE_HAL_SWITCH_PORT_TMAC_64B_PAD 1 393221167Sgnn#define VXGE_HAL_SWITCH_PORT_TMAC_PAD_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 394221167Sgnn 395221167Sgnn u32 tmac_pad_byte; 396221167Sgnn#define VXGE_HAL_SWITCH_PORT_MIN_TMAC_PAD_BYTE 0 397221167Sgnn#define VXGE_HAL_SWITCH_PORT_MAX_TMAC_PAD_BYTE 255 398221167Sgnn#define VXGE_HAL_SWITCH_PORT_DEF_TMAC_PAD_BYTE VXGE_HAL_USE_FLASH_DEFAULT 399221167Sgnn 400221167Sgnn u32 tmac_util_period; 401221167Sgnn#define VXGE_HAL_SWITCH_PORT_MIN_TMAC_UTIL_PERIOD 0 402221167Sgnn#define VXGE_HAL_SWITCH_PORT_MAX_TMAC_UTIL_PERIOD 15 403221167Sgnn#define VXGE_HAL_SWITCH_PORT_DEF_TMAC_UTIL_PERIOD VXGE_HAL_USE_FLASH_DEFAULT 404221167Sgnn 405221167Sgnn u32 rmac_strip_fcs; 406221167Sgnn#define VXGE_HAL_SWITCH_PORT_RMAC_STRIP_FCS 1 407221167Sgnn#define VXGE_HAL_SWITCH_PORT_RMAC_SEND_FCS_TO_HOST 0 408221167Sgnn#define VXGE_HAL_SWITCH_PORT_RMAC_STRIP_FCS_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 409221167Sgnn 410221167Sgnn u32 rmac_prom_en; 411221167Sgnn#define VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_ENABLE 1 412221167Sgnn#define VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_DISABLE 0 413221167Sgnn#define VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 414221167Sgnn 415221167Sgnn u32 rmac_discard_pfrm; 416221167Sgnn#define VXGE_HAL_SWITCH_PORT_RMAC_DISCARD_PFRM 1 417221167Sgnn#define VXGE_HAL_SWITCH_PORT_RMAC_SEND_PFRM_TO_HOST 0 418221167Sgnn#define VXGE_HAL_SWITCH_PORT_RMAC_DISCARD_PFRM_DEFAULT \ 419221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 420221167Sgnn 421221167Sgnn u32 rmac_util_period; 422221167Sgnn#define VXGE_HAL_SWITCH_PORT_MIN_RMAC_UTIL_PERIOD 0 423221167Sgnn#define VXGE_HAL_SWITCH_PORT_MAX_RMAC_UTIL_PERIOD 15 424221167Sgnn#define VXGE_HAL_SWITCH_PORT_DEF_RMAC_UTIL_PERIOD VXGE_HAL_USE_FLASH_DEFAULT 425221167Sgnn 426221167Sgnn u32 rmac_pause_gen_en; 427221167Sgnn#define VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_ENABLE 1 428221167Sgnn#define VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_DISABLE 0 429221167Sgnn#define VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_DEFAULT \ 430221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 431221167Sgnn 432221167Sgnn u32 rmac_pause_rcv_en; 433221167Sgnn#define VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_ENABLE 1 434221167Sgnn#define VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_DISABLE 0 435221167Sgnn#define VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_DEFAULT \ 436221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 437221167Sgnn 438221167Sgnn u32 rmac_pause_time; 439221167Sgnn#define VXGE_HAL_SWITCH_PORT_MIN_RMAC_HIGH_PTIME 16 440221167Sgnn#define VXGE_HAL_SWITCH_PORT_MAX_RMAC_HIGH_PTIME 65535 441221167Sgnn#define VXGE_HAL_SWITCH_PORT_DEF_RMAC_HIGH_PTIME VXGE_HAL_USE_FLASH_DEFAULT 442221167Sgnn 443221167Sgnn u32 limiter_en; 444221167Sgnn#define VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_ENABLE 1 445221167Sgnn#define VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_DISABLE 0 446221167Sgnn#define VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_DEFAULT \ 447221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 448221167Sgnn 449221167Sgnn u32 max_limit; 450221167Sgnn#define VXGE_HAL_SWITCH_PORT_MIN_RMAC_MAX_LIMIT 0 451221167Sgnn#define VXGE_HAL_SWITCH_PORT_MAX_RMAC_MAX_LIMIT 255 452221167Sgnn#define VXGE_HAL_SWITCH_PORT_DEF_RMAC_MAX_LIMIT VXGE_HAL_USE_FLASH_DEFAULT 453221167Sgnn 454221167Sgnn} vxge_hal_switch_port_config_t; 455221167Sgnn 456221167Sgnn/* 457221167Sgnn * struct vxge_hal_mac_config_t - MAC configuration (Physical ports). 458221167Sgnn * @wire_port_config: Wire Port configuration 459221167Sgnn * @switch_port_config: Switch Port configuration 460221167Sgnn * @network_stability_period: The wait period for network stability 461221167Sgnn * @mc_pause_threshold: Contains thresholds for pause frame generation 462221167Sgnn * for queues 0 through 15. The threshold value indicates portion 463221167Sgnn * of the individual receive buffer queue size. Thresholds have a 464221167Sgnn * range of 0 to 255, allowing 256 possible watermarks in a queue. 465221167Sgnn * @tmac_perma_stop_en: Controls TMAC reaction to double ECC errors on its 466221167Sgnn * internal SRAMs. 467221167Sgnn * 0 - Disable TMAC permanent stop 468221167Sgnn * 1 - Enable TMAC permanent stop whenever double ECC errors are 469221167Sgnn * detected on the internal transmit SRAMs. 470221167Sgnn * @tmac_tx_switch_dis: Allows the user to disable the switching of transmit 471221167Sgnn * frames back to the receive path. 472221167Sgnn * 0 - Tx frames are switched based on the result of the DA lookup 473221167Sgnn * 1 - The DA lookup result is ignored and all traffic is sent to 474221167Sgnn * the wire. 475221167Sgnn * Note that this register field does not impact the multicast 476221167Sgnn * replication on the receive side. 477221167Sgnn * @tmac_lossy_switch_en: Controls the behaviour of the internal Tx to Rx switch 478221167Sgnn * in the event of back-pressure on the receive path due to 479221167Sgnn * priority given to traffic arriving off the wire or simply due to 480221167Sgnn * a full receive external buffer. br> 481221167Sgnn * 0 - No frames are dropped on the switch path. Instead, in the 482221167Sgnn * event of back-pressure, the transmit path is backed up. 483221167Sgnn * 1 - Whenever back-pressure is present and the next frame is 484221167Sgnn * bound for the switch path, then the frame is dropped. 485221167Sgnn * If it is also destined for the transmit wire, it is still 486221167Sgnn * sent there. 487221167Sgnn * Note: HIP traffic that is bound for the switch path is never 488221167Sgnn * dropped - the transmit path is forced to backup. 489221167Sgnn * @tmac_lossy_wire_en: Controls the behaviour of the TMAC when the wire path 490221167Sgnn * is unavailable. This occurs when the target wire port is down. 491221167Sgnn * 0 - No frames are dropped on the wire path. Instead,in the event 492221167Sgnn * of port failure, the transmit path is backed up. 493221167Sgnn * 1 - Whenever a wire port is down and the next frame is bound for 494221167Sgnn * that port, then the frame is dropped. If it is also destined 495221167Sgnn * for the switch path, it is still sent there. 496221167Sgnn * @tmac_bcast_to_wire_dis: Suppresses the transmission of broadcast frames to 497221167Sgnn * the wire. 498221167Sgnn * 0 - Transmit broadcast frames are sent out the wire and also 499221167Sgnn * sent along the switch path. 500221167Sgnn * 1 - Transmit broadcast frame are only sent along the switch path 501221167Sgnn * @tmac_bcast_to_switch_dis: Suppresses the transmission of broadcast frames 502221167Sgnn * along the switch path. 503221167Sgnn * 0 - Transmit broadcast frames are sent out the wire and also 504221167Sgnn * sent along the switch path. 505221167Sgnn * 1 - Transmit broadcast frame are only sent out the wire. 506221167Sgnn * @tmac_host_append_fcs_en: Suppresses the H/W from appending the FCS to the 507221167Sgnn * end of transmitted frames. The host is responsible for tacking 508221167Sgnn * on the 4-byte FCS at the end of the frame. 509221167Sgnn * 0 - Normal operation. H/W appends FCS to all transmitted frames. 510221167Sgnn * 1 - Host appends FCS to frame. Transmit MAC passes it through 511221167Sgnn * @tpa_support_snap_ab_n: When set to 0, the TPA will accept LLC-SAP values of 512221167Sgnn * 0xAB as valid. If set to 1, the TPA rejects LLC-SAP values of 513221167Sgnn * 0xAB (only 0xAA is accepted). 514221167Sgnn * @tpa_ecc_enable_n: Allows ECC protection of TPA internal memories to be 515221167Sgnn * disabled without having to disable ECC protection for entire 516221167Sgnn * chip. 517221167Sgnn * 0 - Disable TPA ECC protection 518221167Sgnn * 1 - Enable TPA ECC protection. 519221167Sgnn * Note: If chip-wide ECC protection is disabled, then so is TPA 520221167Sgnn * ECC protection. 521221167Sgnn * @rpa_ignore_frame_err: Ignore Frame Error. The RPA may detect frame integrity 522221167Sgnn * errors as it processes each received frame. If this bit is set 523221167Sgnn * to '0', the RPA will tag such frames as "errored" in the RxDMA 524221167Sgnn * descriptor. If the bit is set to '1', the frame will not be 525221167Sgnn * tagged as "errored". 526221167Sgnn * Detectable errors include: 527221167Sgnn * 1) early end-of-frame error, which occurs when the frame ends 528221167Sgnn * before the number of bytes predicted by the IP "total length" 529221167Sgnn * field have been received; 530221167Sgnn * 2) IP version mismatches; 531221167Sgnn * 3) IPv6 packets that include routing headers that are not type 0 532221167Sgnn * 4) Frames which contain IP packets but have an illegal SNAP-OUI 533221167Sgnn * or LLC-CTRL fields, unless IGNORE_SNAP_OUI or IGNORE_LLC_CTRL 534221167Sgnn * are set 535221167Sgnn * @rpa_support_snap_ab_n: When set to 0, the RPA will accept LLC-SAP values of 536221167Sgnn * 0xAB as valid. If set to 1, the RPA rejects LLC-SAP values of 537221167Sgnn * 0xAB (only 0xAA is accepted). 538221167Sgnn * @rpa_search_for_hao: Enable searching for the Home Address Option.If this bit 539221167Sgnn * is set, the RPA will parse through Destination Address Headers 540221167Sgnn * searching for the H.A.O. If the bit is not set, the RPA will not 541221167Sgnn * perform a search and these headers will effectively be ignored. 542221167Sgnn * @rpa_support_ipv6_mobile_hdrs: Enable/disable support for the mobile-ipv6 543221167Sgnn * Home Address Option (HAO) and Route 2 Routing Headers,as defined 544221167Sgnn * in RFC 3775. 545221167Sgnn * 0 - Do not support mobile IPv6. 546221167Sgnn * 1 - Support mobile IPv6 547221167Sgnn * @rpa_ipv6_stop_searching: Enable/disable unknown IPv6 extension header 548221167Sgnn * parsing. If the adapter discovers an unknown extension header, 549221167Sgnn * it can either continue to search for a L4 protocol, or stop 550221167Sgnn * searching. 551221167Sgnn * 0 - do not stop searching for L4 when an unknown header is 552221167Sgnn * encountered. 553221167Sgnn * 1 - stop searching when an unknown header is encountered. 554221167Sgnn * @rpa_no_ps_if_unknown: Enable/disable pseudo-header inclusion if an unknown 555221167Sgnn * IPv6 extension header is encountered. 556221167Sgnn * If this bit is set to '1' and an unknown routing header or IPv6 557221167Sgnn * extension header is discovered, the L4 checksum will not include 558221167Sgnn * a pseudo-header. 559221167Sgnn * If it is set to '0', the adapter will use the addresses found 560221167Sgnn * in the IPv6 base header, and/or the addresses found in a Routing 561221167Sgnn * Header or Home Address Option (if it is enabled). 562221167Sgnn * This applies to frames not on LRO sessions only. For frames on 563221167Sgnn * LRO sessions, the pseudo-header is always included in the L4 564221167Sgnn * checksum 565221167Sgnn * @rpa_search_for_etype: For receive traffic steering purposes, indicates 566221167Sgnn * whether the RPA should parse through the LLC header to find the 567221167Sgnn * Ethertype of the packet. 568221167Sgnn * 0 - RPA presents the 802.3 length/type field, which for an 569221167Sgnn * LLC-encoded frame is interpreted as a length. 570221167Sgnn * 1 - RPA parses the LLC-header and presents the Ethertype to the 571221167Sgnn * traffic steering logic. When SEARCH_FOR_ETYPE is set and a jumbo 572221167Sgnn * snap frame is received then GLOBAL_PA_CFG.EN_JS determines the 573221167Sgnn * value that is presented to the traffic steering logic. If EN_JS 574221167Sgnn * is set, then the RPA parses inside the header to find the 575221167Sgnn * Ethertype, while if EN_JS is not set the RPA presents 0x8870. 576221167Sgnn * @rpa_repl_l4_comp_csum: Controls whether or not to complement the L4 checksum 577221167Sgnn * after the final calculation. 578221167Sgnn * 0: Do not complement the L4 checksum. 579221167Sgnn * 1: Complement the L4 checksum. 580221167Sgnn * For the behaviour on non-replicated frames see FAU_RPA_VCFG. 581221167Sgnn * @rpa_repl_l3_incl_cf: Controls whether or not to include the L3 checksum 582221167Sgnn * field in the checksum calculation. 583221167Sgnn * 0: Do not include the L3 checksum field in checksum calculation 584221167Sgnn * 1: Include the L4 checksum field in the checksum calculation. 585221167Sgnn * For the behaviour on non-replicated frames see FAU_RPA_VCFG. 586221167Sgnn * @rpa_repl_l3_comp_csum: Controls whether or not to complement the L3 checksum 587221167Sgnn * after the final calculation. 588221167Sgnn * 0: Do not complement the L3 checksum. 589221167Sgnn * 1: Complement the L3 checksum. 590221167Sgnn * For the behaviour on non-replicated frames see FAU_RPA_VCFG. 591221167Sgnn * @rpa_repl_ipv4_tcp_incl_ph: For received frames that are replicated at the 592221167Sgnn * internal L2 switch, determines whether the pseudo-header is 593221167Sgnn * included in the calculation of the L4 checksum that is passed to 594221167Sgnn * the host. 595221167Sgnn * @rpa_repl_ipv6_tcp_incl_ph: For received frames that are replicated at the 596221167Sgnn * internal L2 switch, determines whether the pseudo-header is 597221167Sgnn * included in the calculation of the L4 checksum that is passed to 598221167Sgnn * the host. 599221167Sgnn * @rpa_repl_ipv4_udp_incl_ph: For received frames that are replicated at the 600221167Sgnn * internal L2 switch, determines whether the pseudo-header is 601221167Sgnn * included in the calculation of the L4 checksum that is passed to 602221167Sgnn * the host. 603221167Sgnn * @rpa_repl_ipv6_udp_incl_ph: For received frames that are replicated at the 604221167Sgnn * internal L2 switch, determines whether the pseudo-header is 605221167Sgnn * included in the calculation of the L4 checksum that is passed to 606221167Sgnn * the host. 607221167Sgnn * @rpa_repl_l4_incl_cf: For received frames that are replicated at the internal 608221167Sgnn * L2 switch, determines whether the checksum field (CF) of the 609221167Sgnn * received frame is included in the calculation of the L4 610221167Sgnn * checksum that is passed to the host. 611221167Sgnn * @rpa_repl_strip_vlan_tag: Strip VLAN Tag enable/disable. Instructs the device 612221167Sgnn * to remove the VLAN tag from all received tagged frames that 613221167Sgnn * are replicated at the internal L2 switch (i.e. multicast frames 614221167Sgnn * that are placed in the replication queue). 615221167Sgnn * 0 - Do not strip the VLAN tag. 616221167Sgnn * 1 - Strip the VLAN tag. 617221167Sgnn * Regardless of this setting, VLAN tags are always placed into 618221167Sgnn * the RxDMA descriptor. 619221167Sgnn * 620221167Sgnn * MAC configuration. This includes various aspects of configuration, including: 621221167Sgnn * - Pause frame threshold; 622221167Sgnn * - sampling rate to calculate link utilization; 623221167Sgnn * - enabling/disabling broadcasts. 624221167Sgnn * 625221167Sgnn * See X3100 ER User Guide for more details. 626221167Sgnn * Note: Valid (min, max) range for each attribute is specified in the body of 627221167Sgnn * the vxge_hal_mac_config_t {} structure. Please refer to the 628221167Sgnn * corresponding include file. 629221167Sgnn */ 630221167Sgnntypedef struct vxge_hal_mac_config_t { 631221167Sgnn 632221167Sgnn vxge_hal_wire_port_config_t wire_port_config[ \ 633221167Sgnn VXGE_HAL_MAC_MAX_WIRE_PORTS]; 634221167Sgnn vxge_hal_switch_port_config_t switch_port_config; 635221167Sgnn 636221167Sgnn u32 network_stability_period; 637221167Sgnn#define VXGE_HAL_MAC_MIN_NETWORK_STABILITY_PERIOD 0x0 /* 0s */ 638221167Sgnn#define VXGE_HAL_MAC_MAX_NETWORK_STABILITY_PERIOD 0x7 /* 2s */ 639221167Sgnn#define VXGE_HAL_MAC_DEF_NETWORK_STABILITY_PERIOD VXGE_HAL_USE_FLASH_DEFAULT 640221167Sgnn 641221167Sgnn u32 mc_pause_threshold[16]; 642221167Sgnn#define VXGE_HAL_MAC_MIN_MC_PAUSE_THRESHOLD 0 643221167Sgnn#define VXGE_HAL_MAC_MAX_MC_PAUSE_THRESHOLD 254 644221167Sgnn#define VXGE_HAL_MAC_DEF_MC_PAUSE_THRESHOLD VXGE_HAL_USE_FLASH_DEFAULT 645221167Sgnn 646221167Sgnn u32 tmac_perma_stop_en; 647221167Sgnn#define VXGE_HAL_MAC_TMAC_PERMA_STOP_ENABLE 1 648221167Sgnn#define VXGE_HAL_MAC_TMAC_PERMA_STOP_DISABLE 0 649221167Sgnn#define VXGE_HAL_MAC_TMAC_PERMA_STOP_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 650221167Sgnn 651221167Sgnn u32 tmac_tx_switch_dis; 652221167Sgnn#define VXGE_HAL_MAC_TMAC_TX_SWITCH_ENABLE 0 653221167Sgnn#define VXGE_HAL_MAC_TMAC_TX_SWITCH_DISABLE 1 654221167Sgnn#define VXGE_HAL_MAC_TMAC_TX_SWITCH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 655221167Sgnn 656221167Sgnn u32 tmac_lossy_switch_en; 657221167Sgnn#define VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_ENABLE 1 658221167Sgnn#define VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_DISABLE 0 659221167Sgnn#define VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 660221167Sgnn 661221167Sgnn u32 tmac_lossy_wire_en; 662221167Sgnn#define VXGE_HAL_MAC_TMAC_LOSSY_WIRE_ENABLE 1 663221167Sgnn#define VXGE_HAL_MAC_TMAC_LOSSY_WIRE_DISABLE 0 664221167Sgnn#define VXGE_HAL_MAC_TMAC_LOSSY_WIRE_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 665221167Sgnn 666221167Sgnn u32 tmac_bcast_to_wire_dis; 667221167Sgnn#define VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_DISABLE 1 668221167Sgnn#define VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_ENABLE 0 669221167Sgnn#define VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 670221167Sgnn 671221167Sgnn u32 tmac_bcast_to_switch_dis; 672221167Sgnn#define VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_DISABLE 1 673221167Sgnn#define VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_ENABLE 0 674221167Sgnn#define VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 675221167Sgnn 676221167Sgnn u32 tmac_host_append_fcs_en; 677221167Sgnn#define VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_ENABLE 1 678221167Sgnn#define VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_DISABLE 0 679221167Sgnn#define VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 680221167Sgnn 681221167Sgnn u32 tpa_support_snap_ab_n; 682221167Sgnn#define VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_LLC_SAP_AB 0 683221167Sgnn#define VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_LLC_SAP_AA 1 684221167Sgnn#define VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 685221167Sgnn 686221167Sgnn u32 tpa_ecc_enable_n; 687221167Sgnn#define VXGE_HAL_MAC_TPA_ECC_ENABLE_N_ENABLE 1 688221167Sgnn#define VXGE_HAL_MAC_TPA_ECC_ENABLE_N_DISABLE 0 689221167Sgnn#define VXGE_HAL_MAC_TPA_ECC_ENABLE_N_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 690221167Sgnn 691221167Sgnn u32 rpa_ignore_frame_err; 692221167Sgnn#define VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_ENABLE 1 693221167Sgnn#define VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_DISABLE 0 694221167Sgnn#define VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 695221167Sgnn 696221167Sgnn u32 rpa_support_snap_ab_n; 697221167Sgnn#define VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_ENABLE 1 698221167Sgnn#define VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_DISABLE 0 699221167Sgnn#define VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 700221167Sgnn 701221167Sgnn u32 rpa_search_for_hao; 702221167Sgnn#define VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_ENABLE 1 703221167Sgnn#define VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_DISABLE 0 704221167Sgnn#define VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 705221167Sgnn 706221167Sgnn u32 rpa_support_ipv6_mobile_hdrs; 707221167Sgnn#define VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_ENABLE 1 708221167Sgnn#define VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_DISABLE 0 709221167Sgnn#define VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_DEFAULT \ 710221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 711221167Sgnn 712221167Sgnn u32 rpa_ipv6_stop_searching; 713221167Sgnn#define VXGE_HAL_MAC_RPA_IPV6_STOP_SEARCHING 1 714221167Sgnn#define VXGE_HAL_MAC_RPA_IPV6_DONT_STOP_SEARCHING 0 715221167Sgnn#define VXGE_HAL_MAC_RPA_IPV6_STOP_SEARCHING_DEFAULT \ 716221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 717221167Sgnn 718221167Sgnn u32 rpa_no_ps_if_unknown; 719221167Sgnn#define VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_ENABLE 1 720221167Sgnn#define VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_DISABLE 0 721221167Sgnn#define VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 722221167Sgnn 723221167Sgnn u32 rpa_search_for_etype; 724221167Sgnn#define VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_ENABLE 1 725221167Sgnn#define VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_DISABLE 0 726221167Sgnn#define VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 727221167Sgnn 728221167Sgnn u32 rpa_repl_l4_comp_csum; 729221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_L4_COMP_CSUM_ENABLE 1 730221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_L4_COMP_CSUM_DISABLE 0 731221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_l4_COMP_CSUM_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 732221167Sgnn 733221167Sgnn u32 rpa_repl_l3_incl_cf; 734221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_ENABLE 1 735221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_DISABLE 0 736221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 737221167Sgnn 738221167Sgnn u32 rpa_repl_l3_comp_csum; 739221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_L3_COMP_CSUM_ENABLE 1 740221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_L3_COMP_CSUM_DISABLE 0 741221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_l3_COMP_CSUM_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 742221167Sgnn 743221167Sgnn u32 rpa_repl_ipv4_tcp_incl_ph; 744221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_ENABLE 1 745221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_DISABLE 0 746221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_DEFAULT \ 747221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 748221167Sgnn 749221167Sgnn u32 rpa_repl_ipv6_tcp_incl_ph; 750221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_ENABLE 1 751221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_DISABLE 0 752221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_DEFAULT \ 753221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 754221167Sgnn 755221167Sgnn u32 rpa_repl_ipv4_udp_incl_ph; 756221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_ENABLE 1 757221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_DISABLE 0 758221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_DEFAULT \ 759221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 760221167Sgnn 761221167Sgnn u32 rpa_repl_ipv6_udp_incl_ph; 762221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_ENABLE 1 763221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_DISABLE 0 764221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_DEFAULT \ 765221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 766221167Sgnn 767221167Sgnn u32 rpa_repl_l4_incl_cf; 768221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_ENABLE 1 769221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_DISABLE 0 770221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 771221167Sgnn 772221167Sgnn u32 rpa_repl_strip_vlan_tag; 773221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_ENABLE 1 774221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DISABLE 0 775221167Sgnn#define VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DEFAULT \ 776221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 777221167Sgnn 778221167Sgnn} vxge_hal_mac_config_t; 779221167Sgnn 780221167Sgnn/* 781221167Sgnn * struct vxge_hal_lag_port_config_t - LAG Port configuration(For privileged 782221167Sgnn * mode driver only) 783221167Sgnn * 784221167Sgnn * @port_id: Port Id 785221167Sgnn * @lag_en: Enables or disables the port from joining a link aggregation group. 786221167Sgnn * If link aggregation is enabled and this port is disabled, then 787221167Sgnn * this port does not carry traffic (it is not associated with an 788221167Sgnn * Aggregator). Both this bit and port_enabled from the physical 789221167Sgnn * layer logic must be asserted to permit the Receive machine to 790221167Sgnn * move beyond the PORT_DISABLED state. 791221167Sgnn * 0 - Disable; 792221167Sgnn * 1 - Enable; 793221167Sgnn * @discard_slow_proto: Discard received frames that contain the Slow Protocols 794221167Sgnn * Multicast address (IEEE 802.3-2005 Clause 43B) -- Such frames 795221167Sgnn * are used for link aggregation Marker Protocol and for LACP. 796221167Sgnn * 0 - Pass to host; 797221167Sgnn * 1 - Discard; 798221167Sgnn * @host_chosen_aggr: When the host is running the Link Aggregation Control 799221167Sgnn * algorithm, this field determines which aggregator is attached 800221167Sgnn * to this port. This field is only valid when LAG_LACP_CFG.EN is 0 801221167Sgnn * 0 - Aggregator 0 is attached to this port. 802221167Sgnn * 1 - Aggregator 1 is attached to this port. 803221167Sgnn * @discard_unknown_slow_proto: Discard received frames that contain the Slow 804221167Sgnn * Protocols Multicast address (IEEE 802.3-2005 Clause 43B), 805221167Sgnn * but have an unknown Slow Protocols PDU. 806221167Sgnn * 0 - Pass to host 807221167Sgnn * 1 - Discard 808221167Sgnn * Note: This field is only relevant when DISCARD_SLOW_PROTO 809221167Sgnn * is set to 0. 810221167Sgnn * @actor_port_num: The port number assigned to the port. Port Number 0 is 811221167Sgnn * reserved and must not be assigned to any port. 812221167Sgnn * @actor_port_priority: The priority value assigned to the port. 813221167Sgnn * @actor_key_10g: The port's administrative Key when auto-negotiated to 10Gbps 814221167Sgnn * The null (all zeros) Key value is not available for local use. 815221167Sgnn * @actor_key_1g: The port's administrative Key when auto-negotiated to 1Gbps. 816221167Sgnn * The null (all zeros) Key value is not available for local use. 817221167Sgnn * @actor_lacp_activity: Indicates the Activity control value for this port. 818221167Sgnn * 0 - Passive LACP 819221167Sgnn * 1 - Active LACP 820221167Sgnn * @actor_lacp_timeout: Indicates the Timeout control value for this port. 821221167Sgnn * 0 - Long Timeout 822221167Sgnn * 1 - Short Timeout 823221167Sgnn * @actor_aggregation: Indicates if the port is a potential candidate for 824221167Sgnn * aggregation. 825221167Sgnn * 0 - Link is Individual 826221167Sgnn * 1 - Link is Aggregateable 827221167Sgnn * @actor_synchronization: Indicates if the port is in sync. 828221167Sgnn * 0 - Link is out of sync; it is in the wrong Aggregation 829221167Sgnn * 1 - Link is in sync (allocated to the correct Link Aggregation 830221167Sgnn * Group, the group is associated with a compatible Aggregator, 831221167Sgnn * and the identity of the Link Aggregation Group is consistent 832221167Sgnn * with the System ID and operational Key information transmitted) 833221167Sgnn * @actor_collecting: Indicates whether collecting of incoming frames is enabled 834221167Sgnn * on this port. 835221167Sgnn * 0 - Not collecting 836221167Sgnn * 1 - Collection is enabled 837221167Sgnn * @actor_distributing: Indicates whether distribution of outgoing frames is 838221167Sgnn * enabled on this port. 839221167Sgnn * 0 - Not distributing 840221167Sgnn * 1 - Distribution is enabled 841221167Sgnn * @actor_defaulted: Indicates whether the Actor's Receive state machine is 842221167Sgnn * using administratively configured information for the Partner. 843221167Sgnn * 0 - The operational Partner info has been received in a LACPDU 844221167Sgnn * 1 - The operation Partner info is using administrative defaults 845221167Sgnn * @actor_expired: Indicates whether the Actor's Receive state machine is in the 846221167Sgnn * EXPIRED state. 847221167Sgnn * 0 - Not in the EXPIRED state 848221167Sgnn * 1 - Is in the EXPIRED state 849221167Sgnn * @partner_sys_pri: The administrative default for the System Priority 850221167Sgnn * component of the System Identifier of the Partner. 851221167Sgnn * @partner_key: The administrative default for the Partner's Key. The null 852221167Sgnn * (all zeros) Key value is not available for local use. 853221167Sgnn * @partner_port_num: The administrative default for the Port Number component 854221167Sgnn * of the Partner's Port Identifier. 855221167Sgnn * @partner_port_priority: The administrative default for the Port Identifier 856221167Sgnn * component of the Partner's Port Identifier. 857221167Sgnn * @partner_lacp_activity: Indicates the Activity control value for this port. 858221167Sgnn * 0 - Passive LACP 859221167Sgnn * 1 - Active LACP 860221167Sgnn * @partner_lacp_timeout: Indicates the Timeout control value for this port. 861221167Sgnn * 0 - Long Timeout 862221167Sgnn * 1 - Short Timeout 863221167Sgnn * @partner_aggregation: Indicates if the port is a potential candidate for 864221167Sgnn * aggregation. 865221167Sgnn * 0 - Link is Individual 866221167Sgnn * 1 - Link is Aggregateable 867221167Sgnn * @partner_synchronization: Indicates if the port is in sync. 868221167Sgnn * 0 - Link is out of sync; it is in the wrong Aggregation 869221167Sgnn * 1 - Link is in sync (allocated to the correct Link Aggregation 870221167Sgnn * Group, the group is associated with a compatible Aggregator, 871221167Sgnn * and the identity of the Link Aggregation Group is consistent 872221167Sgnn * with the System ID and operational Key information transmitted) 873221167Sgnn * @partner_collecting: Indicates whether collecting of incoming frames is 874221167Sgnn * enabled on this port. 875221167Sgnn * 0 - Not collecting 876221167Sgnn * 1 - Collection is enabled. 877221167Sgnn * Note: According to IEEE 802.3-2005, the value of the 878221167Sgnn * partner_collecting field of this register must be the same as 879221167Sgnn * the value of the partner_synchronization field of this register 880221167Sgnn * @partner_distributing: Indicates whether distribution of outgoing frames is 881221167Sgnn * enabled on this port. 882221167Sgnn * 0 - Not distributing 883221167Sgnn * 1 - Distribution is enabled 884221167Sgnn * @partner_defaulted: Indicates whether the Actor's Receive state machine is 885221167Sgnn * using administratively configured information for the Partner. 886221167Sgnn * 0 - The operational Partner information has been received in 887221167Sgnn * a LACPDU 888221167Sgnn * 1 - The operation Partner information is using administrative 889221167Sgnn * defaults 890221167Sgnn * @partner_expired: Indicates whether the Actor's Receive state machine is in 891221167Sgnn * the expired state. 892221167Sgnn * 0 - Not in the EXPIRED state 893221167Sgnn * 1 - Is in the EXPIRED state 894221167Sgnn * @partner_mac_addr: Default value for the MAC address of the Partner. 895221167Sgnn * 896221167Sgnn * This structure is configuration for LAG Port of device 897221167Sgnn */ 898221167Sgnntypedef struct vxge_hal_lag_port_config_t { 899221167Sgnn u32 port_id; 900221167Sgnn#define VXGE_HAL_LAG_PORT_PORT_ID_0 1 901221167Sgnn#define VXGE_HAL_LAG_PORT_PORT_ID_1 2 902221167Sgnn#define VXGE_HAL_LAG_PORT_MAX_PORTS VXGE_HAL_MAC_MAX_WIRE_PORTS 903221167Sgnn 904221167Sgnn u32 lag_en; 905221167Sgnn#define VXGE_HAL_LAG_PORT_LAG_EN_DISABLE 0 906221167Sgnn#define VXGE_HAL_LAG_PORT_LAG_EN_ENABLE 1 907221167Sgnn#define VXGE_HAL_LAG_PORT_LAG_EN_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 908221167Sgnn 909221167Sgnn u32 discard_slow_proto; 910221167Sgnn#define VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_DISABLE 0 911221167Sgnn#define VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_ENABLE 1 912221167Sgnn#define VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_DEFAULT \ 913221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 914221167Sgnn 915221167Sgnn u32 host_chosen_aggr; 916221167Sgnn#define VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_0 0 917221167Sgnn#define VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_1 1 918221167Sgnn#define VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 919221167Sgnn 920221167Sgnn u32 discard_unknown_slow_proto; 921221167Sgnn#define VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_DISABLE 0 922221167Sgnn#define VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_ENABLE 1 923221167Sgnn#define VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_DEFAULT \ 924221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 925221167Sgnn 926221167Sgnn u32 actor_port_num; 927221167Sgnn#define VXGE_HAL_LAG_PORT_MIN_ACTOR_PORT_NUM 0 928221167Sgnn#define VXGE_HAL_LAG_PORT_MAX_ACTOR_PORT_NUM 65535 929221167Sgnn#define VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_NUM VXGE_HAL_USE_FLASH_DEFAULT 930221167Sgnn 931221167Sgnn u32 actor_port_priority; 932221167Sgnn#define VXGE_HAL_LAG_PORT_MIN_ACTOR_PORT_PRIORITY 0 933221167Sgnn#define VXGE_HAL_LAG_PORT_MAX_ACTOR_PORT_PRIORITY 65535 934221167Sgnn#define VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_PRIORITY VXGE_HAL_USE_FLASH_DEFAULT 935221167Sgnn 936221167Sgnn u32 actor_key_10g; 937221167Sgnn#define VXGE_HAL_LAG_PORT_MIN_ACTOR_KEY_10G 0 938221167Sgnn#define VXGE_HAL_LAG_PORT_MAX_ACTOR_KEY_10G 65535 939221167Sgnn#define VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_10G VXGE_HAL_USE_FLASH_DEFAULT 940221167Sgnn 941221167Sgnn u32 actor_key_1g; 942221167Sgnn#define VXGE_HAL_LAG_PORT_MIN_ACTOR_KEY_1G 0 943221167Sgnn#define VXGE_HAL_LAG_PORT_MAX_ACTOR_KEY_1G 65535 944221167Sgnn#define VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_1G VXGE_HAL_USE_FLASH_DEFAULT 945221167Sgnn 946221167Sgnn u32 actor_lacp_activity; 947221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_PASSIVE 0 948221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_ACTIVE 1 949221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_DEFAULT \ 950221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 951221167Sgnn 952221167Sgnn u32 actor_lacp_timeout; 953221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_LONG 0 954221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_SHORT 1 955221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_DEFAULT \ 956221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 957221167Sgnn 958221167Sgnn u32 actor_aggregation; 959221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_INDIVIDUAL 0 960221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_AGGREGATEABLE 1 961221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 962221167Sgnn 963221167Sgnn u32 actor_synchronization; 964221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_OUT_OF_SYNC 0 965221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_IN_SYNC 1 966221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_DEFAULT \ 967221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 968221167Sgnn 969221167Sgnn u32 actor_collecting; 970221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_DISABLE 0 971221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_ENABLE 1 972221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 973221167Sgnn 974221167Sgnn u32 actor_distributing; 975221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DISABLE 0 976221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_ENABLE 1 977221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DEFAULT \ 978221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 979221167Sgnn 980221167Sgnn u32 actor_defaulted; 981221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_DEFAULTED 0 982221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_NOT_DEFAULTED 1 983221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_DEFAULTED_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 984221167Sgnn 985221167Sgnn u32 actor_expired; 986221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_EXPIRED 0 987221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_NOT_EXPIRED 1 988221167Sgnn#define VXGE_HAL_LAG_PORT_ACTOR_EXPIRED_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 989221167Sgnn 990221167Sgnn u32 partner_sys_pri; 991221167Sgnn#define VXGE_HAL_LAG_PORT_MIN_PARTNER_SYS_PRI 0 992221167Sgnn#define VXGE_HAL_LAG_PORT_MAX_PARTNER_SYS_PRI 65535 993221167Sgnn#define VXGE_HAL_LAG_PORT_DEF_PARTNER_SYS_PRI VXGE_HAL_USE_FLASH_DEFAULT 994221167Sgnn 995221167Sgnn u32 partner_key; 996221167Sgnn#define VXGE_HAL_LAG_PORT_MIN_PARTNER_KEY 0 997221167Sgnn#define VXGE_HAL_LAG_PORT_MAX_PARTNER_KEY 65535 998221167Sgnn#define VXGE_HAL_LAG_PORT_DEF_PARTNER_KEY VXGE_HAL_USE_FLASH_DEFAULT 999221167Sgnn 1000221167Sgnn u32 partner_port_num; 1001221167Sgnn#define VXGE_HAL_LAG_PORT_MIN_PARTNER_PORT_NUM 0 1002221167Sgnn#define VXGE_HAL_LAG_PORT_MAX_PARTNER_PORT_NUM 65535 1003221167Sgnn#define VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_NUM VXGE_HAL_USE_FLASH_DEFAULT 1004221167Sgnn 1005221167Sgnn u32 partner_port_priority; 1006221167Sgnn#define VXGE_HAL_LAG_PORT_MIN_PARTNER_PORT_PRIORITY 0 1007221167Sgnn#define VXGE_HAL_LAG_PORT_MAX_PARTNER_PORT_PRIORITY 65535 1008221167Sgnn#define VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_PRIORITY VXGE_HAL_USE_FLASH_DEFAULT 1009221167Sgnn 1010221167Sgnn u32 partner_lacp_activity; 1011221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_PASSIVE 0 1012221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_ACTIVE 1 1013221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_DEFAULT \ 1014221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 1015221167Sgnn 1016221167Sgnn u32 partner_lacp_timeout; 1017221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_LONG 0 1018221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_SHORT 1 1019221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_DEFAULT \ 1020221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 1021221167Sgnn 1022221167Sgnn u32 partner_aggregation; 1023221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_INDIVIDUAL 0 1024221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_AGGREGATEABLE 1 1025221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_DEFAULT \ 1026221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 1027221167Sgnn 1028221167Sgnn u32 partner_synchronization; 1029221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_OUT_OF_SYNC 0 1030221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_IN_SYNC 1 1031221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_DEFAULT \ 1032221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 1033221167Sgnn 1034221167Sgnn u32 partner_collecting; 1035221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_DISABLE 0 1036221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_ENABLE 1 1037221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_DEFAULT \ 1038221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 1039221167Sgnn 1040221167Sgnn u32 partner_distributing; 1041221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DISABLE 0 1042221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_ENABLE 1 1043221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DEFAULT \ 1044221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 1045221167Sgnn 1046221167Sgnn u32 partner_defaulted; 1047221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_DEFAULTED 0 1048221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_NOT_DEFAULTED 1 1049221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_DEFAULTED_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1050221167Sgnn 1051221167Sgnn u32 partner_expired; 1052221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_EXPIRED 0 1053221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_NOT_EXPIRED 1 1054221167Sgnn#define VXGE_HAL_LAG_PORT_PARTNER_EXPIRED_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1055221167Sgnn 1056221167Sgnn macaddr_t partner_mac_addr; 1057221167Sgnn 1058221167Sgnn} vxge_hal_lag_port_config_t; 1059221167Sgnn 1060221167Sgnn/* 1061221167Sgnn * struct vxge_hal_lag_aggr_config_t - LAG Aggregator configuration 1062221167Sgnn * (For privileged mode driver only) 1063221167Sgnn * 1064221167Sgnn * @aggr_id: Aggregator Id 1065221167Sgnn * @mac_addr: The MAC address assigned to the Aggregator. 1066221167Sgnn * @use_port_mac_addr: Indicates whether the Aggregator should use: 1067221167Sgnn * 0 - the address specified in this register 1068221167Sgnn * 1 - the station address of one of the ports to which 1069221167Sgnn * it is attached 1070221167Sgnn * @mac_addr_sel: Indicates which port address to use, if use_port_mac_addr 1071221167Sgnn * is set and two ports are attached to the aggregator: 1072221167Sgnn * 0 - the station address of port 0 1073221167Sgnn * 1 - the station address of port 1. 1074221167Sgnn * @admin_key: The Aggregator's administrative Key under most circumstances 1075221167Sgnn * (see alt_admin_key for exceptions). The null (all zeros) Key 1076221167Sgnn * value is not available for local use. 1077221167Sgnn * This structure is configuration for LAG Aggregators of device 1078221167Sgnn */ 1079221167Sgnntypedef struct vxge_hal_lag_aggr_config_t { 1080221167Sgnn u32 aggr_id; 1081221167Sgnn#define VXGE_HAL_LAG_AGGR_AGGR_ID_1 1 1082221167Sgnn#define VXGE_HAL_LAG_AGGR_AGGR_ID_2 2 1083221167Sgnn#define VXGE_HAL_LAG_AGGR_MAX_PORTS VXGE_HAL_MAC_MAX_AGGR_PORTS 1084221167Sgnn 1085221167Sgnn macaddr_t mac_addr; 1086221167Sgnn 1087221167Sgnn u32 use_port_mac_addr; 1088221167Sgnn#define VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_DISBALE 0 1089221167Sgnn#define VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_ENABLE 1 1090221167Sgnn#define VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1091221167Sgnn 1092221167Sgnn u32 mac_addr_sel; 1093221167Sgnn#define VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_PORT_0 0 1094221167Sgnn#define VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_PORT_1 1 1095221167Sgnn#define VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1096221167Sgnn 1097221167Sgnn u32 admin_key; 1098221167Sgnn#define VXGE_HAL_LAG_AGGR_MIN_ADMIN_KEY 0 1099221167Sgnn#define VXGE_HAL_LAG_AGGR_MAX_ADMIN_KEY 65535 1100221167Sgnn#define VXGE_HAL_LAG_AGGR_DEF_ADMIN_KEY VXGE_HAL_USE_FLASH_DEFAULT 1101221167Sgnn 1102221167Sgnn} vxge_hal_lag_aggr_config_t; 1103221167Sgnn 1104221167Sgnn/* 1105221167Sgnn * struct vxge_hal_lag_la_config_t - LAG Link Aggregator mode configuration( 1106221167Sgnn * For privileged mode driver only) 1107221167Sgnn * 1108221167Sgnn * @tx_discard: When the state of the port state attached to the Tx Aggregator 1109221167Sgnn * is not Distributing, this field determines whether frames from 1110221167Sgnn * the Frame Distributor are discarded by the Aggregator Mux 1111221167Sgnn * @distrib_alg_sel: Configures the link aggregation distribution algorithm, 1112221167Sgnn * which determines the destination port of each wire-bound frame. 1113221167Sgnn * 0x0 - The source VPATH determines the target port and the 1114221167Sgnn * mapping is controlled by the MAP_VPATHn fields of this 1115221167Sgnn * register. 1116221167Sgnn * 0x1 - Even parity over the frame's MAC destination address 1117221167Sgnn * 0x2 - Even parity over the frame's MAC source address 1118221167Sgnn * 0x3 - Even parity over the frame's MAC destination address and 1119221167Sgnn * MAC source address 1120221167Sgnn * Note: If the host changes this mapping while traffic is flowing, 1121221167Sgnn * then (to avoid mis-ordering at the receiver) host must either 1122221167Sgnn * enable the Marker protocol or assume responsibility for ensuring 1123221167Sgnn * that no frames pertaining to the conversations (that are moving 1124221167Sgnn * to a new port) are in flight. 1125221167Sgnn * @distrib_dest: When LAG_TX_CFG.DISTRIB_ALG_SEL is set to use the source 1126221167Sgnn * VPATH, then this field indicates the target adapter port for 1127221167Sgnn * frames that come from a particular VPATH. 1128221167Sgnn * 0 - Send frames from this VPATH to port 0 1129221167Sgnn * 1 - Send frames from this VPATH to port 1 1130221167Sgnn * Note: If the host updates this mapping while traffic is flowing, 1131221167Sgnn * then (to avoid mis-ordering at the receiver) the host must 1132221167Sgnn * either enable the Marker protocol or assume responsibility for 1133221167Sgnn * ensuring that no frames pertaining to the conversations (that 1134221167Sgnn * are moving to a new port) are in flight. 1135221167Sgnn * @distrib_remap_if_fail: When lag_mode is Link Aggregated, this field controls 1136221167Sgnn * whether frames are re-distributed to the working port if one 1137221167Sgnn * port goes down. 1138221167Sgnn * 0 - Don't remap. Enforce frames destined for port 'x' to remain 1139221167Sgnn * destined for it and let LAG_CFG.TX_DISCARD_BEHAV determine 1140221167Sgnn * what happens to the frames. 1141221167Sgnn * 1 - Remap the frames to the working port, essentially ignoring 1142221167Sgnn * the mapping table. 1143221167Sgnn * @coll_max_delay: Collector Max Delay - the maximum amount of time (measured 1144221167Sgnn * in units of tens of microseconds) that the Frame Collector is 1145221167Sgnn * allowed to delay delivery of frames to the host. The contents 1146221167Sgnn * of this field are placed into the transmitted LACPDU. 1147221167Sgnn * @rx_discard: When the state of the port state attached to the Rx Aggregator 1148221167Sgnn * is not Collecting, this field determines whether frames to the 1149221167Sgnn * Frame Collector are discarded by the Aggregator Parser 1150221167Sgnn * 1151221167Sgnn * Link Aggregation Link Aggregator Mode Configuration 1152221167Sgnn */ 1153221167Sgnntypedef struct vxge_hal_lag_la_config_t { 1154221167Sgnn u32 tx_discard; 1155221167Sgnn#define VXGE_HAL_LAG_TX_DISCARD_DISBALE 0 1156221167Sgnn#define VXGE_HAL_LAG_TX_DISCARD_ENABLE 1 1157221167Sgnn#define VXGE_HAL_LAG_TX_DISCARD_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1158221167Sgnn 1159221167Sgnn u32 distrib_alg_sel; 1160221167Sgnn#define VXGE_HAL_LAG_DISTRIB_ALG_SEL_SRC_VPATH 0 1161221167Sgnn#define VXGE_HAL_LAG_DISTRIB_ALG_SEL_DEST_MAC_ADDR 1 1162221167Sgnn#define VXGE_HAL_LAG_DISTRIB_ALG_SEL_SRC_MAC_ADDR 2 1163221167Sgnn#define VXGE_HAL_LAG_DISTRIB_ALG_SEL_BOTH_MAC_ADDR 3 1164221167Sgnn#define VXGE_HAL_LAG_DISTRIB_ALG_SEL_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1165221167Sgnn 1166221167Sgnn u64 distrib_dest; 1167221167Sgnn#define VXGE_HAL_LAG_DISTRIB_DEST_VPATH_TO_PORT_PORT0(vpid) 0 1168221167Sgnn#define VXGE_HAL_LAG_DISTRIB_DEST_VPATH_TO_PORT_PORT1(vpid) mBIT(vpid) 1169221167Sgnn#define VXGE_HAL_LAG_DISTRIB_DEST_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1170221167Sgnn 1171221167Sgnn u32 distrib_remap_if_fail; 1172221167Sgnn#define VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_DISBALE 0 1173221167Sgnn#define VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_ENABLE 1 1174221167Sgnn#define VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1175221167Sgnn 1176221167Sgnn u32 coll_max_delay; 1177221167Sgnn#define VXGE_HAL_LAG_MIN_COLL_MAX_DELAY 0 1178221167Sgnn#define VXGE_HAL_LAG_MAX_COLL_MAX_DELAY 65535 1179221167Sgnn#define VXGE_HAL_LAG_DEF_COLL_MAX_DELAY VXGE_HAL_USE_FLASH_DEFAULT 1180221167Sgnn 1181221167Sgnn u32 rx_discard; 1182221167Sgnn#define VXGE_HAL_LAG_RX_DISCARD_DISBALE 0 1183221167Sgnn#define VXGE_HAL_LAG_RX_DISCARD_ENABLE 1 1184221167Sgnn#define VXGE_HAL_LAG_RX_DISCARD_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1185221167Sgnn 1186221167Sgnn 1187221167Sgnn} vxge_hal_lag_la_config_t; 1188221167Sgnn 1189221167Sgnn/* 1190221167Sgnn * struct vxge_hal_lag_ap_config_t - LAG Active Passive Failover mode 1191221167Sgnn * configuration(For privileged mode driver only) 1192221167Sgnn * 1193221167Sgnn * @hot_standby: Keep the standby port alive even when it is not carrying 1194221167Sgnn * traffic 1195221167Sgnn * 0 - Standby port disabled until needed. The hardware behaves as 1196221167Sgnn * if XGMAC_CFG_PORTn.PORT_EN has disabled the port. 1197221167Sgnn * 1 - Standby port kept up 1198221167Sgnn * @lacp_decides: This field determines whether or not the LACP Selection logic 1199221167Sgnn * handles hot standby port interaction. This field is only used 1200221167Sgnn * when hot_standby is 1. 1201221167Sgnn * 0 - LACP Selection logic does not explicitly determine standby 1202221167Sgnn * port, instead internal logic changes the aggregator's key 1203221167Sgnn * using information found in the alt_admin_key 1204221167Sgnn * field. Note that this does not disable LACP. 1205221167Sgnn * 1 - LACP Selection logic explicitly determines standby port by 1206221167Sgnn * enforcing a rule that if one port is already attached to any 1207221167Sgnn * aggregator, then the other port is put into STANDBY. Assuming 1208221167Sgnn * both ports have the same Key, at startup (or anytime both 1209221167Sgnn * ports have become UNSELECTED) the Selection logic uses 1210221167Sgnn * pref_active_port to choose the active (and consequently 1211221167Sgnn * standby) port. After that it only selects a new port when 1212221167Sgnn * the active port goes down. 1213221167Sgnn * @pref_active_port: Indicates the preferred active port number. 1214221167Sgnn * If hot_standby is disabled (i.e. "cold standby"), then 1215221167Sgnn * pref_active_port determines which port remains powered up 1216221167Sgnn * (and consequently which one is powered down). If hot_standby is 1217221167Sgnn * enabled, then pref_active_port is used by the Selection logic 1218221167Sgnn * whenever both ports have become UNSELECTED and the Selection 1219221167Sgnn * logic must decide which to make SELECTED and which to make 1220221167Sgnn * STANDBY. 1221221167Sgnn * 0 - Link0 is preferred (Link1 becomes the standby port). 1222221167Sgnn * 1 - Link1 is preferred 1223221167Sgnn * @auto_failback: When LACP Selection logic is not handling standby port 1224221167Sgnn * interaction, this register provides additional user flexibility 1225221167Sgnn * for standby port handling. The AUTO_FAILBACK field controls 1226221167Sgnn * whether the device automatically fails back to the preferred 1227221167Sgnn * (i.e. non-alternate) Aggregator+Port pair in the event that the 1228221167Sgnn * preferred port comes back up after a failure. Only used when 1229221167Sgnn * hot_standby is set to 1 and lacp_decides is set to 0. 1230221167Sgnn * 0 - After a failure on the preferred port, stay on alternate 1231221167Sgnn * port even if the preferred port comes back up. Return to 1232221167Sgnn * preferred port only when host indicates to return 1233221167Sgnn * (via FAILBACK_EN) 1234221167Sgnn * 1 - After a failure on the preferred port,automatically failback 1235221167Sgnn * to preferred port whenever it comes back up. 1236221167Sgnn * @failback_en: This field is used when hot_standby is set to 1,lacp_decides is 1237221167Sgnn * set to 0, and AUTO_FAILBACK is set to 0. The field is also used 1238221167Sgnn * when hot_standby is set to 0. The failback_en field allow the 1239221167Sgnn * host to control when the adapter is allowed to fail back to the 1240221167Sgnn * preferred port. The driver sets this field to indicate to the 1241221167Sgnn * adapter that it okay to fail back to the preferred port (i.e. 1242221167Sgnn * attempt to acquire a good port on the preferred port). This 1243221167Sgnn * field is self-clearing -- the adapter clears it immediately. 1244221167Sgnn * Note that the host can use waiting_to_fallback to tell if the 1245221167Sgnn * adapter is waiting for host intervention. 1246221167Sgnn * 0 - Adapter has acknowledged the request to fail back. 1247221167Sgnn * 1 - Host requests that the adapter fail back to preferred port. 1248221167Sgnn * @cold_failover_timeout: When cold standby mode is entered, this field 1249221167Sgnn * controls how long (in msec) the adapter waits for the preferred 1250221167Sgnn * port to come alive (assuming it isn't alreay alive. It the 1251221167Sgnn * preferred port does not come up, then the adapter fails over 1252221167Sgnn * to the standby port when the timer expires. At the time of 1253221167Sgnn * standby port initialization, the timer is started again and 1254221167Sgnn * if the standby port does not come up after the timer expires, 1255221167Sgnn * then both ports are shut down. 1256221167Sgnn * @alt_admin_key: The Aggregator's administrative Key whenever the device is in 1257221167Sgnn * active-passive failover mode and both ports are up. This 1258221167Sgnn * prevents both ports from becoming active in this case. 1259221167Sgnn * The H/W is responsible for choosing the proper key to use in 1260221167Sgnn * this case. The null (all zeros) Key value is not available for 1261221167Sgnn * local use. 1262221167Sgnn * @alt_aggr: Identifies which Aggregator is designated as the alternate 1263221167Sgnn * (i.e. unused) Aggregator, when both ports are up. 1264221167Sgnn * 0 - Aggregator0 is the alternate 1265221167Sgnn * 1 - Aggregator1 is the alternate 1266221167Sgnn * 1267221167Sgnn * Link Aggregation Active Passive failover mode Configuration 1268221167Sgnn */ 1269221167Sgnntypedef struct vxge_hal_lag_ap_config_t { 1270221167Sgnn u32 hot_standby; 1271221167Sgnn#define VXGE_HAL_LAG_HOT_STANDBY_DISBALE_PORT 0 1272221167Sgnn#define VXGE_HAL_LAG_HOT_STANDBY_KEEP_UP_PORT 1 1273221167Sgnn#define VXGE_HAL_LAG_HOT_STANDBY_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1274221167Sgnn 1275221167Sgnn u32 lacp_decides; 1276221167Sgnn#define VXGE_HAL_LAG_LACP_DECIDES_DISBALE 0 1277221167Sgnn#define VXGE_HAL_LAG_LACP_DECIDES_ENBALE 1 1278221167Sgnn#define VXGE_HAL_LAG_LACP_DECIDES_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1279221167Sgnn 1280221167Sgnn u32 pref_active_port; 1281221167Sgnn#define VXGE_HAL_LAG_PREF_ACTIVE_PORT_0 0 1282221167Sgnn#define VXGE_HAL_LAG_PREF_ACTIVE_PORT_1 1 1283221167Sgnn#define VXGE_HAL_LAG_PREF_ACTIVE_PORT_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1284221167Sgnn 1285221167Sgnn u32 auto_failback; 1286221167Sgnn#define VXGE_HAL_LAG_AUTO_FAILBACK_DISBALE 0 1287221167Sgnn#define VXGE_HAL_LAG_AUTO_FAILBACK_ENBALE 1 1288221167Sgnn#define VXGE_HAL_LAG_AUTO_FAILBACK_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1289221167Sgnn 1290221167Sgnn u32 failback_en; 1291221167Sgnn#define VXGE_HAL_LAG_FAILBACK_EN_DISBALE 0 1292221167Sgnn#define VXGE_HAL_LAG_FAILBACK_EN_ENBALE 1 1293221167Sgnn#define VXGE_HAL_LAG_FAILBACK_EN_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1294221167Sgnn 1295221167Sgnn u32 cold_failover_timeout; 1296221167Sgnn#define VXGE_HAL_LAG_MIN_COLD_FAILOVER_TIMEOUT 0 1297221167Sgnn#define VXGE_HAL_LAG_MAX_COLD_FAILOVER_TIMEOUT 65535 1298221167Sgnn#define VXGE_HAL_LAG_DEF_COLD_FAILOVER_TIMEOUT VXGE_HAL_USE_FLASH_DEFAULT 1299221167Sgnn 1300221167Sgnn u32 alt_admin_key; 1301221167Sgnn#define VXGE_HAL_LAG_MIN_ALT_ADMIN_KEY 0 1302221167Sgnn#define VXGE_HAL_LAG_MAX_ALT_ADMIN_KEY 65535 1303221167Sgnn#define VXGE_HAL_LAG_DEF_ALT_ADMIN_KEY VXGE_HAL_USE_FLASH_DEFAULT 1304221167Sgnn 1305221167Sgnn u32 alt_aggr; 1306221167Sgnn#define VXGE_HAL_LAG_ALT_AGGR_0 0 1307221167Sgnn#define VXGE_HAL_LAG_ALT_AGGR_1 1 1308221167Sgnn#define VXGE_HAL_LAG_ALT_AGGR_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1309221167Sgnn 1310221167Sgnn} vxge_hal_lag_ap_config_t; 1311221167Sgnn 1312221167Sgnn/* 1313221167Sgnn * struct vxge_hal_lag_sl_config_t - LAG Single Link configuration(For 1314221167Sgnn * privileged mode driver only) 1315221167Sgnn * 1316221167Sgnn * @pref_indiv_port: For Single Link mode, this field indicates the preferred 1317221167Sgnn * active port number. It is used by the Selection logic whenever 1318221167Sgnn * both ports have become UNSELECTED and the Selection logic must 1319221167Sgnn * decide which to make SELECTED and which to keep UNSELECTED. 1320221167Sgnn * This field is only valid when the MODE field is set to 1321221167Sgnn * 'Single Link'. 1322221167Sgnn * 1323221167Sgnn * Link Aggregation Single Link Configuration 1324221167Sgnn */ 1325221167Sgnntypedef struct vxge_hal_lag_sl_config_t { 1326221167Sgnn u32 pref_indiv_port; 1327221167Sgnn#define VXGE_HAL_LAG_PREF_INDIV_PORT_0 0 1328221167Sgnn#define VXGE_HAL_LAG_PREF_INDIV_PORT_1 1 1329221167Sgnn#define VXGE_HAL_LAG_PREF_INDIV_PORT_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1330221167Sgnn} vxge_hal_lag_sl_config_t; 1331221167Sgnn 1332221167Sgnn/* 1333221167Sgnn * struct vxge_hal_lag_lacp_config_t - LAG LACP configuration(For privileged 1334221167Sgnn * mode driver only) 1335221167Sgnn * 1336221167Sgnn * @lacp_en: Enables use of the on-chip LACP implementation. 1337221167Sgnn * @lacp_begin: Re-initializes the LACP protocol state machines. 1338221167Sgnn * @discard_lacp: If LACP is not enabled on the device, then all LACP frames 1339221167Sgnn * are passed to the host. However, when LACP is enabled,this field 1340221167Sgnn * determines whether the LACP frames are still passed to the host. 1341221167Sgnn * @liberal_len_chk: Controls the length checks that are performed on the 1342221167Sgnn * received LACPDU by the RX FSM. Normally, the received value of 1343221167Sgnn * the following length fields is a known constant and(as suggested 1344221167Sgnn * by IEEE 802.3-2005 43.4.12) the hardware validates them: 1345221167Sgnn * Actor_Information_Length, Partner_Information_Length, 1346221167Sgnn * Collector_Information_Length, and Terminator_Information_Length. 1347221167Sgnn * @marker_gen_recv_en: Enables marker generator/receiver. If this functionality 1348221167Sgnn * is disabled, then the host must assume responsibility for 1349221167Sgnn * ensuring that no frames pertaining to the conversations (that 1350221167Sgnn * are moving to a new port) are in flight, whenever the transmit 1351221167Sgnn * distribution algorithm is updated. 1352221167Sgnn * @marker_resp_en: Enables the transmission of Marker Response PDUs. Adapter 1353221167Sgnn * sends a Marker Response PDU in response to a received Marker PDU 1354221167Sgnn * @marker_resp_timeout: Timeout value for response to Marker frame - number 1355221167Sgnn * of milliseconds that the frame distribution logic will wait 1356221167Sgnn * before assuming that all frames transmitted on a particular 1357221167Sgnn * conversation have been successfully received. If a Marker 1358221167Sgnn * Response PDU comes back before the timer expires, then the 1359221167Sgnn * same assumption is made. 1360221167Sgnn * @slow_proto_mrkr_min_interval: Minimum interval (in milliseconds) between 1361221167Sgnn * Marker PDU transmissions. Includes both Marker PDUs and Marker 1362221167Sgnn * Response PDUs. According to IEEE 802.3-2005 Annex 43B.2, the 1363221167Sgnn * device should send no more than 10 frames in any one-second 1364221167Sgnn * period. Thus, waiting 100ms between successive transmission 1365221167Sgnn * of Slow Protocol frames for the Marker Protocol (i.e. those 1366221167Sgnn * that are sourced by our Marker Generator), guarantee that we 1367221167Sgnn * satisfy this requirement. To be overly conservative the default 1368221167Sgnn * value of this register allows for 200ms between frames. 1369221167Sgnn * @throttle_mrkr_resp: Permits the adapter to throttle the tranmission of 1370221167Sgnn * Marker Response PDUs to satisfy the Slow Protocols transmission 1371221167Sgnn * rate (see IEEE 802.3-2005 Annex 43B). 1372221167Sgnn * 0 - Transmission of Marker Response PDUs is not moderated. 1373221167Sgnn * A Marker Response PDU is sent in response to every received 1374221167Sgnn * Marker frame, regardless of whether the Marker frames are 1375221167Sgnn * being received at a rate below the Slow Protocols rate. 1376221167Sgnn * 1 - Limit the transmission of Marker Response PDUs to the Slow 1377221167Sgnn * Protocols transmission rate. If a remote host is generating 1378221167Sgnn * Marker frames too quickly, then some of these frames will 1379221167Sgnn * have no corresponding Marker Response PDU generated by the 1380221167Sgnn * adapter. 1381221167Sgnn * 1382221167Sgnn * Link Aggregation LACP Configuration 1383221167Sgnn */ 1384221167Sgnntypedef struct vxge_hal_lag_lacp_config_t { 1385221167Sgnn u32 lacp_en; 1386221167Sgnn#define VXGE_HAL_LAG_LACP_EN_DISBALE 0 1387221167Sgnn#define VXGE_HAL_LAG_LACP_EN_ENABLE 1 1388221167Sgnn#define VXGE_HAL_LAG_LACP_EN_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1389221167Sgnn 1390221167Sgnn u32 lacp_begin; 1391221167Sgnn#define VXGE_HAL_LAG_LACP_BEGIN_NORMAL 0 1392221167Sgnn#define VXGE_HAL_LAG_LACP_BEGIN_RESET 1 1393221167Sgnn#define VXGE_HAL_LAG_LACP_BEGIN_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1394221167Sgnn 1395221167Sgnn u32 discard_lacp; 1396221167Sgnn#define VXGE_HAL_LAG_DISCARD_LACP_DISBALE 0 1397221167Sgnn#define VXGE_HAL_LAG_DISCARD_LACP_ENABLE 1 1398221167Sgnn#define VXGE_HAL_LAG_DISCARD_LACP_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1399221167Sgnn 1400221167Sgnn u32 liberal_len_chk; 1401221167Sgnn#define VXGE_HAL_LAG_LIBERAL_LEN_CHK_DISBALE 0 1402221167Sgnn#define VXGE_HAL_LAG_LIBERAL_LEN_CHK_ENABLE 1 1403221167Sgnn#define VXGE_HAL_LAG_LIBERAL_LEN_CHK_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1404221167Sgnn 1405221167Sgnn u32 marker_gen_recv_en; 1406221167Sgnn#define VXGE_HAL_LAG_MARKER_GEN_RECV_EN_DISBALE 0 1407221167Sgnn#define VXGE_HAL_LAG_MARKER_GEN_RECV_EN_ENABLE 1 1408221167Sgnn#define VXGE_HAL_LAG_MARKER_GEN_RECV_EN_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1409221167Sgnn 1410221167Sgnn u32 marker_resp_en; 1411221167Sgnn#define VXGE_HAL_LAG_MARKER_RESP_EN_DISBALE 0 1412221167Sgnn#define VXGE_HAL_LAG_MARKER_RESP_EN_ENABLE 1 1413221167Sgnn#define VXGE_HAL_LAG_MARKER_RESP_EN_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1414221167Sgnn 1415221167Sgnn u32 marker_resp_timeout; 1416221167Sgnn#define VXGE_HAL_LAG_MIN_MARKER_RESP_TIMEOUT 0 1417221167Sgnn#define VXGE_HAL_LAG_MAX_MARKER_RESP_TIMEOUT 65535 1418221167Sgnn#define VXGE_HAL_LAG_DEF_MARKER_RESP_TIMEOUT VXGE_HAL_USE_FLASH_DEFAULT 1419221167Sgnn 1420221167Sgnn u32 slow_proto_mrkr_min_interval; 1421221167Sgnn#define VXGE_HAL_LAG_MIN_SLOW_PROTO_MRKR_MIN_INTERVAL 0 1422221167Sgnn#define VXGE_HAL_LAG_MAX_SLOW_PROTO_MRKR_MIN_INTERVAL 65535 1423221167Sgnn#define VXGE_HAL_LAG_DEF_SLOW_PROTO_MRKR_MIN_INTERVAL \ 1424221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 1425221167Sgnn 1426221167Sgnn u32 throttle_mrkr_resp; 1427221167Sgnn#define VXGE_HAL_LAG_THROTTLE_MRKR_RESP_DISBALE 0 1428221167Sgnn#define VXGE_HAL_LAG_THROTTLE_MRKR_RESP_ENABLE 1 1429221167Sgnn#define VXGE_HAL_LAG_THROTTLE_MRKR_RESP_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1430221167Sgnn 1431221167Sgnn} vxge_hal_lag_lacp_config_t; 1432221167Sgnn 1433221167Sgnn/* 1434221167Sgnn * struct vxge_hal_lag_config_t - LAG configuration(For privileged 1435221167Sgnn * mode driver only) 1436221167Sgnn * 1437221167Sgnn * @lag_en: Enables link aggregation 1438221167Sgnn * @lag_mode: Select the mode of operation for link aggregation. The options: 1439221167Sgnn * 00 - Link Aggregated 1440221167Sgnn * 01 - Active/Passive Failover 1441221167Sgnn * 10 - Single Link 1442221167Sgnn * @la_mode_config: LAG Link Aggregator mode config 1443221167Sgnn * @ap_mode_config: LAG Active Passive Failover mode config 1444221167Sgnn * @sl_mode_config: LAG Single Link mode config 1445221167Sgnn * @lacp_config: LAG LACP config 1446221167Sgnn * @incr_tx_aggr_stats: Controls whether Tx aggregator stats are incremented 1447221167Sgnn * when Link Aggregation is disabled. 1448221167Sgnn * 0 - Don't increment 1449221167Sgnn * 1 - Increment 1450221167Sgnn * Note: When LAG is enabled, aggregator stats are always 1451221167Sgnn * incremented. 1452221167Sgnn * @port_config: Lag Port configuration. See vxge_hal_lag_port_config_t {} 1453221167Sgnn * @aggr_config: Lag Aggregator configuration. See vxge_hal_lag_aggr_config_t {} 1454221167Sgnn * @sys_pri: The System Priority of the System. Numerically lower values have 1455221167Sgnn * higher priority. 1456221167Sgnn * @mac_addr: The MAC address assigned to the System. Should be non-zero. 1457221167Sgnn * @use_port_mac_addr: Indicates whether the Aggregator should use: 1458221167Sgnn * 0 - the address specified in this register. 1459221167Sgnn * 1 - the station address of one of the ports in the System 1460221167Sgnn * @mac_addr_sel: Indicates which port address to use, if USE_PORT_ADDR is set: 1461221167Sgnn * 0 - the station address of port 0 1462221167Sgnn * 1 - the station address of port 1. 1463221167Sgnn * @fast_per_time: Fast Periodic Time - number of seconds between periodic 1464221167Sgnn * transmissions of Short Timeouts. 1465221167Sgnn * @slow_per_time: Slow Periodic Time - number of seconds between periodic 1466221167Sgnn * transmissions of Long Timeouts. 1467221167Sgnn * @short_timeout: Short Timeout Time - number of seconds before 1468221167Sgnn * invalidating received LACPDU information using Short 1469221167Sgnn * Timeouts (3 x Fast Periodic Time). 1470221167Sgnn * @long_timeout: Long Timeout Time - number of seconds before invalidating 1471221167Sgnn * received LACPDU information using Long Timeouts 1472221167Sgnn * (3 x Slow Periodic Time). 1473221167Sgnn * @churn_det_time: Churn Detection Time - number of seconds that the 1474221167Sgnn * Actor and Partner Churn state machines wait for the Actor 1475221167Sgnn * or Partner Sync state to stabilize. 1476221167Sgnn * @aggr_wait_time: Aggregate Wait Time - number of seconds to delay 1477221167Sgnn * aggregation,to allow multiple links to aggregate simultaneously 1478221167Sgnn * @short_timer_scale: For simulation purposes, this field allows scaling of 1479221167Sgnn * link aggregation timers. Specifically, the included timers are 1480221167Sgnn * short (programmed with units of msec) and include 'Emptied Link 1481221167Sgnn * Timer', 'Slow Proto Timer for Marker PDU', 'Slow Proto Timer for 1482221167Sgnn * Marker Response PDU', and 'Cold Failover Timer'. 1483221167Sgnn * 0x0 - No scaling 1484221167Sgnn * 0x1 - Scale by 10X (counter expires 10 times faster) 1485221167Sgnn * 0x2 - Scale by 100X 1486221167Sgnn * 0x3 - Scale by 1000X 1487221167Sgnn * @long_timer_scale: For simulation purposes, this field allows scaling of link 1488221167Sgnn * aggregation timers. Specifically, the included timers are long 1489221167Sgnn * (programmed with units of seconds) and include 'Current While 1490221167Sgnn * Timer', 'Periodic Timer', 'Wait While Timer', 'Transmit LACP 1491221167Sgnn * Timer', 'Actor Churn Timer', 'Partner Churn Timer', 1492221167Sgnn * 0x0 - No scaling 1493221167Sgnn * 0x1 - Scale by 10X (counter expires 10 times faster) 1494221167Sgnn * 0x2 - Scale by 100X 1495221167Sgnn * 0x3 - Scale by 1000X 1496221167Sgnn * 0x4 - Scale by 10000X 1497221167Sgnn * 0x5 - Scale by 100000X 1498221167Sgnn * 0x6 - Scale by 1000000X 1499221167Sgnn * 1500221167Sgnn * Link Aggregation Configuration 1501221167Sgnn */ 1502221167Sgnntypedef struct vxge_hal_lag_config_t { 1503221167Sgnn u32 lag_en; 1504221167Sgnn#define VXGE_HAL_LAG_LAG_EN_DISABLE 0 1505221167Sgnn#define VXGE_HAL_LAG_LAG_EN_ENABLE 1 1506221167Sgnn#define VXGE_HAL_LAG_LAG_EN_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1507221167Sgnn 1508221167Sgnn u32 lag_mode; 1509221167Sgnn#define VXGE_HAL_LAG_LAG_MODE_LAG 0 1510221167Sgnn#define VXGE_HAL_LAG_LAG_MODE_ACTIVE_PASSIVE_FAILOVER 1 1511221167Sgnn#define VXGE_HAL_LAG_LAG_MODE_SINGLE_LINK 2 1512221167Sgnn#define VXGE_HAL_LAG_LAG_MODE_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1513221167Sgnn 1514221167Sgnn vxge_hal_lag_la_config_t la_mode_config; 1515221167Sgnn vxge_hal_lag_ap_config_t ap_mode_config; 1516221167Sgnn vxge_hal_lag_sl_config_t sl_mode_config; 1517221167Sgnn vxge_hal_lag_lacp_config_t lacp_config; 1518221167Sgnn 1519221167Sgnn u32 incr_tx_aggr_stats; 1520221167Sgnn#define VXGE_HAL_LAG_INCR_TX_AGGR_STATS_DISBALE 0 1521221167Sgnn#define VXGE_HAL_LAG_INCR_TX_AGGR_STATS_ENABLE 1 1522221167Sgnn#define VXGE_HAL_LAG_INCR_TX_AGGR_STATS_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1523221167Sgnn 1524221167Sgnn vxge_hal_lag_port_config_t port_config[VXGE_HAL_LAG_PORT_MAX_PORTS]; 1525221167Sgnn vxge_hal_lag_aggr_config_t aggr_config[VXGE_HAL_LAG_AGGR_MAX_PORTS]; 1526221167Sgnn 1527221167Sgnn u32 sys_pri; 1528221167Sgnn#define VXGE_HAL_LAG_MIN_SYS_PRI 0 1529221167Sgnn#define VXGE_HAL_LAG_MAX_SYS_PRI 65535 1530221167Sgnn#define VXGE_HAL_LAG_DEF_SYS_PRI VXGE_HAL_USE_FLASH_DEFAULT 1531221167Sgnn 1532221167Sgnn macaddr_t mac_addr; 1533221167Sgnn 1534221167Sgnn u32 use_port_mac_addr; 1535221167Sgnn#define VXGE_HAL_LAG_USE_PORT_MAC_ADDR_DISBALE 0 1536221167Sgnn#define VXGE_HAL_LAG_USE_PORT_MAC_ADDR_ENABLE 1 1537221167Sgnn#define VXGE_HAL_LAG_USE_PORT_MAC_ADDR_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1538221167Sgnn 1539221167Sgnn u32 mac_addr_sel; 1540221167Sgnn#define VXGE_HAL_LAG_MAC_ADDR_SEL_PORT_0 0 1541221167Sgnn#define VXGE_HAL_LAG_MAC_ADDR_SEL_PORT_1 1 1542221167Sgnn#define VXGE_HAL_LAG_MAC_ADDR_SEL_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1543221167Sgnn 1544221167Sgnn u32 fast_per_time; 1545221167Sgnn#define VXGE_HAL_LAG_MIN_FAST_PER_TIME 0 1546221167Sgnn#define VXGE_HAL_LAG_MAX_FAST_PER_TIME 65535 1547221167Sgnn#define VXGE_HAL_LAG_DEF_FAST_PER_TIME VXGE_HAL_USE_FLASH_DEFAULT 1548221167Sgnn 1549221167Sgnn u32 slow_per_time; 1550221167Sgnn#define VXGE_HAL_LAG_MIN_SLOW_PER_TIME 0 1551221167Sgnn#define VXGE_HAL_LAG_MAX_SLOW_PER_TIME 65535 1552221167Sgnn#define VXGE_HAL_LAG_DEF_SLOW_PER_TIME VXGE_HAL_USE_FLASH_DEFAULT 1553221167Sgnn 1554221167Sgnn u32 short_timeout; 1555221167Sgnn#define VXGE_HAL_LAG_MIN_SHORT_TIMEOUT 0 1556221167Sgnn#define VXGE_HAL_LAG_MAX_SHORT_TIMEOUT 65535 1557221167Sgnn#define VXGE_HAL_LAG_DEF_SHORT_TIMEOUT VXGE_HAL_USE_FLASH_DEFAULT 1558221167Sgnn 1559221167Sgnn u32 long_timeout; 1560221167Sgnn#define VXGE_HAL_LAG_MIN_LONG_TIMEOUT 0 1561221167Sgnn#define VXGE_HAL_LAG_MAX_LONG_TIMEOUT 65535 1562221167Sgnn#define VXGE_HAL_LAG_DEF_LONG_TIMEOUT VXGE_HAL_USE_FLASH_DEFAULT 1563221167Sgnn 1564221167Sgnn u32 churn_det_time; 1565221167Sgnn#define VXGE_HAL_LAG_MIN_CHURN_DET_TIME 0 1566221167Sgnn#define VXGE_HAL_LAG_MAX_CHURN_DET_TIME 65535 1567221167Sgnn#define VXGE_HAL_LAG_DEF_CHURN_DET_TIME VXGE_HAL_USE_FLASH_DEFAULT 1568221167Sgnn 1569221167Sgnn u32 aggr_wait_time; 1570221167Sgnn#define VXGE_HAL_LAG_MIN_AGGR_WAIT_TIME 0 1571221167Sgnn#define VXGE_HAL_LAG_MAX_AGGR_WAIT_TIME 65535 1572221167Sgnn#define VXGE_HAL_LAG_DEF_AGGR_WAIT_TIME VXGE_HAL_USE_FLASH_DEFAULT 1573221167Sgnn 1574221167Sgnn u32 short_timer_scale; 1575221167Sgnn#define VXGE_HAL_LAG_SHORT_TIMER_SCALE_1X 0 1576221167Sgnn#define VXGE_HAL_LAG_SHORT_TIMER_SCALE_10X 1 1577221167Sgnn#define VXGE_HAL_LAG_SHORT_TIMER_SCALE_100X 2 1578221167Sgnn#define VXGE_HAL_LAG_SHORT_TIMER_SCALE_1000X 3 1579221167Sgnn#define VXGE_HAL_LAG_SHORT_TIMER_SCALE_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1580221167Sgnn 1581221167Sgnn u32 long_timer_scale; 1582221167Sgnn#define VXGE_HAL_LAG_LONG_TIMER_SCALE_1X 0 1583221167Sgnn#define VXGE_HAL_LAG_LONG_TIMER_SCALE_10X 1 1584221167Sgnn#define VXGE_HAL_LAG_LONG_TIMER_SCALE_100X 2 1585221167Sgnn#define VXGE_HAL_LAG_LONG_TIMER_SCALE_1000X 3 1586221167Sgnn#define VXGE_HAL_LAG_LONG_TIMER_SCALE_10000X 4 1587221167Sgnn#define VXGE_HAL_LAG_LONG_TIMER_SCALE_100000X 5 1588221167Sgnn#define VXGE_HAL_LAG_LONG_TIMER_SCALE_1000000X 6 1589221167Sgnn#define VXGE_HAL_LAG_LONG_TIMER_SCALE_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1590221167Sgnn 1591221167Sgnn} vxge_hal_lag_config_t; 1592221167Sgnn 1593221167Sgnn/* 1594221167Sgnn * struct vxge_hal_vpath_qos_config_t - Vpath qos(For privileged 1595221167Sgnn * mode driver only) 1596221167Sgnn * @priority: The priority of vpath 1597221167Sgnn * @min_bandwidth: Minimum Guaranteed bandwidth 1598221167Sgnn * @max_bandwidth: Maximum allowed bandwidth 1599221167Sgnn * 1600221167Sgnn * This structure is vpath qos configuration for MRPCIM section of device 1601221167Sgnn */ 1602221167Sgnntypedef struct vxge_hal_vpath_qos_config_t { 1603221167Sgnn u32 priority; 1604221167Sgnn#define VXGE_HAL_VPATH_QOS_PRIORITY_MIN 0 1605221167Sgnn#define VXGE_HAL_VPATH_QOS_PRIORITY_MAX 16 1606221167Sgnn#define VXGE_HAL_VPATH_QOS_PRIORITY_DEFAULT 0 1607221167Sgnn 1608221167Sgnn u32 min_bandwidth; 1609221167Sgnn#define VXGE_HAL_VPATH_QOS_MIN_BANDWIDTH_MIN 0 1610221167Sgnn#define VXGE_HAL_VPATH_QOS_MIN_BANDWIDTH_MAX 100 1611221167Sgnn#define VXGE_HAL_VPATH_QOS_MIN_BANDWIDTH_DEFAULT 0 1612221167Sgnn 1613221167Sgnn u32 max_bandwidth; 1614221167Sgnn#define VXGE_HAL_VPATH_QOS_MAX_BANDWIDTH_MIN 0 1615221167Sgnn#define VXGE_HAL_VPATH_QOS_MAX_BANDWIDTH_MAX 100 1616221167Sgnn#define VXGE_HAL_VPATH_QOS_MAX_BANDWIDTH_DEFAULT 0 1617221167Sgnn 1618221167Sgnn} vxge_hal_vpath_qos_config_t; 1619221167Sgnn 1620221167Sgnn/* 1621221167Sgnn * struct vxge_hal_mrpcim_config_t - MRPCIM secion configuration(For privileged 1622221167Sgnn * mode driver only) 1623221167Sgnn * 1624221167Sgnn * @mac_config: MAC Port Config. See vxge_hal_mac_config_t {} 1625221167Sgnn * @lag_config: MAC Port Config. See vxge_hal_lag_config_t {} 1626221167Sgnn * @vp_qos: Vpath QOS 1627221167Sgnn * @vpath_to_wire_port_map_en: Mask to enable vpath to wire port mapping. 1628221167Sgnn * @vpath_to_wire_port_map: If LAG is not enabled or lag_distrib_dest is not set 1629221167Sgnn * then vpath_to_wire_port_map is used to assign independent ports 1630221167Sgnn * to vpath 1631221167Sgnn * 1632221167Sgnn * This structure is configuration for MRPCIM section of device 1633221167Sgnn */ 1634221167Sgnntypedef struct vxge_hal_mrpcim_config_t { 1635221167Sgnn vxge_hal_mac_config_t mac_config; 1636221167Sgnn vxge_hal_lag_config_t lag_config; 1637221167Sgnn u64 vpath_to_wire_port_map_en; 1638221167Sgnn#define VXGE_HAL_VPATH_TO_WIRE_PORT_MAP_EN_DISABLE(vpid) 0 1639221167Sgnn#define VXGE_HAL_VPATH_TO_WIRE_PORT_MAP_EN_ENABLE(vpid) mBIT(vpid) 1640221167Sgnn#define VXGE_HAL_VPATH_WIRE_PORTS_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1641221167Sgnn u64 vpath_to_wire_port_map; 1642221167Sgnn#define VXGE_HAL_VPATH_TO_WIRE_PORT_MAP_PORT0(vpid) 0 1643221167Sgnn#define VXGE_HAL_VPATH_TO_WIRE_PORT_MAP_PORT1(vpid) mBIT(vpid) 1644221167Sgnn#define VXGE_HAL_VPATH_TO_WIRE_PORT_MAP_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1645221167Sgnn vxge_hal_vpath_qos_config_t vp_qos[VXGE_HAL_MAX_VIRTUAL_PATHS]; 1646221167Sgnn} vxge_hal_mrpcim_config_t; 1647221167Sgnn 1648221167Sgnn/* 1649221167Sgnn * struct vxge_hal_tim_intr_config_t - X3100 Tim interrupt configuration. 1650221167Sgnn * @intr_enable: Set to 1, if interrupt is enabled. 1651221167Sgnn * @btimer_val: Boundary Timer Initialization value in units of 272 ns. 1652221167Sgnn * @timer_ac_en: Timer Automatic Cancel. 1 : Automatic Canceling Enable: when 1653221167Sgnn * asserted, other interrupt-generating entities will cancel the 1654221167Sgnn * scheduled timer interrupt. 1655221167Sgnn * @timer_ci_en: Timer Continuous Interrupt. 1 : Continuous Interrupting Enable: 1656221167Sgnn * When asserted, an interrupt will be generated every time the 1657221167Sgnn * boundary timer expires, even if no traffic has been transmitted 1658221167Sgnn * on this interrupt. 1659221167Sgnn * @timer_ri_en: Timer Consecutive (Re-) Interrupt 1 : Consecutive 1660221167Sgnn * (Re-) Interrupt Enable: When asserted, an interrupt will be 1661221167Sgnn * generated the next time the timer expires,even if no traffic has 1662221167Sgnn * been transmitted on this interrupt. (This will only happen once 1663221167Sgnn * each time that this value is written to the TIM.) This bit is 1664221167Sgnn * cleared by H/W at the end of the current-timer-interval when 1665221167Sgnn * the interrupt is triggered. 1666221167Sgnn * @rtimer_event_sf: Restriction Timer Event Scale Factor. A scale factor that 1667221167Sgnn * is to be applied to the current event count before it is added 1668226436Seadler * to the restriction timer value when the restriction timer 1669221167Sgnn * is started. 1670221167Sgnn * The scale factor is applied as a right or left shift to multiply 1671221167Sgnn * or divide by the event count. The programmable values are as 1672221167Sgnn * follows: 1673221167Sgnn * 0-disable restriction timer and use the base timer value. 1674221167Sgnn * 1-Multiply the event count by 2, shift left by 1. 1675221167Sgnn * 2-Multiply the event count by 4, shift left by 2. 1676221167Sgnn * 3-Multiply the event count by 8, shift left by 3. 1677221167Sgnn * 4-Multiply the event count by 16, shift left by 4. 1678221167Sgnn * 5-Multiply the event count by 32, shift left by 5. 1679221167Sgnn * 6-Multiply the event count by 64, shift left by 6. 1680221167Sgnn * 7-Multiply the event count by 128, shift left by 7. 1681221167Sgnn * 8-add the event count, no shifting. 1682221167Sgnn * 9-Divide the event count by 128, shift right by 7. 1683221167Sgnn * 10-Divide the event count by 64, shift right by 6. 1684221167Sgnn * 11-Divide the event count by 32, shift right by 5. 1685221167Sgnn * 12-Divide the event count by 16, shift right by 4. 1686221167Sgnn * 13-Divide the event count by 8, shift right by 3. 1687221167Sgnn * 14-Divide the event count by 4, shift right by 2. 1688221167Sgnn * 15-Divide the event count by 2, shift right by 1. 1689221167Sgnn * @rtimer_val: Restriction Timer Initialization value in units of 272 ns. 1690221167Sgnn * @util_sel: Utilization Selector. Selects which of the workload approximations 1691221167Sgnn * to use (e.g. legacy Tx utilization, Tx/Rx utilization, host 1692221167Sgnn * specified utilization etc.),selects one of the 17 host 1693221167Sgnn * configured values. 1694221167Sgnn * 0-Virtual Path 0 1695221167Sgnn * 1-Virtual Path 1 1696221167Sgnn * ... 1697221167Sgnn * 16-Virtual Path 17 1698221167Sgnn * 17-Legacy Tx network utilization, provided by TPA 1699221167Sgnn * 18-Legacy Rx network utilization, provided by FAU 1700221167Sgnn * 19-Average of legacy Rx and Tx utilization calculated from link 1701221167Sgnn * utilization values. 1702221167Sgnn * 20-31-Invalid configurations 1703221167Sgnn * 32-Host utilization for Virtual Path 0 1704221167Sgnn * 33-Host utilization for Virtual Path 1 1705221167Sgnn * ... 1706221167Sgnn * 48-Host utilization for Virtual Path 17 1707221167Sgnn * 49-Legacy Tx network utilization, provided by TPA 1708221167Sgnn * 50-Legacy Rx network utilization, provided by FAU 1709221167Sgnn * 51-Average of legacy Rx and Tx utilization calculated from 1710221167Sgnn * link utilization values. 1711221167Sgnn * 52-63-Invalid configurations 1712221167Sgnn * @ltimer_val: Latency Timer Initialization Value in units of 272 ns. 1713221167Sgnn * @txfrm_cnt_en: Transmit Frame Event Count Enable. This configuration bit 1714221167Sgnn * when set to 1 enables counting of transmit frame's(signalled by 1715221167Sgnn * SM), towards utilization event count values. 1716221167Sgnn * @txd_cnt_en: TxD Return Event Count Enable. This configuration bit when set 1717221167Sgnn * to 1 enables counting of TxD0 returns (signalled by PCC's), 1718221167Sgnn * towards utilization event count values. 1719221167Sgnn * @urange_a: Defines the upper limit (in percent) for this utilization range 1720221167Sgnn * to be active. This range is considered active 1721221167Sgnn * if 0 = UTIL = URNG_A and the UEC_A field (below) is non-zero. 1722221167Sgnn * @uec_a: Utilization Event Count A. If this range is active, the adapter will 1723221167Sgnn * wait until UEC_A events have occurred on the interrupt before 1724221167Sgnn * generating an interrupt. 1725221167Sgnn * @urange_b: Link utilization range B. 1726221167Sgnn * @uec_b: Utilization Event Count B. 1727221167Sgnn * @urange_c: Link utilization range C. 1728221167Sgnn * @uec_c: Utilization Event Count C. 1729221167Sgnn * @urange_d: Link utilization range D. 1730221167Sgnn * @uec_d: Utilization Event Count D. 1731221167Sgnn * @ufca_intr_thres 1732221167Sgnn * @ufca_lo_lim 1733221167Sgnn * @ufca_hi_lim 1734221167Sgnn * @ufca_lbolt_period: 1735221167Sgnn * 1736221167Sgnn * Traffic Interrupt Controller Module interrupt configuration. 1737221167Sgnn */ 1738221167Sgnntypedef struct vxge_hal_tim_intr_config_t { 1739221167Sgnn 1740221167Sgnn u32 intr_enable; 1741221167Sgnn#define VXGE_HAL_TIM_INTR_ENABLE 1 1742221167Sgnn#define VXGE_HAL_TIM_INTR_DISABLE 0 1743221167Sgnn#define VXGE_HAL_TIM_INTR_DEFAULT 0 1744221167Sgnn 1745221167Sgnn u32 btimer_val; 1746221167Sgnn#define VXGE_HAL_MIN_TIM_BTIMER_VAL 0 1747221167Sgnn#define VXGE_HAL_MAX_TIM_BTIMER_VAL 67108864 1748221167Sgnn#define VXGE_HAL_USE_FLASH_DEFAULT_TIM_BTIMER_VAL VXGE_HAL_USE_FLASH_DEFAULT 1749221167Sgnn 1750221167Sgnn u32 timer_ac_en; 1751221167Sgnn#define VXGE_HAL_TIM_TIMER_AC_ENABLE 1 1752221167Sgnn#define VXGE_HAL_TIM_TIMER_AC_DISABLE 0 1753221167Sgnn#define VXGE_HAL_TIM_TIMER_AC_USE_FLASH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1754221167Sgnn 1755221167Sgnn u32 timer_ci_en; 1756221167Sgnn#define VXGE_HAL_TIM_TIMER_CI_ENABLE 1 1757221167Sgnn#define VXGE_HAL_TIM_TIMER_CI_DISABLE 0 1758221167Sgnn#define VXGE_HAL_TIM_TIMER_CI_USE_FLASH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1759221167Sgnn 1760221167Sgnn u32 timer_ri_en; 1761221167Sgnn#define VXGE_HAL_TIM_TIMER_RI_ENABLE 1 1762221167Sgnn#define VXGE_HAL_TIM_TIMER_RI_DISABLE 0 1763221167Sgnn#define VXGE_HAL_TIM_TIMER_RI_USE_FLASH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1764221167Sgnn 1765221167Sgnn u32 rtimer_event_sf; 1766221167Sgnn#define VXGE_HAL_MIN_TIM_RTIMER_EVENT_SF 0 1767221167Sgnn#define VXGE_HAL_MAX_TIM_RTIMER_EVENT_SF 15 1768221167Sgnn#define VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_EVENT_SF \ 1769221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 1770221167Sgnn 1771221167Sgnn u32 rtimer_val; 1772221167Sgnn#define VXGE_HAL_MIN_TIM_RTIMER_VAL 0 1773221167Sgnn#define VXGE_HAL_MAX_TIM_RTIMER_VAL 67108864 1774221167Sgnn#define VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_VAL VXGE_HAL_USE_FLASH_DEFAULT 1775221167Sgnn 1776221167Sgnn u32 util_sel; 1777221167Sgnn#define VXGE_HAL_TIM_UTIL_SEL_VPATH(n) n 1778221167Sgnn#define VXGE_HAL_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL 17 1779221167Sgnn#define VXGE_HAL_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL 18 1780221167Sgnn#define VXGE_HAL_TIM_UTIL_SEL_LEGACY_TX_RX_AVE_NET_UTIL 19 1781221167Sgnn#define VXGE_HAL_TIM_UTIL_SEL_VPATH(n) n 1782221167Sgnn#define VXGE_HAL_TIM_UTIL_SEL_VPATH(n) n 1783221167Sgnn#define VXGE_HAL_TIM_UTIL_SEL_HOST_UTIL_VPATH(n) (32+n) 1784221167Sgnn#define VXGE_HAL_TIM_UTIL_SEL_TIM_UTIL_VPATH(n) 63 1785221167Sgnn#define VXGE_HAL_TIM_UTIL_SEL_USE_FLASH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1786221167Sgnn 1787221167Sgnn u32 ltimer_val; 1788221167Sgnn#define VXGE_HAL_MIN_TIM_LTIMER_VAL 0 1789221167Sgnn#define VXGE_HAL_MAX_TIM_LTIMER_VAL 67108864 1790221167Sgnn#define VXGE_HAL_USE_FLASH_DEFAULT_TIM_LTIMER_VAL VXGE_HAL_USE_FLASH_DEFAULT 1791221167Sgnn 1792221167Sgnn /* Line utilization interrupts */ 1793221167Sgnn u32 txfrm_cnt_en; 1794221167Sgnn#define VXGE_HAL_TXFRM_CNT_EN_ENABLE 1 1795221167Sgnn#define VXGE_HAL_TXFRM_CNT_EN_DISABLE 0 1796221167Sgnn#define VXGE_HAL_TXFRM_CNT_EN_USE_FLASH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1797221167Sgnn 1798221167Sgnn u32 txd_cnt_en; 1799221167Sgnn#define VXGE_HAL_TXD_CNT_EN_ENABLE 1 1800221167Sgnn#define VXGE_HAL_TXD_CNT_EN_DISABLE 0 1801221167Sgnn#define VXGE_HAL_TXD_CNT_EN_USE_FLASH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1802221167Sgnn 1803221167Sgnn u32 urange_a; 1804221167Sgnn#define VXGE_HAL_MIN_TIM_URANGE_A 0 1805221167Sgnn#define VXGE_HAL_MAX_TIM_URANGE_A 100 1806221167Sgnn#define VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_A VXGE_HAL_USE_FLASH_DEFAULT 1807221167Sgnn 1808221167Sgnn u32 uec_a; 1809221167Sgnn#define VXGE_HAL_MIN_TIM_UEC_A 0 1810221167Sgnn#define VXGE_HAL_MAX_TIM_UEC_A 65535 1811221167Sgnn#define VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_A VXGE_HAL_USE_FLASH_DEFAULT 1812221167Sgnn 1813221167Sgnn u32 urange_b; 1814221167Sgnn#define VXGE_HAL_MIN_TIM_URANGE_B 0 1815221167Sgnn#define VXGE_HAL_MAX_TIM_URANGE_B 100 1816221167Sgnn#define VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_B VXGE_HAL_USE_FLASH_DEFAULT 1817221167Sgnn 1818221167Sgnn u32 uec_b; 1819221167Sgnn#define VXGE_HAL_MIN_TIM_UEC_B 0 1820221167Sgnn#define VXGE_HAL_MAX_TIM_UEC_B 65535 1821221167Sgnn#define VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_B VXGE_HAL_USE_FLASH_DEFAULT 1822221167Sgnn 1823221167Sgnn u32 urange_c; 1824221167Sgnn#define VXGE_HAL_MIN_TIM_URANGE_C 0 1825221167Sgnn#define VXGE_HAL_MAX_TIM_URANGE_C 100 1826221167Sgnn#define VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_C VXGE_HAL_USE_FLASH_DEFAULT 1827221167Sgnn 1828221167Sgnn u32 uec_c; 1829221167Sgnn#define VXGE_HAL_MIN_TIM_UEC_C 0 1830221167Sgnn#define VXGE_HAL_MAX_TIM_UEC_C 65535 1831221167Sgnn#define VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_C VXGE_HAL_USE_FLASH_DEFAULT 1832221167Sgnn 1833221167Sgnn u32 uec_d; 1834221167Sgnn#define VXGE_HAL_MIN_TIM_UEC_D 0 1835221167Sgnn#define VXGE_HAL_MAX_TIM_UEC_D 65535 1836221167Sgnn#define VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_D VXGE_HAL_USE_FLASH_DEFAULT 1837221167Sgnn 1838221167Sgnn u32 ufca_intr_thres; 1839221167Sgnn#define VXGE_HAL_MIN_UFCA_INTR_THRES 1 1840221167Sgnn#define VXGE_HAL_MAX_UFCA_INTR_THRES 4096 1841221167Sgnn#define VXGE_HAL_USE_FLASH_DEFAULT_UFCA_INTR_THRES VXGE_HAL_USE_FLASH_DEFAULT 1842221167Sgnn 1843221167Sgnn u32 ufca_lo_lim; 1844221167Sgnn#define VXGE_HAL_MIN_UFCA_LO_LIM 1 1845221167Sgnn#define VXGE_HAL_MAX_UFCA_LO_LIM 16 1846221167Sgnn#define VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LO_LIM VXGE_HAL_USE_FLASH_DEFAULT 1847221167Sgnn 1848221167Sgnn u32 ufca_hi_lim; 1849221167Sgnn#define VXGE_HAL_MIN_UFCA_HI_LIM 1 1850221167Sgnn#define VXGE_HAL_MAX_UFCA_HI_LIM 256 1851221167Sgnn#define VXGE_HAL_USE_FLASH_DEFAULT_UFCA_HI_LIM VXGE_HAL_USE_FLASH_DEFAULT 1852221167Sgnn 1853221167Sgnn u32 ufca_lbolt_period; 1854221167Sgnn#define VXGE_HAL_MIN_UFCA_LBOLT_PERIOD 1 1855221167Sgnn#define VXGE_HAL_MAX_UFCA_LBOLT_PERIOD 1024 1856221167Sgnn#define VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LBOLT_PERIOD \ 1857221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 1858221167Sgnn 1859221167Sgnn} vxge_hal_tim_intr_config_t; 1860221167Sgnn 1861221167Sgnn/* 1862221167Sgnn * struct vxge_hal_fifo_config_t - Configuration of fifo. 1863221167Sgnn * @enable: Is this fifo to be commissioned 1864221167Sgnn * @fifo_length: Numbers of TxDLs (that is, lists of Tx descriptors)per queue. 1865221167Sgnn * @max_frags: Max number of Tx buffers per TxDL (that is, per single 1866221167Sgnn * transmit operation). 1867221167Sgnn * No more than 256 transmit buffers can be specified. 1868221167Sgnn * @alignment_size: per Tx fragment DMA-able memory used to align transmit data 1869221167Sgnn * (e.g., to align on a cache line). 1870221167Sgnn * @max_aligned_frags: Number of fragments to be aligned out of 1871221167Sgnn * maximum fragments (see @max_frags). 1872221167Sgnn * @intr: Boolean. Use 1 to generate interrupt for each completed TxDL. 1873221167Sgnn * Use 0 otherwise. 1874221167Sgnn * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation, 1875221167Sgnn * which generally improves latency of the host bridge operation 1876221167Sgnn * (see PCI specification). For valid values please refer 1877221167Sgnn * to vxge_hal_fifo_config_t {} in the driver sources. 1878221167Sgnn * Configuration of all X3100 fifos. 1879221167Sgnn * Note: Valid (min, max) range for each attribute is specified in the body of 1880221167Sgnn * the vxge_hal_fifo_config_t {} structure. 1881221167Sgnn */ 1882221167Sgnntypedef struct vxge_hal_fifo_config_t { 1883221167Sgnn u32 enable; 1884221167Sgnn#define VXGE_HAL_FIFO_ENABLE 1 1885221167Sgnn#define VXGE_HAL_FIFO_DISABLE 0 1886221167Sgnn#define VXGE_HAL_FIFO_DEFAULT 1 1887221167Sgnn 1888221167Sgnn u32 fifo_length; 1889221167Sgnn#define VXGE_HAL_MIN_FIFO_LENGTH 1 1890221167Sgnn#define VXGE_HAL_MAX_FIFO_LENGTH 12*1024 1891221167Sgnn#define VXGE_HAL_DEF_FIFO_LENGTH 512 1892221167Sgnn 1893221167Sgnn u32 max_frags; 1894221167Sgnn#define VXGE_HAL_MIN_FIFO_FRAGS 1 1895221167Sgnn#define VXGE_HAL_MAX_FIFO_FRAGS 256 1896221167Sgnn#define VXGE_HAL_DEF_FIFO_FRAGS 256 1897221167Sgnn 1898221167Sgnn u32 alignment_size; 1899221167Sgnn#define VXGE_HAL_MIN_FIFO_ALIGNMENT_SIZE 0 1900221167Sgnn#define VXGE_HAL_MAX_FIFO_ALIGNMENT_SIZE 65536 1901221167Sgnn#define VXGE_HAL_DEF_FIFO_ALIGNMENT_SIZE __vxge_os_cacheline_size 1902221167Sgnn 1903221167Sgnn u32 max_aligned_frags; 1904221167Sgnn /* range: (1, @max_frags) */ 1905221167Sgnn 1906221167Sgnn u32 intr; 1907221167Sgnn#define VXGE_HAL_FIFO_QUEUE_INTR_ENABLE 1 1908221167Sgnn#define VXGE_HAL_FIFO_QUEUE_INTR_DISABLE 0 1909221167Sgnn#define VXGE_HAL_FIFO_QUEUE_INTR_DEFAULT 0 1910221167Sgnn 1911221167Sgnn u32 no_snoop_bits; 1912221167Sgnn#define VXGE_HAL_FIFO_NO_SNOOP_DISABLED 0 1913221167Sgnn#define VXGE_HAL_FIFO_NO_SNOOP_TXD 1 1914221167Sgnn#define VXGE_HAL_FIFO_NO_SNOOP_FRM 2 1915221167Sgnn#define VXGE_HAL_FIFO_NO_SNOOP_ALL 3 1916221167Sgnn#define VXGE_HAL_FIFO_NO_SNOOP_DEFAULT 0 1917221167Sgnn 1918221167Sgnn} vxge_hal_fifo_config_t; 1919221167Sgnn 1920221167Sgnn/* 1921221167Sgnn * struct vxge_hal_ring_config_t - Ring configurations. 1922221167Sgnn * @enable: Is this ring to be commissioned 1923221167Sgnn * @ring_length: Numbers of RxDs in the ring 1924221167Sgnn * @buffer_mode: Receive buffer mode (1, 2, 3, or 5); for details please refer 1925221167Sgnn * to X3100 User Guide. 1926221167Sgnn * @scatter_mode: X3100 supports two receive scatter modes: A and B. 1927221167Sgnn * For details please refer to X3100 User Guide. 1928221167Sgnn * @post_mode: The RxD post mode. 1929221167Sgnn * @max_frm_len: Maximum frame length that can be received on _that_ ring. 1930221167Sgnn * Setting this field to VXGE_HAL_USE_FLASH_DEFAULT ensures that 1931221167Sgnn * the ring will "accept" 1932221167Sgnn * MTU-size frames (note that MTU can be changed at runtime). 1933221167Sgnn * Any value other than (VXGE_HAL_USE_FLASH_DEFAULT) specifies a 1934221167Sgnn * certain "hard" limit on the receive frame sizes. The field can 1935221167Sgnn * be used to activate receive frame-length based steering. 1936221167Sgnn * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation, 1937221167Sgnn * which generally improves latency of the host bridge operation 1938221167Sgnn * (see PCI specification). For valid values please refer 1939221167Sgnn * to vxge_hal_ring_config_t {} in the driver sources. 1940221167Sgnn * @rx_timer_val: The number of 32ns periods that would be counted between two 1941221167Sgnn * timer interrupts. 1942221167Sgnn * @greedy_return: If Set it forces the device to return absolutely all RxD 1943221167Sgnn * that are consumed and still on board when a timer interrupt 1944221167Sgnn * triggers. If Clear, then if the device has already returned 1945221167Sgnn * RxD before current timer interrupt trigerred and after the 1946221167Sgnn * previous timer interrupt triggered, then the device is not 1947221167Sgnn * forced to returned the rest of the consumed RxD that it has 1948221167Sgnn * on board which account for a byte count less than the one 1949221167Sgnn * programmed into PRC_CFG6.RXD_CRXDT field 1950221167Sgnn * @rx_timer_ci: TBD 1951221167Sgnn * @backoff_interval_us: Time (in microseconds), after which X3100 1952221167Sgnn * tries to download RxDs posted by the host. 1953221167Sgnn * Note that the "backoff" does not happen if host posts receive 1954221167Sgnn * descriptors in the timely fashion. 1955221167Sgnn * @indicate_max_pkts: Sets maximum number of received frames to be processed 1956221167Sgnn * within single interrupt. 1957221167Sgnn * @sw_lro_sessions: Number of LRO Sessions 1958221167Sgnn * @sw_lro_sg_size: Size of LROable segment 1959221167Sgnn * @sw_lro_frm_len: Length of LROable frame 1960221167Sgnn * 1961221167Sgnn * Ring configuration. 1962221167Sgnn */ 1963221167Sgnntypedef struct vxge_hal_ring_config_t { 1964221167Sgnn u32 enable; 1965221167Sgnn#define VXGE_HAL_RING_ENABLE 1 1966221167Sgnn#define VXGE_HAL_RING_DISABLE 0 1967221167Sgnn#define VXGE_HAL_RING_DEFAULT 1 1968221167Sgnn 1969221167Sgnn u32 ring_length; 1970221167Sgnn#define VXGE_HAL_MIN_RING_LENGTH 1 1971221167Sgnn#define VXGE_HAL_MAX_RING_LENGTH 8096 1972221167Sgnn#define VXGE_HAL_DEF_RING_LENGTH 512 1973221167Sgnn 1974221167Sgnn u32 buffer_mode; 1975221167Sgnn#define VXGE_HAL_RING_RXD_BUFFER_MODE_1 1 1976221167Sgnn#define VXGE_HAL_RING_RXD_BUFFER_MODE_3 3 1977221167Sgnn#define VXGE_HAL_RING_RXD_BUFFER_MODE_5 5 1978221167Sgnn#define VXGE_HAL_RING_RXD_BUFFER_MODE_DEFAULT 1 1979221167Sgnn 1980221167Sgnn u32 scatter_mode; 1981221167Sgnn#define VXGE_HAL_RING_SCATTER_MODE_A 0 1982221167Sgnn#define VXGE_HAL_RING_SCATTER_MODE_B 1 1983221167Sgnn#define VXGE_HAL_RING_SCATTER_MODE_C 2 1984221167Sgnn#define VXGE_HAL_RING_SCATTER_MODE_USE_FLASH_DEFAULT \ 1985221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 1986221167Sgnn 1987221167Sgnn u32 post_mode; 1988221167Sgnn#define VXGE_HAL_RING_POST_MODE_LEGACY 0 1989221167Sgnn#define VXGE_HAL_RING_POST_MODE_DOORBELL 1 1990221167Sgnn#define VXGE_HAL_RING_POST_MODE_USE_FLASH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 1991221167Sgnn 1992221167Sgnn u32 max_frm_len; 1993221167Sgnn#define VXGE_HAL_MIN_RING_MAX_FRM_LEN VXGE_HAL_MIN_MTU 1994221167Sgnn#define VXGE_HAL_MAX_RING_MAX_FRM_LEN VXGE_HAL_MAX_MTU 1995221167Sgnn#define VXGE_HAL_MAX_RING_FRM_LEN_USE_MTU VXGE_HAL_USE_FLASH_DEFAULT 1996221167Sgnn 1997221167Sgnn u32 no_snoop_bits; 1998221167Sgnn#define VXGE_HAL_RING_NO_SNOOP_DISABLED 0 1999221167Sgnn#define VXGE_HAL_RING_NO_SNOOP_RXD 1 2000221167Sgnn#define VXGE_HAL_RING_NO_SNOOP_FRM 2 2001221167Sgnn#define VXGE_HAL_RING_NO_SNOOP_ALL 3 2002221167Sgnn#define VXGE_HAL_RING_NO_SNOOP_USE_FLASH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 2003221167Sgnn 2004221167Sgnn u32 rx_timer_val; 2005221167Sgnn#define VXGE_HAL_RING_MIN_RX_TIMER_VAL 0 2006221167Sgnn#define VXGE_HAL_RING_MAX_RX_TIMER_VAL 536870912 2007221167Sgnn#define VXGE_HAL_RING_USE_FLASH_DEFAULT_RX_TIMER_VAL \ 2008221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2009221167Sgnn 2010221167Sgnn u32 greedy_return; 2011221167Sgnn#define VXGE_HAL_RING_GREEDY_RETURN_ENABLE 1 2012221167Sgnn#define VXGE_HAL_RING_GREEDY_RETURN_DISABLE 0 2013221167Sgnn#define VXGE_HAL_RING_GREEDY_RETURN_USE_FLASH_DEFAULT \ 2014221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2015221167Sgnn 2016221167Sgnn u32 rx_timer_ci; 2017221167Sgnn#define VXGE_HAL_RING_RX_TIMER_CI_ENABLE 1 2018221167Sgnn#define VXGE_HAL_RING_RX_TIMER_CI_DISABLE 0 2019221167Sgnn#define VXGE_HAL_RING_RX_TIMER_CI_USE_FLASH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 2020221167Sgnn 2021221167Sgnn u32 backoff_interval_us; 2022221167Sgnn#define VXGE_HAL_MIN_BACKOFF_INTERVAL_US 1 2023221167Sgnn#define VXGE_HAL_MAX_BACKOFF_INTERVAL_US 125000 2024221167Sgnn#define VXGE_HAL_USE_FLASH_DEFAULT_BACKOFF_INTERVAL_US \ 2025221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2026221167Sgnn 2027221167Sgnn u32 indicate_max_pkts; 2028221167Sgnn#define VXGE_HAL_MIN_RING_INDICATE_MAX_PKTS 1 2029221167Sgnn#define VXGE_HAL_MAX_RING_INDICATE_MAX_PKTS 65536 2030221167Sgnn#define VXGE_HAL_DEF_RING_INDICATE_MAX_PKTS 65536 2031221167Sgnn 2032221167Sgnn 2033221167Sgnn} vxge_hal_ring_config_t; 2034221167Sgnn 2035221167Sgnn 2036221167Sgnn/* 2037221167Sgnn * struct vxge_hal_vp_config_t - Configuration of virtual path 2038221167Sgnn * @vp_id: Virtual Path Id 2039221167Sgnn * @wire_port: Wire port to be associated with the vpath 2040221167Sgnn * @bandwidth_limit: Desired bandwidth limit for this vpath. 2041221167Sgnn * 0 = Disable limit, 1 = 8192 kBps, 2 = 16384 kBps, ... , 2042221167Sgnn * >152588 = 1 GBps 2043221167Sgnn * @no_snoop: Enable or disable no snoop for vpath 2044221167Sgnn * @ring: See vxge_hal_ring_config_t {}. 2045221167Sgnn * @fifo: See vxge_hal_fifo_config_t {}. 2046221167Sgnn * @dmq: See vxge_hal_dmq_config_t {}; 2047221167Sgnn * @umq: See vxge_hal_umq_config_t {}; 2048221167Sgnn * @lro: See vxge_hal_lro_config_t {}; 2049221167Sgnn * @tti: Configuration of interrupt associated with Transmit. 2050221167Sgnn * see vxge_hal_tim_intr_config_t(); 2051221167Sgnn * @rti: Configuration of interrupt associated with Receive. 2052221167Sgnn * see vxge_hal_tim_intr_config_t(); 2053221167Sgnn * @mtu: mtu size used on this port. 2054221167Sgnn * @tpa_lsov2_en: LSOv2 Behaviour for IP ID roll-over 2055221167Sgnn * @tpa_ignore_frame_error: Ignore Frame Error. TPA may detect frame integrity 2056221167Sgnn * errors as it processes each frame. If this bit is set to '0', 2057221167Sgnn * the TPA will tag such frames as invalid and they will be dropped 2058221167Sgnn * by the transmit MAC. If the bit is set to '1',the frame will not 2059221167Sgnn * be tagged as "errored". Detectable errors include: 2060221167Sgnn * 1) early end-of-frame error, which occurs when the frame ends 2061221167Sgnn * before the number of bytes predicted by the IP "total length" 2062221167Sgnn * field have been received; 2063221167Sgnn * 2) IP version mismatches; 2064221167Sgnn * 3) IPv6 packets that include routing headers that are not type 0 2065221167Sgnn * 4) Frames which contain IP packets but have an illegal SNAP-OUI 2066221167Sgnn * or LLC-CTRL fields, unless IGNORE_SNAP_OUI or IGNORE_LLC_CTRL 2067221167Sgnn * are set (see below). 2068221167Sgnn * @tpa_ipv6_keep_searching: If unknown IPv6 header is found, 2069221167Sgnn * 0 - stop searching for TCP 2070221167Sgnn * 1 - keep searching for TCP 2071221167Sgnn * @tpa_l4_pshdr_present: If asserted true, indicates the host has provided a 2072221167Sgnn * valid pseudo header for TCP or UDP running over IPv4 or IPv6 2073221167Sgnn * @tpa_support_mobile_ipv6_hdrs: This register is somewhat equivalent to 2074221167Sgnn * asserting both Hercules register fields LSO_RT2_EN and 2075221167Sgnn * LSO_IPV6_HAO_EN. Enable/disable support for Type 2 Routing 2076221167Sgnn * Headers, and for Mobile-IPv6 Home Address Option (HAO), 2077221167Sgnn * as defined by mobile-ipv6. 2078221167Sgnn * @rpa_ipv4_tcp_incl_ph: Determines if the pseudo-header is included in the 2079221167Sgnn * calculation of the L4 checksum that is passed to the host. This 2080221167Sgnn * field applies to TCP/IPv4 packets only. This field affects both 2081221167Sgnn * non-offload and LRO traffic. Note that the RPA always includes 2082221167Sgnn * the pseudo-header in the "Checksum Ok" L4 checksum calculation 2083221167Sgnn * i.e. the checksum that decides whether a frame is a candidate to 2084221167Sgnn * be offloaded. 2085221167Sgnn * 0 - Do not include the pseudo-header in L4 checksum calculation. 2086221167Sgnn * This setting should be used if the adapter is incorrectly 2087221167Sgnn * calculating the pseudo-header. 2088221167Sgnn * 1 - Include the pseudo-header in L4 checksum calculation 2089221167Sgnn * @rpa_ipv6_tcp_incl_ph: Determines whether the pseudo-header is included in 2090221167Sgnn * the calculation of the L4 checksum that is passed to the host. 2091221167Sgnn * This field applies to TCP/IPv6 packets only. This field affects 2092221167Sgnn * both non-offload and LRO traffic. Note that the RPA always 2093221167Sgnn * includes the pseudo-header in the "Checksum Ok" L4 checksum 2094221167Sgnn * calculation. i.e. the checksum that decides whether a frame 2095221167Sgnn * is a candidate to be offloaded. 2096221167Sgnn * 0 - Do not include the pseudo-header in L4 checksum calculation. 2097221167Sgnn * This setting should be used if the adapter is incorrectly 2098221167Sgnn * calculating the pseudo-header. 2099221167Sgnn * 1 - Include the pseudo-header in L4 checksum calculation 2100221167Sgnn * @rpa_ipv4_udp_incl_ph: Determines whether the pseudo-header is included in 2101221167Sgnn * the calculation of the L4 checksum that is passed to the host. 2102221167Sgnn * This field applies to UDP/IPv4 packets only. It only affects 2103221167Sgnn * non-offload traffic(since UDP frames are not candidates for LRO) 2104221167Sgnn * 0 - Do not include the pseudo-header in L4 checksum calculation. 2105221167Sgnn * This setting should be used if the adapter is incorrectly 2106221167Sgnn * calculating the pseudo-header. 2107221167Sgnn * 1 - Include the pseudo-header in L4 checksum calculation 2108221167Sgnn * @rpa_ipv6_udp_incl_ph: Determines if the pseudo-header is included in the 2109221167Sgnn * calculation of the L4 checksum that is passed to the host. This 2110221167Sgnn * field applies to UDP/IPv6 packets only. It only affects 2111221167Sgnn * non-offload traffic(since UDP frames are not candidates for LRO) 2112221167Sgnn * 0 - Do not include the pseudo-header in L4 checksum calculation. 2113221167Sgnn * This setting should be used if the adapter is incorrectly 2114221167Sgnn * calculating the pseudo-header. 2115221167Sgnn * 1 - Include the pseudo-header in L4 checksum calculation 2116221167Sgnn * @rpa_l4_incl_cf: Determines whether the checksum field (CF) of the received 2117221167Sgnn * frame is included in the calculation of the L4 checksum that is 2118221167Sgnn * passed to the host. This field affects both non-offload and LRO 2119221167Sgnn * traffic. Note that the RPA always includes the checksum field in 2120221167Sgnn * the "Checksum Ok" L4 checksum calculation -- i.e. the checksum 2121221167Sgnn * that decides whether a frame is a candidate to be offloaded. 2122221167Sgnn * 0 - Do not include the checksum field in L4 checksum calculation 2123221167Sgnn * 1 - Include the checksum field in L4 checksum calculation 2124221167Sgnn * @rpa_strip_vlan_tag: Strip VLAN Tag enable/disable. Instructs the device to 2125221167Sgnn * remove the VLAN tag from all received tagged frames that are not 2126221167Sgnn * replicated at the internal L2 switch. 2127221167Sgnn * 0 - Do not strip the VLAN tag. 2128221167Sgnn * 1 - Strip the VLAN tag. Regardless of this setting,VLAN tags are 2129221167Sgnn * always placed into the RxDMA descriptor. 2130221167Sgnn * @rpa_l4_comp_csum: Determines whether the calculated L4 checksum should be 2131221167Sgnn * complemented before it is passed to the host This field affects 2132221167Sgnn * both non-offload and LRO traffic. 2133221167Sgnn * 0 - Do not complement the calculated L4 checksum. 2134221167Sgnn * 1 - Complement the calculated L4 checksum 2135221167Sgnn * @rpa_l3_incl_cf: Determines whether the checksum field (CF) of the received 2136221167Sgnn * frame is included in the calculation of the L3 checksum that is 2137221167Sgnn * passed to the host. This field affects both non-offload and LRO 2138221167Sgnn * traffic. Note that the RPA always includes the checksum field in 2139221167Sgnn * the "Checksum Ok" L3 checksum calculation--i.e. the checksum 2140221167Sgnn * that decides whether a frame is a candidate to be offloaded. 2141221167Sgnn * 0 - Do not include the checksum field in L3 checksum calculation 2142221167Sgnn * 1 - Include the checksum field in L3 checksum calculation 2143221167Sgnn * @rpa_l3_comp_csum: Determines whether the calculated L3 checksum should be 2144221167Sgnn * complemented before it is passed to the host This field affects 2145221167Sgnn * both non-offload and LRO traffic. 2146221167Sgnn * 0 - Do not complement the calculated L3 checksum. 2147221167Sgnn * 1 - Complement the calculated L3 checksum 2148221167Sgnn * @rpa_ucast_all_addr_en: Enables frames with any unicast address (as its 2149221167Sgnn * destination address) to be passed to the host. 2150221167Sgnn * @rpa_mcast_all_addr_en: Enables frames with any multicast address (as its 2151221167Sgnn * destination address) to be passed to the host. 2152221167Sgnn * @rpa_bcast_en: Enables frames with any broadicast address (as its 2153221167Sgnn * destination address) to be passed to the host. 2154221167Sgnn * @rpa_all_vid_en: romiscuous mode, it overrides the value held in this field. 2155221167Sgnn * 0 - Disable; 2156221167Sgnn * 1 - Enable 2157221167Sgnn * Note: RXMAC_GLOBAL_CFG.AUTHORIZE_VP_ALL_VID must be set to 2158221167Sgnn * allow this. 2159221167Sgnn * @vp_queue_l2_flow: Allows per-VPATH receive queue from 2160221167Sgnn * contributing to L2 flow control. Has precedence over 2161221167Sgnn * RMAC_PAUSE_CFG_PORTn.LIMITER_EN. 2162221167Sgnn * 0 - Queue is not allowed to contribute to L2 flow control. 2163221167Sgnn * 1 - Queue is allowed to contribute to L2 flow control. 2164221167Sgnn * 2165221167Sgnn * This structure is used by the driver to pass the configuration parameters to 2166221167Sgnn * configure Virtual Path. 2167221167Sgnn */ 2168221167Sgnntypedef struct vxge_hal_vp_config_t { 2169221167Sgnn u32 vp_id; 2170221167Sgnn 2171221167Sgnn u32 wire_port; 2172221167Sgnn#define VXGE_HAL_VPATH_USE_DEFAULT_PORT VXGE_HAL_FIFO_HOST_STEER_NORMAL 2173221167Sgnn#define VXGE_HAL_VPATH_USE_PORT0 VXGE_HAL_FIFO_HOST_STEER_PORT0 2174221167Sgnn#define VXGE_HAL_VPATH_USE_PORT1 VXGE_HAL_FIFO_HOST_STEER_PORT1 2175221167Sgnn#define VXGE_HAL_VPATH_USE_BOTH VXGE_HAL_FIFO_HOST_STEER_BOTH 2176221167Sgnn 2177221167Sgnn u32 bandwidth; 2178221167Sgnn#define VXGE_HAL_VPATH_BW_LIMIT_MAX 10000 2179221167Sgnn#define VXGE_HAL_VPATH_BW_LIMIT_MIN 100 2180221167Sgnn#define VXGE_HAL_VPATH_BW_LIMIT_DEFAULT 0XFFFFFFFF 2181221167Sgnn#define VXGE_HAL_TX_BW_VPATH_LIMIT 8 2182221167Sgnn 2183221167Sgnn u32 priority; 2184221167Sgnn#define VXGE_HAL_VPATH_PRIORITY_MIN 0 2185221167Sgnn#define VXGE_HAL_VPATH_PRIORITY_MAX 3 2186221167Sgnn#define VXGE_HAL_VPATH_PRIORITY_DEFAULT 0XFFFFFFFF 2187221167Sgnn 2188221167Sgnn u32 no_snoop; 2189221167Sgnn#define VXGE_HAL_VPATH_NO_SNOOP_ENABLE 1 2190221167Sgnn#define VXGE_HAL_VPATH_NO_SNOOP_DISABLE 0 2191221167Sgnn#define VXGE_HAL_VPATH_NO_SNOOP_USE_FLASH_DEFAULT \ 2192221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2193221167Sgnn 2194221167Sgnn vxge_hal_ring_config_t ring; 2195221167Sgnn vxge_hal_fifo_config_t fifo; 2196221167Sgnn 2197221167Sgnn vxge_hal_tim_intr_config_t tti; 2198221167Sgnn vxge_hal_tim_intr_config_t rti; 2199221167Sgnn 2200221167Sgnn u32 mtu; 2201221167Sgnn#define VXGE_HAL_VPATH_MIN_INITIAL_MTU VXGE_HAL_MIN_MTU 2202221167Sgnn#define VXGE_HAL_VPATH_MAX_INITIAL_MTU VXGE_HAL_MAX_MTU 2203221167Sgnn#define VXGE_HAL_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU \ 2204221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2205221167Sgnn 2206221167Sgnn u32 tpa_lsov2_en; 2207221167Sgnn#define VXGE_HAL_VPATH_TPA_LSOV2_EN_ENABLE 1 2208221167Sgnn#define VXGE_HAL_VPATH_TPA_LSOV2_EN_DISABLE 0 2209221167Sgnn#define VXGE_HAL_VPATH_TPA_LSOV2_EN_USE_FLASH_DEFAULT \ 2210221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2211221167Sgnn 2212221167Sgnn u32 tpa_ignore_frame_error; 2213221167Sgnn#define VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_ENABLE 1 2214221167Sgnn#define VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_DISABLE 0 2215221167Sgnn#define VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_USE_FLASH_DEFAULT \ 2216221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2217221167Sgnn 2218221167Sgnn u32 tpa_ipv6_keep_searching; 2219221167Sgnn#define VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_ENABLE 1 2220221167Sgnn#define VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_DISABLE 0 2221221167Sgnn#define VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_USE_FLASH_DEFAULT \ 2222221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2223221167Sgnn 2224221167Sgnn u32 tpa_l4_pshdr_present; 2225221167Sgnn#define VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_ENABLE 1 2226221167Sgnn#define VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_DISABLE 0 2227221167Sgnn#define VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_USE_FLASH_DEFAULT \ 2228221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2229221167Sgnn 2230221167Sgnn u32 tpa_support_mobile_ipv6_hdrs; 2231221167Sgnn#define VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_ENABLE 1 2232221167Sgnn#define VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_DISABLE 0 2233221167Sgnn#define VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_USE_FLASH_DEFAULT \ 2234221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2235221167Sgnn#define VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_DEFAULT \ 2236221167Sgnn VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_USE_FLASH_DEFAULT 2237221167Sgnn 2238221167Sgnn u32 rpa_ipv4_tcp_incl_ph; 2239221167Sgnn#define VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_ENABLE 1 2240221167Sgnn#define VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_DISABLE 0 2241221167Sgnn#define VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_USE_FLASH_DEFAULT \ 2242221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2243221167Sgnn 2244221167Sgnn u32 rpa_ipv6_tcp_incl_ph; 2245221167Sgnn#define VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_ENABLE 1 2246221167Sgnn#define VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_DISABLE 0 2247221167Sgnn#define VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_USE_FLASH_DEFAULT \ 2248221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2249221167Sgnn 2250221167Sgnn u32 rpa_ipv4_udp_incl_ph; 2251221167Sgnn#define VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_ENABLE 1 2252221167Sgnn#define VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_DISABLE 0 2253221167Sgnn#define VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_USE_FLASH_DEFAULT \ 2254221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2255221167Sgnn 2256221167Sgnn u32 rpa_ipv6_udp_incl_ph; 2257221167Sgnn#define VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_ENABLE 1 2258221167Sgnn#define VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_DISABLE 0 2259221167Sgnn#define VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_USE_FLASH_DEFAULT \ 2260221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2261221167Sgnn 2262221167Sgnn u32 rpa_l4_incl_cf; 2263221167Sgnn#define VXGE_HAL_VPATH_RPA_L4_INCL_CF_ENABLE 1 2264221167Sgnn#define VXGE_HAL_VPATH_RPA_L4_INCL_CF_DISABLE 0 2265221167Sgnn#define VXGE_HAL_VPATH_RPA_L4_INCL_CF_USE_FLASH_DEFAULT \ 2266221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2267221167Sgnn 2268221167Sgnn u32 rpa_strip_vlan_tag; 2269221167Sgnn#define VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_ENABLE 1 2270221167Sgnn#define VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_DISABLE 0 2271221167Sgnn#define VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT \ 2272221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2273221167Sgnn 2274221167Sgnn u32 rpa_l4_comp_csum; 2275221167Sgnn#define VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_ENABLE 1 2276221167Sgnn#define VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_DISABLE 0 2277221167Sgnn#define VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_USE_FLASH_DEFAULT \ 2278221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2279221167Sgnn 2280221167Sgnn u32 rpa_l3_incl_cf; 2281221167Sgnn#define VXGE_HAL_VPATH_RPA_L3_INCL_CF_ENABLE 1 2282221167Sgnn#define VXGE_HAL_VPATH_RPA_L3_INCL_CF_DISABLE 0 2283221167Sgnn#define VXGE_HAL_VPATH_RPA_L3_INCL_CF_USE_FLASH_DEFAULT \ 2284221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2285221167Sgnn 2286221167Sgnn u32 rpa_l3_comp_csum; 2287221167Sgnn#define VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_ENABLE 1 2288221167Sgnn#define VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_DISABLE 0 2289221167Sgnn#define VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_USE_FLASH_DEFAULT \ 2290221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2291221167Sgnn 2292221167Sgnn u32 rpa_ucast_all_addr_en; 2293221167Sgnn#define VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_ENABLE 1 2294221167Sgnn#define VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_DISABLE 0 2295221167Sgnn#define VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_USE_FLASH_DEFAULT \ 2296221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2297221167Sgnn 2298221167Sgnn u32 rpa_mcast_all_addr_en; 2299221167Sgnn#define VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_ENABLE 1 2300221167Sgnn#define VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_DISABLE 0 2301221167Sgnn#define VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_USE_FLASH_DEFAULT \ 2302221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2303221167Sgnn 2304221167Sgnn u32 rpa_bcast_en; 2305221167Sgnn#define VXGE_HAL_VPATH_RPA_BCAST_ENABLE 1 2306221167Sgnn#define VXGE_HAL_VPATH_RPA_BCAST_DISABLE 0 2307221167Sgnn#define VXGE_HAL_VPATH_RPA_BCAST_USE_FLASH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT 2308221167Sgnn 2309221167Sgnn u32 rpa_all_vid_en; 2310221167Sgnn#define VXGE_HAL_VPATH_RPA_ALL_VID_ENABLE 1 2311221167Sgnn#define VXGE_HAL_VPATH_RPA_ALL_VID_DISABLE 0 2312221167Sgnn#define VXGE_HAL_VPATH_RPA_ALL_VID_USE_FLASH_DEFAULT \ 2313221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2314221167Sgnn 2315221167Sgnn u32 vp_queue_l2_flow; 2316221167Sgnn#define VXGE_HAL_VPATH_VP_Q_L2_FLOW_ENABLE 1 2317221167Sgnn#define VXGE_HAL_VPATH_VP_Q_L2_FLOW_DISABLE 0 2318221167Sgnn#define VXGE_HAL_VPATH_VP_Q_L2_FLOW_USE_FLASH_DEFAULT \ 2319221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT 2320221167Sgnn 2321221167Sgnn} vxge_hal_vp_config_t; 2322221167Sgnn 2323221167Sgnn/* 2324221167Sgnn * struct vxge_hal_device_config_t - Device configuration. 2325221167Sgnn * @dma_blockpool_min: Minimum blocks in the DMA pool 2326221167Sgnn * @dma_blockpool_initial: Initial size of DMA Pool 2327221167Sgnn * @dma_blockpool_incr: Number of blocks to request each time number of blocks 2328221167Sgnn * in the pool reaches dma_pool_min 2329221167Sgnn * @dma_blockpool_max: Maximum blocks in DMA pool 2330221167Sgnn * @mrpcim_config: MRPCIM section config. Used only for the privileged mode ULD 2331221167Sgnn * instance. 2332221167Sgnn * @isr_polling_cnt: Maximum number of times to "poll" for Tx and Rx 2333221167Sgnn * completions. Used in vxge_hal_device_handle_irq(). 2334221167Sgnn * @max_payload_size: Maximum TLP payload size for the device/fFunction. 2335221167Sgnn * As a Receiver, the Function/device must handle TLPs as large 2336221167Sgnn * as the set value; as . As a Transmitter, the Function/device 2337221167Sgnn * must not generate TLPs exceeding the set value. Permissible 2338221167Sgnn * values that can be programmed are indicated by the 2339221167Sgnn * Max_Payload_Size Supported in the Device Capabilities register 2340221167Sgnn * @mmrb_count: Maximum Memory Read Byte Count. Use (VXGE_HAL_USE_FLASH_DEFAULT) 2341221167Sgnn * to use default BIOS value. 2342221167Sgnn * @stats_refresh_time_sec: Sets the default interval for automatic stats 2343221167Sgnn * transfer to the host. This includes MAC stats as well as 2344221167Sgnn * PCI stats. 2345221167Sgnn * @intr_mode: Line, or MSI-X interrupt. 2346221167Sgnn * 2347221167Sgnn * @dump_on_unknown: Dump adapter state ("about", statistics, registers) 2348221167Sgnn * on UNKNWON#. 2349221167Sgnn * @dump_on_serr: Dump adapter state ("about", statistics, registers) on SERR#. 2350221167Sgnn * @dump_on_critical: Dump adapter state ("about", statistics, registers) 2351221167Sgnn * on CRITICAL#. 2352221167Sgnn * @dump_on_eccerr: Dump adapter state ("about", statistics, registers) on 2353221167Sgnn * ECC error. 2354221167Sgnn * @rth_en: Enable Receive Traffic Hashing(RTH) using IT(Indirection Table). 2355221167Sgnn * @rth_it_type: RTH IT table programming type 2356221167Sgnn * @rts_mac_en: Enable Receive Traffic Steering using MAC destination address 2357221167Sgnn * @rts_qos_en: TBD 2358221167Sgnn * @rts_port_en: TBD 2359221167Sgnn * @vp_config: Configuration for virtual paths 2360221167Sgnn * @max_cqe_groups: The maximum number of adapter CQE group blocks a CQRQ 2361221167Sgnn * can own at any one time. 2362221167Sgnn * @max_num_wqe_od_groups: The maximum number of WQE Headers/OD Groups that 2363221167Sgnn * this S-RQ can own at any one time. 2364221167Sgnn * @no_wqe_threshold: Maximum number of times adapter polls WQE Hdr blocks for 2365221167Sgnn * WQEs before generating a message or interrupt. 2366221167Sgnn * @refill_threshold_high:This field provides a hysteresis upper bound for 2367221167Sgnn * automatic adapter refill operations. 2368221167Sgnn * @refill_threshold_low:This field provides a hysteresis lower bound for 2369221167Sgnn * automatic adapter refill operations. 2370221167Sgnn * @eol_policy: This field sets the policy for handling the end of list 2371221167Sgnn * condition. 2372221167Sgnn * 2'b00 - When EOL is reached, poll until last block wrapper 2373221167Sgnn * size is no longer 0. 2374221167Sgnn * 2'b01 - Send UMQ message when EOL is reached. 2375221167Sgnn * 2'b1x - Poll until the poll_count_max is reached and 2376221167Sgnn * if still EOL, send UMQ message 2377221167Sgnn * @eol_poll_count_max:sets the maximum number of times the queue manager will 2378221167Sgnn * poll fora non-zero block wrapper before giving up and sending 2379221167Sgnn * a UMQ message 2380221167Sgnn * @ack_blk_limit: Limit on the maximum number of ACK list blocks that can be 2381221167Sgnn * held by a session at any one time. 2382221167Sgnn * @poll_or_doorbell: TBD 2383221167Sgnn * @stats_read_method: Stats read method.(DMA or PIO) 2384221167Sgnn * @device_poll_millis: Specify the interval (in mulliseconds) to wait for 2385221167Sgnn * register reads 2386221167Sgnn * @debug_level: Debug logging level. see vxge_debug_level_e {} 2387221167Sgnn * @debug_mask: Module mask for debug logging level. for masks see vxge_debug.h 2388221167Sgnn * @lro_enable: SW LRO enable mask 2389221167Sgnn * @tracebuf_size: Size of the trace buffer. Set it to '0' to disable. 2390221167Sgnn * 2391221167Sgnn * X3100 configuration. 2392221167Sgnn * Contains per-device configuration parameters, including: 2393221167Sgnn * - latency timer (settable via PCI configuration space); 2394221167Sgnn * - maximum number of split transactions; 2395221167Sgnn * - maximum number of shared splits; 2396221167Sgnn * - stats sampling interval, etc. 2397221167Sgnn * 2398221167Sgnn * In addition, vxge_hal_device_config_t {} includes "subordinate" 2399221167Sgnn * configurations, including: 2400221167Sgnn * - fifos and rings; 2401221167Sgnn * - MAC (done at firmware level). 2402221167Sgnn * 2403221167Sgnn * See X3100 User Guide for more details. 2404221167Sgnn * Note: Valid (min, max) range for each attribute is specified in the body of 2405221167Sgnn * the vxge_hal_device_config_t {} structure. Please refer to the 2406221167Sgnn * corresponding include file. 2407221167Sgnn * See also: vxge_hal_tim_intr_config_t {}. 2408221167Sgnn */ 2409221167Sgnntypedef struct vxge_hal_device_config_t { 2410221167Sgnn u32 dma_blockpool_min; 2411221167Sgnn u32 dma_blockpool_initial; 2412221167Sgnn u32 dma_blockpool_incr; 2413221167Sgnn u32 dma_blockpool_max; 2414221167Sgnn#define VXGE_HAL_MIN_DMA_BLOCK_POOL_SIZE 0 2415221167Sgnn#define VXGE_HAL_INITIAL_DMA_BLOCK_POOL_SIZE 0 2416221167Sgnn#define VXGE_HAL_INCR_DMA_BLOCK_POOL_SIZE 4 2417221167Sgnn#define VXGE_HAL_MAX_DMA_BLOCK_POOL_SIZE 4096 2418221167Sgnn 2419221167Sgnn vxge_hal_mrpcim_config_t mrpcim_config; 2420221167Sgnn 2421221167Sgnn u32 isr_polling_cnt; 2422221167Sgnn#define VXGE_HAL_MIN_ISR_POLLING_CNT 0 2423221167Sgnn#define VXGE_HAL_MAX_ISR_POLLING_CNT 65536 2424221167Sgnn#define VXGE_HAL_DEF_ISR_POLLING_CNT 1 2425221167Sgnn 2426221167Sgnn u32 max_payload_size; 2427221167Sgnn#define VXGE_HAL_USE_BIOS_DEFAULT_PAYLOAD_SIZE VXGE_HAL_USE_FLASH_DEFAULT 2428221167Sgnn#define VXGE_HAL_MAX_PAYLOAD_SIZE_128 0 2429221167Sgnn#define VXGE_HAL_MAX_PAYLOAD_SIZE_256 1 2430221167Sgnn#define VXGE_HAL_MAX_PAYLOAD_SIZE_512 2 2431221167Sgnn#define VXGE_HAL_MAX_PAYLOAD_SIZE_1024 3 2432221167Sgnn#define VXGE_HAL_MAX_PAYLOAD_SIZE_2048 4 2433221167Sgnn#define VXGE_HAL_MAX_PAYLOAD_SIZE_4096 5 2434221167Sgnn 2435221167Sgnn u32 mmrb_count; 2436221167Sgnn#define VXGE_HAL_USE_BIOS_DEFAULT_MMRB_COUNT VXGE_HAL_USE_FLASH_DEFAULT 2437221167Sgnn#define VXGE_HAL_MMRB_COUNT_128 0 2438221167Sgnn#define VXGE_HAL_MMRB_COUNT_256 1 2439221167Sgnn#define VXGE_HAL_MMRB_COUNT_512 2 2440221167Sgnn#define VXGE_HAL_MMRB_COUNT_1024 3 2441221167Sgnn#define VXGE_HAL_MMRB_COUNT_2048 4 2442221167Sgnn#define VXGE_HAL_MMRB_COUNT_4096 5 2443221167Sgnn 2444221167Sgnn u32 stats_refresh_time_sec; 2445221167Sgnn#define VXGE_HAL_STATS_REFRESH_DISABLE 0 2446221167Sgnn#define VXGE_HAL_MIN_STATS_REFRESH_TIME 1 2447221167Sgnn#define VXGE_HAL_MAX_STATS_REFRESH_TIME 300 2448221167Sgnn#define VXGE_HAL_USE_FLASH_DEFAULT_STATS_REFRESH_TIME 30 2449221167Sgnn 2450221167Sgnn u32 intr_mode; 2451221167Sgnn#define VXGE_HAL_INTR_MODE_IRQLINE 0 2452221167Sgnn#define VXGE_HAL_INTR_MODE_MSIX 1 2453221167Sgnn#define VXGE_HAL_INTR_MODE_MSIX_ONE_SHOT 2 2454221167Sgnn#define VXGE_HAL_INTR_MODE_EMULATED_INTA 3 2455221167Sgnn#define VXGE_HAL_INTR_MODE_DEF 0 2456221167Sgnn 2457221167Sgnn u32 dump_on_unknown; 2458221167Sgnn#define VXGE_HAL_DUMP_ON_UNKNOWN_DISABLE 0 2459221167Sgnn#define VXGE_HAL_DUMP_ON_UNKNOWN_ENABLE 1 2460221167Sgnn#define VXGE_HAL_DUMP_ON_UNKNOWN_DEFAULT 0 2461221167Sgnn 2462221167Sgnn u32 dump_on_serr; 2463221167Sgnn#define VXGE_HAL_DUMP_ON_SERR_DISABLE 0 2464221167Sgnn#define VXGE_HAL_DUMP_ON_SERR_ENABLE 1 2465221167Sgnn#define VXGE_HAL_DUMP_ON_SERR_DEFAULT 0 2466221167Sgnn 2467221167Sgnn u32 dump_on_critical; 2468221167Sgnn#define VXGE_HAL_DUMP_ON_CRITICAL_DISABLE 0 2469221167Sgnn#define VXGE_HAL_DUMP_ON_CRITICAL_ENABLE 1 2470221167Sgnn#define VXGE_HAL_DUMP_ON_CRITICAL_DEFAULT 0 2471221167Sgnn 2472221167Sgnn u32 dump_on_eccerr; 2473221167Sgnn#define VXGE_HAL_DUMP_ON_ECCERR_DISABLE 0 2474221167Sgnn#define VXGE_HAL_DUMP_ON_ECCERR_ENABLE 1 2475221167Sgnn#define VXGE_HAL_DUMP_ON_ECCERR_DEFAULT 0 2476221167Sgnn 2477221167Sgnn u32 rth_en; 2478221167Sgnn#define VXGE_HAL_RTH_DISABLE 0 2479221167Sgnn#define VXGE_HAL_RTH_ENABLE 1 2480221167Sgnn#define VXGE_HAL_RTH_DEFAULT 0 2481221167Sgnn 2482221167Sgnn u32 rth_it_type; 2483221167Sgnn#define VXGE_HAL_RTH_IT_TYPE_SOLO_IT 0 2484221167Sgnn#define VXGE_HAL_RTH_IT_TYPE_MULTI_IT 1 2485221167Sgnn#define VXGE_HAL_RTH_IT_TYPE_DEFAULT 0 2486221167Sgnn 2487221167Sgnn u32 rts_mac_en; 2488221167Sgnn#define VXGE_HAL_RTS_MAC_DISABLE 0 2489221167Sgnn#define VXGE_HAL_RTS_MAC_ENABLE 1 2490221167Sgnn#define VXGE_HAL_RTS_MAC_DEFAULT 0 2491221167Sgnn 2492221167Sgnn u32 rts_qos_en; 2493221167Sgnn#define VXGE_HAL_RTS_QOS_DISABLE 0 2494221167Sgnn#define VXGE_HAL_RTS_QOS_ENABLE 1 2495221167Sgnn#define VXGE_HAL_RTS_QOS_DEFAULT 0 2496221167Sgnn 2497221167Sgnn u32 rts_port_en; 2498221167Sgnn#define VXGE_HAL_RTS_PORT_DISABLE 0 2499221167Sgnn#define VXGE_HAL_RTS_PORT_ENABLE 1 2500221167Sgnn#define VXGE_HAL_RTS_PORT_DEFAULT 0 2501221167Sgnn 2502221167Sgnn vxge_hal_vp_config_t vp_config[VXGE_HAL_MAX_VIRTUAL_PATHS]; 2503221167Sgnn 2504221167Sgnn u32 max_cqe_groups; 2505221167Sgnn#define VXGE_HAL_MIN_MAX_CQE_GROUPS 1 2506221167Sgnn#define VXGE_HAL_MAX_MAX_CQE_GROUPS 16 2507221167Sgnn#define VXGE_HAL_DEF_MAX_CQE_GROUPS 16 2508221167Sgnn 2509221167Sgnn u32 max_num_wqe_od_groups; 2510221167Sgnn#define VXGE_HAL_MIN_MAX_NUM_OD_GROUPS 1 2511221167Sgnn#define VXGE_HAL_MAX_MAX_NUM_OD_GROUPS 16 2512221167Sgnn#define VXGE_HAL_DEF_MAX_NUM_OD_GROUPS 16 2513221167Sgnn 2514221167Sgnn u32 no_wqe_threshold; 2515221167Sgnn#define VXGE_HAL_MIN_NO_WQE_THRESHOLD 1 2516221167Sgnn#define VXGE_HAL_MAX_NO_WQE_THRESHOLD 16 2517221167Sgnn#define VXGE_HAL_DEF_NO_WQE_THRESHOLD 16 2518221167Sgnn 2519221167Sgnn u32 refill_threshold_high; 2520221167Sgnn#define VXGE_HAL_MIN_REFILL_THRESHOLD_HIGH 1 2521221167Sgnn#define VXGE_HAL_MAX_REFILL_THRESHOLD_HIGH 16 2522221167Sgnn#define VXGE_HAL_DEF_REFILL_THRESHOLD_HIGH 16 2523221167Sgnn 2524221167Sgnn u32 refill_threshold_low; 2525221167Sgnn#define VXGE_HAL_MIN_REFILL_THRESHOLD_LOW 1 2526221167Sgnn#define VXGE_HAL_MAX_REFILL_THRESHOLD_LOW 16 2527221167Sgnn#define VXGE_HAL_DEF_REFILL_THRESHOLD_LOW 16 2528221167Sgnn 2529221167Sgnn u32 ack_blk_limit; 2530221167Sgnn#define VXGE_HAL_MIN_ACK_BLOCK_LIMIT 1 2531221167Sgnn#define VXGE_HAL_MAX_ACK_BLOCK_LIMIT 16 2532221167Sgnn#define VXGE_HAL_DEF_ACK_BLOCK_LIMIT 16 2533221167Sgnn 2534221167Sgnn u32 poll_or_doorbell; 2535221167Sgnn#define VXGE_HAL_POLL_OR_DOORBELL_POLL 1 2536221167Sgnn#define VXGE_HAL_POLL_OR_DOORBELL_DOORBELL 0 2537221167Sgnn#define VXGE_HAL_POLL_OR_DOORBELL_DEFAULT 1 2538221167Sgnn 2539221167Sgnn u32 stats_read_method; 2540221167Sgnn#define VXGE_HAL_STATS_READ_METHOD_DMA 1 2541221167Sgnn#define VXGE_HAL_STATS_READ_METHOD_PIO 0 2542221167Sgnn#define VXGE_HAL_STATS_READ_METHOD_DEFAULT 1 2543221167Sgnn 2544221167Sgnn u32 device_poll_millis; 2545221167Sgnn#define VXGE_HAL_MIN_DEVICE_POLL_MILLIS 1 2546221167Sgnn#define VXGE_HAL_MAX_DEVICE_POLL_MILLIS 100000 2547221167Sgnn#define VXGE_HAL_DEF_DEVICE_POLL_MILLIS 1000 2548221167Sgnn 2549221167Sgnn vxge_debug_level_e debug_level; 2550221167Sgnn 2551221167Sgnn u32 debug_mask; 2552221167Sgnn 2553221167Sgnn 2554221167Sgnn#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR) 2555221167Sgnn u32 tracebuf_size; 2556221167Sgnn#define VXGE_HAL_MIN_CIRCULAR_ARR 4096 2557221167Sgnn#define VXGE_HAL_MAX_CIRCULAR_ARR 65536 2558221167Sgnn#define VXGE_HAL_DEF_CIRCULAR_ARR 16384 2559221167Sgnn#endif 2560221167Sgnn} vxge_hal_device_config_t; 2561221167Sgnn 2562221167Sgnn__EXTERN_END_DECLS 2563221167Sgnn 2564221167Sgnn#endif /* VXGE_HAL_CONFIG_H */ 2565