if_axereg.h revision 226743
1227569Sphilip/*- 2227569Sphilip * Copyright (c) 1997, 1998, 1999, 2000-2003 3227569Sphilip * Bill Paul <wpaul@windriver.com>. All rights reserved. 4227569Sphilip * 5227569Sphilip * Redistribution and use in source and binary forms, with or without 6227569Sphilip * modification, are permitted provided that the following conditions 7227569Sphilip * are met: 8227569Sphilip * 1. Redistributions of source code must retain the above copyright 9227569Sphilip * notice, this list of conditions and the following disclaimer. 10227569Sphilip * 2. Redistributions in binary form must reproduce the above copyright 11227569Sphilip * notice, this list of conditions and the following disclaimer in the 12227569Sphilip * documentation and/or other materials provided with the distribution. 13227569Sphilip * 3. All advertising materials mentioning features or use of this software 14227569Sphilip * must display the following acknowledgement: 15227569Sphilip * This product includes software developed by Bill Paul. 16227569Sphilip * 4. Neither the name of the author nor the names of any co-contributors 17227569Sphilip * may be used to endorse or promote products derived from this software 18227569Sphilip * without specific prior written permission. 19227569Sphilip * 20227569Sphilip * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21227569Sphilip * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22227569Sphilip * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23227569Sphilip * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24227569Sphilip * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25227569Sphilip * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26227569Sphilip * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27227569Sphilip * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28227569Sphilip * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29227569Sphilip * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30227569Sphilip * THE POSSIBILITY OF SUCH DAMAGE. 31227569Sphilip * 32227569Sphilip * $FreeBSD: head/sys/dev/usb/net/if_axereg.h 226743 2011-10-25 18:36:18Z yongari $ 33227569Sphilip */ 34227569Sphilip 35227569Sphilip/* 36227569Sphilip * Definitions for the ASIX Electronics AX88172, AX88178 37227569Sphilip * and AX88772 to ethernet controllers. 38227569Sphilip */ 39227569Sphilip 40227569Sphilip/* 41227569Sphilip * Vendor specific commands. ASIX conveniently doesn't document the 'set 42227569Sphilip * NODEID' command in their datasheet (thanks a lot guys). 43227569Sphilip * To make handling these commands easier, I added some extra data which is 44227569Sphilip * decided by the axe_cmd() routine. Commands are encoded in 16 bits, with 45227569Sphilip * the format: LDCC. L and D are both nibbles in the high byte. L represents 46227569Sphilip * the data length (0 to 15) and D represents the direction (0 for vendor read, 47227569Sphilip * 1 for vendor write). CC is the command byte, as specified in the manual. 48227569Sphilip */ 49227569Sphilip 50227569Sphilip#define AXE_CMD_IS_WRITE(x) (((x) & 0x0F00) >> 8) 51227569Sphilip#define AXE_CMD_LEN(x) (((x) & 0xF000) >> 12) 52227569Sphilip#define AXE_CMD_CMD(x) ((x) & 0x00FF) 53227569Sphilip 54227569Sphilip#define AXE_172_CMD_READ_RXTX_SRAM 0x2002 55227569Sphilip#define AXE_182_CMD_READ_RXTX_SRAM 0x8002 56227569Sphilip#define AXE_172_CMD_WRITE_RX_SRAM 0x0103 57227569Sphilip#define AXE_182_CMD_WRITE_RXTX_SRAM 0x8103 58227569Sphilip#define AXE_172_CMD_WRITE_TX_SRAM 0x0104 59227569Sphilip#define AXE_CMD_MII_OPMODE_SW 0x0106 60227569Sphilip#define AXE_CMD_MII_READ_REG 0x2007 61227569Sphilip#define AXE_CMD_MII_WRITE_REG 0x2108 62227569Sphilip#define AXE_CMD_MII_READ_OPMODE 0x1009 63227569Sphilip#define AXE_CMD_MII_OPMODE_HW 0x010A 64227569Sphilip#define AXE_CMD_SROM_READ 0x200B 65227569Sphilip#define AXE_CMD_SROM_WRITE 0x010C 66227569Sphilip#define AXE_CMD_SROM_WR_ENABLE 0x010D 67227569Sphilip#define AXE_CMD_SROM_WR_DISABLE 0x010E 68227569Sphilip#define AXE_CMD_RXCTL_READ 0x200F 69227569Sphilip#define AXE_CMD_RXCTL_WRITE 0x0110 70227569Sphilip#define AXE_CMD_READ_IPG012 0x3011 71227569Sphilip#define AXE_172_CMD_WRITE_IPG0 0x0112 72227569Sphilip#define AXE_178_CMD_WRITE_IPG012 0x0112 73227569Sphilip#define AXE_172_CMD_WRITE_IPG1 0x0113 74227569Sphilip#define AXE_178_CMD_READ_NODEID 0x6013 75227569Sphilip#define AXE_172_CMD_WRITE_IPG2 0x0114 76227569Sphilip#define AXE_178_CMD_WRITE_NODEID 0x6114 77227569Sphilip#define AXE_CMD_READ_MCAST 0x8015 78227569Sphilip#define AXE_CMD_WRITE_MCAST 0x8116 79227569Sphilip#define AXE_172_CMD_READ_NODEID 0x6017 80227569Sphilip#define AXE_172_CMD_WRITE_NODEID 0x6118 81227569Sphilip 82227569Sphilip#define AXE_CMD_READ_PHYID 0x2019 83227569Sphilip#define AXE_172_CMD_READ_MEDIA 0x101A 84227569Sphilip#define AXE_178_CMD_READ_MEDIA 0x201A 85227569Sphilip#define AXE_CMD_WRITE_MEDIA 0x011B 86227569Sphilip#define AXE_CMD_READ_MONITOR_MODE 0x101C 87227569Sphilip#define AXE_CMD_WRITE_MONITOR_MODE 0x011D 88227569Sphilip#define AXE_CMD_READ_GPIO 0x101E 89227569Sphilip#define AXE_CMD_WRITE_GPIO 0x011F 90227569Sphilip 91227569Sphilip#define AXE_CMD_SW_RESET_REG 0x0120 92227569Sphilip#define AXE_CMD_SW_PHY_STATUS 0x0021 93227569Sphilip#define AXE_CMD_SW_PHY_SELECT 0x0122 94227569Sphilip 95227569Sphilip/* AX88772A and AX88772B only. */ 96227569Sphilip#define AXE_CMD_READ_VLAN_CTRL 0x4027 97227569Sphilip#define AXE_CMD_WRITE_VLAN_CTRL 0x4028 98227569Sphilip 99227569Sphilip#define AXE_772B_CMD_RXCTL_WRITE_CFG 0x012A 100227569Sphilip#define AXE_772B_CMD_READ_RXCSUM 0x002B 101227569Sphilip#define AXE_772B_CMD_WRITE_RXCSUM 0x012C 102227569Sphilip#define AXE_772B_CMD_READ_TXCSUM 0x002D 103227569Sphilip#define AXE_772B_CMD_WRITE_TXCSUM 0x012E 104227569Sphilip 105227569Sphilip#define AXE_SW_RESET_CLEAR 0x00 106227569Sphilip#define AXE_SW_RESET_RR 0x01 107227569Sphilip#define AXE_SW_RESET_RT 0x02 108227569Sphilip#define AXE_SW_RESET_PRTE 0x04 109227569Sphilip#define AXE_SW_RESET_PRL 0x08 110227569Sphilip#define AXE_SW_RESET_BZ 0x10 111227569Sphilip#define AXE_SW_RESET_IPRL 0x20 112227569Sphilip#define AXE_SW_RESET_IPPD 0x40 113227569Sphilip 114227569Sphilip/* AX88178 documentation says to always write this bit... */ 115227569Sphilip#define AXE_178_RESET_MAGIC 0x40 116227569Sphilip 117227569Sphilip#define AXE_178_MEDIA_GMII 0x0001 118227569Sphilip#define AXE_MEDIA_FULL_DUPLEX 0x0002 119227569Sphilip#define AXE_172_MEDIA_TX_ABORT_ALLOW 0x0004 120227569Sphilip 121227569Sphilip/* AX88178/88772 documentation says to always write 1 to bit 2 */ 122227569Sphilip#define AXE_178_MEDIA_MAGIC 0x0004 123227569Sphilip/* AX88772 documentation says to always write 0 to bit 3 */ 124227569Sphilip#define AXE_178_MEDIA_ENCK 0x0008 125227569Sphilip#define AXE_172_MEDIA_FLOW_CONTROL_EN 0x0010 126227569Sphilip#define AXE_178_MEDIA_RXFLOW_CONTROL_EN 0x0010 127227569Sphilip#define AXE_178_MEDIA_TXFLOW_CONTROL_EN 0x0020 128227569Sphilip#define AXE_178_MEDIA_JUMBO_EN 0x0040 129227569Sphilip#define AXE_178_MEDIA_LTPF_ONLY 0x0080 130227569Sphilip#define AXE_178_MEDIA_RX_EN 0x0100 131227569Sphilip#define AXE_178_MEDIA_100TX 0x0200 132227569Sphilip#define AXE_178_MEDIA_SBP 0x0800 133227569Sphilip#define AXE_178_MEDIA_SUPERMAC 0x1000 134227569Sphilip 135227569Sphilip#define AXE_RXCMD_PROMISC 0x0001 136227569Sphilip#define AXE_RXCMD_ALLMULTI 0x0002 137227569Sphilip#define AXE_172_RXCMD_UNICAST 0x0004 138227569Sphilip#define AXE_178_RXCMD_KEEP_INVALID_CRC 0x0004 139227569Sphilip#define AXE_RXCMD_BROADCAST 0x0008 140227569Sphilip#define AXE_RXCMD_MULTICAST 0x0010 141227569Sphilip#define AXE_RXCMD_ACCEPT_RUNT 0x0040 /* AX88772B */ 142227569Sphilip#define AXE_RXCMD_ENABLE 0x0080 143227569Sphilip#define AXE_178_RXCMD_MFB_MASK 0x0300 144227569Sphilip#define AXE_178_RXCMD_MFB_2048 0x0000 145227569Sphilip#define AXE_178_RXCMD_MFB_4096 0x0100 146227569Sphilip#define AXE_178_RXCMD_MFB_8192 0x0200 147227569Sphilip#define AXE_178_RXCMD_MFB_16384 0x0300 148227569Sphilip#define AXE_772B_RXCMD_HDR_TYPE_0 0x0000 149227569Sphilip#define AXE_772B_RXCMD_HDR_TYPE_1 0x0100 150227569Sphilip#define AXE_772B_RXCMD_IPHDR_ALIGN 0x0200 151227569Sphilip#define AXE_772B_RXCMD_ADD_CHKSUM 0x0400 152227569Sphilip#define AXE_RXCMD_LOOPBACK 0x1000 /* AX88772A/AX88772B */ 153227569Sphilip 154227569Sphilip#define AXE_PHY_SEL_PRI 1 155227569Sphilip#define AXE_PHY_SEL_SEC 0 156227569Sphilip#define AXE_PHY_TYPE_MASK 0xE0 157227569Sphilip#define AXE_PHY_TYPE_SHIFT 5 158227569Sphilip#define AXE_PHY_TYPE(x) \ 159227569Sphilip (((x) & AXE_PHY_TYPE_MASK) >> AXE_PHY_TYPE_SHIFT) 160227569Sphilip 161227569Sphilip#define PHY_TYPE_100_HOME 0 /* 10/100 or 1M HOME PHY */ 162227569Sphilip#define PHY_TYPE_GIG 1 /* Gigabit PHY */ 163227569Sphilip#define PHY_TYPE_SPECIAL 4 /* Special case */ 164227569Sphilip#define PHY_TYPE_RSVD 5 /* Reserved */ 165227569Sphilip#define PHY_TYPE_NON_SUP 7 /* Non-supported PHY */ 166227569Sphilip 167227569Sphilip#define AXE_PHY_NO_MASK 0x1F 168227569Sphilip#define AXE_PHY_NO(x) ((x) & AXE_PHY_NO_MASK) 169227569Sphilip 170227569Sphilip#define AXE_772_PHY_NO_EPHY 0x10 /* Embedded 10/100 PHY of AX88772 */ 171227569Sphilip 172227569Sphilip#define AXE_GPIO0_EN 0x01 173227569Sphilip#define AXE_GPIO0 0x02 174227569Sphilip#define AXE_GPIO1_EN 0x04 175227569Sphilip#define AXE_GPIO1 0x08 176227569Sphilip#define AXE_GPIO2_EN 0x10 177227569Sphilip#define AXE_GPIO2 0x20 178227569Sphilip#define AXE_GPIO_RELOAD_EEPROM 0x80 179227569Sphilip 180227569Sphilip#define AXE_PHY_MODE_MARVELL 0x00 181227569Sphilip#define AXE_PHY_MODE_CICADA 0x01 182227569Sphilip#define AXE_PHY_MODE_AGERE 0x02 183227569Sphilip#define AXE_PHY_MODE_CICADA_V2 0x05 184227569Sphilip#define AXE_PHY_MODE_AGERE_GMII 0x06 185227569Sphilip#define AXE_PHY_MODE_CICADA_V2_ASIX 0x09 186227569Sphilip#define AXE_PHY_MODE_REALTEK_8211CL 0x0C 187227569Sphilip#define AXE_PHY_MODE_REALTEK_8211BN 0x0D 188227569Sphilip#define AXE_PHY_MODE_REALTEK_8251CL 0x0E 189227569Sphilip#define AXE_PHY_MODE_ATTANSIC 0x40 190227569Sphilip 191227569Sphilip/* AX88772A/AX88772B only. */ 192227569Sphilip#define AXE_SW_PHY_SELECT_EXT 0x0000 193227569Sphilip#define AXE_SW_PHY_SELECT_EMBEDDED 0x0001 194227569Sphilip#define AXE_SW_PHY_SELECT_AUTO 0x0002 195227569Sphilip#define AXE_SW_PHY_SELECT_SS_MII 0x0004 196227569Sphilip#define AXE_SW_PHY_SELECT_SS_RVRS_MII 0x0008 197227569Sphilip#define AXE_SW_PHY_SELECT_SS_RVRS_RMII 0x000C 198227569Sphilip#define AXE_SW_PHY_SELECT_SS_ENB 0x0010 199227569Sphilip 200227569Sphilip/* AX88772A/AX88772B VLAN control. */ 201227569Sphilip#define AXE_VLAN_CTRL_ENB 0x00001000 202227569Sphilip#define AXE_VLAN_CTRL_STRIP 0x00002000 203227569Sphilip#define AXE_VLAN_CTRL_VID1_MASK 0x00000FFF 204227569Sphilip#define AXE_VLAN_CTRL_VID2_MASK 0x0FFF0000 205227569Sphilip 206227569Sphilip#define AXE_RXCSUM_IP 0x0001 207227569Sphilip#define AXE_RXCSUM_IPVE 0x0002 208227569Sphilip#define AXE_RXCSUM_IPV6E 0x0004 209227569Sphilip#define AXE_RXCSUM_TCP 0x0008 210227569Sphilip#define AXE_RXCSUM_UDP 0x0010 211227569Sphilip#define AXE_RXCSUM_ICMP 0x0020 212227569Sphilip#define AXE_RXCSUM_IGMP 0x0040 213227569Sphilip#define AXE_RXCSUM_ICMP6 0x0080 214227569Sphilip#define AXE_RXCSUM_TCPV6 0x0100 215227569Sphilip#define AXE_RXCSUM_UDPV6 0x0200 216227569Sphilip#define AXE_RXCSUM_ICMPV6 0x0400 217227569Sphilip#define AXE_RXCSUM_IGMPV6 0x0800 218227569Sphilip#define AXE_RXCSUM_ICMP6V6 0x1000 219227569Sphilip#define AXE_RXCSUM_FOPC 0x8000 220227569Sphilip 221227569Sphilip#define AXE_RXCSUM_64TE 0x0100 222227569Sphilip#define AXE_RXCSUM_PPPOE 0x0200 223227569Sphilip#define AXE_RXCSUM_RPCE 0x8000 224227569Sphilip 225227569Sphilip#define AXE_TXCSUM_IP 0x0001 226227569Sphilip#define AXE_TXCSUM_TCP 0x0002 227227569Sphilip#define AXE_TXCSUM_UDP 0x0004 228227569Sphilip#define AXE_TXCSUM_ICMP 0x0008 229227569Sphilip#define AXE_TXCSUM_IGMP 0x0010 230227569Sphilip#define AXE_TXCSUM_ICMP6 0x0020 231227569Sphilip#define AXE_TXCSUM_TCPV6 0x0100 232227569Sphilip#define AXE_TXCSUM_UDPV6 0x0200 233227569Sphilip#define AXE_TXCSUM_ICMPV6 0x0400 234227569Sphilip#define AXE_TXCSUM_IGMPV6 0x0800 235227569Sphilip#define AXE_TXCSUM_ICMP6V6 0x1000 236227569Sphilip 237227569Sphilip#define AXE_TXCSUM_64TE 0x0001 238227569Sphilip#define AXE_TXCSUM_PPPOE 0x0002 239227569Sphilip 240227569Sphilip#define AXE_BULK_BUF_SIZE 16384 /* bytes */ 241227569Sphilip 242227569Sphilip#define AXE_CTL_READ 0x01 243227569Sphilip#define AXE_CTL_WRITE 0x02 244227569Sphilip 245227569Sphilip#define AXE_CONFIG_IDX 0 /* config number 1 */ 246227569Sphilip#define AXE_IFACE_IDX 0 247227569Sphilip 248227569Sphilip/* EEPROM Map. */ 249227569Sphilip#define AXE_EEPROM_772B_NODE_ID 0x04 250227569Sphilip#define AXE_EEPROM_772B_PHY_PWRCFG 0x18 251227569Sphilip 252227569Sphilipstruct ax88772b_mfb { 253227569Sphilip int byte_cnt; 254227569Sphilip int threshold; 255227569Sphilip int size; 256227569Sphilip}; 257227569Sphilip#define AX88772B_MFB_2K 0 258227569Sphilip#define AX88772B_MFB_4K 1 259227569Sphilip#define AX88772B_MFB_6K 2 260227569Sphilip#define AX88772B_MFB_8K 3 261227569Sphilip#define AX88772B_MFB_16K 4 262227569Sphilip#define AX88772B_MFB_20K 5 263227569Sphilip#define AX88772B_MFB_24K 6 264227569Sphilip#define AX88772B_MFB_32K 7 265227569Sphilip 266227569Sphilipstruct axe_sframe_hdr { 267227569Sphilip uint16_t len; 268227569Sphilip#define AXE_HDR_LEN_MASK 0xFFFF 269227569Sphilip uint16_t ilen; 270227569Sphilip} __packed; 271227569Sphilip 272227569Sphilip#define AXE_TX_CSUM_PSEUDO_HDR 0x4000 273227569Sphilip#define AXE_TX_CSUM_DIS 0x8000 274227569Sphilip 275227569Sphilip/* 276227569Sphilip * When RX checksum offloading is enabled, AX88772B uses new RX header 277227569Sphilip * format and it's not compatible with previous RX header format. In 278227569Sphilip * addition, IP header align option should be enabled to get correct 279227569Sphilip * frame size including RX header. Total transferred size including 280227569Sphilip * the RX header is multiple of 4 and controller will pad necessary 281227569Sphilip * bytes if the length is not multiple of 4. 282227569Sphilip * This driver does not enable partial checksum feature which will 283227569Sphilip * compute 16bit checksum from 14th byte to the end of the frame. If 284227569Sphilip * this feature is enabled, computed checksum value is embedded into 285227569Sphilip * RX header which in turn means it uses different RX header format. 286227569Sphilip */ 287227569Sphilipstruct axe_csum_hdr { 288227569Sphilip uint16_t len; 289227569Sphilip#define AXE_CSUM_HDR_LEN_MASK 0x07FF 290227569Sphilip#define AXE_CSUM_HDR_CRC_ERR 0x1000 291227569Sphilip#define AXE_CSUM_HDR_MII_ERR 0x2000 292227569Sphilip#define AXE_CSUM_HDR_RUNT 0x4000 293227569Sphilip#define AXE_CSUM_HDR_BMCAST 0x8000 294227569Sphilip uint16_t ilen; 295227569Sphilip uint16_t cstatus; 296227569Sphilip#define AXE_CSUM_HDR_VLAN_MASK 0x0007 297227569Sphilip#define AXE_CSUM_HDR_VLAN_STRIP 0x0008 298227569Sphilip#define AXE_CSUM_HDR_VLAN_PRI_MASK 0x0070 299227569Sphilip#define AXE_CSUM_HDR_L4_CSUM_ERR 0x0100 300227569Sphilip#define AXE_CSUM_HDR_L3_CSUM_ERR 0x0200 301227569Sphilip#define AXE_CSUM_HDR_L4_TYPE_UDP 0x0400 302227569Sphilip#define AXE_CSUM_HDR_L4_TYPE_ICMP 0x0800 303227569Sphilip#define AXE_CSUM_HDR_L4_TYPE_IGMP 0x0C00 304227569Sphilip#define AXE_CSUM_HDR_L4_TYPE_TCP 0x1000 305227569Sphilip#define AXE_CSUM_HDR_L4_TYPE_TCPV6 0x1400 306227569Sphilip#define AXE_CSUM_HDR_L4_TYPE_MASK 0x1C00 307227569Sphilip#define AXE_CSUM_HDR_L3_TYPE_IPV4 0x2000 308227569Sphilip#define AXE_CSUM_HDR_L3_TYPE_IPV6 0x4000 309227569Sphilip 310227569Sphilip#ifdef AXE_APPEND_PARTIAL_CSUM 311227569Sphilip /* 312227569Sphilip * These members present only when partial checksum 313227569Sphilip * offloading is enabled. The checksum value is simple 314227569Sphilip * 16bit sum of received frame starting at offset 14 of 315227569Sphilip * the frame to the end of the frame excluding FCS bytes. 316227569Sphilip */ 317227569Sphilip uint16_t csum_value; 318227569Sphilip uint16_t dummy; 319227569Sphilip#endif 320227569Sphilip} __packed; 321227569Sphilip 322227569Sphilip#define AXE_CSUM_RXBYTES(x) ((x) & AXE_CSUM_HDR_LEN_MASK) 323227569Sphilip 324227569Sphilip#define GET_MII(sc) uether_getmii(&(sc)->sc_ue) 325227569Sphilip 326227569Sphilip/* The interrupt endpoint is currently unused by the ASIX part. */ 327227569Sphilipenum { 328227569Sphilip AXE_BULK_DT_WR, 329227569Sphilip AXE_BULK_DT_RD, 330227569Sphilip AXE_N_TRANSFER, 331227569Sphilip}; 332227569Sphilip 333227569Sphilipstruct axe_softc { 334227569Sphilip struct usb_ether sc_ue; 335227569Sphilip struct mtx sc_mtx; 336227569Sphilip struct usb_xfer *sc_xfer[AXE_N_TRANSFER]; 337227569Sphilip int sc_phyno; 338227569Sphilip 339227569Sphilip int sc_flags; 340227569Sphilip#define AXE_FLAG_LINK 0x0001 341227569Sphilip#define AXE_FLAG_STD_FRAME 0x0010 342227569Sphilip#define AXE_FLAG_CSUM_FRAME 0x0020 343227569Sphilip#define AXE_FLAG_772 0x1000 /* AX88772 */ 344227569Sphilip#define AXE_FLAG_772A 0x2000 /* AX88772A */ 345227569Sphilip#define AXE_FLAG_772B 0x4000 /* AX88772B */ 346227569Sphilip#define AXE_FLAG_178 0x8000 /* AX88178 */ 347227569Sphilip 348227569Sphilip uint8_t sc_ipgs[3]; 349227569Sphilip uint8_t sc_phyaddrs[2]; 350227569Sphilip uint16_t sc_pwrcfg; 351227569Sphilip uint16_t sc_lenmask; 352227569Sphilip int sc_tx_bufsz; 353227569Sphilip}; 354227569Sphilip 355227569Sphilip#define AXE_IS_178_FAMILY(sc) \ 356227569Sphilip ((sc)->sc_flags & (AXE_FLAG_772 | AXE_FLAG_772A | AXE_FLAG_772B | \ 357227569Sphilip AXE_FLAG_178)) 358227569Sphilip 359227569Sphilip#define AXE_IS_772(sc) \ 360227569Sphilip ((sc)->sc_flags & (AXE_FLAG_772 | AXE_FLAG_772A | AXE_FLAG_772B)) 361227569Sphilip 362227569Sphilip#define AXE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 363227569Sphilip#define AXE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 364227569Sphilip#define AXE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) 365227569Sphilip