if_axe.c revision 222581
1/*- 2 * Copyright (c) 1997, 1998, 1999, 2000-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/usb/net/if_axe.c 222581 2011-06-01 18:42:44Z yongari $"); 35 36/* 37 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 38 * Used in the LinkSys USB200M and various other adapters. 39 * 40 * Manuals available from: 41 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF 42 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet 43 * controller) to find the definitions for the RX control register. 44 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF 45 * 46 * Written by Bill Paul <wpaul@windriver.com> 47 * Senior Engineer 48 * Wind River Systems 49 */ 50 51/* 52 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 53 * It uses an external PHY (reference designs use a RealTek chip), 54 * and has a 64-bit multicast hash filter. There is some information 55 * missing from the manual which one needs to know in order to make 56 * the chip function: 57 * 58 * - You must set bit 7 in the RX control register, otherwise the 59 * chip won't receive any packets. 60 * - You must initialize all 3 IPG registers, or you won't be able 61 * to send any packets. 62 * 63 * Note that this device appears to only support loading the station 64 * address via autload from the EEPROM (i.e. there's no way to manaully 65 * set it). 66 * 67 * (Adam Weinberger wanted me to name this driver if_gir.c.) 68 */ 69 70/* 71 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 72 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com 73 * 74 * Manual here: 75 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 76 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 77 */ 78 79#include <sys/stdint.h> 80#include <sys/stddef.h> 81#include <sys/param.h> 82#include <sys/queue.h> 83#include <sys/types.h> 84#include <sys/systm.h> 85#include <sys/kernel.h> 86#include <sys/bus.h> 87#include <sys/module.h> 88#include <sys/lock.h> 89#include <sys/mutex.h> 90#include <sys/condvar.h> 91#include <sys/sysctl.h> 92#include <sys/sx.h> 93#include <sys/unistd.h> 94#include <sys/callout.h> 95#include <sys/malloc.h> 96#include <sys/priv.h> 97 98#include <dev/usb/usb.h> 99#include <dev/usb/usbdi.h> 100#include <dev/usb/usbdi_util.h> 101#include "usbdevs.h" 102 103#define USB_DEBUG_VAR axe_debug 104#include <dev/usb/usb_debug.h> 105#include <dev/usb/usb_process.h> 106 107#include <dev/usb/net/usb_ethernet.h> 108#include <dev/usb/net/if_axereg.h> 109 110/* 111 * AXE_178_MAX_FRAME_BURST 112 * max frame burst size for Ax88178 and Ax88772 113 * 0 2048 bytes 114 * 1 4096 bytes 115 * 2 8192 bytes 116 * 3 16384 bytes 117 * use the largest your system can handle without USB stalling. 118 * 119 * NB: 88772 parts appear to generate lots of input errors with 120 * a 2K rx buffer and 8K is only slightly faster than 4K on an 121 * EHCI port on a T42 so change at your own risk. 122 */ 123#define AXE_178_MAX_FRAME_BURST 1 124 125#ifdef USB_DEBUG 126static int axe_debug = 0; 127 128SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW, 0, "USB axe"); 129SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RW, &axe_debug, 0, 130 "Debug level"); 131#endif 132 133/* 134 * Various supported device vendors/products. 135 */ 136static const struct usb_device_id axe_devs[] = { 137#define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } 138 AXE_DEV(ABOCOM, UF200, 0), 139 AXE_DEV(ACERCM, EP1427X2, 0), 140 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772), 141 AXE_DEV(ASIX, AX88172, 0), 142 AXE_DEV(ASIX, AX88178, AXE_FLAG_178), 143 AXE_DEV(ASIX, AX88772, AXE_FLAG_772), 144 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A), 145 AXE_DEV(ATEN, UC210T, 0), 146 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178), 147 AXE_DEV(BILLIONTON, USB2AR, 0), 148 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A), 149 AXE_DEV(COREGA, FETHER_USB2_TX, 0), 150 AXE_DEV(DLINK, DUBE100, 0), 151 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772), 152 AXE_DEV(GOODWAY, GWUSB2E, 0), 153 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178), 154 AXE_DEV(JVC, MP_PRX1, 0), 155 AXE_DEV(LINKSYS2, USB200M, 0), 156 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178), 157 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178), 158 AXE_DEV(MELCO, LUAU2KTX, 0), 159 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178), 160 AXE_DEV(NETGEAR, FA120, 0), 161 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772), 162 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178), 163 AXE_DEV(SITECOM, LN029, 0), 164 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178), 165 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0), 166#undef AXE_DEV 167}; 168 169static device_probe_t axe_probe; 170static device_attach_t axe_attach; 171static device_detach_t axe_detach; 172 173static usb_callback_t axe_bulk_read_callback; 174static usb_callback_t axe_bulk_write_callback; 175 176static miibus_readreg_t axe_miibus_readreg; 177static miibus_writereg_t axe_miibus_writereg; 178static miibus_statchg_t axe_miibus_statchg; 179 180static uether_fn_t axe_attach_post; 181static uether_fn_t axe_init; 182static uether_fn_t axe_stop; 183static uether_fn_t axe_start; 184static uether_fn_t axe_tick; 185static uether_fn_t axe_setmulti; 186static uether_fn_t axe_setpromisc; 187 188static int axe_ifmedia_upd(struct ifnet *); 189static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 190static int axe_cmd(struct axe_softc *, int, int, int, void *); 191static void axe_ax88178_init(struct axe_softc *); 192static void axe_ax88772_init(struct axe_softc *); 193static void axe_ax88772a_init(struct axe_softc *); 194static int axe_get_phyno(struct axe_softc *, int); 195 196static const struct usb_config axe_config[AXE_N_TRANSFER] = { 197 198 [AXE_BULK_DT_WR] = { 199 .type = UE_BULK, 200 .endpoint = UE_ADDR_ANY, 201 .direction = UE_DIR_OUT, 202 .frames = 16, 203 .bufsize = 16 * MCLBYTES, 204 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 205 .callback = axe_bulk_write_callback, 206 .timeout = 10000, /* 10 seconds */ 207 }, 208 209 [AXE_BULK_DT_RD] = { 210 .type = UE_BULK, 211 .endpoint = UE_ADDR_ANY, 212 .direction = UE_DIR_IN, 213 .bufsize = 16384, /* bytes */ 214 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 215 .callback = axe_bulk_read_callback, 216 .timeout = 0, /* no timeout */ 217 }, 218}; 219 220static device_method_t axe_methods[] = { 221 /* Device interface */ 222 DEVMETHOD(device_probe, axe_probe), 223 DEVMETHOD(device_attach, axe_attach), 224 DEVMETHOD(device_detach, axe_detach), 225 226 /* bus interface */ 227 DEVMETHOD(bus_print_child, bus_generic_print_child), 228 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 229 230 /* MII interface */ 231 DEVMETHOD(miibus_readreg, axe_miibus_readreg), 232 DEVMETHOD(miibus_writereg, axe_miibus_writereg), 233 DEVMETHOD(miibus_statchg, axe_miibus_statchg), 234 235 {0, 0} 236}; 237 238static driver_t axe_driver = { 239 .name = "axe", 240 .methods = axe_methods, 241 .size = sizeof(struct axe_softc), 242}; 243 244static devclass_t axe_devclass; 245 246DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, 0); 247DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, 0, 0); 248MODULE_DEPEND(axe, uether, 1, 1, 1); 249MODULE_DEPEND(axe, usb, 1, 1, 1); 250MODULE_DEPEND(axe, ether, 1, 1, 1); 251MODULE_DEPEND(axe, miibus, 1, 1, 1); 252MODULE_VERSION(axe, 1); 253 254static const struct usb_ether_methods axe_ue_methods = { 255 .ue_attach_post = axe_attach_post, 256 .ue_start = axe_start, 257 .ue_init = axe_init, 258 .ue_stop = axe_stop, 259 .ue_tick = axe_tick, 260 .ue_setmulti = axe_setmulti, 261 .ue_setpromisc = axe_setpromisc, 262 .ue_mii_upd = axe_ifmedia_upd, 263 .ue_mii_sts = axe_ifmedia_sts, 264}; 265 266static int 267axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 268{ 269 struct usb_device_request req; 270 usb_error_t err; 271 272 AXE_LOCK_ASSERT(sc, MA_OWNED); 273 274 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ? 275 UT_WRITE_VENDOR_DEVICE : 276 UT_READ_VENDOR_DEVICE); 277 req.bRequest = AXE_CMD_CMD(cmd); 278 USETW(req.wValue, val); 279 USETW(req.wIndex, index); 280 USETW(req.wLength, AXE_CMD_LEN(cmd)); 281 282 err = uether_do_request(&sc->sc_ue, &req, buf, 1000); 283 284 return (err); 285} 286 287static int 288axe_miibus_readreg(device_t dev, int phy, int reg) 289{ 290 struct axe_softc *sc = device_get_softc(dev); 291 uint16_t val; 292 int locked; 293 294 if (sc->sc_phyno != phy) 295 return (0); 296 297 locked = mtx_owned(&sc->sc_mtx); 298 if (!locked) 299 AXE_LOCK(sc); 300 301 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 302 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val); 303 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 304 305 val = le16toh(val); 306 if (AXE_IS_772(sc) && reg == MII_BMSR) { 307 /* 308 * BMSR of AX88772 indicates that it supports extended 309 * capability but the extended status register is 310 * revered for embedded ethernet PHY. So clear the 311 * extended capability bit of BMSR. 312 */ 313 val &= ~BMSR_EXTCAP; 314 } 315 316 if (!locked) 317 AXE_UNLOCK(sc); 318 return (val); 319} 320 321static int 322axe_miibus_writereg(device_t dev, int phy, int reg, int val) 323{ 324 struct axe_softc *sc = device_get_softc(dev); 325 int locked; 326 327 val = htole32(val); 328 329 if (sc->sc_phyno != phy) 330 return (0); 331 332 locked = mtx_owned(&sc->sc_mtx); 333 if (!locked) 334 AXE_LOCK(sc); 335 336 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 337 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val); 338 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 339 340 if (!locked) 341 AXE_UNLOCK(sc); 342 return (0); 343} 344 345static void 346axe_miibus_statchg(device_t dev) 347{ 348 struct axe_softc *sc = device_get_softc(dev); 349 struct mii_data *mii = GET_MII(sc); 350 struct ifnet *ifp; 351 uint16_t val; 352 int err, locked; 353 354 locked = mtx_owned(&sc->sc_mtx); 355 if (!locked) 356 AXE_LOCK(sc); 357 358 ifp = uether_getifp(&sc->sc_ue); 359 if (mii == NULL || ifp == NULL || 360 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 361 goto done; 362 363 sc->sc_flags &= ~AXE_FLAG_LINK; 364 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 365 (IFM_ACTIVE | IFM_AVALID)) { 366 switch (IFM_SUBTYPE(mii->mii_media_active)) { 367 case IFM_10_T: 368 case IFM_100_TX: 369 sc->sc_flags |= AXE_FLAG_LINK; 370 break; 371 case IFM_1000_T: 372 if ((sc->sc_flags & AXE_FLAG_178) == 0) 373 break; 374 sc->sc_flags |= AXE_FLAG_LINK; 375 break; 376 default: 377 break; 378 } 379 } 380 381 /* Lost link, do nothing. */ 382 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) 383 goto done; 384 385 val = 0; 386 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 387 val |= AXE_MEDIA_FULL_DUPLEX; 388 if (AXE_IS_178_FAMILY(sc)) { 389 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 390 if ((sc->sc_flags & AXE_FLAG_178) != 0) 391 val |= AXE_178_MEDIA_ENCK; 392 switch (IFM_SUBTYPE(mii->mii_media_active)) { 393 case IFM_1000_T: 394 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 395 break; 396 case IFM_100_TX: 397 val |= AXE_178_MEDIA_100TX; 398 break; 399 case IFM_10_T: 400 /* doesn't need to be handled */ 401 break; 402 } 403 } 404 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 405 if (err) 406 device_printf(dev, "media change failed, error %d\n", err); 407done: 408 if (!locked) 409 AXE_UNLOCK(sc); 410} 411 412/* 413 * Set media options. 414 */ 415static int 416axe_ifmedia_upd(struct ifnet *ifp) 417{ 418 struct axe_softc *sc = ifp->if_softc; 419 struct mii_data *mii = GET_MII(sc); 420 struct mii_softc *miisc; 421 int error; 422 423 AXE_LOCK_ASSERT(sc, MA_OWNED); 424 425 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 426 PHY_RESET(miisc); 427 error = mii_mediachg(mii); 428 return (error); 429} 430 431/* 432 * Report current media status. 433 */ 434static void 435axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 436{ 437 struct axe_softc *sc = ifp->if_softc; 438 struct mii_data *mii = GET_MII(sc); 439 440 AXE_LOCK(sc); 441 mii_pollstat(mii); 442 AXE_UNLOCK(sc); 443 ifmr->ifm_active = mii->mii_media_active; 444 ifmr->ifm_status = mii->mii_media_status; 445} 446 447static void 448axe_setmulti(struct usb_ether *ue) 449{ 450 struct axe_softc *sc = uether_getsc(ue); 451 struct ifnet *ifp = uether_getifp(ue); 452 struct ifmultiaddr *ifma; 453 uint32_t h = 0; 454 uint16_t rxmode; 455 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 456 457 AXE_LOCK_ASSERT(sc, MA_OWNED); 458 459 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 460 rxmode = le16toh(rxmode); 461 462 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 463 rxmode |= AXE_RXCMD_ALLMULTI; 464 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 465 return; 466 } 467 rxmode &= ~AXE_RXCMD_ALLMULTI; 468 469 if_maddr_rlock(ifp); 470 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 471 { 472 if (ifma->ifma_addr->sa_family != AF_LINK) 473 continue; 474 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 475 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 476 hashtbl[h / 8] |= 1 << (h % 8); 477 } 478 if_maddr_runlock(ifp); 479 480 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl); 481 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 482} 483 484static int 485axe_get_phyno(struct axe_softc *sc, int sel) 486{ 487 int phyno; 488 489 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) { 490 case PHY_TYPE_100_HOME: 491 case PHY_TYPE_GIG: 492 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]); 493 break; 494 case PHY_TYPE_SPECIAL: 495 /* FALLTHROUGH */ 496 case PHY_TYPE_RSVD: 497 /* FALLTHROUGH */ 498 case PHY_TYPE_NON_SUP: 499 /* FALLTHROUGH */ 500 default: 501 phyno = -1; 502 break; 503 } 504 505 return (phyno); 506} 507 508#define AXE_GPIO_WRITE(x, y) do { \ 509 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 510 uether_pause(ue, (y)); \ 511} while (0) 512 513static void 514axe_ax88178_init(struct axe_softc *sc) 515{ 516 struct usb_ether *ue; 517 int gpio0, ledmode, phymode; 518 uint16_t eeprom, val; 519 520 ue = &sc->sc_ue; 521 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 522 /* XXX magic */ 523 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); 524 eeprom = le16toh(eeprom); 525 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 526 527 /* if EEPROM is invalid we have to use to GPIO0 */ 528 if (eeprom == 0xffff) { 529 phymode = AXE_PHY_MODE_MARVELL; 530 gpio0 = 1; 531 ledmode = 0; 532 } else { 533 phymode = eeprom & 0x7f; 534 gpio0 = (eeprom & 0x80) ? 0 : 1; 535 ledmode = eeprom >> 8; 536 } 537 538 if (bootverbose) 539 device_printf(sc->sc_ue.ue_dev, 540 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom, 541 phymode); 542 /* Program GPIOs depending on PHY hardware. */ 543 switch (phymode) { 544 case AXE_PHY_MODE_MARVELL: 545 if (gpio0 == 1) { 546 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 547 hz / 32); 548 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 549 hz / 32); 550 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 551 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 552 hz / 32); 553 } else { 554 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 555 AXE_GPIO1_EN, hz / 3); 556 if (ledmode == 1) { 557 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 558 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 559 hz / 3); 560 } else { 561 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 562 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 563 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 564 AXE_GPIO2_EN, hz / 4); 565 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 566 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 567 } 568 } 569 break; 570 case AXE_PHY_MODE_CICADA: 571 case AXE_PHY_MODE_CICADA_V2: 572 case AXE_PHY_MODE_CICADA_V2_ASIX: 573 if (gpio0 == 1) 574 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 575 AXE_GPIO0_EN, hz / 32); 576 else 577 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 578 AXE_GPIO1_EN, hz / 32); 579 break; 580 case AXE_PHY_MODE_AGERE: 581 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 582 AXE_GPIO1_EN, hz / 32); 583 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 584 AXE_GPIO2_EN, hz / 32); 585 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 586 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 587 AXE_GPIO2_EN, hz / 32); 588 break; 589 case AXE_PHY_MODE_REALTEK_8211CL: 590 case AXE_PHY_MODE_REALTEK_8211BN: 591 case AXE_PHY_MODE_REALTEK_8251CL: 592 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 593 AXE_GPIO1 | AXE_GPIO1_EN; 594 AXE_GPIO_WRITE(val, hz / 32); 595 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 596 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 597 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 598 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 599 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 600 0x1F, 0x0005); 601 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 602 0x0C, 0x0000); 603 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno, 604 0x0001); 605 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 606 0x01, val | 0x0080); 607 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 608 0x1F, 0x0000); 609 } 610 break; 611 default: 612 /* Unknown PHY model or no need to program GPIOs. */ 613 break; 614 } 615 616 /* soft reset */ 617 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 618 uether_pause(ue, hz / 4); 619 620 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 621 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 622 uether_pause(ue, hz / 4); 623 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 624 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 625 uether_pause(ue, hz / 4); 626 627 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 628} 629 630static void 631axe_ax88772_init(struct axe_softc *sc) 632{ 633 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 634 uether_pause(&sc->sc_ue, hz / 16); 635 636 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 637 /* ask for the embedded PHY */ 638 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL); 639 uether_pause(&sc->sc_ue, hz / 64); 640 641 /* power down and reset state, pin reset state */ 642 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 643 AXE_SW_RESET_CLEAR, NULL); 644 uether_pause(&sc->sc_ue, hz / 16); 645 646 /* power down/reset state, pin operating state */ 647 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 648 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 649 uether_pause(&sc->sc_ue, hz / 4); 650 651 /* power up, reset */ 652 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 653 654 /* power up, operating */ 655 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 656 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 657 } else { 658 /* ask for external PHY */ 659 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL); 660 uether_pause(&sc->sc_ue, hz / 64); 661 662 /* power down internal PHY */ 663 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 664 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 665 } 666 667 uether_pause(&sc->sc_ue, hz / 4); 668 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 669} 670 671static void 672axe_ax88772a_init(struct axe_softc *sc) 673{ 674 struct usb_ether *ue; 675 uint16_t eeprom; 676 677 ue = &sc->sc_ue; 678 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); 679 eeprom = le16toh(eeprom); 680 /* Reload EEPROM. */ 681 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 682 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 683 /* Manually select internal(embedded) PHY - MAC mode. */ 684 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 685 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII, 686 NULL); 687 uether_pause(&sc->sc_ue, hz / 32); 688 } else { 689 /* 690 * Manually select external PHY - MAC mode. 691 * Reverse MII/RMII is for AX88772A PHY mode. 692 */ 693 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 694 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 695 uether_pause(&sc->sc_ue, hz / 32); 696 } 697 /* Take PHY out of power down. */ 698 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 699 AXE_SW_RESET_IPRL, NULL); 700 uether_pause(&sc->sc_ue, hz / 4); 701 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 702 uether_pause(&sc->sc_ue, hz); 703 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 704 uether_pause(&sc->sc_ue, hz / 32); 705 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 706 uether_pause(&sc->sc_ue, hz / 32); 707 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 708} 709 710#undef AXE_GPIO_WRITE 711 712static void 713axe_reset(struct axe_softc *sc) 714{ 715 struct usb_config_descriptor *cd; 716 usb_error_t err; 717 718 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); 719 720 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, 721 cd->bConfigurationValue); 722 if (err) 723 DPRINTF("reset failed (ignored)\n"); 724 725 /* Wait a little while for the chip to get its brains in order. */ 726 uether_pause(&sc->sc_ue, hz / 100); 727 728 /* Reinitialize controller to achieve full reset. */ 729 if (sc->sc_flags & AXE_FLAG_178) 730 axe_ax88178_init(sc); 731 else if (sc->sc_flags & AXE_FLAG_772) 732 axe_ax88772_init(sc); 733 else if (sc->sc_flags & AXE_FLAG_772A) 734 axe_ax88772a_init(sc); 735} 736 737static void 738axe_attach_post(struct usb_ether *ue) 739{ 740 struct axe_softc *sc = uether_getsc(ue); 741 742 /* 743 * Load PHY indexes first. Needed by axe_xxx_init(). 744 */ 745 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs); 746 if (bootverbose) 747 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n", 748 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]); 749 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 750 if (sc->sc_phyno == -1) 751 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 752 if (sc->sc_phyno == -1) { 753 device_printf(sc->sc_ue.ue_dev, 754 "no valid PHY address found, assuming PHY address 0\n"); 755 sc->sc_phyno = 0; 756 } 757 758 if (sc->sc_flags & AXE_FLAG_178) { 759 axe_ax88178_init(sc); 760 sc->sc_tx_bufsz = 16 * 1024; 761 } else if (sc->sc_flags & AXE_FLAG_772) { 762 axe_ax88772_init(sc); 763 sc->sc_tx_bufsz = 8 * 1024; 764 } else if (sc->sc_flags & AXE_FLAG_772A) { 765 axe_ax88772a_init(sc); 766 sc->sc_tx_bufsz = 8 * 1024; 767 } 768 769 /* 770 * Get station address. 771 */ 772 if (AXE_IS_178_FAMILY(sc)) 773 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 774 else 775 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 776 777 /* 778 * Fetch IPG values. 779 */ 780 if (sc->sc_flags & AXE_FLAG_772A) { 781 /* Set IPG values. */ 782 sc->sc_ipgs[0] = 0x15; 783 sc->sc_ipgs[1] = 0x16; 784 sc->sc_ipgs[2] = 0x1A; 785 } else 786 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs); 787} 788 789/* 790 * Probe for a AX88172 chip. 791 */ 792static int 793axe_probe(device_t dev) 794{ 795 struct usb_attach_arg *uaa = device_get_ivars(dev); 796 797 if (uaa->usb_mode != USB_MODE_HOST) 798 return (ENXIO); 799 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX) 800 return (ENXIO); 801 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX) 802 return (ENXIO); 803 804 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa)); 805} 806 807/* 808 * Attach the interface. Allocate softc structures, do ifmedia 809 * setup and ethernet/BPF attach. 810 */ 811static int 812axe_attach(device_t dev) 813{ 814 struct usb_attach_arg *uaa = device_get_ivars(dev); 815 struct axe_softc *sc = device_get_softc(dev); 816 struct usb_ether *ue = &sc->sc_ue; 817 uint8_t iface_index; 818 int error; 819 820 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 821 822 device_set_usb_desc(dev); 823 824 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 825 826 iface_index = AXE_IFACE_IDX; 827 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 828 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx); 829 if (error) { 830 device_printf(dev, "allocating USB transfers failed\n"); 831 goto detach; 832 } 833 834 ue->ue_sc = sc; 835 ue->ue_dev = dev; 836 ue->ue_udev = uaa->device; 837 ue->ue_mtx = &sc->sc_mtx; 838 ue->ue_methods = &axe_ue_methods; 839 840 error = uether_ifattach(ue); 841 if (error) { 842 device_printf(dev, "could not attach interface\n"); 843 goto detach; 844 } 845 return (0); /* success */ 846 847detach: 848 axe_detach(dev); 849 return (ENXIO); /* failure */ 850} 851 852static int 853axe_detach(device_t dev) 854{ 855 struct axe_softc *sc = device_get_softc(dev); 856 struct usb_ether *ue = &sc->sc_ue; 857 858 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER); 859 uether_ifdetach(ue); 860 mtx_destroy(&sc->sc_mtx); 861 862 return (0); 863} 864 865#if (AXE_BULK_BUF_SIZE >= 0x10000) 866#error "Please update axe_bulk_read_callback()!" 867#endif 868 869static void 870axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 871{ 872 struct axe_softc *sc = usbd_xfer_softc(xfer); 873 struct usb_ether *ue = &sc->sc_ue; 874 struct ifnet *ifp = uether_getifp(ue); 875 struct axe_sframe_hdr hdr; 876 struct usb_page_cache *pc; 877 int err, pos, len; 878 int actlen; 879 880 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 881 882 switch (USB_GET_STATE(xfer)) { 883 case USB_ST_TRANSFERRED: 884 pos = 0; 885 len = 0; 886 err = 0; 887 888 pc = usbd_xfer_get_frame(xfer, 0); 889 if (AXE_IS_178_FAMILY(sc)) { 890 while (pos < actlen) { 891 if ((pos + sizeof(hdr)) > actlen) { 892 /* too little data */ 893 err = EINVAL; 894 break; 895 } 896 usbd_copy_out(pc, pos, &hdr, sizeof(hdr)); 897 898 if ((hdr.len ^ hdr.ilen) != 0xFFFF) { 899 /* we lost sync */ 900 err = EINVAL; 901 break; 902 } 903 pos += sizeof(hdr); 904 905 len = le16toh(hdr.len); 906 if ((pos + len) > actlen) { 907 /* invalid length */ 908 err = EINVAL; 909 break; 910 } 911 uether_rxbuf(ue, pc, pos, len); 912 913 pos += len + (len % 2); 914 } 915 } else 916 uether_rxbuf(ue, pc, 0, actlen); 917 918 if (err != 0) 919 ifp->if_ierrors++; 920 921 /* FALLTHROUGH */ 922 case USB_ST_SETUP: 923tr_setup: 924 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 925 usbd_transfer_submit(xfer); 926 uether_rxflush(ue); 927 return; 928 929 default: /* Error */ 930 DPRINTF("bulk read error, %s\n", usbd_errstr(error)); 931 932 if (error != USB_ERR_CANCELLED) { 933 /* try to clear stall first */ 934 usbd_xfer_set_stall(xfer); 935 goto tr_setup; 936 } 937 return; 938 939 } 940} 941 942#if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4))) 943#error "Please update axe_bulk_write_callback()!" 944#endif 945 946static void 947axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 948{ 949 struct axe_softc *sc = usbd_xfer_softc(xfer); 950 struct axe_sframe_hdr hdr; 951 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 952 struct usb_page_cache *pc; 953 struct mbuf *m; 954 int nframes, pos; 955 956 switch (USB_GET_STATE(xfer)) { 957 case USB_ST_TRANSFERRED: 958 DPRINTFN(11, "transfer complete\n"); 959 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 960 /* FALLTHROUGH */ 961 case USB_ST_SETUP: 962tr_setup: 963 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 || 964 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { 965 /* 966 * Don't send anything if there is no link or 967 * controller is busy. 968 */ 969 return; 970 } 971 972 for (nframes = 0; nframes < 16 && 973 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) { 974 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 975 if (m == NULL) 976 break; 977 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, 978 nframes); 979 pos = 0; 980 pc = usbd_xfer_get_frame(xfer, nframes); 981 if (AXE_IS_178_FAMILY(sc)) { 982 hdr.len = htole16(m->m_pkthdr.len); 983 hdr.ilen = ~hdr.len; 984 usbd_copy_in(pc, pos, &hdr, sizeof(hdr)); 985 pos += sizeof(hdr); 986 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 987 pos += m->m_pkthdr.len; 988 if ((pos % 512) == 0) { 989 hdr.len = 0; 990 hdr.ilen = 0xffff; 991 usbd_copy_in(pc, pos, &hdr, 992 sizeof(hdr)); 993 pos += sizeof(hdr); 994 } 995 } else { 996 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 997 pos += m->m_pkthdr.len; 998 } 999 1000 /* 1001 * XXX 1002 * Update TX packet counter here. This is not 1003 * correct way but it seems that there is no way 1004 * to know how many packets are sent at the end 1005 * of transfer because controller combines 1006 * multiple writes into single one if there is 1007 * room in TX buffer of controller. 1008 */ 1009 ifp->if_opackets++; 1010 1011 /* 1012 * if there's a BPF listener, bounce a copy 1013 * of this frame to him: 1014 */ 1015 BPF_MTAP(ifp, m); 1016 1017 m_freem(m); 1018 1019 /* Set frame length. */ 1020 usbd_xfer_set_frame_len(xfer, nframes, pos); 1021 } 1022 if (nframes != 0) { 1023 usbd_xfer_set_frames(xfer, nframes); 1024 usbd_transfer_submit(xfer); 1025 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1026 } 1027 return; 1028 /* NOTREACHED */ 1029 default: /* Error */ 1030 DPRINTFN(11, "transfer error, %s\n", 1031 usbd_errstr(error)); 1032 1033 ifp->if_oerrors++; 1034 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1035 1036 if (error != USB_ERR_CANCELLED) { 1037 /* try to clear stall first */ 1038 usbd_xfer_set_stall(xfer); 1039 goto tr_setup; 1040 } 1041 return; 1042 1043 } 1044} 1045 1046static void 1047axe_tick(struct usb_ether *ue) 1048{ 1049 struct axe_softc *sc = uether_getsc(ue); 1050 struct mii_data *mii = GET_MII(sc); 1051 1052 AXE_LOCK_ASSERT(sc, MA_OWNED); 1053 1054 mii_tick(mii); 1055 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) { 1056 axe_miibus_statchg(ue->ue_dev); 1057 if ((sc->sc_flags & AXE_FLAG_LINK) != 0) 1058 axe_start(ue); 1059 } 1060} 1061 1062static void 1063axe_start(struct usb_ether *ue) 1064{ 1065 struct axe_softc *sc = uether_getsc(ue); 1066 1067 /* 1068 * start the USB transfers, if not already started: 1069 */ 1070 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]); 1071 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]); 1072} 1073 1074static void 1075axe_init(struct usb_ether *ue) 1076{ 1077 struct axe_softc *sc = uether_getsc(ue); 1078 struct ifnet *ifp = uether_getifp(ue); 1079 uint16_t rxmode; 1080 1081 AXE_LOCK_ASSERT(sc, MA_OWNED); 1082 1083 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1084 return; 1085 1086 /* Cancel pending I/O */ 1087 axe_stop(ue); 1088 1089 axe_reset(sc); 1090 1091 /* Set MAC address. */ 1092 if (AXE_IS_178_FAMILY(sc)) 1093 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1094 else 1095 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1096 1097 /* Set transmitter IPG values */ 1098 if (AXE_IS_178_FAMILY(sc)) 1099 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2], 1100 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL); 1101 else { 1102 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL); 1103 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL); 1104 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL); 1105 } 1106 1107 /* Enable receiver, set RX mode */ 1108 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1109 if (AXE_IS_178_FAMILY(sc)) { 1110#if 0 1111 rxmode |= AXE_178_RXCMD_MFB_2048; /* chip default */ 1112#else 1113 /* 1114 * Default Rx buffer size is too small to get 1115 * maximum performance. 1116 */ 1117 rxmode |= AXE_178_RXCMD_MFB_16384; 1118#endif 1119 } else { 1120 rxmode |= AXE_172_RXCMD_UNICAST; 1121 } 1122 1123 /* If we want promiscuous mode, set the allframes bit. */ 1124 if (ifp->if_flags & IFF_PROMISC) 1125 rxmode |= AXE_RXCMD_PROMISC; 1126 1127 if (ifp->if_flags & IFF_BROADCAST) 1128 rxmode |= AXE_RXCMD_BROADCAST; 1129 1130 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1131 1132 /* Load the multicast filter. */ 1133 axe_setmulti(ue); 1134 1135 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]); 1136 1137 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1138 /* Switch to selected media. */ 1139 axe_ifmedia_upd(ifp); 1140 axe_start(ue); 1141} 1142 1143static void 1144axe_setpromisc(struct usb_ether *ue) 1145{ 1146 struct axe_softc *sc = uether_getsc(ue); 1147 struct ifnet *ifp = uether_getifp(ue); 1148 uint16_t rxmode; 1149 1150 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 1151 1152 rxmode = le16toh(rxmode); 1153 1154 if (ifp->if_flags & IFF_PROMISC) { 1155 rxmode |= AXE_RXCMD_PROMISC; 1156 } else { 1157 rxmode &= ~AXE_RXCMD_PROMISC; 1158 } 1159 1160 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1161 1162 axe_setmulti(ue); 1163} 1164 1165static void 1166axe_stop(struct usb_ether *ue) 1167{ 1168 struct axe_softc *sc = uether_getsc(ue); 1169 struct ifnet *ifp = uether_getifp(ue); 1170 1171 AXE_LOCK_ASSERT(sc, MA_OWNED); 1172 1173 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1174 sc->sc_flags &= ~AXE_FLAG_LINK; 1175 1176 /* 1177 * stop all the transfers, if not already stopped: 1178 */ 1179 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]); 1180 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]); 1181} 1182