uhci.h revision 186730
1/* $FreeBSD: head/sys/dev/usb2/controller/uhci2.h 186730 2009-01-04 00:12:01Z alfred $ */ 2/*- 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Lennart Augustsson (lennart@augustsson.net) at 8 * Carlstedt Research & Technology. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#ifndef _UHCI_H_ 40#define _UHCI_H_ 41 42/* PCI config registers */ 43#define PCI_USBREV 0x60 /* USB protocol revision */ 44#define PCI_USB_REV_MASK 0xff 45#define PCI_USB_REV_PRE_1_0 0x00 46#define PCI_USB_REV_1_0 0x10 47#define PCI_USB_REV_1_1 0x11 48#define PCI_LEGSUP 0xc0 /* Legacy Support register */ 49#define PCI_LEGSUP_USBPIRQDEN 0x2000 /* USB PIRQ D Enable */ 50#define PCI_CBIO 0x20 /* configuration base IO */ 51#define PCI_INTERFACE_UHCI 0x00 52 53/* UHCI registers */ 54#define UHCI_CMD 0x00 55#define UHCI_CMD_RS 0x0001 56#define UHCI_CMD_HCRESET 0x0002 57#define UHCI_CMD_GRESET 0x0004 58#define UHCI_CMD_EGSM 0x0008 59#define UHCI_CMD_FGR 0x0010 60#define UHCI_CMD_SWDBG 0x0020 61#define UHCI_CMD_CF 0x0040 62#define UHCI_CMD_MAXP 0x0080 63#define UHCI_STS 0x02 64#define UHCI_STS_USBINT 0x0001 65#define UHCI_STS_USBEI 0x0002 66#define UHCI_STS_RD 0x0004 67#define UHCI_STS_HSE 0x0008 68#define UHCI_STS_HCPE 0x0010 69#define UHCI_STS_HCH 0x0020 70#define UHCI_STS_ALLINTRS 0x003f 71#define UHCI_INTR 0x04 72#define UHCI_INTR_TOCRCIE 0x0001 73#define UHCI_INTR_RIE 0x0002 74#define UHCI_INTR_IOCE 0x0004 75#define UHCI_INTR_SPIE 0x0008 76#define UHCI_FRNUM 0x06 77#define UHCI_FRNUM_MASK 0x03ff 78#define UHCI_FLBASEADDR 0x08 79#define UHCI_SOF 0x0c 80#define UHCI_SOF_MASK 0x7f 81#define UHCI_PORTSC1 0x010 82#define UHCI_PORTSC2 0x012 83#define UHCI_PORTSC_CCS 0x0001 84#define UHCI_PORTSC_CSC 0x0002 85#define UHCI_PORTSC_PE 0x0004 86#define UHCI_PORTSC_POEDC 0x0008 87#define UHCI_PORTSC_LS 0x0030 88#define UHCI_PORTSC_LS_SHIFT 4 89#define UHCI_PORTSC_RD 0x0040 90#define UHCI_PORTSC_LSDA 0x0100 91#define UHCI_PORTSC_PR 0x0200 92#define UHCI_PORTSC_OCI 0x0400 93#define UHCI_PORTSC_OCIC 0x0800 94#define UHCI_PORTSC_SUSP 0x1000 95 96#define URWMASK(x) ((x) & (UHCI_PORTSC_SUSP | \ 97 UHCI_PORTSC_PR | UHCI_PORTSC_RD | \ 98 UHCI_PORTSC_PE)) 99 100#define UHCI_FRAMELIST_COUNT 1024 /* units */ 101#define UHCI_FRAMELIST_ALIGN 4096 /* bytes */ 102 103/* Structures alignment (bytes) */ 104#define UHCI_TD_ALIGN 16 105#define UHCI_QH_ALIGN 16 106 107#if ((USB_PAGE_SIZE < UHCI_TD_ALIGN) || (UHCI_TD_ALIGN == 0) || \ 108 (USB_PAGE_SIZE < UHCI_QH_ALIGN) || (UHCI_QH_ALIGN == 0)) 109#error "Invalid USB page size!" 110#endif 111 112typedef uint32_t uhci_physaddr_t; 113 114#define UHCI_PTR_T 0x00000001 115#define UHCI_PTR_TD 0x00000000 116#define UHCI_PTR_QH 0x00000002 117#define UHCI_PTR_VF 0x00000004 118 119#define UHCI_QH_REMOVE_DELAY 5 /* us - QH remove delay */ 120 121/* 122 * The Queue Heads (QH) and Transfer Descriptors (TD) are accessed by 123 * both the CPU and the USB-controller which run concurrently. Great 124 * care must be taken. When the data-structures are linked into the 125 * USB controller's frame list, the USB-controller "owns" the 126 * td_status and qh_elink fields, which will not be written by the 127 * CPU. 128 * 129 */ 130 131struct uhci_td { 132/* 133 * Data used by the UHCI controller. 134 * volatile is used in order to mantain struct members ordering. 135 */ 136 volatile uint32_t td_next; 137 volatile uint32_t td_status; 138#define UHCI_TD_GET_ACTLEN(s) (((s) + 1) & 0x3ff) 139#define UHCI_TD_ZERO_ACTLEN(t) ((t) | 0x3ff) 140#define UHCI_TD_BITSTUFF 0x00020000 141#define UHCI_TD_CRCTO 0x00040000 142#define UHCI_TD_NAK 0x00080000 143#define UHCI_TD_BABBLE 0x00100000 144#define UHCI_TD_DBUFFER 0x00200000 145#define UHCI_TD_STALLED 0x00400000 146#define UHCI_TD_ACTIVE 0x00800000 147#define UHCI_TD_IOC 0x01000000 148#define UHCI_TD_IOS 0x02000000 149#define UHCI_TD_LS 0x04000000 150#define UHCI_TD_GET_ERRCNT(s) (((s) >> 27) & 3) 151#define UHCI_TD_SET_ERRCNT(n) ((n) << 27) 152#define UHCI_TD_SPD 0x20000000 153 volatile uint32_t td_token; 154#define UHCI_TD_PID 0x000000ff 155#define UHCI_TD_PID_IN 0x00000069 156#define UHCI_TD_PID_OUT 0x000000e1 157#define UHCI_TD_PID_SETUP 0x0000002d 158#define UHCI_TD_GET_PID(s) ((s) & 0xff) 159#define UHCI_TD_SET_DEVADDR(a) ((a) << 8) 160#define UHCI_TD_GET_DEVADDR(s) (((s) >> 8) & 0x7f) 161#define UHCI_TD_SET_ENDPT(e) (((e) & 0xf) << 15) 162#define UHCI_TD_GET_ENDPT(s) (((s) >> 15) & 0xf) 163#define UHCI_TD_SET_DT(t) ((t) << 19) 164#define UHCI_TD_GET_DT(s) (((s) >> 19) & 1) 165#define UHCI_TD_SET_MAXLEN(l) (((l)-1) << 21) 166#define UHCI_TD_GET_MAXLEN(s) ((((s) >> 21) + 1) & 0x7ff) 167#define UHCI_TD_MAXLEN_MASK 0xffe00000 168 volatile uint32_t td_buffer; 169/* 170 * Extra information needed: 171 */ 172 struct uhci_td *next; 173 struct uhci_td *prev; 174 struct uhci_td *obj_next; 175 struct usb2_page_cache *page_cache; 176 struct usb2_page_cache *fix_pc; 177 uint32_t td_self; 178 uint16_t len; 179} __aligned(UHCI_TD_ALIGN); 180 181typedef struct uhci_td uhci_td_t; 182 183#define UHCI_TD_ERROR (UHCI_TD_BITSTUFF | UHCI_TD_CRCTO | \ 184 UHCI_TD_BABBLE | UHCI_TD_DBUFFER | UHCI_TD_STALLED) 185 186#define UHCI_TD_SETUP(len, endp, dev) (UHCI_TD_SET_MAXLEN(len) | \ 187 UHCI_TD_SET_ENDPT(endp) | \ 188 UHCI_TD_SET_DEVADDR(dev) | \ 189 UHCI_TD_PID_SETUP) 190 191#define UHCI_TD_OUT(len, endp, dev, dt) (UHCI_TD_SET_MAXLEN(len) | \ 192 UHCI_TD_SET_ENDPT(endp) | \ 193 UHCI_TD_SET_DEVADDR(dev) | \ 194 UHCI_TD_PID_OUT | UHCI_TD_SET_DT(dt)) 195 196#define UHCI_TD_IN(len, endp, dev, dt) (UHCI_TD_SET_MAXLEN(len) | \ 197 UHCI_TD_SET_ENDPT(endp) | \ 198 UHCI_TD_SET_DEVADDR(dev) | \ 199 UHCI_TD_PID_IN | UHCI_TD_SET_DT(dt)) 200 201struct uhci_qh { 202/* 203 * Data used by the UHCI controller. 204 */ 205 volatile uint32_t qh_h_next; 206 volatile uint32_t qh_e_next; 207/* 208 * Extra information needed: 209 */ 210 struct uhci_qh *h_next; 211 struct uhci_qh *h_prev; 212 struct uhci_qh *obj_next; 213 struct uhci_td *e_next; 214 struct usb2_page_cache *page_cache; 215 uint32_t qh_self; 216 uint16_t intr_pos; 217} __aligned(UHCI_QH_ALIGN); 218 219typedef struct uhci_qh uhci_qh_t; 220 221/* Maximum number of isochronous TD's and QH's interrupt */ 222#define UHCI_VFRAMELIST_COUNT 128 223#define UHCI_IFRAMELIST_COUNT (2 * UHCI_VFRAMELIST_COUNT) 224 225#if (((UHCI_VFRAMELIST_COUNT & (UHCI_VFRAMELIST_COUNT-1)) != 0) || \ 226 (UHCI_VFRAMELIST_COUNT > UHCI_FRAMELIST_COUNT)) 227#error "UHCI_VFRAMELIST_COUNT is not power of two" 228#error "or UHCI_VFRAMELIST_COUNT > UHCI_FRAMELIST_COUNT" 229#endif 230 231#if (UHCI_VFRAMELIST_COUNT < USB_MAX_FS_ISOC_FRAMES_PER_XFER) 232#error "maximum number of full-speed isochronous frames is higher than supported!" 233#endif 234 235struct uhci_config_desc { 236 struct usb2_config_descriptor confd; 237 struct usb2_interface_descriptor ifcd; 238 struct usb2_endpoint_descriptor endpd; 239} __packed; 240 241union uhci_hub_desc { 242 struct usb2_status stat; 243 struct usb2_port_status ps; 244 struct usb2_device_descriptor devd; 245 uint8_t temp[128]; 246}; 247 248struct uhci_hw_softc { 249 struct usb2_page_cache pframes_pc; 250 struct usb2_page_cache isoc_start_pc[UHCI_VFRAMELIST_COUNT]; 251 struct usb2_page_cache intr_start_pc[UHCI_IFRAMELIST_COUNT]; 252 struct usb2_page_cache ls_ctl_start_pc; 253 struct usb2_page_cache fs_ctl_start_pc; 254 struct usb2_page_cache bulk_start_pc; 255 struct usb2_page_cache last_qh_pc; 256 struct usb2_page_cache last_td_pc; 257 258 struct usb2_page pframes_pg; 259 struct usb2_page isoc_start_pg[UHCI_VFRAMELIST_COUNT]; 260 struct usb2_page intr_start_pg[UHCI_IFRAMELIST_COUNT]; 261 struct usb2_page ls_ctl_start_pg; 262 struct usb2_page fs_ctl_start_pg; 263 struct usb2_page bulk_start_pg; 264 struct usb2_page last_qh_pg; 265 struct usb2_page last_td_pg; 266}; 267 268typedef struct uhci_softc { 269 struct uhci_hw_softc sc_hw; 270 struct usb2_bus sc_bus; /* base device */ 271 struct usb2_config_td sc_config_td; 272 union uhci_hub_desc sc_hub_desc; 273 struct usb2_sw_transfer sc_root_ctrl; 274 struct usb2_sw_transfer sc_root_intr; 275 276 struct uhci_td *sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]; /* pointer to last TD 277 * for isochronous */ 278 struct uhci_qh *sc_intr_p_last[UHCI_IFRAMELIST_COUNT]; /* pointer to last QH 279 * for interrupt */ 280 struct uhci_qh *sc_ls_ctl_p_last; /* pointer to last QH for low 281 * speed control */ 282 struct uhci_qh *sc_fs_ctl_p_last; /* pointer to last QH for full 283 * speed control */ 284 struct uhci_qh *sc_bulk_p_last; /* pointer to last QH for bulk */ 285 struct uhci_qh *sc_reclaim_qh_p; 286 struct uhci_qh *sc_last_qh_p; 287 struct uhci_td *sc_last_td_p; 288 struct resource *sc_io_res; 289 struct resource *sc_irq_res; 290 void *sc_intr_hdl; 291 device_t sc_dev; 292 bus_size_t sc_io_size; 293 bus_space_tag_t sc_io_tag; 294 bus_space_handle_t sc_io_hdl; 295 296 uint32_t sc_loops; /* number of QHs that wants looping */ 297 298 uint16_t sc_intr_stat[UHCI_IFRAMELIST_COUNT]; 299 uint16_t sc_saved_frnum; 300 301 uint8_t sc_addr; /* device address */ 302 uint8_t sc_conf; /* device configuration */ 303 uint8_t sc_isreset; /* bits set if a root hub is reset */ 304 uint8_t sc_isresumed; /* bits set if a port was resumed */ 305 uint8_t sc_saved_sof; 306 uint8_t sc_hub_idata[1]; 307 308 char sc_vendor[16]; /* vendor string for root hub */ 309} uhci_softc_t; 310 311usb2_bus_mem_cb_t uhci_iterate_hw_softc; 312 313usb2_error_t uhci_init(uhci_softc_t *sc); 314void uhci_suspend(uhci_softc_t *sc); 315void uhci_resume(uhci_softc_t *sc); 316void uhci_reset(uhci_softc_t *sc); 317void uhci_interrupt(uhci_softc_t *sc); 318 319#endif /* _UHCI_H_ */ 320