ohci.c revision 217265
1/*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/usb/controller/ohci.c 217265 2011-01-11 13:59:06Z jhb $"); 30 31/* 32 * USB Open Host Controller driver. 33 * 34 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 35 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 36 */ 37 38#include <sys/stdint.h> 39#include <sys/stddef.h> 40#include <sys/param.h> 41#include <sys/queue.h> 42#include <sys/types.h> 43#include <sys/systm.h> 44#include <sys/kernel.h> 45#include <sys/bus.h> 46#include <sys/module.h> 47#include <sys/lock.h> 48#include <sys/mutex.h> 49#include <sys/condvar.h> 50#include <sys/sysctl.h> 51#include <sys/sx.h> 52#include <sys/unistd.h> 53#include <sys/callout.h> 54#include <sys/malloc.h> 55#include <sys/priv.h> 56 57#include <dev/usb/usb.h> 58#include <dev/usb/usbdi.h> 59 60#define USB_DEBUG_VAR ohcidebug 61 62#include <dev/usb/usb_core.h> 63#include <dev/usb/usb_debug.h> 64#include <dev/usb/usb_busdma.h> 65#include <dev/usb/usb_process.h> 66#include <dev/usb/usb_transfer.h> 67#include <dev/usb/usb_device.h> 68#include <dev/usb/usb_hub.h> 69#include <dev/usb/usb_util.h> 70 71#include <dev/usb/usb_controller.h> 72#include <dev/usb/usb_bus.h> 73#include <dev/usb/controller/ohci.h> 74#include <dev/usb/controller/ohcireg.h> 75 76#define OHCI_BUS2SC(bus) \ 77 ((ohci_softc_t *)(((uint8_t *)(bus)) - \ 78 ((uint8_t *)&(((ohci_softc_t *)0)->sc_bus)))) 79 80#ifdef USB_DEBUG 81static int ohcidebug = 0; 82 83SYSCTL_NODE(_hw_usb, OID_AUTO, ohci, CTLFLAG_RW, 0, "USB ohci"); 84SYSCTL_INT(_hw_usb_ohci, OID_AUTO, debug, CTLFLAG_RW, 85 &ohcidebug, 0, "ohci debug level"); 86 87TUNABLE_INT("hw.usb.ohci.debug", &ohcidebug); 88 89static void ohci_dumpregs(ohci_softc_t *); 90static void ohci_dump_tds(ohci_td_t *); 91static uint8_t ohci_dump_td(ohci_td_t *); 92static void ohci_dump_ed(ohci_ed_t *); 93static uint8_t ohci_dump_itd(ohci_itd_t *); 94static void ohci_dump_itds(ohci_itd_t *); 95 96#endif 97 98#define OBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 99 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 100#define OWRITE1(sc, r, x) \ 101 do { OBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 102#define OWRITE2(sc, r, x) \ 103 do { OBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 104#define OWRITE4(sc, r, x) \ 105 do { OBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 106#define OREAD1(sc, r) (OBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 107#define OREAD2(sc, r) (OBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 108#define OREAD4(sc, r) (OBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 109 110#define OHCI_INTR_ENDPT 1 111 112extern struct usb_bus_methods ohci_bus_methods; 113extern struct usb_pipe_methods ohci_device_bulk_methods; 114extern struct usb_pipe_methods ohci_device_ctrl_methods; 115extern struct usb_pipe_methods ohci_device_intr_methods; 116extern struct usb_pipe_methods ohci_device_isoc_methods; 117 118static void ohci_do_poll(struct usb_bus *bus); 119static void ohci_device_done(struct usb_xfer *xfer, usb_error_t error); 120static void ohci_timeout(void *arg); 121static uint8_t ohci_check_transfer(struct usb_xfer *xfer); 122static void ohci_root_intr(ohci_softc_t *sc); 123 124struct ohci_std_temp { 125 struct usb_page_cache *pc; 126 ohci_td_t *td; 127 ohci_td_t *td_next; 128 uint32_t average; 129 uint32_t td_flags; 130 uint32_t len; 131 uint16_t max_frame_size; 132 uint8_t shortpkt; 133 uint8_t setup_alt_next; 134 uint8_t last_frame; 135}; 136 137static struct ohci_hcca * 138ohci_get_hcca(ohci_softc_t *sc) 139{ 140 usb_pc_cpu_invalidate(&sc->sc_hw.hcca_pc); 141 return (sc->sc_hcca_p); 142} 143 144void 145ohci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 146{ 147 struct ohci_softc *sc = OHCI_BUS2SC(bus); 148 uint32_t i; 149 150 cb(bus, &sc->sc_hw.hcca_pc, &sc->sc_hw.hcca_pg, 151 sizeof(ohci_hcca_t), OHCI_HCCA_ALIGN); 152 153 cb(bus, &sc->sc_hw.ctrl_start_pc, &sc->sc_hw.ctrl_start_pg, 154 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 155 156 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 157 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 158 159 cb(bus, &sc->sc_hw.isoc_start_pc, &sc->sc_hw.isoc_start_pg, 160 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 161 162 for (i = 0; i != OHCI_NO_EDS; i++) { 163 cb(bus, sc->sc_hw.intr_start_pc + i, sc->sc_hw.intr_start_pg + i, 164 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 165 } 166} 167 168static usb_error_t 169ohci_controller_init(ohci_softc_t *sc) 170{ 171 struct usb_page_search buf_res; 172 uint32_t i; 173 uint32_t ctl; 174 uint32_t ival; 175 uint32_t hcr; 176 uint32_t fm; 177 uint32_t per; 178 uint32_t desca; 179 180 /* Determine in what context we are running. */ 181 ctl = OREAD4(sc, OHCI_CONTROL); 182 if (ctl & OHCI_IR) { 183 /* SMM active, request change */ 184 DPRINTF("SMM active, request owner change\n"); 185 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_OCR); 186 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 187 usb_pause_mtx(NULL, hz / 1000); 188 ctl = OREAD4(sc, OHCI_CONTROL); 189 } 190 if (ctl & OHCI_IR) { 191 device_printf(sc->sc_bus.bdev, 192 "SMM does not respond, resetting\n"); 193 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 194 goto reset; 195 } 196 } else { 197 DPRINTF("cold started\n"); 198reset: 199 /* controller was cold started */ 200 usb_pause_mtx(NULL, 201 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 202 } 203 204 /* 205 * This reset should not be necessary according to the OHCI spec, but 206 * without it some controllers do not start. 207 */ 208 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 209 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 210 211 usb_pause_mtx(NULL, 212 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 213 214 /* we now own the host controller and the bus has been reset */ 215 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL)); 216 217 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 218 /* nominal time for a reset is 10 us */ 219 for (i = 0; i < 10; i++) { 220 DELAY(10); 221 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 222 if (!hcr) { 223 break; 224 } 225 } 226 if (hcr) { 227 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 228 return (USB_ERR_IOERROR); 229 } 230#ifdef USB_DEBUG 231 if (ohcidebug > 15) { 232 ohci_dumpregs(sc); 233 } 234#endif 235 236 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 237 238 /* set up HC registers */ 239 usbd_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 240 OWRITE4(sc, OHCI_HCCA, buf_res.physaddr); 241 242 usbd_get_page(&sc->sc_hw.ctrl_start_pc, 0, &buf_res); 243 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, buf_res.physaddr); 244 245 usbd_get_page(&sc->sc_hw.bulk_start_pc, 0, &buf_res); 246 OWRITE4(sc, OHCI_BULK_HEAD_ED, buf_res.physaddr); 247 248 /* disable all interrupts and then switch on all desired interrupts */ 249 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 250 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 251 /* switch on desired functional features */ 252 ctl = OREAD4(sc, OHCI_CONTROL); 253 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 254 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 255 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL; 256 /* And finally start it! */ 257 OWRITE4(sc, OHCI_CONTROL, ctl); 258 259 /* 260 * The controller is now OPERATIONAL. Set a some final 261 * registers that should be set earlier, but that the 262 * controller ignores when in the SUSPEND state. 263 */ 264 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 265 fm |= OHCI_FSMPS(ival) | ival; 266 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 267 per = OHCI_PERIODIC(ival); /* 90% periodic */ 268 OWRITE4(sc, OHCI_PERIODIC_START, per); 269 270 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 271 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 272 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 273 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 274 usb_pause_mtx(NULL, 275 USB_MS_TO_TICKS(OHCI_ENABLE_POWER_DELAY)); 276 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 277 278 /* 279 * The AMD756 requires a delay before re-reading the register, 280 * otherwise it will occasionally report 0 ports. 281 */ 282 sc->sc_noport = 0; 283 for (i = 0; (i < 10) && (sc->sc_noport == 0); i++) { 284 usb_pause_mtx(NULL, 285 USB_MS_TO_TICKS(OHCI_READ_DESC_DELAY)); 286 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 287 } 288 289#ifdef USB_DEBUG 290 if (ohcidebug > 5) { 291 ohci_dumpregs(sc); 292 } 293#endif 294 return (USB_ERR_NORMAL_COMPLETION); 295} 296 297static struct ohci_ed * 298ohci_init_ed(struct usb_page_cache *pc) 299{ 300 struct usb_page_search buf_res; 301 struct ohci_ed *ed; 302 303 usbd_get_page(pc, 0, &buf_res); 304 305 ed = buf_res.buffer; 306 307 ed->ed_self = htole32(buf_res.physaddr); 308 ed->ed_flags = htole32(OHCI_ED_SKIP); 309 ed->page_cache = pc; 310 311 return (ed); 312} 313 314usb_error_t 315ohci_init(ohci_softc_t *sc) 316{ 317 struct usb_page_search buf_res; 318 uint16_t i; 319 uint16_t bit; 320 uint16_t x; 321 uint16_t y; 322 323 DPRINTF("start\n"); 324 325 sc->sc_eintrs = OHCI_NORMAL_INTRS; 326 327 /* 328 * Setup all ED's 329 */ 330 331 sc->sc_ctrl_p_last = 332 ohci_init_ed(&sc->sc_hw.ctrl_start_pc); 333 334 sc->sc_bulk_p_last = 335 ohci_init_ed(&sc->sc_hw.bulk_start_pc); 336 337 sc->sc_isoc_p_last = 338 ohci_init_ed(&sc->sc_hw.isoc_start_pc); 339 340 for (i = 0; i != OHCI_NO_EDS; i++) { 341 sc->sc_intr_p_last[i] = 342 ohci_init_ed(sc->sc_hw.intr_start_pc + i); 343 } 344 345 /* 346 * the QHs are arranged to give poll intervals that are 347 * powers of 2 times 1ms 348 */ 349 bit = OHCI_NO_EDS / 2; 350 while (bit) { 351 x = bit; 352 while (x & bit) { 353 ohci_ed_t *ed_x; 354 ohci_ed_t *ed_y; 355 356 y = (x ^ bit) | (bit / 2); 357 358 /* 359 * the next QH has half the poll interval 360 */ 361 ed_x = sc->sc_intr_p_last[x]; 362 ed_y = sc->sc_intr_p_last[y]; 363 364 ed_x->next = NULL; 365 ed_x->ed_next = ed_y->ed_self; 366 367 x++; 368 } 369 bit >>= 1; 370 } 371 372 if (1) { 373 374 ohci_ed_t *ed_int; 375 ohci_ed_t *ed_isc; 376 377 ed_int = sc->sc_intr_p_last[0]; 378 ed_isc = sc->sc_isoc_p_last; 379 380 /* the last (1ms) QH */ 381 ed_int->next = ed_isc; 382 ed_int->ed_next = ed_isc->ed_self; 383 } 384 usbd_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 385 386 sc->sc_hcca_p = buf_res.buffer; 387 388 /* 389 * Fill HCCA interrupt table. The bit reversal is to get 390 * the tree set up properly to spread the interrupts. 391 */ 392 for (i = 0; i != OHCI_NO_INTRS; i++) { 393 sc->sc_hcca_p->hcca_interrupt_table[i] = 394 sc->sc_intr_p_last[i | (OHCI_NO_EDS / 2)]->ed_self; 395 } 396 /* flush all cache into memory */ 397 398 usb_bus_mem_flush_all(&sc->sc_bus, &ohci_iterate_hw_softc); 399 400 /* set up the bus struct */ 401 sc->sc_bus.methods = &ohci_bus_methods; 402 403 usb_callout_init_mtx(&sc->sc_tmo_rhsc, &sc->sc_bus.bus_mtx, 0); 404 405#ifdef USB_DEBUG 406 if (ohcidebug > 15) { 407 for (i = 0; i != OHCI_NO_EDS; i++) { 408 printf("ed#%d ", i); 409 ohci_dump_ed(sc->sc_intr_p_last[i]); 410 } 411 printf("iso "); 412 ohci_dump_ed(sc->sc_isoc_p_last); 413 } 414#endif 415 416 sc->sc_bus.usbrev = USB_REV_1_0; 417 418 if (ohci_controller_init(sc)) { 419 return (USB_ERR_INVAL); 420 } else { 421 /* catch any lost interrupts */ 422 ohci_do_poll(&sc->sc_bus); 423 return (USB_ERR_NORMAL_COMPLETION); 424 } 425} 426 427/* 428 * shut down the controller when the system is going down 429 */ 430void 431ohci_detach(struct ohci_softc *sc) 432{ 433 USB_BUS_LOCK(&sc->sc_bus); 434 435 usb_callout_stop(&sc->sc_tmo_rhsc); 436 437 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 438 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 439 440 USB_BUS_UNLOCK(&sc->sc_bus); 441 442 /* XXX let stray task complete */ 443 usb_pause_mtx(NULL, hz / 20); 444 445 usb_callout_drain(&sc->sc_tmo_rhsc); 446} 447 448/* NOTE: suspend/resume is called from 449 * interrupt context and cannot sleep! 450 */ 451void 452ohci_suspend(ohci_softc_t *sc) 453{ 454 uint32_t ctl; 455 456 USB_BUS_LOCK(&sc->sc_bus); 457 458#ifdef USB_DEBUG 459 DPRINTF("\n"); 460 if (ohcidebug > 2) { 461 ohci_dumpregs(sc); 462 } 463#endif 464 465 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 466 if (sc->sc_control == 0) { 467 /* 468 * Preserve register values, in case that APM BIOS 469 * does not recover them. 470 */ 471 sc->sc_control = ctl; 472 sc->sc_intre = OREAD4(sc, OHCI_INTERRUPT_ENABLE); 473 } 474 ctl |= OHCI_HCFS_SUSPEND; 475 OWRITE4(sc, OHCI_CONTROL, ctl); 476 477 usb_pause_mtx(&sc->sc_bus.bus_mtx, 478 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 479 480 USB_BUS_UNLOCK(&sc->sc_bus); 481} 482 483void 484ohci_resume(ohci_softc_t *sc) 485{ 486 uint32_t ctl; 487 488#ifdef USB_DEBUG 489 DPRINTF("\n"); 490 if (ohcidebug > 2) { 491 ohci_dumpregs(sc); 492 } 493#endif 494 /* some broken BIOSes never initialize the Controller chip */ 495 ohci_controller_init(sc); 496 497 USB_BUS_LOCK(&sc->sc_bus); 498 if (sc->sc_intre) { 499 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, 500 sc->sc_intre & (OHCI_ALL_INTRS | OHCI_MIE)); 501 } 502 if (sc->sc_control) 503 ctl = sc->sc_control; 504 else 505 ctl = OREAD4(sc, OHCI_CONTROL); 506 ctl |= OHCI_HCFS_RESUME; 507 OWRITE4(sc, OHCI_CONTROL, ctl); 508 usb_pause_mtx(&sc->sc_bus.bus_mtx, 509 USB_MS_TO_TICKS(USB_RESUME_DELAY)); 510 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 511 OWRITE4(sc, OHCI_CONTROL, ctl); 512 usb_pause_mtx(&sc->sc_bus.bus_mtx, 513 USB_MS_TO_TICKS(USB_RESUME_RECOVERY)); 514 sc->sc_control = sc->sc_intre = 0; 515 516 USB_BUS_UNLOCK(&sc->sc_bus); 517 518 /* catch any lost interrupts */ 519 ohci_do_poll(&sc->sc_bus); 520} 521 522#ifdef USB_DEBUG 523static void 524ohci_dumpregs(ohci_softc_t *sc) 525{ 526 struct ohci_hcca *hcca; 527 528 DPRINTF("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 529 OREAD4(sc, OHCI_REVISION), 530 OREAD4(sc, OHCI_CONTROL), 531 OREAD4(sc, OHCI_COMMAND_STATUS)); 532 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 533 OREAD4(sc, OHCI_INTERRUPT_STATUS), 534 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 535 OREAD4(sc, OHCI_INTERRUPT_DISABLE)); 536 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 537 OREAD4(sc, OHCI_HCCA), 538 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 539 OREAD4(sc, OHCI_CONTROL_HEAD_ED)); 540 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 541 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 542 OREAD4(sc, OHCI_BULK_HEAD_ED), 543 OREAD4(sc, OHCI_BULK_CURRENT_ED)); 544 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 545 OREAD4(sc, OHCI_DONE_HEAD), 546 OREAD4(sc, OHCI_FM_INTERVAL), 547 OREAD4(sc, OHCI_FM_REMAINING)); 548 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 549 OREAD4(sc, OHCI_FM_NUMBER), 550 OREAD4(sc, OHCI_PERIODIC_START), 551 OREAD4(sc, OHCI_LS_THRESHOLD)); 552 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x\n", 553 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 554 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 555 OREAD4(sc, OHCI_RH_STATUS)); 556 DPRINTF(" port1=0x%08x port2=0x%08x\n", 557 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 558 OREAD4(sc, OHCI_RH_PORT_STATUS(2))); 559 560 hcca = ohci_get_hcca(sc); 561 562 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x\n", 563 le32toh(hcca->hcca_frame_number), 564 le32toh(hcca->hcca_done_head)); 565} 566static void 567ohci_dump_tds(ohci_td_t *std) 568{ 569 for (; std; std = std->obj_next) { 570 if (ohci_dump_td(std)) { 571 break; 572 } 573 } 574} 575 576static uint8_t 577ohci_dump_td(ohci_td_t *std) 578{ 579 uint32_t td_flags; 580 uint8_t temp; 581 582 usb_pc_cpu_invalidate(std->page_cache); 583 584 td_flags = le32toh(std->td_flags); 585 temp = (std->td_next == 0); 586 587 printf("TD(%p) at 0x%08x: %s%s%s%s%s delay=%d ec=%d " 588 "cc=%d\ncbp=0x%08x next=0x%08x be=0x%08x\n", 589 std, le32toh(std->td_self), 590 (td_flags & OHCI_TD_R) ? "-R" : "", 591 (td_flags & OHCI_TD_OUT) ? "-OUT" : "", 592 (td_flags & OHCI_TD_IN) ? "-IN" : "", 593 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_1) ? "-TOG1" : "", 594 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_0) ? "-TOG0" : "", 595 OHCI_TD_GET_DI(td_flags), 596 OHCI_TD_GET_EC(td_flags), 597 OHCI_TD_GET_CC(td_flags), 598 le32toh(std->td_cbp), 599 le32toh(std->td_next), 600 le32toh(std->td_be)); 601 602 return (temp); 603} 604 605static uint8_t 606ohci_dump_itd(ohci_itd_t *sitd) 607{ 608 uint32_t itd_flags; 609 uint16_t i; 610 uint8_t temp; 611 612 usb_pc_cpu_invalidate(sitd->page_cache); 613 614 itd_flags = le32toh(sitd->itd_flags); 615 temp = (sitd->itd_next == 0); 616 617 printf("ITD(%p) at 0x%08x: sf=%d di=%d fc=%d cc=%d\n" 618 "bp0=0x%08x next=0x%08x be=0x%08x\n", 619 sitd, le32toh(sitd->itd_self), 620 OHCI_ITD_GET_SF(itd_flags), 621 OHCI_ITD_GET_DI(itd_flags), 622 OHCI_ITD_GET_FC(itd_flags), 623 OHCI_ITD_GET_CC(itd_flags), 624 le32toh(sitd->itd_bp0), 625 le32toh(sitd->itd_next), 626 le32toh(sitd->itd_be)); 627 for (i = 0; i < OHCI_ITD_NOFFSET; i++) { 628 printf("offs[%d]=0x%04x ", i, 629 (uint32_t)le16toh(sitd->itd_offset[i])); 630 } 631 printf("\n"); 632 633 return (temp); 634} 635 636static void 637ohci_dump_itds(ohci_itd_t *sitd) 638{ 639 for (; sitd; sitd = sitd->obj_next) { 640 if (ohci_dump_itd(sitd)) { 641 break; 642 } 643 } 644} 645 646static void 647ohci_dump_ed(ohci_ed_t *sed) 648{ 649 uint32_t ed_flags; 650 uint32_t ed_headp; 651 652 usb_pc_cpu_invalidate(sed->page_cache); 653 654 ed_flags = le32toh(sed->ed_flags); 655 ed_headp = le32toh(sed->ed_headp); 656 657 printf("ED(%p) at 0x%08x: addr=%d endpt=%d maxp=%d flags=%s%s%s%s%s\n" 658 "tailp=0x%08x headflags=%s%s headp=0x%08x nexted=0x%08x\n", 659 sed, le32toh(sed->ed_self), 660 OHCI_ED_GET_FA(ed_flags), 661 OHCI_ED_GET_EN(ed_flags), 662 OHCI_ED_GET_MAXP(ed_flags), 663 (ed_flags & OHCI_ED_DIR_OUT) ? "-OUT" : "", 664 (ed_flags & OHCI_ED_DIR_IN) ? "-IN" : "", 665 (ed_flags & OHCI_ED_SPEED) ? "-LOWSPEED" : "", 666 (ed_flags & OHCI_ED_SKIP) ? "-SKIP" : "", 667 (ed_flags & OHCI_ED_FORMAT_ISO) ? "-ISO" : "", 668 le32toh(sed->ed_tailp), 669 (ed_headp & OHCI_HALTED) ? "-HALTED" : "", 670 (ed_headp & OHCI_TOGGLECARRY) ? "-CARRY" : "", 671 le32toh(sed->ed_headp), 672 le32toh(sed->ed_next)); 673} 674 675#endif 676 677static void 678ohci_transfer_intr_enqueue(struct usb_xfer *xfer) 679{ 680 /* check for early completion */ 681 if (ohci_check_transfer(xfer)) { 682 return; 683 } 684 /* put transfer on interrupt queue */ 685 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 686 687 /* start timeout, if any */ 688 if (xfer->timeout != 0) { 689 usbd_transfer_timeout_ms(xfer, &ohci_timeout, xfer->timeout); 690 } 691} 692 693#define OHCI_APPEND_QH(sed,last) (last) = _ohci_append_qh(sed,last) 694static ohci_ed_t * 695_ohci_append_qh(ohci_ed_t *sed, ohci_ed_t *last) 696{ 697 DPRINTFN(11, "%p to %p\n", sed, last); 698 699 if (sed->prev != NULL) { 700 /* should not happen */ 701 DPRINTFN(0, "ED already linked!\n"); 702 return (last); 703 } 704 /* (sc->sc_bus.bus_mtx) must be locked */ 705 706 sed->next = last->next; 707 sed->ed_next = last->ed_next; 708 sed->ed_tailp = 0; 709 710 sed->prev = last; 711 712 usb_pc_cpu_flush(sed->page_cache); 713 714 /* 715 * the last->next->prev is never followed: sed->next->prev = sed; 716 */ 717 718 last->next = sed; 719 last->ed_next = sed->ed_self; 720 721 usb_pc_cpu_flush(last->page_cache); 722 723 return (sed); 724} 725 726#define OHCI_REMOVE_QH(sed,last) (last) = _ohci_remove_qh(sed,last) 727static ohci_ed_t * 728_ohci_remove_qh(ohci_ed_t *sed, ohci_ed_t *last) 729{ 730 DPRINTFN(11, "%p from %p\n", sed, last); 731 732 /* (sc->sc_bus.bus_mtx) must be locked */ 733 734 /* only remove if not removed from a queue */ 735 if (sed->prev) { 736 737 sed->prev->next = sed->next; 738 sed->prev->ed_next = sed->ed_next; 739 740 usb_pc_cpu_flush(sed->prev->page_cache); 741 742 if (sed->next) { 743 sed->next->prev = sed->prev; 744 usb_pc_cpu_flush(sed->next->page_cache); 745 } 746 last = ((last == sed) ? sed->prev : last); 747 748 sed->prev = 0; 749 750 usb_pc_cpu_flush(sed->page_cache); 751 } 752 return (last); 753} 754 755static void 756ohci_isoc_done(struct usb_xfer *xfer) 757{ 758 uint8_t nframes; 759 uint32_t *plen = xfer->frlengths; 760 volatile uint16_t *olen; 761 uint16_t len = 0; 762 ohci_itd_t *td = xfer->td_transfer_first; 763 764 while (1) { 765 if (td == NULL) { 766 panic("%s:%d: out of TD's\n", 767 __FUNCTION__, __LINE__); 768 } 769#ifdef USB_DEBUG 770 if (ohcidebug > 5) { 771 DPRINTF("isoc TD\n"); 772 ohci_dump_itd(td); 773 } 774#endif 775 usb_pc_cpu_invalidate(td->page_cache); 776 777 nframes = td->frames; 778 olen = &td->itd_offset[0]; 779 780 if (nframes > 8) { 781 nframes = 8; 782 } 783 while (nframes--) { 784 len = le16toh(*olen); 785 786 if ((len >> 12) == OHCI_CC_NOT_ACCESSED) { 787 len = 0; 788 } else { 789 len &= ((1 << 12) - 1); 790 } 791 792 if (len > *plen) { 793 len = 0;/* invalid length */ 794 } 795 *plen = len; 796 plen++; 797 olen++; 798 } 799 800 if (((void *)td) == xfer->td_transfer_last) { 801 break; 802 } 803 td = td->obj_next; 804 } 805 806 xfer->aframes = xfer->nframes; 807 ohci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 808} 809 810#ifdef USB_DEBUG 811static const char *const 812 ohci_cc_strs[] = 813{ 814 "NO_ERROR", 815 "CRC", 816 "BIT_STUFFING", 817 "DATA_TOGGLE_MISMATCH", 818 819 "STALL", 820 "DEVICE_NOT_RESPONDING", 821 "PID_CHECK_FAILURE", 822 "UNEXPECTED_PID", 823 824 "DATA_OVERRUN", 825 "DATA_UNDERRUN", 826 "BUFFER_OVERRUN", 827 "BUFFER_UNDERRUN", 828 829 "reserved", 830 "reserved", 831 "NOT_ACCESSED", 832 "NOT_ACCESSED" 833}; 834 835#endif 836 837static usb_error_t 838ohci_non_isoc_done_sub(struct usb_xfer *xfer) 839{ 840 ohci_td_t *td; 841 ohci_td_t *td_alt_next; 842 uint32_t temp; 843 uint32_t phy_start; 844 uint32_t phy_end; 845 uint32_t td_flags; 846 uint16_t cc; 847 848 td = xfer->td_transfer_cache; 849 td_alt_next = td->alt_next; 850 td_flags = 0; 851 852 if (xfer->aframes != xfer->nframes) { 853 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 854 } 855 while (1) { 856 857 usb_pc_cpu_invalidate(td->page_cache); 858 phy_start = le32toh(td->td_cbp); 859 td_flags = le32toh(td->td_flags); 860 cc = OHCI_TD_GET_CC(td_flags); 861 862 if (phy_start) { 863 /* 864 * short transfer - compute the number of remaining 865 * bytes in the hardware buffer: 866 */ 867 phy_end = le32toh(td->td_be); 868 temp = (OHCI_PAGE(phy_start ^ phy_end) ? 869 (OHCI_PAGE_SIZE + 1) : 0x0001); 870 temp += OHCI_PAGE_OFFSET(phy_end); 871 temp -= OHCI_PAGE_OFFSET(phy_start); 872 873 if (temp > td->len) { 874 /* guard against corruption */ 875 cc = OHCI_CC_STALL; 876 } else if (xfer->aframes != xfer->nframes) { 877 /* 878 * Sum up total transfer length 879 * in "frlengths[]": 880 */ 881 xfer->frlengths[xfer->aframes] += td->len - temp; 882 } 883 } else { 884 if (xfer->aframes != xfer->nframes) { 885 /* transfer was complete */ 886 xfer->frlengths[xfer->aframes] += td->len; 887 } 888 } 889 /* Check for last transfer */ 890 if (((void *)td) == xfer->td_transfer_last) { 891 td = NULL; 892 break; 893 } 894 /* Check transfer status */ 895 if (cc) { 896 /* the transfer is finished */ 897 td = NULL; 898 break; 899 } 900 /* Check for short transfer */ 901 if (phy_start) { 902 if (xfer->flags_int.short_frames_ok) { 903 /* follow alt next */ 904 td = td->alt_next; 905 } else { 906 /* the transfer is finished */ 907 td = NULL; 908 } 909 break; 910 } 911 td = td->obj_next; 912 913 if (td->alt_next != td_alt_next) { 914 /* this USB frame is complete */ 915 break; 916 } 917 } 918 919 /* update transfer cache */ 920 921 xfer->td_transfer_cache = td; 922 923 DPRINTFN(16, "error cc=%d (%s)\n", 924 cc, ohci_cc_strs[cc]); 925 926 return ((cc == 0) ? USB_ERR_NORMAL_COMPLETION : 927 (cc == OHCI_CC_STALL) ? USB_ERR_STALLED : USB_ERR_IOERROR); 928} 929 930static void 931ohci_non_isoc_done(struct usb_xfer *xfer) 932{ 933 usb_error_t err = 0; 934 935 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 936 xfer, xfer->endpoint); 937 938#ifdef USB_DEBUG 939 if (ohcidebug > 10) { 940 ohci_dump_tds(xfer->td_transfer_first); 941 } 942#endif 943 944 /* reset scanner */ 945 946 xfer->td_transfer_cache = xfer->td_transfer_first; 947 948 if (xfer->flags_int.control_xfr) { 949 950 if (xfer->flags_int.control_hdr) { 951 952 err = ohci_non_isoc_done_sub(xfer); 953 } 954 xfer->aframes = 1; 955 956 if (xfer->td_transfer_cache == NULL) { 957 goto done; 958 } 959 } 960 while (xfer->aframes != xfer->nframes) { 961 962 err = ohci_non_isoc_done_sub(xfer); 963 xfer->aframes++; 964 965 if (xfer->td_transfer_cache == NULL) { 966 goto done; 967 } 968 } 969 970 if (xfer->flags_int.control_xfr && 971 !xfer->flags_int.control_act) { 972 973 err = ohci_non_isoc_done_sub(xfer); 974 } 975done: 976 ohci_device_done(xfer, err); 977} 978 979/*------------------------------------------------------------------------* 980 * ohci_check_transfer_sub 981 *------------------------------------------------------------------------*/ 982static void 983ohci_check_transfer_sub(struct usb_xfer *xfer) 984{ 985 ohci_td_t *td; 986 ohci_ed_t *ed; 987 uint32_t phy_start; 988 uint32_t td_flags; 989 uint32_t td_next; 990 uint16_t cc; 991 992 td = xfer->td_transfer_cache; 993 994 while (1) { 995 996 usb_pc_cpu_invalidate(td->page_cache); 997 phy_start = le32toh(td->td_cbp); 998 td_flags = le32toh(td->td_flags); 999 td_next = le32toh(td->td_next); 1000 1001 /* Check for last transfer */ 1002 if (((void *)td) == xfer->td_transfer_last) { 1003 /* the transfer is finished */ 1004 td = NULL; 1005 break; 1006 } 1007 /* Check transfer status */ 1008 cc = OHCI_TD_GET_CC(td_flags); 1009 if (cc) { 1010 /* the transfer is finished */ 1011 td = NULL; 1012 break; 1013 } 1014 /* 1015 * Check if we reached the last packet 1016 * or if there is a short packet: 1017 */ 1018 1019 if (((td_next & (~0xF)) == OHCI_TD_NEXT_END) || phy_start) { 1020 /* follow alt next */ 1021 td = td->alt_next; 1022 break; 1023 } 1024 td = td->obj_next; 1025 } 1026 1027 /* update transfer cache */ 1028 1029 xfer->td_transfer_cache = td; 1030 1031 if (td) { 1032 1033 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1034 1035 ed->ed_headp = td->td_self; 1036 usb_pc_cpu_flush(ed->page_cache); 1037 1038 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1039 1040 /* 1041 * Make sure that the OHCI re-scans the schedule by 1042 * writing the BLF and CLF bits: 1043 */ 1044 1045 if (xfer->xroot->udev->flags.self_suspended) { 1046 /* nothing to do */ 1047 } else if (xfer->endpoint->methods == &ohci_device_bulk_methods) { 1048 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1049 1050 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1051 } else if (xfer->endpoint->methods == &ohci_device_ctrl_methods) { 1052 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1053 1054 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1055 } 1056 } 1057} 1058 1059/*------------------------------------------------------------------------* 1060 * ohci_check_transfer 1061 * 1062 * Return values: 1063 * 0: USB transfer is not finished 1064 * Else: USB transfer is finished 1065 *------------------------------------------------------------------------*/ 1066static uint8_t 1067ohci_check_transfer(struct usb_xfer *xfer) 1068{ 1069 ohci_ed_t *ed; 1070 uint32_t ed_headp; 1071 uint32_t ed_tailp; 1072 1073 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1074 1075 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1076 1077 usb_pc_cpu_invalidate(ed->page_cache); 1078 ed_headp = le32toh(ed->ed_headp); 1079 ed_tailp = le32toh(ed->ed_tailp); 1080 1081 if ((ed_headp & OHCI_HALTED) || 1082 (((ed_headp ^ ed_tailp) & (~0xF)) == 0)) { 1083 if (xfer->endpoint->methods == &ohci_device_isoc_methods) { 1084 /* isochronous transfer */ 1085 ohci_isoc_done(xfer); 1086 } else { 1087 if (xfer->flags_int.short_frames_ok) { 1088 ohci_check_transfer_sub(xfer); 1089 if (xfer->td_transfer_cache) { 1090 /* not finished yet */ 1091 return (0); 1092 } 1093 } 1094 /* store data-toggle */ 1095 if (ed_headp & OHCI_TOGGLECARRY) { 1096 xfer->endpoint->toggle_next = 1; 1097 } else { 1098 xfer->endpoint->toggle_next = 0; 1099 } 1100 1101 /* non-isochronous transfer */ 1102 ohci_non_isoc_done(xfer); 1103 } 1104 return (1); 1105 } 1106 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1107 return (0); 1108} 1109 1110static void 1111ohci_rhsc_enable(ohci_softc_t *sc) 1112{ 1113 DPRINTFN(5, "\n"); 1114 1115 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1116 1117 sc->sc_eintrs |= OHCI_RHSC; 1118 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1119 1120 /* acknowledge any RHSC interrupt */ 1121 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_RHSC); 1122 1123 ohci_root_intr(sc); 1124} 1125 1126static void 1127ohci_interrupt_poll(ohci_softc_t *sc) 1128{ 1129 struct usb_xfer *xfer; 1130 1131repeat: 1132 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1133 /* 1134 * check if transfer is transferred 1135 */ 1136 if (ohci_check_transfer(xfer)) { 1137 /* queue has been modified */ 1138 goto repeat; 1139 } 1140 } 1141} 1142 1143/*------------------------------------------------------------------------* 1144 * ohci_interrupt - OHCI interrupt handler 1145 * 1146 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1147 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1148 * is present ! 1149 *------------------------------------------------------------------------*/ 1150void 1151ohci_interrupt(ohci_softc_t *sc) 1152{ 1153 struct ohci_hcca *hcca; 1154 uint32_t status; 1155 uint32_t done; 1156 1157 USB_BUS_LOCK(&sc->sc_bus); 1158 1159 hcca = ohci_get_hcca(sc); 1160 1161 DPRINTFN(16, "real interrupt\n"); 1162 1163#ifdef USB_DEBUG 1164 if (ohcidebug > 15) { 1165 ohci_dumpregs(sc); 1166 } 1167#endif 1168 1169 done = le32toh(hcca->hcca_done_head); 1170 1171 /* 1172 * The LSb of done is used to inform the HC Driver that an interrupt 1173 * condition exists for both the Done list and for another event 1174 * recorded in HcInterruptStatus. On an interrupt from the HC, the 1175 * HC Driver checks the HccaDoneHead Value. If this value is 0, then 1176 * the interrupt was caused by other than the HccaDoneHead update 1177 * and the HcInterruptStatus register needs to be accessed to 1178 * determine that exact interrupt cause. If HccaDoneHead is nonzero, 1179 * then a Done list update interrupt is indicated and if the LSb of 1180 * done is nonzero, then an additional interrupt event is indicated 1181 * and HcInterruptStatus should be checked to determine its cause. 1182 */ 1183 if (done != 0) { 1184 status = 0; 1185 1186 if (done & ~OHCI_DONE_INTRS) { 1187 status |= OHCI_WDH; 1188 } 1189 if (done & OHCI_DONE_INTRS) { 1190 status |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 1191 } 1192 hcca->hcca_done_head = 0; 1193 1194 usb_pc_cpu_flush(&sc->sc_hw.hcca_pc); 1195 } else { 1196 status = OREAD4(sc, OHCI_INTERRUPT_STATUS) & ~OHCI_WDH; 1197 } 1198 1199 status &= ~OHCI_MIE; 1200 if (status == 0) { 1201 /* 1202 * nothing to be done (PCI shared 1203 * interrupt) 1204 */ 1205 goto done; 1206 } 1207 OWRITE4(sc, OHCI_INTERRUPT_STATUS, status); /* Acknowledge */ 1208 1209 status &= sc->sc_eintrs; 1210 if (status == 0) { 1211 goto done; 1212 } 1213 if (status & (OHCI_SO | OHCI_RD | OHCI_UE | OHCI_RHSC)) { 1214#if 0 1215 if (status & OHCI_SO) { 1216 /* XXX do what */ 1217 } 1218#endif 1219 if (status & OHCI_RD) { 1220 printf("%s: resume detect\n", __FUNCTION__); 1221 /* XXX process resume detect */ 1222 } 1223 if (status & OHCI_UE) { 1224 printf("%s: unrecoverable error, " 1225 "controller halted\n", __FUNCTION__); 1226 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1227 /* XXX what else */ 1228 } 1229 if (status & OHCI_RHSC) { 1230 /* 1231 * Disable RHSC interrupt for now, because it will be 1232 * on until the port has been reset. 1233 */ 1234 sc->sc_eintrs &= ~OHCI_RHSC; 1235 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 1236 1237 ohci_root_intr(sc); 1238 1239 /* do not allow RHSC interrupts > 1 per second */ 1240 usb_callout_reset(&sc->sc_tmo_rhsc, hz, 1241 (void *)&ohci_rhsc_enable, sc); 1242 } 1243 } 1244 status &= ~(OHCI_RHSC | OHCI_WDH | OHCI_SO); 1245 if (status != 0) { 1246 /* Block unprocessed interrupts. XXX */ 1247 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, status); 1248 sc->sc_eintrs &= ~status; 1249 printf("%s: blocking intrs 0x%x\n", 1250 __FUNCTION__, status); 1251 } 1252 /* poll all the USB transfers */ 1253 ohci_interrupt_poll(sc); 1254 1255done: 1256 USB_BUS_UNLOCK(&sc->sc_bus); 1257} 1258 1259/* 1260 * called when a request does not complete 1261 */ 1262static void 1263ohci_timeout(void *arg) 1264{ 1265 struct usb_xfer *xfer = arg; 1266 1267 DPRINTF("xfer=%p\n", xfer); 1268 1269 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1270 1271 /* transfer is transferred */ 1272 ohci_device_done(xfer, USB_ERR_TIMEOUT); 1273} 1274 1275static void 1276ohci_do_poll(struct usb_bus *bus) 1277{ 1278 struct ohci_softc *sc = OHCI_BUS2SC(bus); 1279 1280 USB_BUS_LOCK(&sc->sc_bus); 1281 ohci_interrupt_poll(sc); 1282 USB_BUS_UNLOCK(&sc->sc_bus); 1283} 1284 1285static void 1286ohci_setup_standard_chain_sub(struct ohci_std_temp *temp) 1287{ 1288 struct usb_page_search buf_res; 1289 ohci_td_t *td; 1290 ohci_td_t *td_next; 1291 ohci_td_t *td_alt_next; 1292 uint32_t buf_offset; 1293 uint32_t average; 1294 uint32_t len_old; 1295 uint8_t shortpkt_old; 1296 uint8_t precompute; 1297 1298 td_alt_next = NULL; 1299 buf_offset = 0; 1300 shortpkt_old = temp->shortpkt; 1301 len_old = temp->len; 1302 precompute = 1; 1303 1304 /* software is used to detect short incoming transfers */ 1305 1306 if ((temp->td_flags & htole32(OHCI_TD_DP_MASK)) == htole32(OHCI_TD_IN)) { 1307 temp->td_flags |= htole32(OHCI_TD_R); 1308 } else { 1309 temp->td_flags &= ~htole32(OHCI_TD_R); 1310 } 1311 1312restart: 1313 1314 td = temp->td; 1315 td_next = temp->td_next; 1316 1317 while (1) { 1318 1319 if (temp->len == 0) { 1320 1321 if (temp->shortpkt) { 1322 break; 1323 } 1324 /* send a Zero Length Packet, ZLP, last */ 1325 1326 temp->shortpkt = 1; 1327 average = 0; 1328 1329 } else { 1330 1331 average = temp->average; 1332 1333 if (temp->len < average) { 1334 if (temp->len % temp->max_frame_size) { 1335 temp->shortpkt = 1; 1336 } 1337 average = temp->len; 1338 } 1339 } 1340 1341 if (td_next == NULL) { 1342 panic("%s: out of OHCI transfer descriptors!", __FUNCTION__); 1343 } 1344 /* get next TD */ 1345 1346 td = td_next; 1347 td_next = td->obj_next; 1348 1349 /* check if we are pre-computing */ 1350 1351 if (precompute) { 1352 1353 /* update remaining length */ 1354 1355 temp->len -= average; 1356 1357 continue; 1358 } 1359 /* fill out current TD */ 1360 td->td_flags = temp->td_flags; 1361 1362 /* the next TD uses TOGGLE_CARRY */ 1363 temp->td_flags &= ~htole32(OHCI_TD_TOGGLE_MASK); 1364 1365 if (average == 0) { 1366 /* 1367 * The buffer start and end phys addresses should be 1368 * 0x0 for a zero length packet. 1369 */ 1370 td->td_cbp = 0; 1371 td->td_be = 0; 1372 td->len = 0; 1373 1374 } else { 1375 1376 usbd_get_page(temp->pc, buf_offset, &buf_res); 1377 td->td_cbp = htole32(buf_res.physaddr); 1378 buf_offset += (average - 1); 1379 1380 usbd_get_page(temp->pc, buf_offset, &buf_res); 1381 td->td_be = htole32(buf_res.physaddr); 1382 buf_offset++; 1383 1384 td->len = average; 1385 1386 /* update remaining length */ 1387 1388 temp->len -= average; 1389 } 1390 1391 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1392 /* we need to receive these frames one by one ! */ 1393 td->td_flags &= htole32(~OHCI_TD_INTR_MASK); 1394 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1395 td->td_next = htole32(OHCI_TD_NEXT_END); 1396 } else { 1397 if (td_next) { 1398 /* link the current TD with the next one */ 1399 td->td_next = td_next->td_self; 1400 } 1401 } 1402 1403 td->alt_next = td_alt_next; 1404 1405 usb_pc_cpu_flush(td->page_cache); 1406 } 1407 1408 if (precompute) { 1409 precompute = 0; 1410 1411 /* setup alt next pointer, if any */ 1412 if (temp->last_frame) { 1413 /* no alternate next */ 1414 td_alt_next = NULL; 1415 } else { 1416 /* we use this field internally */ 1417 td_alt_next = td_next; 1418 } 1419 1420 /* restore */ 1421 temp->shortpkt = shortpkt_old; 1422 temp->len = len_old; 1423 goto restart; 1424 } 1425 temp->td = td; 1426 temp->td_next = td_next; 1427} 1428 1429static void 1430ohci_setup_standard_chain(struct usb_xfer *xfer, ohci_ed_t **ed_last) 1431{ 1432 struct ohci_std_temp temp; 1433 struct usb_pipe_methods *methods; 1434 ohci_ed_t *ed; 1435 ohci_td_t *td; 1436 uint32_t ed_flags; 1437 uint32_t x; 1438 1439 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1440 xfer->address, UE_GET_ADDR(xfer->endpointno), 1441 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1442 1443 temp.average = xfer->max_hc_frame_size; 1444 temp.max_frame_size = xfer->max_frame_size; 1445 1446 /* toggle the DMA set we are using */ 1447 xfer->flags_int.curr_dma_set ^= 1; 1448 1449 /* get next DMA set */ 1450 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1451 1452 xfer->td_transfer_first = td; 1453 xfer->td_transfer_cache = td; 1454 1455 temp.td = NULL; 1456 temp.td_next = td; 1457 temp.last_frame = 0; 1458 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1459 1460 methods = xfer->endpoint->methods; 1461 1462 /* check if we should prepend a setup message */ 1463 1464 if (xfer->flags_int.control_xfr) { 1465 if (xfer->flags_int.control_hdr) { 1466 1467 temp.td_flags = htole32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1468 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1469 1470 temp.len = xfer->frlengths[0]; 1471 temp.pc = xfer->frbuffers + 0; 1472 temp.shortpkt = temp.len ? 1 : 0; 1473 /* check for last frame */ 1474 if (xfer->nframes == 1) { 1475 /* no STATUS stage yet, SETUP is last */ 1476 if (xfer->flags_int.control_act) { 1477 temp.last_frame = 1; 1478 temp.setup_alt_next = 0; 1479 } 1480 } 1481 ohci_setup_standard_chain_sub(&temp); 1482 1483 /* 1484 * XXX assume that the setup message is 1485 * contained within one USB packet: 1486 */ 1487 xfer->endpoint->toggle_next = 1; 1488 } 1489 x = 1; 1490 } else { 1491 x = 0; 1492 } 1493 temp.td_flags = htole32(OHCI_TD_NOCC | OHCI_TD_NOINTR); 1494 1495 /* set data toggle */ 1496 1497 if (xfer->endpoint->toggle_next) { 1498 temp.td_flags |= htole32(OHCI_TD_TOGGLE_1); 1499 } else { 1500 temp.td_flags |= htole32(OHCI_TD_TOGGLE_0); 1501 } 1502 1503 /* set endpoint direction */ 1504 1505 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 1506 temp.td_flags |= htole32(OHCI_TD_IN); 1507 } else { 1508 temp.td_flags |= htole32(OHCI_TD_OUT); 1509 } 1510 1511 while (x != xfer->nframes) { 1512 1513 /* DATA0 / DATA1 message */ 1514 1515 temp.len = xfer->frlengths[x]; 1516 temp.pc = xfer->frbuffers + x; 1517 1518 x++; 1519 1520 if (x == xfer->nframes) { 1521 if (xfer->flags_int.control_xfr) { 1522 /* no STATUS stage yet, DATA is last */ 1523 if (xfer->flags_int.control_act) { 1524 temp.last_frame = 1; 1525 temp.setup_alt_next = 0; 1526 } 1527 } else { 1528 temp.last_frame = 1; 1529 temp.setup_alt_next = 0; 1530 } 1531 } 1532 if (temp.len == 0) { 1533 1534 /* make sure that we send an USB packet */ 1535 1536 temp.shortpkt = 0; 1537 1538 } else { 1539 1540 /* regular data transfer */ 1541 1542 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1543 } 1544 1545 ohci_setup_standard_chain_sub(&temp); 1546 } 1547 1548 /* check if we should append a status stage */ 1549 1550 if (xfer->flags_int.control_xfr && 1551 !xfer->flags_int.control_act) { 1552 1553 /* 1554 * Send a DATA1 message and invert the current endpoint 1555 * direction. 1556 */ 1557 1558 /* set endpoint direction and data toggle */ 1559 1560 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 1561 temp.td_flags = htole32(OHCI_TD_OUT | 1562 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1563 } else { 1564 temp.td_flags = htole32(OHCI_TD_IN | 1565 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1566 } 1567 1568 temp.len = 0; 1569 temp.pc = NULL; 1570 temp.shortpkt = 0; 1571 temp.last_frame = 1; 1572 temp.setup_alt_next = 0; 1573 1574 ohci_setup_standard_chain_sub(&temp); 1575 } 1576 td = temp.td; 1577 1578 /* Ensure that last TD is terminating: */ 1579 td->td_next = htole32(OHCI_TD_NEXT_END); 1580 td->td_flags &= ~htole32(OHCI_TD_INTR_MASK); 1581 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1582 1583 usb_pc_cpu_flush(td->page_cache); 1584 1585 /* must have at least one frame! */ 1586 1587 xfer->td_transfer_last = td; 1588 1589#ifdef USB_DEBUG 1590 if (ohcidebug > 8) { 1591 DPRINTF("nexttog=%d; data before transfer:\n", 1592 xfer->endpoint->toggle_next); 1593 ohci_dump_tds(xfer->td_transfer_first); 1594 } 1595#endif 1596 1597 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1598 1599 ed_flags = (OHCI_ED_SET_FA(xfer->address) | 1600 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpointno)) | 1601 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 1602 1603 ed_flags |= (OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD); 1604 1605 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1606 ed_flags |= OHCI_ED_SPEED; 1607 } 1608 ed->ed_flags = htole32(ed_flags); 1609 1610 td = xfer->td_transfer_first; 1611 1612 ed->ed_headp = td->td_self; 1613 1614 if (xfer->xroot->udev->flags.self_suspended == 0) { 1615 /* the append function will flush the endpoint descriptor */ 1616 OHCI_APPEND_QH(ed, *ed_last); 1617 1618 if (methods == &ohci_device_bulk_methods) { 1619 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1620 1621 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1622 } 1623 if (methods == &ohci_device_ctrl_methods) { 1624 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1625 1626 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1627 } 1628 } else { 1629 usb_pc_cpu_flush(ed->page_cache); 1630 } 1631} 1632 1633static void 1634ohci_root_intr(ohci_softc_t *sc) 1635{ 1636 uint32_t hstatus; 1637 uint16_t i; 1638 uint16_t m; 1639 1640 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1641 1642 /* clear any old interrupt data */ 1643 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 1644 1645 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1646 DPRINTF("sc=%p hstatus=0x%08x\n", 1647 sc, hstatus); 1648 1649 /* set bits */ 1650 m = (sc->sc_noport + 1); 1651 if (m > (8 * sizeof(sc->sc_hub_idata))) { 1652 m = (8 * sizeof(sc->sc_hub_idata)); 1653 } 1654 for (i = 1; i < m; i++) { 1655 /* pick out CHANGE bits from the status register */ 1656 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) { 1657 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 1658 DPRINTF("port %d changed\n", i); 1659 } 1660 } 1661 1662 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1663 sizeof(sc->sc_hub_idata)); 1664} 1665 1666/* NOTE: "done" can be run two times in a row, 1667 * from close and from interrupt 1668 */ 1669static void 1670ohci_device_done(struct usb_xfer *xfer, usb_error_t error) 1671{ 1672 struct usb_pipe_methods *methods = xfer->endpoint->methods; 1673 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1674 ohci_ed_t *ed; 1675 1676 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1677 1678 1679 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1680 xfer, xfer->endpoint, error); 1681 1682 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1683 if (ed) { 1684 usb_pc_cpu_invalidate(ed->page_cache); 1685 } 1686 if (methods == &ohci_device_bulk_methods) { 1687 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 1688 } 1689 if (methods == &ohci_device_ctrl_methods) { 1690 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 1691 } 1692 if (methods == &ohci_device_intr_methods) { 1693 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 1694 } 1695 if (methods == &ohci_device_isoc_methods) { 1696 OHCI_REMOVE_QH(ed, sc->sc_isoc_p_last); 1697 } 1698 xfer->td_transfer_first = NULL; 1699 xfer->td_transfer_last = NULL; 1700 1701 /* dequeue transfer and start next transfer */ 1702 usbd_transfer_done(xfer, error); 1703} 1704 1705/*------------------------------------------------------------------------* 1706 * ohci bulk support 1707 *------------------------------------------------------------------------*/ 1708static void 1709ohci_device_bulk_open(struct usb_xfer *xfer) 1710{ 1711 return; 1712} 1713 1714static void 1715ohci_device_bulk_close(struct usb_xfer *xfer) 1716{ 1717 ohci_device_done(xfer, USB_ERR_CANCELLED); 1718} 1719 1720static void 1721ohci_device_bulk_enter(struct usb_xfer *xfer) 1722{ 1723 return; 1724} 1725 1726static void 1727ohci_device_bulk_start(struct usb_xfer *xfer) 1728{ 1729 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1730 1731 /* setup TD's and QH */ 1732 ohci_setup_standard_chain(xfer, &sc->sc_bulk_p_last); 1733 1734 /* put transfer on interrupt queue */ 1735 ohci_transfer_intr_enqueue(xfer); 1736} 1737 1738struct usb_pipe_methods ohci_device_bulk_methods = 1739{ 1740 .open = ohci_device_bulk_open, 1741 .close = ohci_device_bulk_close, 1742 .enter = ohci_device_bulk_enter, 1743 .start = ohci_device_bulk_start, 1744}; 1745 1746/*------------------------------------------------------------------------* 1747 * ohci control support 1748 *------------------------------------------------------------------------*/ 1749static void 1750ohci_device_ctrl_open(struct usb_xfer *xfer) 1751{ 1752 return; 1753} 1754 1755static void 1756ohci_device_ctrl_close(struct usb_xfer *xfer) 1757{ 1758 ohci_device_done(xfer, USB_ERR_CANCELLED); 1759} 1760 1761static void 1762ohci_device_ctrl_enter(struct usb_xfer *xfer) 1763{ 1764 return; 1765} 1766 1767static void 1768ohci_device_ctrl_start(struct usb_xfer *xfer) 1769{ 1770 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1771 1772 /* setup TD's and QH */ 1773 ohci_setup_standard_chain(xfer, &sc->sc_ctrl_p_last); 1774 1775 /* put transfer on interrupt queue */ 1776 ohci_transfer_intr_enqueue(xfer); 1777} 1778 1779struct usb_pipe_methods ohci_device_ctrl_methods = 1780{ 1781 .open = ohci_device_ctrl_open, 1782 .close = ohci_device_ctrl_close, 1783 .enter = ohci_device_ctrl_enter, 1784 .start = ohci_device_ctrl_start, 1785}; 1786 1787/*------------------------------------------------------------------------* 1788 * ohci interrupt support 1789 *------------------------------------------------------------------------*/ 1790static void 1791ohci_device_intr_open(struct usb_xfer *xfer) 1792{ 1793 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1794 uint16_t best; 1795 uint16_t bit; 1796 uint16_t x; 1797 1798 best = 0; 1799 bit = OHCI_NO_EDS / 2; 1800 while (bit) { 1801 if (xfer->interval >= bit) { 1802 x = bit; 1803 best = bit; 1804 while (x & bit) { 1805 if (sc->sc_intr_stat[x] < 1806 sc->sc_intr_stat[best]) { 1807 best = x; 1808 } 1809 x++; 1810 } 1811 break; 1812 } 1813 bit >>= 1; 1814 } 1815 1816 sc->sc_intr_stat[best]++; 1817 xfer->qh_pos = best; 1818 1819 DPRINTFN(3, "best=%d interval=%d\n", 1820 best, xfer->interval); 1821} 1822 1823static void 1824ohci_device_intr_close(struct usb_xfer *xfer) 1825{ 1826 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1827 1828 sc->sc_intr_stat[xfer->qh_pos]--; 1829 1830 ohci_device_done(xfer, USB_ERR_CANCELLED); 1831} 1832 1833static void 1834ohci_device_intr_enter(struct usb_xfer *xfer) 1835{ 1836 return; 1837} 1838 1839static void 1840ohci_device_intr_start(struct usb_xfer *xfer) 1841{ 1842 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1843 1844 /* setup TD's and QH */ 1845 ohci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 1846 1847 /* put transfer on interrupt queue */ 1848 ohci_transfer_intr_enqueue(xfer); 1849} 1850 1851struct usb_pipe_methods ohci_device_intr_methods = 1852{ 1853 .open = ohci_device_intr_open, 1854 .close = ohci_device_intr_close, 1855 .enter = ohci_device_intr_enter, 1856 .start = ohci_device_intr_start, 1857}; 1858 1859/*------------------------------------------------------------------------* 1860 * ohci isochronous support 1861 *------------------------------------------------------------------------*/ 1862static void 1863ohci_device_isoc_open(struct usb_xfer *xfer) 1864{ 1865 return; 1866} 1867 1868static void 1869ohci_device_isoc_close(struct usb_xfer *xfer) 1870{ 1871 /**/ 1872 ohci_device_done(xfer, USB_ERR_CANCELLED); 1873} 1874 1875static void 1876ohci_device_isoc_enter(struct usb_xfer *xfer) 1877{ 1878 struct usb_page_search buf_res; 1879 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1880 struct ohci_hcca *hcca; 1881 uint32_t buf_offset; 1882 uint32_t nframes; 1883 uint32_t ed_flags; 1884 uint32_t *plen; 1885 uint16_t itd_offset[OHCI_ITD_NOFFSET]; 1886 uint16_t length; 1887 uint8_t ncur; 1888 ohci_itd_t *td; 1889 ohci_itd_t *td_last = NULL; 1890 ohci_ed_t *ed; 1891 1892 hcca = ohci_get_hcca(sc); 1893 1894 nframes = le32toh(hcca->hcca_frame_number); 1895 1896 DPRINTFN(6, "xfer=%p isoc_next=%u nframes=%u hcca_fn=%u\n", 1897 xfer, xfer->endpoint->isoc_next, xfer->nframes, nframes); 1898 1899 if ((xfer->endpoint->is_synced == 0) || 1900 (((nframes - xfer->endpoint->isoc_next) & 0xFFFF) < xfer->nframes) || 1901 (((xfer->endpoint->isoc_next - nframes) & 0xFFFF) >= 128)) { 1902 /* 1903 * If there is data underflow or the pipe queue is empty we 1904 * schedule the transfer a few frames ahead of the current 1905 * frame position. Else two isochronous transfers might 1906 * overlap. 1907 */ 1908 xfer->endpoint->isoc_next = (nframes + 3) & 0xFFFF; 1909 xfer->endpoint->is_synced = 1; 1910 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1911 } 1912 /* 1913 * compute how many milliseconds the insertion is ahead of the 1914 * current frame position: 1915 */ 1916 buf_offset = ((xfer->endpoint->isoc_next - nframes) & 0xFFFF); 1917 1918 /* 1919 * pre-compute when the isochronous transfer will be finished: 1920 */ 1921 xfer->isoc_time_complete = 1922 (usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 1923 xfer->nframes); 1924 1925 /* get the real number of frames */ 1926 1927 nframes = xfer->nframes; 1928 1929 buf_offset = 0; 1930 1931 plen = xfer->frlengths; 1932 1933 /* toggle the DMA set we are using */ 1934 xfer->flags_int.curr_dma_set ^= 1; 1935 1936 /* get next DMA set */ 1937 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1938 1939 xfer->td_transfer_first = td; 1940 1941 ncur = 0; 1942 length = 0; 1943 1944 while (nframes--) { 1945 if (td == NULL) { 1946 panic("%s:%d: out of TD's\n", 1947 __FUNCTION__, __LINE__); 1948 } 1949 itd_offset[ncur] = length; 1950 buf_offset += *plen; 1951 length += *plen; 1952 plen++; 1953 ncur++; 1954 1955 if ( /* check if the ITD is full */ 1956 (ncur == OHCI_ITD_NOFFSET) || 1957 /* check if we have put more than 4K into the ITD */ 1958 (length & 0xF000) || 1959 /* check if it is the last frame */ 1960 (nframes == 0)) { 1961 1962 /* fill current ITD */ 1963 td->itd_flags = htole32( 1964 OHCI_ITD_NOCC | 1965 OHCI_ITD_SET_SF(xfer->endpoint->isoc_next) | 1966 OHCI_ITD_NOINTR | 1967 OHCI_ITD_SET_FC(ncur)); 1968 1969 td->frames = ncur; 1970 xfer->endpoint->isoc_next += ncur; 1971 1972 if (length == 0) { 1973 /* all zero */ 1974 td->itd_bp0 = 0; 1975 td->itd_be = ~0; 1976 1977 while (ncur--) { 1978 td->itd_offset[ncur] = 1979 htole16(OHCI_ITD_MK_OFFS(0)); 1980 } 1981 } else { 1982 usbd_get_page(xfer->frbuffers, buf_offset - length, &buf_res); 1983 length = OHCI_PAGE_MASK(buf_res.physaddr); 1984 buf_res.physaddr = 1985 OHCI_PAGE(buf_res.physaddr); 1986 td->itd_bp0 = htole32(buf_res.physaddr); 1987 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 1988 td->itd_be = htole32(buf_res.physaddr); 1989 1990 while (ncur--) { 1991 itd_offset[ncur] += length; 1992 itd_offset[ncur] = 1993 OHCI_ITD_MK_OFFS(itd_offset[ncur]); 1994 td->itd_offset[ncur] = 1995 htole16(itd_offset[ncur]); 1996 } 1997 } 1998 ncur = 0; 1999 length = 0; 2000 td_last = td; 2001 td = td->obj_next; 2002 2003 if (td) { 2004 /* link the last TD with the next one */ 2005 td_last->itd_next = td->itd_self; 2006 } 2007 usb_pc_cpu_flush(td_last->page_cache); 2008 } 2009 } 2010 2011 /* update the last TD */ 2012 td_last->itd_flags &= ~htole32(OHCI_ITD_NOINTR); 2013 td_last->itd_flags |= htole32(OHCI_ITD_SET_DI(0)); 2014 td_last->itd_next = 0; 2015 2016 usb_pc_cpu_flush(td_last->page_cache); 2017 2018 xfer->td_transfer_last = td_last; 2019 2020#ifdef USB_DEBUG 2021 if (ohcidebug > 8) { 2022 DPRINTF("data before transfer:\n"); 2023 ohci_dump_itds(xfer->td_transfer_first); 2024 } 2025#endif 2026 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2027 2028 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 2029 ed_flags = (OHCI_ED_DIR_IN | OHCI_ED_FORMAT_ISO); 2030 else 2031 ed_flags = (OHCI_ED_DIR_OUT | OHCI_ED_FORMAT_ISO); 2032 2033 ed_flags |= (OHCI_ED_SET_FA(xfer->address) | 2034 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpointno)) | 2035 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 2036 2037 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 2038 ed_flags |= OHCI_ED_SPEED; 2039 } 2040 ed->ed_flags = htole32(ed_flags); 2041 2042 td = xfer->td_transfer_first; 2043 2044 ed->ed_headp = td->itd_self; 2045 2046 /* isochronous transfers are not affected by suspend / resume */ 2047 /* the append function will flush the endpoint descriptor */ 2048 2049 OHCI_APPEND_QH(ed, sc->sc_isoc_p_last); 2050} 2051 2052static void 2053ohci_device_isoc_start(struct usb_xfer *xfer) 2054{ 2055 /* put transfer on interrupt queue */ 2056 ohci_transfer_intr_enqueue(xfer); 2057} 2058 2059struct usb_pipe_methods ohci_device_isoc_methods = 2060{ 2061 .open = ohci_device_isoc_open, 2062 .close = ohci_device_isoc_close, 2063 .enter = ohci_device_isoc_enter, 2064 .start = ohci_device_isoc_start, 2065}; 2066 2067/*------------------------------------------------------------------------* 2068 * ohci root control support 2069 *------------------------------------------------------------------------* 2070 * Simulate a hardware hub by handling all the necessary requests. 2071 *------------------------------------------------------------------------*/ 2072 2073static const 2074struct usb_device_descriptor ohci_devd = 2075{ 2076 sizeof(struct usb_device_descriptor), 2077 UDESC_DEVICE, /* type */ 2078 {0x00, 0x01}, /* USB version */ 2079 UDCLASS_HUB, /* class */ 2080 UDSUBCLASS_HUB, /* subclass */ 2081 UDPROTO_FSHUB, /* protocol */ 2082 64, /* max packet */ 2083 {0}, {0}, {0x00, 0x01}, /* device id */ 2084 1, 2, 0, /* string indicies */ 2085 1 /* # of configurations */ 2086}; 2087 2088static const 2089struct ohci_config_desc ohci_confd = 2090{ 2091 .confd = { 2092 .bLength = sizeof(struct usb_config_descriptor), 2093 .bDescriptorType = UDESC_CONFIG, 2094 .wTotalLength[0] = sizeof(ohci_confd), 2095 .bNumInterface = 1, 2096 .bConfigurationValue = 1, 2097 .iConfiguration = 0, 2098 .bmAttributes = UC_SELF_POWERED, 2099 .bMaxPower = 0, /* max power */ 2100 }, 2101 .ifcd = { 2102 .bLength = sizeof(struct usb_interface_descriptor), 2103 .bDescriptorType = UDESC_INTERFACE, 2104 .bNumEndpoints = 1, 2105 .bInterfaceClass = UICLASS_HUB, 2106 .bInterfaceSubClass = UISUBCLASS_HUB, 2107 .bInterfaceProtocol = 0, 2108 }, 2109 .endpd = { 2110 .bLength = sizeof(struct usb_endpoint_descriptor), 2111 .bDescriptorType = UDESC_ENDPOINT, 2112 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2113 .bmAttributes = UE_INTERRUPT, 2114 .wMaxPacketSize[0] = 32,/* max packet (255 ports) */ 2115 .bInterval = 255, 2116 }, 2117}; 2118 2119static const 2120struct usb_hub_descriptor ohci_hubd = 2121{ 2122 0, /* dynamic length */ 2123 UDESC_HUB, 2124 0, 2125 {0, 0}, 2126 0, 2127 0, 2128 {0}, 2129}; 2130 2131static usb_error_t 2132ohci_roothub_exec(struct usb_device *udev, 2133 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2134{ 2135 ohci_softc_t *sc = OHCI_BUS2SC(udev->bus); 2136 const void *ptr; 2137 const char *str_ptr; 2138 uint32_t port; 2139 uint32_t v; 2140 uint16_t len; 2141 uint16_t value; 2142 uint16_t index; 2143 uint8_t l; 2144 usb_error_t err; 2145 2146 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2147 2148 /* buffer reset */ 2149 ptr = (const void *)&sc->sc_hub_desc.temp; 2150 len = 0; 2151 err = 0; 2152 2153 value = UGETW(req->wValue); 2154 index = UGETW(req->wIndex); 2155 2156 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2157 "wValue=0x%04x wIndex=0x%04x\n", 2158 req->bmRequestType, req->bRequest, 2159 UGETW(req->wLength), value, index); 2160 2161#define C(x,y) ((x) | ((y) << 8)) 2162 switch (C(req->bRequest, req->bmRequestType)) { 2163 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2164 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2165 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2166 /* 2167 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2168 * for the integrated root hub. 2169 */ 2170 break; 2171 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2172 len = 1; 2173 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2174 break; 2175 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2176 switch (value >> 8) { 2177 case UDESC_DEVICE: 2178 if ((value & 0xff) != 0) { 2179 err = USB_ERR_IOERROR; 2180 goto done; 2181 } 2182 len = sizeof(ohci_devd); 2183 ptr = (const void *)&ohci_devd; 2184 break; 2185 2186 case UDESC_CONFIG: 2187 if ((value & 0xff) != 0) { 2188 err = USB_ERR_IOERROR; 2189 goto done; 2190 } 2191 len = sizeof(ohci_confd); 2192 ptr = (const void *)&ohci_confd; 2193 break; 2194 2195 case UDESC_STRING: 2196 switch (value & 0xff) { 2197 case 0: /* Language table */ 2198 str_ptr = "\001"; 2199 break; 2200 2201 case 1: /* Vendor */ 2202 str_ptr = sc->sc_vendor; 2203 break; 2204 2205 case 2: /* Product */ 2206 str_ptr = "OHCI root HUB"; 2207 break; 2208 2209 default: 2210 str_ptr = ""; 2211 break; 2212 } 2213 2214 len = usb_make_str_desc( 2215 sc->sc_hub_desc.temp, 2216 sizeof(sc->sc_hub_desc.temp), 2217 str_ptr); 2218 break; 2219 2220 default: 2221 err = USB_ERR_IOERROR; 2222 goto done; 2223 } 2224 break; 2225 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2226 len = 1; 2227 sc->sc_hub_desc.temp[0] = 0; 2228 break; 2229 case C(UR_GET_STATUS, UT_READ_DEVICE): 2230 len = 2; 2231 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2232 break; 2233 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2234 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2235 len = 2; 2236 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2237 break; 2238 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2239 if (value >= OHCI_MAX_DEVICES) { 2240 err = USB_ERR_IOERROR; 2241 goto done; 2242 } 2243 sc->sc_addr = value; 2244 break; 2245 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2246 if ((value != 0) && (value != 1)) { 2247 err = USB_ERR_IOERROR; 2248 goto done; 2249 } 2250 sc->sc_conf = value; 2251 break; 2252 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2253 break; 2254 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2255 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2256 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2257 err = USB_ERR_IOERROR; 2258 goto done; 2259 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2260 break; 2261 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2262 break; 2263 /* Hub requests */ 2264 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2265 break; 2266 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2267 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE " 2268 "port=%d feature=%d\n", 2269 index, value); 2270 if ((index < 1) || 2271 (index > sc->sc_noport)) { 2272 err = USB_ERR_IOERROR; 2273 goto done; 2274 } 2275 port = OHCI_RH_PORT_STATUS(index); 2276 switch (value) { 2277 case UHF_PORT_ENABLE: 2278 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2279 break; 2280 case UHF_PORT_SUSPEND: 2281 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2282 break; 2283 case UHF_PORT_POWER: 2284 /* Yes, writing to the LOW_SPEED bit clears power. */ 2285 OWRITE4(sc, port, UPS_LOW_SPEED); 2286 break; 2287 case UHF_C_PORT_CONNECTION: 2288 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2289 break; 2290 case UHF_C_PORT_ENABLE: 2291 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2292 break; 2293 case UHF_C_PORT_SUSPEND: 2294 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2295 break; 2296 case UHF_C_PORT_OVER_CURRENT: 2297 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2298 break; 2299 case UHF_C_PORT_RESET: 2300 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2301 break; 2302 default: 2303 err = USB_ERR_IOERROR; 2304 goto done; 2305 } 2306 switch (value) { 2307 case UHF_C_PORT_CONNECTION: 2308 case UHF_C_PORT_ENABLE: 2309 case UHF_C_PORT_SUSPEND: 2310 case UHF_C_PORT_OVER_CURRENT: 2311 case UHF_C_PORT_RESET: 2312 /* enable RHSC interrupt if condition is cleared. */ 2313 if ((OREAD4(sc, port) >> 16) == 0) 2314 ohci_rhsc_enable(sc); 2315 break; 2316 default: 2317 break; 2318 } 2319 break; 2320 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2321 if ((value & 0xff) != 0) { 2322 err = USB_ERR_IOERROR; 2323 goto done; 2324 } 2325 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2326 2327 sc->sc_hub_desc.hubd = ohci_hubd; 2328 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 2329 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, 2330 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2331 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2332 /* XXX overcurrent */ 2333 ); 2334 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2335 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2336 2337 for (l = 0; l < sc->sc_noport; l++) { 2338 if (v & 1) { 2339 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] |= (1 << (l % 8)); 2340 } 2341 v >>= 1; 2342 } 2343 sc->sc_hub_desc.hubd.bDescLength = 2344 8 + ((sc->sc_noport + 7) / 8); 2345 len = sc->sc_hub_desc.hubd.bDescLength; 2346 break; 2347 2348 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2349 len = 16; 2350 bzero(sc->sc_hub_desc.temp, 16); 2351 break; 2352 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2353 DPRINTFN(9, "get port status i=%d\n", 2354 index); 2355 if ((index < 1) || 2356 (index > sc->sc_noport)) { 2357 err = USB_ERR_IOERROR; 2358 goto done; 2359 } 2360 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2361 DPRINTFN(9, "port status=0x%04x\n", v); 2362 USETW(sc->sc_hub_desc.ps.wPortStatus, v); 2363 USETW(sc->sc_hub_desc.ps.wPortChange, v >> 16); 2364 len = sizeof(sc->sc_hub_desc.ps); 2365 break; 2366 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2367 err = USB_ERR_IOERROR; 2368 goto done; 2369 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2370 break; 2371 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2372 if ((index < 1) || 2373 (index > sc->sc_noport)) { 2374 err = USB_ERR_IOERROR; 2375 goto done; 2376 } 2377 port = OHCI_RH_PORT_STATUS(index); 2378 switch (value) { 2379 case UHF_PORT_ENABLE: 2380 OWRITE4(sc, port, UPS_PORT_ENABLED); 2381 break; 2382 case UHF_PORT_SUSPEND: 2383 OWRITE4(sc, port, UPS_SUSPEND); 2384 break; 2385 case UHF_PORT_RESET: 2386 DPRINTFN(6, "reset port %d\n", index); 2387 OWRITE4(sc, port, UPS_RESET); 2388 for (v = 0;; v++) { 2389 if (v < 12) { 2390 usb_pause_mtx(&sc->sc_bus.bus_mtx, 2391 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY)); 2392 2393 if ((OREAD4(sc, port) & UPS_RESET) == 0) { 2394 break; 2395 } 2396 } else { 2397 err = USB_ERR_TIMEOUT; 2398 goto done; 2399 } 2400 } 2401 DPRINTFN(9, "ohci port %d reset, status = 0x%04x\n", 2402 index, OREAD4(sc, port)); 2403 break; 2404 case UHF_PORT_POWER: 2405 DPRINTFN(3, "set port power %d\n", index); 2406 OWRITE4(sc, port, UPS_PORT_POWER); 2407 break; 2408 default: 2409 err = USB_ERR_IOERROR; 2410 goto done; 2411 } 2412 break; 2413 default: 2414 err = USB_ERR_IOERROR; 2415 goto done; 2416 } 2417done: 2418 *plength = len; 2419 *pptr = ptr; 2420 return (err); 2421} 2422 2423static void 2424ohci_xfer_setup(struct usb_setup_params *parm) 2425{ 2426 struct usb_page_search page_info; 2427 struct usb_page_cache *pc; 2428 ohci_softc_t *sc; 2429 struct usb_xfer *xfer; 2430 void *last_obj; 2431 uint32_t ntd; 2432 uint32_t nitd; 2433 uint32_t nqh; 2434 uint32_t n; 2435 2436 sc = OHCI_BUS2SC(parm->udev->bus); 2437 xfer = parm->curr_xfer; 2438 2439 parm->hc_max_packet_size = 0x500; 2440 parm->hc_max_packet_count = 1; 2441 parm->hc_max_frame_size = OHCI_PAGE_SIZE; 2442 2443 /* 2444 * calculate ntd and nqh 2445 */ 2446 if (parm->methods == &ohci_device_ctrl_methods) { 2447 xfer->flags_int.bdma_enable = 1; 2448 2449 usbd_transfer_setup_sub(parm); 2450 2451 nitd = 0; 2452 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2453 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2454 nqh = 1; 2455 2456 } else if (parm->methods == &ohci_device_bulk_methods) { 2457 xfer->flags_int.bdma_enable = 1; 2458 2459 usbd_transfer_setup_sub(parm); 2460 2461 nitd = 0; 2462 ntd = ((2 * xfer->nframes) 2463 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2464 nqh = 1; 2465 2466 } else if (parm->methods == &ohci_device_intr_methods) { 2467 xfer->flags_int.bdma_enable = 1; 2468 2469 usbd_transfer_setup_sub(parm); 2470 2471 nitd = 0; 2472 ntd = ((2 * xfer->nframes) 2473 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2474 nqh = 1; 2475 2476 } else if (parm->methods == &ohci_device_isoc_methods) { 2477 xfer->flags_int.bdma_enable = 1; 2478 2479 usbd_transfer_setup_sub(parm); 2480 2481 nitd = ((xfer->max_data_length / OHCI_PAGE_SIZE) + 2482 ((xfer->nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET) + 2483 1 /* EXTRA */ ); 2484 ntd = 0; 2485 nqh = 1; 2486 2487 } else { 2488 2489 usbd_transfer_setup_sub(parm); 2490 2491 nitd = 0; 2492 ntd = 0; 2493 nqh = 0; 2494 } 2495 2496alloc_dma_set: 2497 2498 if (parm->err) { 2499 return; 2500 } 2501 last_obj = NULL; 2502 2503 if (usbd_transfer_setup_sub_malloc( 2504 parm, &pc, sizeof(ohci_td_t), 2505 OHCI_TD_ALIGN, ntd)) { 2506 parm->err = USB_ERR_NOMEM; 2507 return; 2508 } 2509 if (parm->buf) { 2510 for (n = 0; n != ntd; n++) { 2511 ohci_td_t *td; 2512 2513 usbd_get_page(pc + n, 0, &page_info); 2514 2515 td = page_info.buffer; 2516 2517 /* init TD */ 2518 td->td_self = htole32(page_info.physaddr); 2519 td->obj_next = last_obj; 2520 td->page_cache = pc + n; 2521 2522 last_obj = td; 2523 2524 usb_pc_cpu_flush(pc + n); 2525 } 2526 } 2527 if (usbd_transfer_setup_sub_malloc( 2528 parm, &pc, sizeof(ohci_itd_t), 2529 OHCI_ITD_ALIGN, nitd)) { 2530 parm->err = USB_ERR_NOMEM; 2531 return; 2532 } 2533 if (parm->buf) { 2534 for (n = 0; n != nitd; n++) { 2535 ohci_itd_t *itd; 2536 2537 usbd_get_page(pc + n, 0, &page_info); 2538 2539 itd = page_info.buffer; 2540 2541 /* init TD */ 2542 itd->itd_self = htole32(page_info.physaddr); 2543 itd->obj_next = last_obj; 2544 itd->page_cache = pc + n; 2545 2546 last_obj = itd; 2547 2548 usb_pc_cpu_flush(pc + n); 2549 } 2550 } 2551 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2552 2553 last_obj = NULL; 2554 2555 if (usbd_transfer_setup_sub_malloc( 2556 parm, &pc, sizeof(ohci_ed_t), 2557 OHCI_ED_ALIGN, nqh)) { 2558 parm->err = USB_ERR_NOMEM; 2559 return; 2560 } 2561 if (parm->buf) { 2562 for (n = 0; n != nqh; n++) { 2563 ohci_ed_t *ed; 2564 2565 usbd_get_page(pc + n, 0, &page_info); 2566 2567 ed = page_info.buffer; 2568 2569 /* init QH */ 2570 ed->ed_self = htole32(page_info.physaddr); 2571 ed->obj_next = last_obj; 2572 ed->page_cache = pc + n; 2573 2574 last_obj = ed; 2575 2576 usb_pc_cpu_flush(pc + n); 2577 } 2578 } 2579 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 2580 2581 if (!xfer->flags_int.curr_dma_set) { 2582 xfer->flags_int.curr_dma_set = 1; 2583 goto alloc_dma_set; 2584 } 2585} 2586 2587static void 2588ohci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2589 struct usb_endpoint *ep) 2590{ 2591 ohci_softc_t *sc = OHCI_BUS2SC(udev->bus); 2592 2593 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2594 ep, udev->address, 2595 edesc->bEndpointAddress, udev->flags.usb_mode, 2596 sc->sc_addr); 2597 2598 if (udev->flags.usb_mode != USB_MODE_HOST) { 2599 /* not supported */ 2600 return; 2601 } 2602 if (udev->device_index != sc->sc_addr) { 2603 switch (edesc->bmAttributes & UE_XFERTYPE) { 2604 case UE_CONTROL: 2605 ep->methods = &ohci_device_ctrl_methods; 2606 break; 2607 case UE_INTERRUPT: 2608 ep->methods = &ohci_device_intr_methods; 2609 break; 2610 case UE_ISOCHRONOUS: 2611 if (udev->speed == USB_SPEED_FULL) { 2612 ep->methods = &ohci_device_isoc_methods; 2613 } 2614 break; 2615 case UE_BULK: 2616 ep->methods = &ohci_device_bulk_methods; 2617 break; 2618 default: 2619 /* do nothing */ 2620 break; 2621 } 2622 } 2623} 2624 2625static void 2626ohci_xfer_unsetup(struct usb_xfer *xfer) 2627{ 2628 return; 2629} 2630 2631static void 2632ohci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 2633{ 2634 /* 2635 * Wait until hardware has finished any possible use of the 2636 * transfer descriptor(s) and QH 2637 */ 2638 *pus = (1125); /* microseconds */ 2639} 2640 2641static void 2642ohci_device_resume(struct usb_device *udev) 2643{ 2644 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2645 struct usb_xfer *xfer; 2646 struct usb_pipe_methods *methods; 2647 ohci_ed_t *ed; 2648 2649 DPRINTF("\n"); 2650 2651 USB_BUS_LOCK(udev->bus); 2652 2653 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2654 2655 if (xfer->xroot->udev == udev) { 2656 2657 methods = xfer->endpoint->methods; 2658 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2659 2660 if (methods == &ohci_device_bulk_methods) { 2661 OHCI_APPEND_QH(ed, sc->sc_bulk_p_last); 2662 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2663 } 2664 if (methods == &ohci_device_ctrl_methods) { 2665 OHCI_APPEND_QH(ed, sc->sc_ctrl_p_last); 2666 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2667 } 2668 if (methods == &ohci_device_intr_methods) { 2669 OHCI_APPEND_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2670 } 2671 } 2672 } 2673 2674 USB_BUS_UNLOCK(udev->bus); 2675 2676 return; 2677} 2678 2679static void 2680ohci_device_suspend(struct usb_device *udev) 2681{ 2682 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2683 struct usb_xfer *xfer; 2684 struct usb_pipe_methods *methods; 2685 ohci_ed_t *ed; 2686 2687 DPRINTF("\n"); 2688 2689 USB_BUS_LOCK(udev->bus); 2690 2691 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2692 2693 if (xfer->xroot->udev == udev) { 2694 2695 methods = xfer->endpoint->methods; 2696 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2697 2698 if (methods == &ohci_device_bulk_methods) { 2699 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 2700 } 2701 if (methods == &ohci_device_ctrl_methods) { 2702 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 2703 } 2704 if (methods == &ohci_device_intr_methods) { 2705 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2706 } 2707 } 2708 } 2709 2710 USB_BUS_UNLOCK(udev->bus); 2711 2712 return; 2713} 2714 2715static void 2716ohci_set_hw_power(struct usb_bus *bus) 2717{ 2718 struct ohci_softc *sc = OHCI_BUS2SC(bus); 2719 uint32_t temp; 2720 uint32_t flags; 2721 2722 DPRINTF("\n"); 2723 2724 USB_BUS_LOCK(bus); 2725 2726 flags = bus->hw_power_state; 2727 2728 temp = OREAD4(sc, OHCI_CONTROL); 2729 temp &= ~(OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE); 2730 2731 if (flags & USB_HW_POWER_CONTROL) 2732 temp |= OHCI_CLE; 2733 2734 if (flags & USB_HW_POWER_BULK) 2735 temp |= OHCI_BLE; 2736 2737 if (flags & USB_HW_POWER_INTERRUPT) 2738 temp |= OHCI_PLE; 2739 2740 if (flags & USB_HW_POWER_ISOC) 2741 temp |= OHCI_IE | OHCI_PLE; 2742 2743 OWRITE4(sc, OHCI_CONTROL, temp); 2744 2745 USB_BUS_UNLOCK(bus); 2746 2747 return; 2748} 2749 2750struct usb_bus_methods ohci_bus_methods = 2751{ 2752 .endpoint_init = ohci_ep_init, 2753 .xfer_setup = ohci_xfer_setup, 2754 .xfer_unsetup = ohci_xfer_unsetup, 2755 .get_dma_delay = ohci_get_dma_delay, 2756 .device_resume = ohci_device_resume, 2757 .device_suspend = ohci_device_suspend, 2758 .set_hw_power = ohci_set_hw_power, 2759 .roothub_exec = ohci_roothub_exec, 2760 .xfer_poll = ohci_do_poll, 2761}; 2762