ohci.c revision 190174
1/*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/usb/controller/ohci.c 190174 2009-03-20 19:04:31Z thompsa $"); 30 31/* 32 * USB Open Host Controller driver. 33 * 34 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 35 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 36 */ 37 38#include <dev/usb/usb.h> 39#include <dev/usb/usb_mfunc.h> 40#include <dev/usb/usb_error.h> 41 42#define USB_DEBUG_VAR ohcidebug 43 44#include <dev/usb/usb_core.h> 45#include <dev/usb/usb_debug.h> 46#include <dev/usb/usb_busdma.h> 47#include <dev/usb/usb_process.h> 48#include <dev/usb/usb_sw_transfer.h> 49#include <dev/usb/usb_transfer.h> 50#include <dev/usb/usb_device.h> 51#include <dev/usb/usb_hub.h> 52#include <dev/usb/usb_util.h> 53 54#include <dev/usb/usb_controller.h> 55#include <dev/usb/usb_bus.h> 56#include <dev/usb/controller/ohci.h> 57 58#define OHCI_BUS2SC(bus) ((ohci_softc_t *)(((uint8_t *)(bus)) - \ 59 USB_P2U(&(((ohci_softc_t *)0)->sc_bus)))) 60 61#if USB_DEBUG 62static int ohcidebug = 0; 63 64SYSCTL_NODE(_hw_usb2, OID_AUTO, ohci, CTLFLAG_RW, 0, "USB ohci"); 65SYSCTL_INT(_hw_usb2_ohci, OID_AUTO, debug, CTLFLAG_RW, 66 &ohcidebug, 0, "ohci debug level"); 67static void ohci_dumpregs(ohci_softc_t *); 68static void ohci_dump_tds(ohci_td_t *); 69static uint8_t ohci_dump_td(ohci_td_t *); 70static void ohci_dump_ed(ohci_ed_t *); 71static uint8_t ohci_dump_itd(ohci_itd_t *); 72static void ohci_dump_itds(ohci_itd_t *); 73 74#endif 75 76#define OBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 77 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 78#define OWRITE1(sc, r, x) \ 79 do { OBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 80#define OWRITE2(sc, r, x) \ 81 do { OBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 82#define OWRITE4(sc, r, x) \ 83 do { OBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 84#define OREAD1(sc, r) (OBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 85#define OREAD2(sc, r) (OBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 86#define OREAD4(sc, r) (OBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 87 88#define OHCI_INTR_ENDPT 1 89 90extern struct usb2_bus_methods ohci_bus_methods; 91extern struct usb2_pipe_methods ohci_device_bulk_methods; 92extern struct usb2_pipe_methods ohci_device_ctrl_methods; 93extern struct usb2_pipe_methods ohci_device_intr_methods; 94extern struct usb2_pipe_methods ohci_device_isoc_methods; 95extern struct usb2_pipe_methods ohci_root_ctrl_methods; 96extern struct usb2_pipe_methods ohci_root_intr_methods; 97 98static void ohci_root_ctrl_poll(struct ohci_softc *sc); 99static void ohci_do_poll(struct usb2_bus *bus); 100static void ohci_device_done(struct usb2_xfer *xfer, usb2_error_t error); 101 102static usb2_sw_transfer_func_t ohci_root_intr_done; 103static usb2_sw_transfer_func_t ohci_root_ctrl_done; 104static void ohci_timeout(void *arg); 105static uint8_t ohci_check_transfer(struct usb2_xfer *xfer); 106 107struct ohci_std_temp { 108 struct usb2_page_cache *pc; 109 ohci_td_t *td; 110 ohci_td_t *td_next; 111 uint32_t average; 112 uint32_t td_flags; 113 uint32_t len; 114 uint16_t max_frame_size; 115 uint8_t shortpkt; 116 uint8_t setup_alt_next; 117 uint8_t short_frames_ok; 118}; 119 120static struct ohci_hcca * 121ohci_get_hcca(ohci_softc_t *sc) 122{ 123 usb2_pc_cpu_invalidate(&sc->sc_hw.hcca_pc); 124 return (sc->sc_hcca_p); 125} 126 127void 128ohci_iterate_hw_softc(struct usb2_bus *bus, usb2_bus_mem_sub_cb_t *cb) 129{ 130 struct ohci_softc *sc = OHCI_BUS2SC(bus); 131 uint32_t i; 132 133 cb(bus, &sc->sc_hw.hcca_pc, &sc->sc_hw.hcca_pg, 134 sizeof(ohci_hcca_t), OHCI_HCCA_ALIGN); 135 136 cb(bus, &sc->sc_hw.ctrl_start_pc, &sc->sc_hw.ctrl_start_pg, 137 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 138 139 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 140 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 141 142 cb(bus, &sc->sc_hw.isoc_start_pc, &sc->sc_hw.isoc_start_pg, 143 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 144 145 for (i = 0; i != OHCI_NO_EDS; i++) { 146 cb(bus, sc->sc_hw.intr_start_pc + i, sc->sc_hw.intr_start_pg + i, 147 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 148 } 149} 150 151static usb2_error_t 152ohci_controller_init(ohci_softc_t *sc) 153{ 154 struct usb2_page_search buf_res; 155 uint32_t i; 156 uint32_t ctl; 157 uint32_t ival; 158 uint32_t hcr; 159 uint32_t fm; 160 uint32_t per; 161 uint32_t desca; 162 163 /* Determine in what context we are running. */ 164 ctl = OREAD4(sc, OHCI_CONTROL); 165 if (ctl & OHCI_IR) { 166 /* SMM active, request change */ 167 DPRINTF("SMM active, request owner change\n"); 168 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_OCR); 169 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 170 usb2_pause_mtx(NULL, hz / 1000); 171 ctl = OREAD4(sc, OHCI_CONTROL); 172 } 173 if (ctl & OHCI_IR) { 174 device_printf(sc->sc_bus.bdev, 175 "SMM does not respond, resetting\n"); 176 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 177 goto reset; 178 } 179 } else { 180 DPRINTF("cold started\n"); 181reset: 182 /* controller was cold started */ 183 usb2_pause_mtx(NULL, 184 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 185 } 186 187 /* 188 * This reset should not be necessary according to the OHCI spec, but 189 * without it some controllers do not start. 190 */ 191 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 192 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 193 194 usb2_pause_mtx(NULL, 195 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 196 197 /* we now own the host controller and the bus has been reset */ 198 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL)); 199 200 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 201 /* nominal time for a reset is 10 us */ 202 for (i = 0; i < 10; i++) { 203 DELAY(10); 204 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 205 if (!hcr) { 206 break; 207 } 208 } 209 if (hcr) { 210 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 211 return (USB_ERR_IOERROR); 212 } 213#if USB_DEBUG 214 if (ohcidebug > 15) { 215 ohci_dumpregs(sc); 216 } 217#endif 218 219 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 220 221 /* set up HC registers */ 222 usb2_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 223 OWRITE4(sc, OHCI_HCCA, buf_res.physaddr); 224 225 usb2_get_page(&sc->sc_hw.ctrl_start_pc, 0, &buf_res); 226 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, buf_res.physaddr); 227 228 usb2_get_page(&sc->sc_hw.bulk_start_pc, 0, &buf_res); 229 OWRITE4(sc, OHCI_BULK_HEAD_ED, buf_res.physaddr); 230 231 /* disable all interrupts and then switch on all desired interrupts */ 232 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 233 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 234 /* switch on desired functional features */ 235 ctl = OREAD4(sc, OHCI_CONTROL); 236 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 237 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 238 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL; 239 /* And finally start it! */ 240 OWRITE4(sc, OHCI_CONTROL, ctl); 241 242 /* 243 * The controller is now OPERATIONAL. Set a some final 244 * registers that should be set earlier, but that the 245 * controller ignores when in the SUSPEND state. 246 */ 247 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 248 fm |= OHCI_FSMPS(ival) | ival; 249 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 250 per = OHCI_PERIODIC(ival); /* 90% periodic */ 251 OWRITE4(sc, OHCI_PERIODIC_START, per); 252 253 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 254 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 255 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 256 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 257 usb2_pause_mtx(NULL, 258 USB_MS_TO_TICKS(OHCI_ENABLE_POWER_DELAY)); 259 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 260 261 /* 262 * The AMD756 requires a delay before re-reading the register, 263 * otherwise it will occasionally report 0 ports. 264 */ 265 sc->sc_noport = 0; 266 for (i = 0; (i < 10) && (sc->sc_noport == 0); i++) { 267 usb2_pause_mtx(NULL, 268 USB_MS_TO_TICKS(OHCI_READ_DESC_DELAY)); 269 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 270 } 271 272#if USB_DEBUG 273 if (ohcidebug > 5) { 274 ohci_dumpregs(sc); 275 } 276#endif 277 return (USB_ERR_NORMAL_COMPLETION); 278} 279 280static struct ohci_ed * 281ohci_init_ed(struct usb2_page_cache *pc) 282{ 283 struct usb2_page_search buf_res; 284 struct ohci_ed *ed; 285 286 usb2_get_page(pc, 0, &buf_res); 287 288 ed = buf_res.buffer; 289 290 ed->ed_self = htole32(buf_res.physaddr); 291 ed->ed_flags = htole32(OHCI_ED_SKIP); 292 ed->page_cache = pc; 293 294 return (ed); 295} 296 297usb2_error_t 298ohci_init(ohci_softc_t *sc) 299{ 300 struct usb2_page_search buf_res; 301 uint16_t i; 302 uint16_t bit; 303 uint16_t x; 304 uint16_t y; 305 306 DPRINTF("start\n"); 307 308 sc->sc_eintrs = OHCI_NORMAL_INTRS; 309 310 /* 311 * Setup all ED's 312 */ 313 314 sc->sc_ctrl_p_last = 315 ohci_init_ed(&sc->sc_hw.ctrl_start_pc); 316 317 sc->sc_bulk_p_last = 318 ohci_init_ed(&sc->sc_hw.bulk_start_pc); 319 320 sc->sc_isoc_p_last = 321 ohci_init_ed(&sc->sc_hw.isoc_start_pc); 322 323 for (i = 0; i != OHCI_NO_EDS; i++) { 324 sc->sc_intr_p_last[i] = 325 ohci_init_ed(sc->sc_hw.intr_start_pc + i); 326 } 327 328 /* 329 * the QHs are arranged to give poll intervals that are 330 * powers of 2 times 1ms 331 */ 332 bit = OHCI_NO_EDS / 2; 333 while (bit) { 334 x = bit; 335 while (x & bit) { 336 ohci_ed_t *ed_x; 337 ohci_ed_t *ed_y; 338 339 y = (x ^ bit) | (bit / 2); 340 341 /* 342 * the next QH has half the poll interval 343 */ 344 ed_x = sc->sc_intr_p_last[x]; 345 ed_y = sc->sc_intr_p_last[y]; 346 347 ed_x->next = NULL; 348 ed_x->ed_next = ed_y->ed_self; 349 350 x++; 351 } 352 bit >>= 1; 353 } 354 355 if (1) { 356 357 ohci_ed_t *ed_int; 358 ohci_ed_t *ed_isc; 359 360 ed_int = sc->sc_intr_p_last[0]; 361 ed_isc = sc->sc_isoc_p_last; 362 363 /* the last (1ms) QH */ 364 ed_int->next = ed_isc; 365 ed_int->ed_next = ed_isc->ed_self; 366 } 367 usb2_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 368 369 sc->sc_hcca_p = buf_res.buffer; 370 371 /* 372 * Fill HCCA interrupt table. The bit reversal is to get 373 * the tree set up properly to spread the interrupts. 374 */ 375 for (i = 0; i != OHCI_NO_INTRS; i++) { 376 sc->sc_hcca_p->hcca_interrupt_table[i] = 377 sc->sc_intr_p_last[i | (OHCI_NO_EDS / 2)]->ed_self; 378 } 379 /* flush all cache into memory */ 380 381 usb2_bus_mem_flush_all(&sc->sc_bus, &ohci_iterate_hw_softc); 382 383 /* set up the bus struct */ 384 sc->sc_bus.methods = &ohci_bus_methods; 385 386 usb2_callout_init_mtx(&sc->sc_tmo_rhsc, &sc->sc_bus.bus_mtx, 0); 387 388#if USB_DEBUG 389 if (ohcidebug > 15) { 390 for (i = 0; i != OHCI_NO_EDS; i++) { 391 printf("ed#%d ", i); 392 ohci_dump_ed(sc->sc_intr_p_last[i]); 393 } 394 printf("iso "); 395 ohci_dump_ed(sc->sc_isoc_p_last); 396 } 397#endif 398 399 sc->sc_bus.usbrev = USB_REV_1_0; 400 401 if (ohci_controller_init(sc)) { 402 return (USB_ERR_INVAL); 403 } else { 404 /* catch any lost interrupts */ 405 ohci_do_poll(&sc->sc_bus); 406 return (USB_ERR_NORMAL_COMPLETION); 407 } 408} 409 410/* 411 * shut down the controller when the system is going down 412 */ 413void 414ohci_detach(struct ohci_softc *sc) 415{ 416 USB_BUS_LOCK(&sc->sc_bus); 417 418 usb2_callout_stop(&sc->sc_tmo_rhsc); 419 420 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 421 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 422 423 USB_BUS_UNLOCK(&sc->sc_bus); 424 425 /* XXX let stray task complete */ 426 usb2_pause_mtx(NULL, hz / 20); 427 428 usb2_callout_drain(&sc->sc_tmo_rhsc); 429} 430 431/* NOTE: suspend/resume is called from 432 * interrupt context and cannot sleep! 433 */ 434void 435ohci_suspend(ohci_softc_t *sc) 436{ 437 uint32_t ctl; 438 439 USB_BUS_LOCK(&sc->sc_bus); 440 441#if USB_DEBUG 442 DPRINTF("\n"); 443 if (ohcidebug > 2) { 444 ohci_dumpregs(sc); 445 } 446#endif 447 448 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 449 if (sc->sc_control == 0) { 450 /* 451 * Preserve register values, in case that APM BIOS 452 * does not recover them. 453 */ 454 sc->sc_control = ctl; 455 sc->sc_intre = OREAD4(sc, OHCI_INTERRUPT_ENABLE); 456 } 457 ctl |= OHCI_HCFS_SUSPEND; 458 OWRITE4(sc, OHCI_CONTROL, ctl); 459 460 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 461 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 462 463 USB_BUS_UNLOCK(&sc->sc_bus); 464} 465 466void 467ohci_resume(ohci_softc_t *sc) 468{ 469 uint32_t ctl; 470 471#if USB_DEBUG 472 DPRINTF("\n"); 473 if (ohcidebug > 2) { 474 ohci_dumpregs(sc); 475 } 476#endif 477 /* some broken BIOSes never initialize the Controller chip */ 478 ohci_controller_init(sc); 479 480 USB_BUS_LOCK(&sc->sc_bus); 481 if (sc->sc_intre) { 482 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, 483 sc->sc_intre & (OHCI_ALL_INTRS | OHCI_MIE)); 484 } 485 if (sc->sc_control) 486 ctl = sc->sc_control; 487 else 488 ctl = OREAD4(sc, OHCI_CONTROL); 489 ctl |= OHCI_HCFS_RESUME; 490 OWRITE4(sc, OHCI_CONTROL, ctl); 491 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 492 USB_MS_TO_TICKS(USB_RESUME_DELAY)); 493 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 494 OWRITE4(sc, OHCI_CONTROL, ctl); 495 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 496 USB_MS_TO_TICKS(USB_RESUME_RECOVERY)); 497 sc->sc_control = sc->sc_intre = 0; 498 499 USB_BUS_UNLOCK(&sc->sc_bus); 500 501 /* catch any lost interrupts */ 502 ohci_do_poll(&sc->sc_bus); 503} 504 505#if USB_DEBUG 506static void 507ohci_dumpregs(ohci_softc_t *sc) 508{ 509 struct ohci_hcca *hcca; 510 511 DPRINTF("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 512 OREAD4(sc, OHCI_REVISION), 513 OREAD4(sc, OHCI_CONTROL), 514 OREAD4(sc, OHCI_COMMAND_STATUS)); 515 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 516 OREAD4(sc, OHCI_INTERRUPT_STATUS), 517 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 518 OREAD4(sc, OHCI_INTERRUPT_DISABLE)); 519 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 520 OREAD4(sc, OHCI_HCCA), 521 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 522 OREAD4(sc, OHCI_CONTROL_HEAD_ED)); 523 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 524 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 525 OREAD4(sc, OHCI_BULK_HEAD_ED), 526 OREAD4(sc, OHCI_BULK_CURRENT_ED)); 527 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 528 OREAD4(sc, OHCI_DONE_HEAD), 529 OREAD4(sc, OHCI_FM_INTERVAL), 530 OREAD4(sc, OHCI_FM_REMAINING)); 531 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 532 OREAD4(sc, OHCI_FM_NUMBER), 533 OREAD4(sc, OHCI_PERIODIC_START), 534 OREAD4(sc, OHCI_LS_THRESHOLD)); 535 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x\n", 536 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 537 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 538 OREAD4(sc, OHCI_RH_STATUS)); 539 DPRINTF(" port1=0x%08x port2=0x%08x\n", 540 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 541 OREAD4(sc, OHCI_RH_PORT_STATUS(2))); 542 543 hcca = ohci_get_hcca(sc); 544 545 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x\n", 546 le32toh(hcca->hcca_frame_number), 547 le32toh(hcca->hcca_done_head)); 548} 549static void 550ohci_dump_tds(ohci_td_t *std) 551{ 552 for (; std; std = std->obj_next) { 553 if (ohci_dump_td(std)) { 554 break; 555 } 556 } 557} 558 559static uint8_t 560ohci_dump_td(ohci_td_t *std) 561{ 562 uint32_t td_flags; 563 uint8_t temp; 564 565 usb2_pc_cpu_invalidate(std->page_cache); 566 567 td_flags = le32toh(std->td_flags); 568 temp = (std->td_next == 0); 569 570 printf("TD(%p) at 0x%08x: %s%s%s%s%s delay=%d ec=%d " 571 "cc=%d\ncbp=0x%08x next=0x%08x be=0x%08x\n", 572 std, le32toh(std->td_self), 573 (td_flags & OHCI_TD_R) ? "-R" : "", 574 (td_flags & OHCI_TD_OUT) ? "-OUT" : "", 575 (td_flags & OHCI_TD_IN) ? "-IN" : "", 576 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_1) ? "-TOG1" : "", 577 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_0) ? "-TOG0" : "", 578 OHCI_TD_GET_DI(td_flags), 579 OHCI_TD_GET_EC(td_flags), 580 OHCI_TD_GET_CC(td_flags), 581 le32toh(std->td_cbp), 582 le32toh(std->td_next), 583 le32toh(std->td_be)); 584 585 return (temp); 586} 587 588static uint8_t 589ohci_dump_itd(ohci_itd_t *sitd) 590{ 591 uint32_t itd_flags; 592 uint16_t i; 593 uint8_t temp; 594 595 usb2_pc_cpu_invalidate(sitd->page_cache); 596 597 itd_flags = le32toh(sitd->itd_flags); 598 temp = (sitd->itd_next == 0); 599 600 printf("ITD(%p) at 0x%08x: sf=%d di=%d fc=%d cc=%d\n" 601 "bp0=0x%08x next=0x%08x be=0x%08x\n", 602 sitd, le32toh(sitd->itd_self), 603 OHCI_ITD_GET_SF(itd_flags), 604 OHCI_ITD_GET_DI(itd_flags), 605 OHCI_ITD_GET_FC(itd_flags), 606 OHCI_ITD_GET_CC(itd_flags), 607 le32toh(sitd->itd_bp0), 608 le32toh(sitd->itd_next), 609 le32toh(sitd->itd_be)); 610 for (i = 0; i < OHCI_ITD_NOFFSET; i++) { 611 printf("offs[%d]=0x%04x ", i, 612 (uint32_t)le16toh(sitd->itd_offset[i])); 613 } 614 printf("\n"); 615 616 return (temp); 617} 618 619static void 620ohci_dump_itds(ohci_itd_t *sitd) 621{ 622 for (; sitd; sitd = sitd->obj_next) { 623 if (ohci_dump_itd(sitd)) { 624 break; 625 } 626 } 627} 628 629static void 630ohci_dump_ed(ohci_ed_t *sed) 631{ 632 uint32_t ed_flags; 633 uint32_t ed_headp; 634 635 usb2_pc_cpu_invalidate(sed->page_cache); 636 637 ed_flags = le32toh(sed->ed_flags); 638 ed_headp = le32toh(sed->ed_headp); 639 640 printf("ED(%p) at 0x%08x: addr=%d endpt=%d maxp=%d flags=%s%s%s%s%s\n" 641 "tailp=0x%08x headflags=%s%s headp=0x%08x nexted=0x%08x\n", 642 sed, le32toh(sed->ed_self), 643 OHCI_ED_GET_FA(ed_flags), 644 OHCI_ED_GET_EN(ed_flags), 645 OHCI_ED_GET_MAXP(ed_flags), 646 (ed_flags & OHCI_ED_DIR_OUT) ? "-OUT" : "", 647 (ed_flags & OHCI_ED_DIR_IN) ? "-IN" : "", 648 (ed_flags & OHCI_ED_SPEED) ? "-LOWSPEED" : "", 649 (ed_flags & OHCI_ED_SKIP) ? "-SKIP" : "", 650 (ed_flags & OHCI_ED_FORMAT_ISO) ? "-ISO" : "", 651 le32toh(sed->ed_tailp), 652 (ed_headp & OHCI_HALTED) ? "-HALTED" : "", 653 (ed_headp & OHCI_TOGGLECARRY) ? "-CARRY" : "", 654 le32toh(sed->ed_headp), 655 le32toh(sed->ed_next)); 656} 657 658#endif 659 660static void 661ohci_transfer_intr_enqueue(struct usb2_xfer *xfer) 662{ 663 /* check for early completion */ 664 if (ohci_check_transfer(xfer)) { 665 return; 666 } 667 /* put transfer on interrupt queue */ 668 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 669 670 /* start timeout, if any */ 671 if (xfer->timeout != 0) { 672 usb2_transfer_timeout_ms(xfer, &ohci_timeout, xfer->timeout); 673 } 674} 675 676#define OHCI_APPEND_QH(sed,last) (last) = _ohci_append_qh(sed,last) 677static ohci_ed_t * 678_ohci_append_qh(ohci_ed_t *sed, ohci_ed_t *last) 679{ 680 DPRINTFN(11, "%p to %p\n", sed, last); 681 682 if (sed->prev != NULL) { 683 /* should not happen */ 684 DPRINTFN(0, "ED already linked!\n"); 685 return (last); 686 } 687 /* (sc->sc_bus.bus_mtx) must be locked */ 688 689 sed->next = last->next; 690 sed->ed_next = last->ed_next; 691 sed->ed_tailp = 0; 692 693 sed->prev = last; 694 695 usb2_pc_cpu_flush(sed->page_cache); 696 697 /* 698 * the last->next->prev is never followed: sed->next->prev = sed; 699 */ 700 701 last->next = sed; 702 last->ed_next = sed->ed_self; 703 704 usb2_pc_cpu_flush(last->page_cache); 705 706 return (sed); 707} 708 709#define OHCI_REMOVE_QH(sed,last) (last) = _ohci_remove_qh(sed,last) 710static ohci_ed_t * 711_ohci_remove_qh(ohci_ed_t *sed, ohci_ed_t *last) 712{ 713 DPRINTFN(11, "%p from %p\n", sed, last); 714 715 /* (sc->sc_bus.bus_mtx) must be locked */ 716 717 /* only remove if not removed from a queue */ 718 if (sed->prev) { 719 720 sed->prev->next = sed->next; 721 sed->prev->ed_next = sed->ed_next; 722 723 usb2_pc_cpu_flush(sed->prev->page_cache); 724 725 if (sed->next) { 726 sed->next->prev = sed->prev; 727 usb2_pc_cpu_flush(sed->next->page_cache); 728 } 729 last = ((last == sed) ? sed->prev : last); 730 731 sed->prev = 0; 732 733 usb2_pc_cpu_flush(sed->page_cache); 734 } 735 return (last); 736} 737 738static void 739ohci_isoc_done(struct usb2_xfer *xfer) 740{ 741 uint8_t nframes; 742 uint32_t *plen = xfer->frlengths; 743 volatile uint16_t *olen; 744 uint16_t len = 0; 745 ohci_itd_t *td = xfer->td_transfer_first; 746 747 while (1) { 748 if (td == NULL) { 749 panic("%s:%d: out of TD's\n", 750 __FUNCTION__, __LINE__); 751 } 752#if USB_DEBUG 753 if (ohcidebug > 5) { 754 DPRINTF("isoc TD\n"); 755 ohci_dump_itd(td); 756 } 757#endif 758 usb2_pc_cpu_invalidate(td->page_cache); 759 760 nframes = td->frames; 761 olen = &td->itd_offset[0]; 762 763 if (nframes > 8) { 764 nframes = 8; 765 } 766 while (nframes--) { 767 len = le16toh(*olen); 768 769 if ((len >> 12) == OHCI_CC_NOT_ACCESSED) { 770 len = 0; 771 } else { 772 len &= ((1 << 12) - 1); 773 } 774 775 if (len > *plen) { 776 len = 0;/* invalid length */ 777 } 778 *plen = len; 779 plen++; 780 olen++; 781 } 782 783 if (((void *)td) == xfer->td_transfer_last) { 784 break; 785 } 786 td = td->obj_next; 787 } 788 789 xfer->aframes = xfer->nframes; 790 ohci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 791} 792 793#if USB_DEBUG 794static const char *const 795 ohci_cc_strs[] = 796{ 797 "NO_ERROR", 798 "CRC", 799 "BIT_STUFFING", 800 "DATA_TOGGLE_MISMATCH", 801 802 "STALL", 803 "DEVICE_NOT_RESPONDING", 804 "PID_CHECK_FAILURE", 805 "UNEXPECTED_PID", 806 807 "DATA_OVERRUN", 808 "DATA_UNDERRUN", 809 "BUFFER_OVERRUN", 810 "BUFFER_UNDERRUN", 811 812 "reserved", 813 "reserved", 814 "NOT_ACCESSED", 815 "NOT_ACCESSED" 816}; 817 818#endif 819 820static usb2_error_t 821ohci_non_isoc_done_sub(struct usb2_xfer *xfer) 822{ 823 ohci_td_t *td; 824 ohci_td_t *td_alt_next; 825 uint32_t temp; 826 uint32_t phy_start; 827 uint32_t phy_end; 828 uint32_t td_flags; 829 uint16_t cc; 830 831 td = xfer->td_transfer_cache; 832 td_alt_next = td->alt_next; 833 td_flags = 0; 834 835 if (xfer->aframes != xfer->nframes) { 836 xfer->frlengths[xfer->aframes] = 0; 837 } 838 while (1) { 839 840 usb2_pc_cpu_invalidate(td->page_cache); 841 phy_start = le32toh(td->td_cbp); 842 td_flags = le32toh(td->td_flags); 843 cc = OHCI_TD_GET_CC(td_flags); 844 845 if (phy_start) { 846 /* 847 * short transfer - compute the number of remaining 848 * bytes in the hardware buffer: 849 */ 850 phy_end = le32toh(td->td_be); 851 temp = (OHCI_PAGE(phy_start ^ phy_end) ? 852 (OHCI_PAGE_SIZE + 1) : 0x0001); 853 temp += OHCI_PAGE_OFFSET(phy_end); 854 temp -= OHCI_PAGE_OFFSET(phy_start); 855 856 if (temp > td->len) { 857 /* guard against corruption */ 858 cc = OHCI_CC_STALL; 859 } else if (xfer->aframes != xfer->nframes) { 860 /* 861 * Sum up total transfer length 862 * in "frlengths[]": 863 */ 864 xfer->frlengths[xfer->aframes] += td->len - temp; 865 } 866 } else { 867 if (xfer->aframes != xfer->nframes) { 868 /* transfer was complete */ 869 xfer->frlengths[xfer->aframes] += td->len; 870 } 871 } 872 /* Check for last transfer */ 873 if (((void *)td) == xfer->td_transfer_last) { 874 td = NULL; 875 break; 876 } 877 /* Check transfer status */ 878 if (cc) { 879 /* the transfer is finished */ 880 td = NULL; 881 break; 882 } 883 /* Check for short transfer */ 884 if (phy_start) { 885 if (xfer->flags_int.short_frames_ok) { 886 /* follow alt next */ 887 td = td->alt_next; 888 } else { 889 /* the transfer is finished */ 890 td = NULL; 891 } 892 break; 893 } 894 td = td->obj_next; 895 896 if (td->alt_next != td_alt_next) { 897 /* this USB frame is complete */ 898 break; 899 } 900 } 901 902 /* update transfer cache */ 903 904 xfer->td_transfer_cache = td; 905 906 DPRINTFN(16, "error cc=%d (%s)\n", 907 cc, ohci_cc_strs[cc]); 908 909 return ((cc == 0) ? USB_ERR_NORMAL_COMPLETION : 910 (cc == OHCI_CC_STALL) ? USB_ERR_STALLED : USB_ERR_IOERROR); 911} 912 913static void 914ohci_non_isoc_done(struct usb2_xfer *xfer) 915{ 916 usb2_error_t err = 0; 917 918 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 919 xfer, xfer->pipe); 920 921#if USB_DEBUG 922 if (ohcidebug > 10) { 923 ohci_dump_tds(xfer->td_transfer_first); 924 } 925#endif 926 927 /* reset scanner */ 928 929 xfer->td_transfer_cache = xfer->td_transfer_first; 930 931 if (xfer->flags_int.control_xfr) { 932 933 if (xfer->flags_int.control_hdr) { 934 935 err = ohci_non_isoc_done_sub(xfer); 936 } 937 xfer->aframes = 1; 938 939 if (xfer->td_transfer_cache == NULL) { 940 goto done; 941 } 942 } 943 while (xfer->aframes != xfer->nframes) { 944 945 err = ohci_non_isoc_done_sub(xfer); 946 xfer->aframes++; 947 948 if (xfer->td_transfer_cache == NULL) { 949 goto done; 950 } 951 } 952 953 if (xfer->flags_int.control_xfr && 954 !xfer->flags_int.control_act) { 955 956 err = ohci_non_isoc_done_sub(xfer); 957 } 958done: 959 ohci_device_done(xfer, err); 960} 961 962/*------------------------------------------------------------------------* 963 * ohci_check_transfer_sub 964 *------------------------------------------------------------------------*/ 965static void 966ohci_check_transfer_sub(struct usb2_xfer *xfer) 967{ 968 ohci_td_t *td; 969 ohci_ed_t *ed; 970 uint32_t phy_start; 971 uint32_t td_flags; 972 uint32_t td_next; 973 uint16_t cc; 974 975 td = xfer->td_transfer_cache; 976 977 while (1) { 978 979 usb2_pc_cpu_invalidate(td->page_cache); 980 phy_start = le32toh(td->td_cbp); 981 td_flags = le32toh(td->td_flags); 982 td_next = le32toh(td->td_next); 983 984 /* Check for last transfer */ 985 if (((void *)td) == xfer->td_transfer_last) { 986 /* the transfer is finished */ 987 td = NULL; 988 break; 989 } 990 /* Check transfer status */ 991 cc = OHCI_TD_GET_CC(td_flags); 992 if (cc) { 993 /* the transfer is finished */ 994 td = NULL; 995 break; 996 } 997 /* 998 * Check if we reached the last packet 999 * or if there is a short packet: 1000 */ 1001 1002 if (((td_next & (~0xF)) == OHCI_TD_NEXT_END) || phy_start) { 1003 /* follow alt next */ 1004 td = td->alt_next; 1005 break; 1006 } 1007 td = td->obj_next; 1008 } 1009 1010 /* update transfer cache */ 1011 1012 xfer->td_transfer_cache = td; 1013 1014 if (td) { 1015 1016 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1017 1018 ed->ed_headp = td->td_self; 1019 usb2_pc_cpu_flush(ed->page_cache); 1020 1021 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1022 } 1023} 1024 1025/*------------------------------------------------------------------------* 1026 * ohci_check_transfer 1027 * 1028 * Return values: 1029 * 0: USB transfer is not finished 1030 * Else: USB transfer is finished 1031 *------------------------------------------------------------------------*/ 1032static uint8_t 1033ohci_check_transfer(struct usb2_xfer *xfer) 1034{ 1035 ohci_ed_t *ed; 1036 uint32_t ed_flags; 1037 uint32_t ed_headp; 1038 uint32_t ed_tailp; 1039 1040 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1041 1042 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1043 1044 usb2_pc_cpu_invalidate(ed->page_cache); 1045 ed_flags = le32toh(ed->ed_flags); 1046 ed_headp = le32toh(ed->ed_headp); 1047 ed_tailp = le32toh(ed->ed_tailp); 1048 1049 if ((ed_flags & OHCI_ED_SKIP) || 1050 (ed_headp & OHCI_HALTED) || 1051 (((ed_headp ^ ed_tailp) & (~0xF)) == 0)) { 1052 if (xfer->pipe->methods == &ohci_device_isoc_methods) { 1053 /* isochronous transfer */ 1054 ohci_isoc_done(xfer); 1055 } else { 1056 if (xfer->flags_int.short_frames_ok) { 1057 ohci_check_transfer_sub(xfer); 1058 if (xfer->td_transfer_cache) { 1059 /* not finished yet */ 1060 return (0); 1061 } 1062 } 1063 /* store data-toggle */ 1064 if (ed_headp & OHCI_TOGGLECARRY) { 1065 xfer->pipe->toggle_next = 1; 1066 } else { 1067 xfer->pipe->toggle_next = 0; 1068 } 1069 1070 /* non-isochronous transfer */ 1071 ohci_non_isoc_done(xfer); 1072 } 1073 return (1); 1074 } 1075 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1076 return (0); 1077} 1078 1079static void 1080ohci_rhsc_enable(ohci_softc_t *sc) 1081{ 1082 DPRINTFN(5, "\n"); 1083 1084 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1085 1086 sc->sc_eintrs |= OHCI_RHSC; 1087 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1088 1089 /* acknowledge any RHSC interrupt */ 1090 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_RHSC); 1091 1092 usb2_sw_transfer(&sc->sc_root_intr, 1093 &ohci_root_intr_done); 1094} 1095 1096static void 1097ohci_interrupt_poll(ohci_softc_t *sc) 1098{ 1099 struct usb2_xfer *xfer; 1100 1101repeat: 1102 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1103 /* 1104 * check if transfer is transferred 1105 */ 1106 if (ohci_check_transfer(xfer)) { 1107 /* queue has been modified */ 1108 goto repeat; 1109 } 1110 } 1111} 1112 1113/*------------------------------------------------------------------------* 1114 * ohci_interrupt - OHCI interrupt handler 1115 * 1116 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1117 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1118 * is present ! 1119 *------------------------------------------------------------------------*/ 1120void 1121ohci_interrupt(ohci_softc_t *sc) 1122{ 1123 struct ohci_hcca *hcca; 1124 uint32_t status; 1125 uint32_t done; 1126 1127 USB_BUS_LOCK(&sc->sc_bus); 1128 1129 hcca = ohci_get_hcca(sc); 1130 1131 DPRINTFN(16, "real interrupt\n"); 1132 1133#if USB_DEBUG 1134 if (ohcidebug > 15) { 1135 ohci_dumpregs(sc); 1136 } 1137#endif 1138 1139 done = le32toh(hcca->hcca_done_head); 1140 1141 /* 1142 * The LSb of done is used to inform the HC Driver that an interrupt 1143 * condition exists for both the Done list and for another event 1144 * recorded in HcInterruptStatus. On an interrupt from the HC, the 1145 * HC Driver checks the HccaDoneHead Value. If this value is 0, then 1146 * the interrupt was caused by other than the HccaDoneHead update 1147 * and the HcInterruptStatus register needs to be accessed to 1148 * determine that exact interrupt cause. If HccaDoneHead is nonzero, 1149 * then a Done list update interrupt is indicated and if the LSb of 1150 * done is nonzero, then an additional interrupt event is indicated 1151 * and HcInterruptStatus should be checked to determine its cause. 1152 */ 1153 if (done != 0) { 1154 status = 0; 1155 1156 if (done & ~OHCI_DONE_INTRS) { 1157 status |= OHCI_WDH; 1158 } 1159 if (done & OHCI_DONE_INTRS) { 1160 status |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 1161 } 1162 hcca->hcca_done_head = 0; 1163 1164 usb2_pc_cpu_flush(&sc->sc_hw.hcca_pc); 1165 } else { 1166 status = OREAD4(sc, OHCI_INTERRUPT_STATUS) & ~OHCI_WDH; 1167 } 1168 1169 status &= ~OHCI_MIE; 1170 if (status == 0) { 1171 /* 1172 * nothing to be done (PCI shared 1173 * interrupt) 1174 */ 1175 goto done; 1176 } 1177 OWRITE4(sc, OHCI_INTERRUPT_STATUS, status); /* Acknowledge */ 1178 1179 status &= sc->sc_eintrs; 1180 if (status == 0) { 1181 goto done; 1182 } 1183 if (status & (OHCI_SO | OHCI_RD | OHCI_UE | OHCI_RHSC)) { 1184#if 0 1185 if (status & OHCI_SO) { 1186 /* XXX do what */ 1187 } 1188#endif 1189 if (status & OHCI_RD) { 1190 printf("%s: resume detect\n", __FUNCTION__); 1191 /* XXX process resume detect */ 1192 } 1193 if (status & OHCI_UE) { 1194 printf("%s: unrecoverable error, " 1195 "controller halted\n", __FUNCTION__); 1196 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1197 /* XXX what else */ 1198 } 1199 if (status & OHCI_RHSC) { 1200 /* 1201 * Disable RHSC interrupt for now, because it will be 1202 * on until the port has been reset. 1203 */ 1204 sc->sc_eintrs &= ~OHCI_RHSC; 1205 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 1206 1207 usb2_sw_transfer(&sc->sc_root_intr, 1208 &ohci_root_intr_done); 1209 1210 /* do not allow RHSC interrupts > 1 per second */ 1211 usb2_callout_reset(&sc->sc_tmo_rhsc, hz, 1212 (void *)&ohci_rhsc_enable, sc); 1213 } 1214 } 1215 status &= ~(OHCI_RHSC | OHCI_WDH | OHCI_SO); 1216 if (status != 0) { 1217 /* Block unprocessed interrupts. XXX */ 1218 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, status); 1219 sc->sc_eintrs &= ~status; 1220 printf("%s: blocking intrs 0x%x\n", 1221 __FUNCTION__, status); 1222 } 1223 /* poll all the USB transfers */ 1224 ohci_interrupt_poll(sc); 1225 1226done: 1227 USB_BUS_UNLOCK(&sc->sc_bus); 1228} 1229 1230/* 1231 * called when a request does not complete 1232 */ 1233static void 1234ohci_timeout(void *arg) 1235{ 1236 struct usb2_xfer *xfer = arg; 1237 1238 DPRINTF("xfer=%p\n", xfer); 1239 1240 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1241 1242 /* transfer is transferred */ 1243 ohci_device_done(xfer, USB_ERR_TIMEOUT); 1244} 1245 1246static void 1247ohci_do_poll(struct usb2_bus *bus) 1248{ 1249 struct ohci_softc *sc = OHCI_BUS2SC(bus); 1250 1251 USB_BUS_LOCK(&sc->sc_bus); 1252 ohci_interrupt_poll(sc); 1253 ohci_root_ctrl_poll(sc); 1254 USB_BUS_UNLOCK(&sc->sc_bus); 1255} 1256 1257static void 1258ohci_setup_standard_chain_sub(struct ohci_std_temp *temp) 1259{ 1260 struct usb2_page_search buf_res; 1261 ohci_td_t *td; 1262 ohci_td_t *td_next; 1263 ohci_td_t *td_alt_next; 1264 uint32_t buf_offset; 1265 uint32_t average; 1266 uint32_t len_old; 1267 uint8_t shortpkt_old; 1268 uint8_t precompute; 1269 1270 td_alt_next = NULL; 1271 buf_offset = 0; 1272 shortpkt_old = temp->shortpkt; 1273 len_old = temp->len; 1274 precompute = 1; 1275 1276 /* software is used to detect short incoming transfers */ 1277 1278 if ((temp->td_flags & htole32(OHCI_TD_DP_MASK)) == htole32(OHCI_TD_IN)) { 1279 temp->td_flags |= htole32(OHCI_TD_R); 1280 } else { 1281 temp->td_flags &= ~htole32(OHCI_TD_R); 1282 } 1283 1284restart: 1285 1286 td = temp->td; 1287 td_next = temp->td_next; 1288 1289 while (1) { 1290 1291 if (temp->len == 0) { 1292 1293 if (temp->shortpkt) { 1294 break; 1295 } 1296 /* send a Zero Length Packet, ZLP, last */ 1297 1298 temp->shortpkt = 1; 1299 average = 0; 1300 1301 } else { 1302 1303 average = temp->average; 1304 1305 if (temp->len < average) { 1306 if (temp->len % temp->max_frame_size) { 1307 temp->shortpkt = 1; 1308 } 1309 average = temp->len; 1310 } 1311 } 1312 1313 if (td_next == NULL) { 1314 panic("%s: out of OHCI transfer descriptors!", __FUNCTION__); 1315 } 1316 /* get next TD */ 1317 1318 td = td_next; 1319 td_next = td->obj_next; 1320 1321 /* check if we are pre-computing */ 1322 1323 if (precompute) { 1324 1325 /* update remaining length */ 1326 1327 temp->len -= average; 1328 1329 continue; 1330 } 1331 /* fill out current TD */ 1332 td->td_flags = temp->td_flags; 1333 1334 /* the next TD uses TOGGLE_CARRY */ 1335 temp->td_flags &= ~htole32(OHCI_TD_TOGGLE_MASK); 1336 1337 if (average == 0) { 1338 1339 td->td_cbp = 0; 1340 td->td_be = ~0; 1341 td->len = 0; 1342 1343 } else { 1344 1345 usb2_get_page(temp->pc, buf_offset, &buf_res); 1346 td->td_cbp = htole32(buf_res.physaddr); 1347 buf_offset += (average - 1); 1348 1349 usb2_get_page(temp->pc, buf_offset, &buf_res); 1350 td->td_be = htole32(buf_res.physaddr); 1351 buf_offset++; 1352 1353 td->len = average; 1354 1355 /* update remaining length */ 1356 1357 temp->len -= average; 1358 } 1359 1360 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1361 /* we need to receive these frames one by one ! */ 1362 td->td_flags &= htole32(~OHCI_TD_INTR_MASK); 1363 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1364 td->td_next = htole32(OHCI_TD_NEXT_END); 1365 } else { 1366 if (td_next) { 1367 /* link the current TD with the next one */ 1368 td->td_next = td_next->td_self; 1369 } 1370 } 1371 1372 td->alt_next = td_alt_next; 1373 1374 usb2_pc_cpu_flush(td->page_cache); 1375 } 1376 1377 if (precompute) { 1378 precompute = 0; 1379 1380 /* setup alt next pointer, if any */ 1381 if (temp->short_frames_ok) { 1382 if (temp->setup_alt_next) { 1383 td_alt_next = td_next; 1384 } 1385 } else { 1386 /* we use this field internally */ 1387 td_alt_next = td_next; 1388 } 1389 1390 /* restore */ 1391 temp->shortpkt = shortpkt_old; 1392 temp->len = len_old; 1393 goto restart; 1394 } 1395 temp->td = td; 1396 temp->td_next = td_next; 1397} 1398 1399static void 1400ohci_setup_standard_chain(struct usb2_xfer *xfer, ohci_ed_t **ed_last) 1401{ 1402 struct ohci_std_temp temp; 1403 struct usb2_pipe_methods *methods; 1404 ohci_ed_t *ed; 1405 ohci_td_t *td; 1406 uint32_t ed_flags; 1407 uint32_t x; 1408 1409 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1410 xfer->address, UE_GET_ADDR(xfer->endpoint), 1411 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 1412 1413 temp.average = xfer->max_usb2_frame_size; 1414 temp.max_frame_size = xfer->max_frame_size; 1415 1416 /* toggle the DMA set we are using */ 1417 xfer->flags_int.curr_dma_set ^= 1; 1418 1419 /* get next DMA set */ 1420 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1421 1422 xfer->td_transfer_first = td; 1423 xfer->td_transfer_cache = td; 1424 1425 temp.td = NULL; 1426 temp.td_next = td; 1427 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1428 temp.short_frames_ok = xfer->flags_int.short_frames_ok; 1429 1430 methods = xfer->pipe->methods; 1431 1432 /* check if we should prepend a setup message */ 1433 1434 if (xfer->flags_int.control_xfr) { 1435 if (xfer->flags_int.control_hdr) { 1436 1437 temp.td_flags = htole32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1438 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1439 1440 temp.len = xfer->frlengths[0]; 1441 temp.pc = xfer->frbuffers + 0; 1442 temp.shortpkt = temp.len ? 1 : 0; 1443 1444 ohci_setup_standard_chain_sub(&temp); 1445 1446 /* 1447 * XXX assume that the setup message is 1448 * contained within one USB packet: 1449 */ 1450 xfer->pipe->toggle_next = 1; 1451 } 1452 x = 1; 1453 } else { 1454 x = 0; 1455 } 1456 temp.td_flags = htole32(OHCI_TD_NOCC | OHCI_TD_NOINTR); 1457 1458 /* set data toggle */ 1459 1460 if (xfer->pipe->toggle_next) { 1461 temp.td_flags |= htole32(OHCI_TD_TOGGLE_1); 1462 } else { 1463 temp.td_flags |= htole32(OHCI_TD_TOGGLE_0); 1464 } 1465 1466 /* set endpoint direction */ 1467 1468 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 1469 temp.td_flags |= htole32(OHCI_TD_IN); 1470 } else { 1471 temp.td_flags |= htole32(OHCI_TD_OUT); 1472 } 1473 1474 while (x != xfer->nframes) { 1475 1476 /* DATA0 / DATA1 message */ 1477 1478 temp.len = xfer->frlengths[x]; 1479 temp.pc = xfer->frbuffers + x; 1480 1481 x++; 1482 1483 if (x == xfer->nframes) { 1484 temp.setup_alt_next = 0; 1485 } 1486 if (temp.len == 0) { 1487 1488 /* make sure that we send an USB packet */ 1489 1490 temp.shortpkt = 0; 1491 1492 } else { 1493 1494 /* regular data transfer */ 1495 1496 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1497 } 1498 1499 ohci_setup_standard_chain_sub(&temp); 1500 } 1501 1502 /* check if we should append a status stage */ 1503 1504 if (xfer->flags_int.control_xfr && 1505 !xfer->flags_int.control_act) { 1506 1507 /* 1508 * Send a DATA1 message and invert the current endpoint 1509 * direction. 1510 */ 1511 1512 /* set endpoint direction and data toggle */ 1513 1514 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 1515 temp.td_flags = htole32(OHCI_TD_OUT | 1516 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1517 } else { 1518 temp.td_flags = htole32(OHCI_TD_IN | 1519 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1520 } 1521 1522 temp.len = 0; 1523 temp.pc = NULL; 1524 temp.shortpkt = 0; 1525 1526 ohci_setup_standard_chain_sub(&temp); 1527 } 1528 td = temp.td; 1529 1530 td->td_next = htole32(OHCI_TD_NEXT_END); 1531 td->td_flags &= ~htole32(OHCI_TD_INTR_MASK); 1532 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1533 1534 usb2_pc_cpu_flush(td->page_cache); 1535 1536 /* must have at least one frame! */ 1537 1538 xfer->td_transfer_last = td; 1539 1540#if USB_DEBUG 1541 if (ohcidebug > 8) { 1542 DPRINTF("nexttog=%d; data before transfer:\n", 1543 xfer->pipe->toggle_next); 1544 ohci_dump_tds(xfer->td_transfer_first); 1545 } 1546#endif 1547 1548 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1549 1550 ed_flags = (OHCI_ED_SET_FA(xfer->address) | 1551 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpoint)) | 1552 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 1553 1554 ed_flags |= (OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD); 1555 1556 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1557 ed_flags |= OHCI_ED_SPEED; 1558 } 1559 ed->ed_flags = htole32(ed_flags); 1560 1561 td = xfer->td_transfer_first; 1562 1563 ed->ed_headp = td->td_self; 1564 1565 if (xfer->xroot->udev->pwr_save.suspended == 0) { 1566 /* the append function will flush the endpoint descriptor */ 1567 OHCI_APPEND_QH(ed, *ed_last); 1568 1569 if (methods == &ohci_device_bulk_methods) { 1570 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1571 1572 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1573 } 1574 if (methods == &ohci_device_ctrl_methods) { 1575 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1576 1577 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1578 } 1579 } else { 1580 usb2_pc_cpu_flush(ed->page_cache); 1581 } 1582} 1583 1584static void 1585ohci_root_intr_done(struct usb2_xfer *xfer, 1586 struct usb2_sw_transfer *std) 1587{ 1588 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1589 uint32_t hstatus; 1590 uint16_t i; 1591 uint16_t m; 1592 1593 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1594 1595 if (std->state != USB_SW_TR_PRE_DATA) { 1596 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1597 /* transfer transferred */ 1598 ohci_device_done(xfer, std->err); 1599 } 1600 goto done; 1601 } 1602 /* setup buffer */ 1603 std->ptr = sc->sc_hub_idata; 1604 std->len = sizeof(sc->sc_hub_idata); 1605 1606 /* clear any old interrupt data */ 1607 bzero(sc->sc_hub_idata, sizeof(sc->sc_hub_idata)); 1608 1609 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1610 DPRINTF("sc=%p xfer=%p hstatus=0x%08x\n", 1611 sc, xfer, hstatus); 1612 1613 /* set bits */ 1614 m = (sc->sc_noport + 1); 1615 if (m > (8 * sizeof(sc->sc_hub_idata))) { 1616 m = (8 * sizeof(sc->sc_hub_idata)); 1617 } 1618 for (i = 1; i < m; i++) { 1619 /* pick out CHANGE bits from the status register */ 1620 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) { 1621 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 1622 DPRINTF("port %d changed\n", i); 1623 } 1624 } 1625done: 1626 return; 1627} 1628 1629/* NOTE: "done" can be run two times in a row, 1630 * from close and from interrupt 1631 */ 1632static void 1633ohci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1634{ 1635 struct usb2_pipe_methods *methods = xfer->pipe->methods; 1636 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1637 ohci_ed_t *ed; 1638 1639 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1640 1641 1642 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1643 xfer, xfer->pipe, error); 1644 1645 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1646 if (ed) { 1647 usb2_pc_cpu_invalidate(ed->page_cache); 1648 } 1649 if (methods == &ohci_device_bulk_methods) { 1650 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 1651 } 1652 if (methods == &ohci_device_ctrl_methods) { 1653 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 1654 } 1655 if (methods == &ohci_device_intr_methods) { 1656 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 1657 } 1658 if (methods == &ohci_device_isoc_methods) { 1659 OHCI_REMOVE_QH(ed, sc->sc_isoc_p_last); 1660 } 1661 xfer->td_transfer_first = NULL; 1662 xfer->td_transfer_last = NULL; 1663 1664 /* dequeue transfer and start next transfer */ 1665 usb2_transfer_done(xfer, error); 1666} 1667 1668/*------------------------------------------------------------------------* 1669 * ohci bulk support 1670 *------------------------------------------------------------------------*/ 1671static void 1672ohci_device_bulk_open(struct usb2_xfer *xfer) 1673{ 1674 return; 1675} 1676 1677static void 1678ohci_device_bulk_close(struct usb2_xfer *xfer) 1679{ 1680 ohci_device_done(xfer, USB_ERR_CANCELLED); 1681} 1682 1683static void 1684ohci_device_bulk_enter(struct usb2_xfer *xfer) 1685{ 1686 return; 1687} 1688 1689static void 1690ohci_device_bulk_start(struct usb2_xfer *xfer) 1691{ 1692 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1693 1694 /* setup TD's and QH */ 1695 ohci_setup_standard_chain(xfer, &sc->sc_bulk_p_last); 1696 1697 /* put transfer on interrupt queue */ 1698 ohci_transfer_intr_enqueue(xfer); 1699} 1700 1701struct usb2_pipe_methods ohci_device_bulk_methods = 1702{ 1703 .open = ohci_device_bulk_open, 1704 .close = ohci_device_bulk_close, 1705 .enter = ohci_device_bulk_enter, 1706 .start = ohci_device_bulk_start, 1707 .enter_is_cancelable = 1, 1708 .start_is_cancelable = 1, 1709}; 1710 1711/*------------------------------------------------------------------------* 1712 * ohci control support 1713 *------------------------------------------------------------------------*/ 1714static void 1715ohci_device_ctrl_open(struct usb2_xfer *xfer) 1716{ 1717 return; 1718} 1719 1720static void 1721ohci_device_ctrl_close(struct usb2_xfer *xfer) 1722{ 1723 ohci_device_done(xfer, USB_ERR_CANCELLED); 1724} 1725 1726static void 1727ohci_device_ctrl_enter(struct usb2_xfer *xfer) 1728{ 1729 return; 1730} 1731 1732static void 1733ohci_device_ctrl_start(struct usb2_xfer *xfer) 1734{ 1735 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1736 1737 /* setup TD's and QH */ 1738 ohci_setup_standard_chain(xfer, &sc->sc_ctrl_p_last); 1739 1740 /* put transfer on interrupt queue */ 1741 ohci_transfer_intr_enqueue(xfer); 1742} 1743 1744struct usb2_pipe_methods ohci_device_ctrl_methods = 1745{ 1746 .open = ohci_device_ctrl_open, 1747 .close = ohci_device_ctrl_close, 1748 .enter = ohci_device_ctrl_enter, 1749 .start = ohci_device_ctrl_start, 1750 .enter_is_cancelable = 1, 1751 .start_is_cancelable = 1, 1752}; 1753 1754/*------------------------------------------------------------------------* 1755 * ohci interrupt support 1756 *------------------------------------------------------------------------*/ 1757static void 1758ohci_device_intr_open(struct usb2_xfer *xfer) 1759{ 1760 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1761 uint16_t best; 1762 uint16_t bit; 1763 uint16_t x; 1764 1765 best = 0; 1766 bit = OHCI_NO_EDS / 2; 1767 while (bit) { 1768 if (xfer->interval >= bit) { 1769 x = bit; 1770 best = bit; 1771 while (x & bit) { 1772 if (sc->sc_intr_stat[x] < 1773 sc->sc_intr_stat[best]) { 1774 best = x; 1775 } 1776 x++; 1777 } 1778 break; 1779 } 1780 bit >>= 1; 1781 } 1782 1783 sc->sc_intr_stat[best]++; 1784 xfer->qh_pos = best; 1785 1786 DPRINTFN(3, "best=%d interval=%d\n", 1787 best, xfer->interval); 1788} 1789 1790static void 1791ohci_device_intr_close(struct usb2_xfer *xfer) 1792{ 1793 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1794 1795 sc->sc_intr_stat[xfer->qh_pos]--; 1796 1797 ohci_device_done(xfer, USB_ERR_CANCELLED); 1798} 1799 1800static void 1801ohci_device_intr_enter(struct usb2_xfer *xfer) 1802{ 1803 return; 1804} 1805 1806static void 1807ohci_device_intr_start(struct usb2_xfer *xfer) 1808{ 1809 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1810 1811 /* setup TD's and QH */ 1812 ohci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 1813 1814 /* put transfer on interrupt queue */ 1815 ohci_transfer_intr_enqueue(xfer); 1816} 1817 1818struct usb2_pipe_methods ohci_device_intr_methods = 1819{ 1820 .open = ohci_device_intr_open, 1821 .close = ohci_device_intr_close, 1822 .enter = ohci_device_intr_enter, 1823 .start = ohci_device_intr_start, 1824 .enter_is_cancelable = 1, 1825 .start_is_cancelable = 1, 1826}; 1827 1828/*------------------------------------------------------------------------* 1829 * ohci isochronous support 1830 *------------------------------------------------------------------------*/ 1831static void 1832ohci_device_isoc_open(struct usb2_xfer *xfer) 1833{ 1834 return; 1835} 1836 1837static void 1838ohci_device_isoc_close(struct usb2_xfer *xfer) 1839{ 1840 /**/ 1841 ohci_device_done(xfer, USB_ERR_CANCELLED); 1842} 1843 1844static void 1845ohci_device_isoc_enter(struct usb2_xfer *xfer) 1846{ 1847 struct usb2_page_search buf_res; 1848 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1849 struct ohci_hcca *hcca; 1850 uint32_t buf_offset; 1851 uint32_t nframes; 1852 uint32_t ed_flags; 1853 uint32_t *plen; 1854 uint16_t itd_offset[OHCI_ITD_NOFFSET]; 1855 uint16_t length; 1856 uint8_t ncur; 1857 ohci_itd_t *td; 1858 ohci_itd_t *td_last = NULL; 1859 ohci_ed_t *ed; 1860 1861 hcca = ohci_get_hcca(sc); 1862 1863 nframes = le32toh(hcca->hcca_frame_number); 1864 1865 DPRINTFN(6, "xfer=%p isoc_next=%u nframes=%u hcca_fn=%u\n", 1866 xfer, xfer->pipe->isoc_next, xfer->nframes, nframes); 1867 1868 if ((xfer->pipe->is_synced == 0) || 1869 (((nframes - xfer->pipe->isoc_next) & 0xFFFF) < xfer->nframes) || 1870 (((xfer->pipe->isoc_next - nframes) & 0xFFFF) >= 128)) { 1871 /* 1872 * If there is data underflow or the pipe queue is empty we 1873 * schedule the transfer a few frames ahead of the current 1874 * frame position. Else two isochronous transfers might 1875 * overlap. 1876 */ 1877 xfer->pipe->isoc_next = (nframes + 3) & 0xFFFF; 1878 xfer->pipe->is_synced = 1; 1879 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 1880 } 1881 /* 1882 * compute how many milliseconds the insertion is ahead of the 1883 * current frame position: 1884 */ 1885 buf_offset = ((xfer->pipe->isoc_next - nframes) & 0xFFFF); 1886 1887 /* 1888 * pre-compute when the isochronous transfer will be finished: 1889 */ 1890 xfer->isoc_time_complete = 1891 (usb2_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 1892 xfer->nframes); 1893 1894 /* get the real number of frames */ 1895 1896 nframes = xfer->nframes; 1897 1898 buf_offset = 0; 1899 1900 plen = xfer->frlengths; 1901 1902 /* toggle the DMA set we are using */ 1903 xfer->flags_int.curr_dma_set ^= 1; 1904 1905 /* get next DMA set */ 1906 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1907 1908 xfer->td_transfer_first = td; 1909 1910 ncur = 0; 1911 length = 0; 1912 1913 while (nframes--) { 1914 if (td == NULL) { 1915 panic("%s:%d: out of TD's\n", 1916 __FUNCTION__, __LINE__); 1917 } 1918 itd_offset[ncur] = length; 1919 buf_offset += *plen; 1920 length += *plen; 1921 plen++; 1922 ncur++; 1923 1924 if ( /* check if the ITD is full */ 1925 (ncur == OHCI_ITD_NOFFSET) || 1926 /* check if we have put more than 4K into the ITD */ 1927 (length & 0xF000) || 1928 /* check if it is the last frame */ 1929 (nframes == 0)) { 1930 1931 /* fill current ITD */ 1932 td->itd_flags = htole32( 1933 OHCI_ITD_NOCC | 1934 OHCI_ITD_SET_SF(xfer->pipe->isoc_next) | 1935 OHCI_ITD_NOINTR | 1936 OHCI_ITD_SET_FC(ncur)); 1937 1938 td->frames = ncur; 1939 xfer->pipe->isoc_next += ncur; 1940 1941 if (length == 0) { 1942 /* all zero */ 1943 td->itd_bp0 = 0; 1944 td->itd_be = ~0; 1945 1946 while (ncur--) { 1947 td->itd_offset[ncur] = 1948 htole16(OHCI_ITD_MK_OFFS(0)); 1949 } 1950 } else { 1951 usb2_get_page(xfer->frbuffers, buf_offset - length, &buf_res); 1952 length = OHCI_PAGE_MASK(buf_res.physaddr); 1953 buf_res.physaddr = 1954 OHCI_PAGE(buf_res.physaddr); 1955 td->itd_bp0 = htole32(buf_res.physaddr); 1956 usb2_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 1957 td->itd_be = htole32(buf_res.physaddr); 1958 1959 while (ncur--) { 1960 itd_offset[ncur] += length; 1961 itd_offset[ncur] = 1962 OHCI_ITD_MK_OFFS(itd_offset[ncur]); 1963 td->itd_offset[ncur] = 1964 htole16(itd_offset[ncur]); 1965 } 1966 } 1967 ncur = 0; 1968 length = 0; 1969 td_last = td; 1970 td = td->obj_next; 1971 1972 if (td) { 1973 /* link the last TD with the next one */ 1974 td_last->itd_next = td->itd_self; 1975 } 1976 usb2_pc_cpu_flush(td_last->page_cache); 1977 } 1978 } 1979 1980 /* update the last TD */ 1981 td_last->itd_flags &= ~htole32(OHCI_ITD_NOINTR); 1982 td_last->itd_flags |= htole32(OHCI_ITD_SET_DI(0)); 1983 td_last->itd_next = 0; 1984 1985 usb2_pc_cpu_flush(td_last->page_cache); 1986 1987 xfer->td_transfer_last = td_last; 1988 1989#if USB_DEBUG 1990 if (ohcidebug > 8) { 1991 DPRINTF("data before transfer:\n"); 1992 ohci_dump_itds(xfer->td_transfer_first); 1993 } 1994#endif 1995 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1996 1997 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) 1998 ed_flags = (OHCI_ED_DIR_IN | OHCI_ED_FORMAT_ISO); 1999 else 2000 ed_flags = (OHCI_ED_DIR_OUT | OHCI_ED_FORMAT_ISO); 2001 2002 ed_flags |= (OHCI_ED_SET_FA(xfer->address) | 2003 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpoint)) | 2004 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 2005 2006 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 2007 ed_flags |= OHCI_ED_SPEED; 2008 } 2009 ed->ed_flags = htole32(ed_flags); 2010 2011 td = xfer->td_transfer_first; 2012 2013 ed->ed_headp = td->itd_self; 2014 2015 /* isochronous transfers are not affected by suspend / resume */ 2016 /* the append function will flush the endpoint descriptor */ 2017 2018 OHCI_APPEND_QH(ed, sc->sc_isoc_p_last); 2019} 2020 2021static void 2022ohci_device_isoc_start(struct usb2_xfer *xfer) 2023{ 2024 /* put transfer on interrupt queue */ 2025 ohci_transfer_intr_enqueue(xfer); 2026} 2027 2028struct usb2_pipe_methods ohci_device_isoc_methods = 2029{ 2030 .open = ohci_device_isoc_open, 2031 .close = ohci_device_isoc_close, 2032 .enter = ohci_device_isoc_enter, 2033 .start = ohci_device_isoc_start, 2034 .enter_is_cancelable = 1, 2035 .start_is_cancelable = 1, 2036}; 2037 2038/*------------------------------------------------------------------------* 2039 * ohci root control support 2040 *------------------------------------------------------------------------* 2041 * simulate a hardware hub by handling 2042 * all the necessary requests 2043 *------------------------------------------------------------------------*/ 2044 2045static void 2046ohci_root_ctrl_open(struct usb2_xfer *xfer) 2047{ 2048 return; 2049} 2050 2051static void 2052ohci_root_ctrl_close(struct usb2_xfer *xfer) 2053{ 2054 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 2055 2056 if (sc->sc_root_ctrl.xfer == xfer) { 2057 sc->sc_root_ctrl.xfer = NULL; 2058 } 2059 ohci_device_done(xfer, USB_ERR_CANCELLED); 2060} 2061 2062/* data structures and routines 2063 * to emulate the root hub: 2064 */ 2065static const 2066struct usb2_device_descriptor ohci_devd = 2067{ 2068 sizeof(struct usb2_device_descriptor), 2069 UDESC_DEVICE, /* type */ 2070 {0x00, 0x01}, /* USB version */ 2071 UDCLASS_HUB, /* class */ 2072 UDSUBCLASS_HUB, /* subclass */ 2073 UDPROTO_FSHUB, /* protocol */ 2074 64, /* max packet */ 2075 {0}, {0}, {0x00, 0x01}, /* device id */ 2076 1, 2, 0, /* string indicies */ 2077 1 /* # of configurations */ 2078}; 2079 2080static const 2081struct ohci_config_desc ohci_confd = 2082{ 2083 .confd = { 2084 .bLength = sizeof(struct usb2_config_descriptor), 2085 .bDescriptorType = UDESC_CONFIG, 2086 .wTotalLength[0] = sizeof(ohci_confd), 2087 .bNumInterface = 1, 2088 .bConfigurationValue = 1, 2089 .iConfiguration = 0, 2090 .bmAttributes = UC_SELF_POWERED, 2091 .bMaxPower = 0, /* max power */ 2092 }, 2093 2094 .ifcd = { 2095 .bLength = sizeof(struct usb2_interface_descriptor), 2096 .bDescriptorType = UDESC_INTERFACE, 2097 .bNumEndpoints = 1, 2098 .bInterfaceClass = UICLASS_HUB, 2099 .bInterfaceSubClass = UISUBCLASS_HUB, 2100 .bInterfaceProtocol = UIPROTO_FSHUB, 2101 }, 2102 2103 .endpd = { 2104 .bLength = sizeof(struct usb2_endpoint_descriptor), 2105 .bDescriptorType = UDESC_ENDPOINT, 2106 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2107 .bmAttributes = UE_INTERRUPT, 2108 .wMaxPacketSize[0] = 32,/* max packet (255 ports) */ 2109 .bInterval = 255, 2110 }, 2111}; 2112 2113static const 2114struct usb2_hub_descriptor ohci_hubd = 2115{ 2116 0, /* dynamic length */ 2117 UDESC_HUB, 2118 0, 2119 {0, 0}, 2120 0, 2121 0, 2122 {0}, 2123}; 2124 2125static void 2126ohci_root_ctrl_enter(struct usb2_xfer *xfer) 2127{ 2128 return; 2129} 2130 2131static void 2132ohci_root_ctrl_start(struct usb2_xfer *xfer) 2133{ 2134 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 2135 2136 sc->sc_root_ctrl.xfer = xfer; 2137 2138 usb2_bus_roothub_exec(xfer->xroot->bus); 2139} 2140 2141static void 2142ohci_root_ctrl_task(struct usb2_bus *bus) 2143{ 2144 ohci_root_ctrl_poll(OHCI_BUS2SC(bus)); 2145} 2146 2147static void 2148ohci_root_ctrl_done(struct usb2_xfer *xfer, 2149 struct usb2_sw_transfer *std) 2150{ 2151 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 2152 char *ptr; 2153 uint32_t port; 2154 uint32_t v; 2155 uint16_t value; 2156 uint16_t index; 2157 uint8_t l; 2158 2159 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2160 2161 if (std->state != USB_SW_TR_SETUP) { 2162 if (std->state == USB_SW_TR_PRE_CALLBACK) { 2163 /* transfer transferred */ 2164 ohci_device_done(xfer, std->err); 2165 } 2166 goto done; 2167 } 2168 /* buffer reset */ 2169 std->ptr = sc->sc_hub_desc.temp; 2170 std->len = 0; 2171 2172 value = UGETW(std->req.wValue); 2173 index = UGETW(std->req.wIndex); 2174 2175 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2176 "wValue=0x%04x wIndex=0x%04x\n", 2177 std->req.bmRequestType, std->req.bRequest, 2178 UGETW(std->req.wLength), value, index); 2179 2180#define C(x,y) ((x) | ((y) << 8)) 2181 switch (C(std->req.bRequest, std->req.bmRequestType)) { 2182 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2183 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2184 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2185 /* 2186 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2187 * for the integrated root hub. 2188 */ 2189 break; 2190 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2191 std->len = 1; 2192 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2193 break; 2194 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2195 switch (value >> 8) { 2196 case UDESC_DEVICE: 2197 if ((value & 0xff) != 0) { 2198 std->err = USB_ERR_IOERROR; 2199 goto done; 2200 } 2201 std->len = sizeof(ohci_devd); 2202 sc->sc_hub_desc.devd = ohci_devd; 2203 break; 2204 2205 case UDESC_CONFIG: 2206 if ((value & 0xff) != 0) { 2207 std->err = USB_ERR_IOERROR; 2208 goto done; 2209 } 2210 std->len = sizeof(ohci_confd); 2211 std->ptr = USB_ADD_BYTES(&ohci_confd, 0); 2212 break; 2213 2214 case UDESC_STRING: 2215 switch (value & 0xff) { 2216 case 0: /* Language table */ 2217 ptr = "\001"; 2218 break; 2219 2220 case 1: /* Vendor */ 2221 ptr = sc->sc_vendor; 2222 break; 2223 2224 case 2: /* Product */ 2225 ptr = "OHCI root HUB"; 2226 break; 2227 2228 default: 2229 ptr = ""; 2230 break; 2231 } 2232 2233 std->len = usb2_make_str_desc 2234 (sc->sc_hub_desc.temp, 2235 sizeof(sc->sc_hub_desc.temp), 2236 ptr); 2237 break; 2238 2239 default: 2240 std->err = USB_ERR_IOERROR; 2241 goto done; 2242 } 2243 break; 2244 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2245 std->len = 1; 2246 sc->sc_hub_desc.temp[0] = 0; 2247 break; 2248 case C(UR_GET_STATUS, UT_READ_DEVICE): 2249 std->len = 2; 2250 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2251 break; 2252 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2253 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2254 std->len = 2; 2255 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2256 break; 2257 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2258 if (value >= OHCI_MAX_DEVICES) { 2259 std->err = USB_ERR_IOERROR; 2260 goto done; 2261 } 2262 sc->sc_addr = value; 2263 break; 2264 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2265 if ((value != 0) && (value != 1)) { 2266 std->err = USB_ERR_IOERROR; 2267 goto done; 2268 } 2269 sc->sc_conf = value; 2270 break; 2271 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2272 break; 2273 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2274 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2275 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2276 std->err = USB_ERR_IOERROR; 2277 goto done; 2278 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2279 break; 2280 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2281 break; 2282 /* Hub requests */ 2283 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2284 break; 2285 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2286 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE " 2287 "port=%d feature=%d\n", 2288 index, value); 2289 if ((index < 1) || 2290 (index > sc->sc_noport)) { 2291 std->err = USB_ERR_IOERROR; 2292 goto done; 2293 } 2294 port = OHCI_RH_PORT_STATUS(index); 2295 switch (value) { 2296 case UHF_PORT_ENABLE: 2297 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2298 break; 2299 case UHF_PORT_SUSPEND: 2300 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2301 break; 2302 case UHF_PORT_POWER: 2303 /* Yes, writing to the LOW_SPEED bit clears power. */ 2304 OWRITE4(sc, port, UPS_LOW_SPEED); 2305 break; 2306 case UHF_C_PORT_CONNECTION: 2307 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2308 break; 2309 case UHF_C_PORT_ENABLE: 2310 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2311 break; 2312 case UHF_C_PORT_SUSPEND: 2313 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2314 break; 2315 case UHF_C_PORT_OVER_CURRENT: 2316 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2317 break; 2318 case UHF_C_PORT_RESET: 2319 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2320 break; 2321 default: 2322 std->err = USB_ERR_IOERROR; 2323 goto done; 2324 } 2325 switch (value) { 2326 case UHF_C_PORT_CONNECTION: 2327 case UHF_C_PORT_ENABLE: 2328 case UHF_C_PORT_SUSPEND: 2329 case UHF_C_PORT_OVER_CURRENT: 2330 case UHF_C_PORT_RESET: 2331 /* enable RHSC interrupt if condition is cleared. */ 2332 if ((OREAD4(sc, port) >> 16) == 0) 2333 ohci_rhsc_enable(sc); 2334 break; 2335 default: 2336 break; 2337 } 2338 break; 2339 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2340 if ((value & 0xff) != 0) { 2341 std->err = USB_ERR_IOERROR; 2342 goto done; 2343 } 2344 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2345 2346 sc->sc_hub_desc.hubd = ohci_hubd; 2347 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 2348 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, 2349 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2350 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2351 /* XXX overcurrent */ 2352 ); 2353 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2354 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2355 2356 for (l = 0; l < sc->sc_noport; l++) { 2357 if (v & 1) { 2358 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] |= (1 << (l % 8)); 2359 } 2360 v >>= 1; 2361 } 2362 sc->sc_hub_desc.hubd.bDescLength = 2363 8 + ((sc->sc_noport + 7) / 8); 2364 std->len = sc->sc_hub_desc.hubd.bDescLength; 2365 break; 2366 2367 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2368 std->len = 16; 2369 bzero(sc->sc_hub_desc.temp, 16); 2370 break; 2371 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2372 DPRINTFN(9, "get port status i=%d\n", 2373 index); 2374 if ((index < 1) || 2375 (index > sc->sc_noport)) { 2376 std->err = USB_ERR_IOERROR; 2377 goto done; 2378 } 2379 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2380 DPRINTFN(9, "port status=0x%04x\n", v); 2381 USETW(sc->sc_hub_desc.ps.wPortStatus, v); 2382 USETW(sc->sc_hub_desc.ps.wPortChange, v >> 16); 2383 std->len = sizeof(sc->sc_hub_desc.ps); 2384 break; 2385 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2386 std->err = USB_ERR_IOERROR; 2387 goto done; 2388 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2389 break; 2390 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2391 if ((index < 1) || 2392 (index > sc->sc_noport)) { 2393 std->err = USB_ERR_IOERROR; 2394 goto done; 2395 } 2396 port = OHCI_RH_PORT_STATUS(index); 2397 switch (value) { 2398 case UHF_PORT_ENABLE: 2399 OWRITE4(sc, port, UPS_PORT_ENABLED); 2400 break; 2401 case UHF_PORT_SUSPEND: 2402 OWRITE4(sc, port, UPS_SUSPEND); 2403 break; 2404 case UHF_PORT_RESET: 2405 DPRINTFN(6, "reset port %d\n", index); 2406 OWRITE4(sc, port, UPS_RESET); 2407 for (v = 0;; v++) { 2408 if (v < 12) { 2409 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 2410 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY)); 2411 2412 if ((OREAD4(sc, port) & UPS_RESET) == 0) { 2413 break; 2414 } 2415 } else { 2416 std->err = USB_ERR_TIMEOUT; 2417 goto done; 2418 } 2419 } 2420 DPRINTFN(9, "ohci port %d reset, status = 0x%04x\n", 2421 index, OREAD4(sc, port)); 2422 break; 2423 case UHF_PORT_POWER: 2424 DPRINTFN(3, "set port power %d\n", index); 2425 OWRITE4(sc, port, UPS_PORT_POWER); 2426 break; 2427 default: 2428 std->err = USB_ERR_IOERROR; 2429 goto done; 2430 } 2431 break; 2432 default: 2433 std->err = USB_ERR_IOERROR; 2434 goto done; 2435 } 2436done: 2437 return; 2438} 2439 2440static void 2441ohci_root_ctrl_poll(struct ohci_softc *sc) 2442{ 2443 usb2_sw_transfer(&sc->sc_root_ctrl, 2444 &ohci_root_ctrl_done); 2445} 2446 2447struct usb2_pipe_methods ohci_root_ctrl_methods = 2448{ 2449 .open = ohci_root_ctrl_open, 2450 .close = ohci_root_ctrl_close, 2451 .enter = ohci_root_ctrl_enter, 2452 .start = ohci_root_ctrl_start, 2453 .enter_is_cancelable = 1, 2454 .start_is_cancelable = 0, 2455}; 2456 2457/*------------------------------------------------------------------------* 2458 * ohci root interrupt support 2459 *------------------------------------------------------------------------*/ 2460static void 2461ohci_root_intr_open(struct usb2_xfer *xfer) 2462{ 2463 return; 2464} 2465 2466static void 2467ohci_root_intr_close(struct usb2_xfer *xfer) 2468{ 2469 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 2470 2471 if (sc->sc_root_intr.xfer == xfer) { 2472 sc->sc_root_intr.xfer = NULL; 2473 } 2474 ohci_device_done(xfer, USB_ERR_CANCELLED); 2475} 2476 2477static void 2478ohci_root_intr_enter(struct usb2_xfer *xfer) 2479{ 2480 return; 2481} 2482 2483static void 2484ohci_root_intr_start(struct usb2_xfer *xfer) 2485{ 2486 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 2487 2488 sc->sc_root_intr.xfer = xfer; 2489} 2490 2491struct usb2_pipe_methods ohci_root_intr_methods = 2492{ 2493 .open = ohci_root_intr_open, 2494 .close = ohci_root_intr_close, 2495 .enter = ohci_root_intr_enter, 2496 .start = ohci_root_intr_start, 2497 .enter_is_cancelable = 1, 2498 .start_is_cancelable = 1, 2499}; 2500 2501static void 2502ohci_xfer_setup(struct usb2_setup_params *parm) 2503{ 2504 struct usb2_page_search page_info; 2505 struct usb2_page_cache *pc; 2506 ohci_softc_t *sc; 2507 struct usb2_xfer *xfer; 2508 void *last_obj; 2509 uint32_t ntd; 2510 uint32_t nitd; 2511 uint32_t nqh; 2512 uint32_t n; 2513 2514 sc = OHCI_BUS2SC(parm->udev->bus); 2515 xfer = parm->curr_xfer; 2516 2517 parm->hc_max_packet_size = 0x500; 2518 parm->hc_max_packet_count = 1; 2519 parm->hc_max_frame_size = OHCI_PAGE_SIZE; 2520 2521 /* 2522 * calculate ntd and nqh 2523 */ 2524 if (parm->methods == &ohci_device_ctrl_methods) { 2525 xfer->flags_int.bdma_enable = 1; 2526 2527 usb2_transfer_setup_sub(parm); 2528 2529 nitd = 0; 2530 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2531 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 2532 nqh = 1; 2533 2534 } else if (parm->methods == &ohci_device_bulk_methods) { 2535 xfer->flags_int.bdma_enable = 1; 2536 2537 usb2_transfer_setup_sub(parm); 2538 2539 nitd = 0; 2540 ntd = ((2 * xfer->nframes) 2541 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 2542 nqh = 1; 2543 2544 } else if (parm->methods == &ohci_device_intr_methods) { 2545 xfer->flags_int.bdma_enable = 1; 2546 2547 usb2_transfer_setup_sub(parm); 2548 2549 nitd = 0; 2550 ntd = ((2 * xfer->nframes) 2551 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 2552 nqh = 1; 2553 2554 } else if (parm->methods == &ohci_device_isoc_methods) { 2555 xfer->flags_int.bdma_enable = 1; 2556 2557 usb2_transfer_setup_sub(parm); 2558 2559 nitd = ((xfer->max_data_length / OHCI_PAGE_SIZE) + 2560 ((xfer->nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET) + 2561 1 /* EXTRA */ ); 2562 ntd = 0; 2563 nqh = 1; 2564 2565 } else { 2566 2567 usb2_transfer_setup_sub(parm); 2568 2569 nitd = 0; 2570 ntd = 0; 2571 nqh = 0; 2572 } 2573 2574alloc_dma_set: 2575 2576 if (parm->err) { 2577 return; 2578 } 2579 last_obj = NULL; 2580 2581 if (usb2_transfer_setup_sub_malloc( 2582 parm, &pc, sizeof(ohci_td_t), 2583 OHCI_TD_ALIGN, ntd)) { 2584 parm->err = USB_ERR_NOMEM; 2585 return; 2586 } 2587 if (parm->buf) { 2588 for (n = 0; n != ntd; n++) { 2589 ohci_td_t *td; 2590 2591 usb2_get_page(pc + n, 0, &page_info); 2592 2593 td = page_info.buffer; 2594 2595 /* init TD */ 2596 td->td_self = htole32(page_info.physaddr); 2597 td->obj_next = last_obj; 2598 td->page_cache = pc + n; 2599 2600 last_obj = td; 2601 2602 usb2_pc_cpu_flush(pc + n); 2603 } 2604 } 2605 if (usb2_transfer_setup_sub_malloc( 2606 parm, &pc, sizeof(ohci_itd_t), 2607 OHCI_ITD_ALIGN, nitd)) { 2608 parm->err = USB_ERR_NOMEM; 2609 return; 2610 } 2611 if (parm->buf) { 2612 for (n = 0; n != nitd; n++) { 2613 ohci_itd_t *itd; 2614 2615 usb2_get_page(pc + n, 0, &page_info); 2616 2617 itd = page_info.buffer; 2618 2619 /* init TD */ 2620 itd->itd_self = htole32(page_info.physaddr); 2621 itd->obj_next = last_obj; 2622 itd->page_cache = pc + n; 2623 2624 last_obj = itd; 2625 2626 usb2_pc_cpu_flush(pc + n); 2627 } 2628 } 2629 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2630 2631 last_obj = NULL; 2632 2633 if (usb2_transfer_setup_sub_malloc( 2634 parm, &pc, sizeof(ohci_ed_t), 2635 OHCI_ED_ALIGN, nqh)) { 2636 parm->err = USB_ERR_NOMEM; 2637 return; 2638 } 2639 if (parm->buf) { 2640 for (n = 0; n != nqh; n++) { 2641 ohci_ed_t *ed; 2642 2643 usb2_get_page(pc + n, 0, &page_info); 2644 2645 ed = page_info.buffer; 2646 2647 /* init QH */ 2648 ed->ed_self = htole32(page_info.physaddr); 2649 ed->obj_next = last_obj; 2650 ed->page_cache = pc + n; 2651 2652 last_obj = ed; 2653 2654 usb2_pc_cpu_flush(pc + n); 2655 } 2656 } 2657 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 2658 2659 if (!xfer->flags_int.curr_dma_set) { 2660 xfer->flags_int.curr_dma_set = 1; 2661 goto alloc_dma_set; 2662 } 2663} 2664 2665static void 2666ohci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2667 struct usb2_pipe *pipe) 2668{ 2669 ohci_softc_t *sc = OHCI_BUS2SC(udev->bus); 2670 2671 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2672 pipe, udev->address, 2673 edesc->bEndpointAddress, udev->flags.usb2_mode, 2674 sc->sc_addr); 2675 2676 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2677 /* not supported */ 2678 return; 2679 } 2680 if (udev->device_index == sc->sc_addr) { 2681 switch (edesc->bEndpointAddress) { 2682 case USB_CONTROL_ENDPOINT: 2683 pipe->methods = &ohci_root_ctrl_methods; 2684 break; 2685 case UE_DIR_IN | OHCI_INTR_ENDPT: 2686 pipe->methods = &ohci_root_intr_methods; 2687 break; 2688 default: 2689 /* do nothing */ 2690 break; 2691 } 2692 } else { 2693 switch (edesc->bmAttributes & UE_XFERTYPE) { 2694 case UE_CONTROL: 2695 pipe->methods = &ohci_device_ctrl_methods; 2696 break; 2697 case UE_INTERRUPT: 2698 pipe->methods = &ohci_device_intr_methods; 2699 break; 2700 case UE_ISOCHRONOUS: 2701 if (udev->speed == USB_SPEED_FULL) { 2702 pipe->methods = &ohci_device_isoc_methods; 2703 } 2704 break; 2705 case UE_BULK: 2706 if (udev->speed != USB_SPEED_LOW) { 2707 pipe->methods = &ohci_device_bulk_methods; 2708 } 2709 break; 2710 default: 2711 /* do nothing */ 2712 break; 2713 } 2714 } 2715} 2716 2717static void 2718ohci_xfer_unsetup(struct usb2_xfer *xfer) 2719{ 2720 return; 2721} 2722 2723static void 2724ohci_get_dma_delay(struct usb2_bus *bus, uint32_t *pus) 2725{ 2726 /* 2727 * Wait until hardware has finished any possible use of the 2728 * transfer descriptor(s) and QH 2729 */ 2730 *pus = (1125); /* microseconds */ 2731} 2732 2733static void 2734ohci_device_resume(struct usb2_device *udev) 2735{ 2736 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2737 struct usb2_xfer *xfer; 2738 struct usb2_pipe_methods *methods; 2739 ohci_ed_t *ed; 2740 2741 DPRINTF("\n"); 2742 2743 USB_BUS_LOCK(udev->bus); 2744 2745 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2746 2747 if (xfer->xroot->udev == udev) { 2748 2749 methods = xfer->pipe->methods; 2750 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2751 2752 if (methods == &ohci_device_bulk_methods) { 2753 OHCI_APPEND_QH(ed, sc->sc_bulk_p_last); 2754 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2755 } 2756 if (methods == &ohci_device_ctrl_methods) { 2757 OHCI_APPEND_QH(ed, sc->sc_ctrl_p_last); 2758 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2759 } 2760 if (methods == &ohci_device_intr_methods) { 2761 OHCI_APPEND_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2762 } 2763 } 2764 } 2765 2766 USB_BUS_UNLOCK(udev->bus); 2767 2768 return; 2769} 2770 2771static void 2772ohci_device_suspend(struct usb2_device *udev) 2773{ 2774 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2775 struct usb2_xfer *xfer; 2776 struct usb2_pipe_methods *methods; 2777 ohci_ed_t *ed; 2778 2779 DPRINTF("\n"); 2780 2781 USB_BUS_LOCK(udev->bus); 2782 2783 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2784 2785 if (xfer->xroot->udev == udev) { 2786 2787 methods = xfer->pipe->methods; 2788 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2789 2790 if (methods == &ohci_device_bulk_methods) { 2791 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 2792 } 2793 if (methods == &ohci_device_ctrl_methods) { 2794 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 2795 } 2796 if (methods == &ohci_device_intr_methods) { 2797 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2798 } 2799 } 2800 } 2801 2802 USB_BUS_UNLOCK(udev->bus); 2803 2804 return; 2805} 2806 2807static void 2808ohci_set_hw_power(struct usb2_bus *bus) 2809{ 2810 struct ohci_softc *sc = OHCI_BUS2SC(bus); 2811 uint32_t temp; 2812 uint32_t flags; 2813 2814 DPRINTF("\n"); 2815 2816 USB_BUS_LOCK(bus); 2817 2818 flags = bus->hw_power_state; 2819 2820 temp = OREAD4(sc, OHCI_CONTROL); 2821 temp &= ~(OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE); 2822 2823 if (flags & USB_HW_POWER_CONTROL) 2824 temp |= OHCI_CLE; 2825 2826 if (flags & USB_HW_POWER_BULK) 2827 temp |= OHCI_BLE; 2828 2829 if (flags & USB_HW_POWER_INTERRUPT) 2830 temp |= OHCI_PLE; 2831 2832 if (flags & USB_HW_POWER_ISOC) 2833 temp |= OHCI_IE | OHCI_PLE; 2834 2835 OWRITE4(sc, OHCI_CONTROL, temp); 2836 2837 USB_BUS_UNLOCK(bus); 2838 2839 return; 2840} 2841 2842struct usb2_bus_methods ohci_bus_methods = 2843{ 2844 .pipe_init = ohci_pipe_init, 2845 .xfer_setup = ohci_xfer_setup, 2846 .xfer_unsetup = ohci_xfer_unsetup, 2847 .get_dma_delay = ohci_get_dma_delay, 2848 .device_resume = ohci_device_resume, 2849 .device_suspend = ohci_device_suspend, 2850 .set_hw_power = ohci_set_hw_power, 2851 .roothub_exec = ohci_root_ctrl_task, 2852}; 2853