ohci.c revision 188942
1/*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/usb/controller/ohci.c 188942 2009-02-23 18:31:00Z thompsa $"); 30 31/* 32 * USB Open Host Controller driver. 33 * 34 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 35 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 36 */ 37 38#include <dev/usb/usb.h> 39#include <dev/usb/usb_mfunc.h> 40#include <dev/usb/usb_error.h> 41#include <dev/usb/usb_defs.h> 42 43#define USB_DEBUG_VAR ohcidebug 44 45#include <dev/usb/usb_core.h> 46#include <dev/usb/usb_debug.h> 47#include <dev/usb/usb_busdma.h> 48#include <dev/usb/usb_process.h> 49#include <dev/usb/usb_sw_transfer.h> 50#include <dev/usb/usb_transfer.h> 51#include <dev/usb/usb_device.h> 52#include <dev/usb/usb_hub.h> 53#include <dev/usb/usb_util.h> 54 55#include <dev/usb/usb_controller.h> 56#include <dev/usb/usb_bus.h> 57#include <dev/usb/controller/ohci.h> 58 59#define OHCI_BUS2SC(bus) ((ohci_softc_t *)(((uint8_t *)(bus)) - \ 60 USB_P2U(&(((ohci_softc_t *)0)->sc_bus)))) 61 62#if USB_DEBUG 63static int ohcidebug = 0; 64 65SYSCTL_NODE(_hw_usb2, OID_AUTO, ohci, CTLFLAG_RW, 0, "USB ohci"); 66SYSCTL_INT(_hw_usb2_ohci, OID_AUTO, debug, CTLFLAG_RW, 67 &ohcidebug, 0, "ohci debug level"); 68static void ohci_dumpregs(ohci_softc_t *); 69static void ohci_dump_tds(ohci_td_t *); 70static uint8_t ohci_dump_td(ohci_td_t *); 71static void ohci_dump_ed(ohci_ed_t *); 72static uint8_t ohci_dump_itd(ohci_itd_t *); 73static void ohci_dump_itds(ohci_itd_t *); 74 75#endif 76 77#define OBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 78 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 79#define OWRITE1(sc, r, x) \ 80 do { OBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 81#define OWRITE2(sc, r, x) \ 82 do { OBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 83#define OWRITE4(sc, r, x) \ 84 do { OBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 85#define OREAD1(sc, r) (OBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 86#define OREAD2(sc, r) (OBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 87#define OREAD4(sc, r) (OBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 88 89#define OHCI_INTR_ENDPT 1 90 91extern struct usb2_bus_methods ohci_bus_methods; 92extern struct usb2_pipe_methods ohci_device_bulk_methods; 93extern struct usb2_pipe_methods ohci_device_ctrl_methods; 94extern struct usb2_pipe_methods ohci_device_intr_methods; 95extern struct usb2_pipe_methods ohci_device_isoc_methods; 96extern struct usb2_pipe_methods ohci_root_ctrl_methods; 97extern struct usb2_pipe_methods ohci_root_intr_methods; 98 99static void ohci_root_ctrl_poll(struct ohci_softc *sc); 100static void ohci_do_poll(struct usb2_bus *bus); 101static void ohci_device_done(struct usb2_xfer *xfer, usb2_error_t error); 102 103static usb2_sw_transfer_func_t ohci_root_intr_done; 104static usb2_sw_transfer_func_t ohci_root_ctrl_done; 105static void ohci_timeout(void *arg); 106static uint8_t ohci_check_transfer(struct usb2_xfer *xfer); 107 108struct ohci_std_temp { 109 struct usb2_page_cache *pc; 110 ohci_td_t *td; 111 ohci_td_t *td_next; 112 uint32_t average; 113 uint32_t td_flags; 114 uint32_t len; 115 uint16_t max_frame_size; 116 uint8_t shortpkt; 117 uint8_t setup_alt_next; 118 uint8_t short_frames_ok; 119}; 120 121static struct ohci_hcca * 122ohci_get_hcca(ohci_softc_t *sc) 123{ 124 usb2_pc_cpu_invalidate(&sc->sc_hw.hcca_pc); 125 return (sc->sc_hcca_p); 126} 127 128void 129ohci_iterate_hw_softc(struct usb2_bus *bus, usb2_bus_mem_sub_cb_t *cb) 130{ 131 struct ohci_softc *sc = OHCI_BUS2SC(bus); 132 uint32_t i; 133 134 cb(bus, &sc->sc_hw.hcca_pc, &sc->sc_hw.hcca_pg, 135 sizeof(ohci_hcca_t), OHCI_HCCA_ALIGN); 136 137 cb(bus, &sc->sc_hw.ctrl_start_pc, &sc->sc_hw.ctrl_start_pg, 138 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 139 140 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 141 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 142 143 cb(bus, &sc->sc_hw.isoc_start_pc, &sc->sc_hw.isoc_start_pg, 144 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 145 146 for (i = 0; i != OHCI_NO_EDS; i++) { 147 cb(bus, sc->sc_hw.intr_start_pc + i, sc->sc_hw.intr_start_pg + i, 148 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 149 } 150} 151 152static usb2_error_t 153ohci_controller_init(ohci_softc_t *sc) 154{ 155 struct usb2_page_search buf_res; 156 uint32_t i; 157 uint32_t ctl; 158 uint32_t ival; 159 uint32_t hcr; 160 uint32_t fm; 161 uint32_t per; 162 uint32_t desca; 163 164 /* Determine in what context we are running. */ 165 ctl = OREAD4(sc, OHCI_CONTROL); 166 if (ctl & OHCI_IR) { 167 /* SMM active, request change */ 168 DPRINTF("SMM active, request owner change\n"); 169 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_OCR); 170 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 171 usb2_pause_mtx(NULL, hz / 1000); 172 ctl = OREAD4(sc, OHCI_CONTROL); 173 } 174 if (ctl & OHCI_IR) { 175 device_printf(sc->sc_bus.bdev, 176 "SMM does not respond, resetting\n"); 177 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 178 goto reset; 179 } 180 } else { 181 DPRINTF("cold started\n"); 182reset: 183 /* controller was cold started */ 184 usb2_pause_mtx(NULL, 185 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 186 } 187 188 /* 189 * This reset should not be necessary according to the OHCI spec, but 190 * without it some controllers do not start. 191 */ 192 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 193 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 194 195 usb2_pause_mtx(NULL, 196 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 197 198 /* we now own the host controller and the bus has been reset */ 199 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL)); 200 201 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 202 /* nominal time for a reset is 10 us */ 203 for (i = 0; i < 10; i++) { 204 DELAY(10); 205 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 206 if (!hcr) { 207 break; 208 } 209 } 210 if (hcr) { 211 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 212 return (USB_ERR_IOERROR); 213 } 214#if USB_DEBUG 215 if (ohcidebug > 15) { 216 ohci_dumpregs(sc); 217 } 218#endif 219 220 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 221 222 /* set up HC registers */ 223 usb2_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 224 OWRITE4(sc, OHCI_HCCA, buf_res.physaddr); 225 226 usb2_get_page(&sc->sc_hw.ctrl_start_pc, 0, &buf_res); 227 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, buf_res.physaddr); 228 229 usb2_get_page(&sc->sc_hw.bulk_start_pc, 0, &buf_res); 230 OWRITE4(sc, OHCI_BULK_HEAD_ED, buf_res.physaddr); 231 232 /* disable all interrupts and then switch on all desired interrupts */ 233 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 234 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 235 /* switch on desired functional features */ 236 ctl = OREAD4(sc, OHCI_CONTROL); 237 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 238 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 239 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL; 240 /* And finally start it! */ 241 OWRITE4(sc, OHCI_CONTROL, ctl); 242 243 /* 244 * The controller is now OPERATIONAL. Set a some final 245 * registers that should be set earlier, but that the 246 * controller ignores when in the SUSPEND state. 247 */ 248 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 249 fm |= OHCI_FSMPS(ival) | ival; 250 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 251 per = OHCI_PERIODIC(ival); /* 90% periodic */ 252 OWRITE4(sc, OHCI_PERIODIC_START, per); 253 254 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 255 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 256 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 257 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 258 usb2_pause_mtx(NULL, 259 USB_MS_TO_TICKS(OHCI_ENABLE_POWER_DELAY)); 260 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 261 262 /* 263 * The AMD756 requires a delay before re-reading the register, 264 * otherwise it will occasionally report 0 ports. 265 */ 266 sc->sc_noport = 0; 267 for (i = 0; (i < 10) && (sc->sc_noport == 0); i++) { 268 usb2_pause_mtx(NULL, 269 USB_MS_TO_TICKS(OHCI_READ_DESC_DELAY)); 270 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 271 } 272 273#if USB_DEBUG 274 if (ohcidebug > 5) { 275 ohci_dumpregs(sc); 276 } 277#endif 278 return (USB_ERR_NORMAL_COMPLETION); 279} 280 281static struct ohci_ed * 282ohci_init_ed(struct usb2_page_cache *pc) 283{ 284 struct usb2_page_search buf_res; 285 struct ohci_ed *ed; 286 287 usb2_get_page(pc, 0, &buf_res); 288 289 ed = buf_res.buffer; 290 291 ed->ed_self = htole32(buf_res.physaddr); 292 ed->ed_flags = htole32(OHCI_ED_SKIP); 293 ed->page_cache = pc; 294 295 return (ed); 296} 297 298usb2_error_t 299ohci_init(ohci_softc_t *sc) 300{ 301 struct usb2_page_search buf_res; 302 uint16_t i; 303 uint16_t bit; 304 uint16_t x; 305 uint16_t y; 306 307 DPRINTF("start\n"); 308 309 sc->sc_eintrs = OHCI_NORMAL_INTRS; 310 311 /* 312 * Setup all ED's 313 */ 314 315 sc->sc_ctrl_p_last = 316 ohci_init_ed(&sc->sc_hw.ctrl_start_pc); 317 318 sc->sc_bulk_p_last = 319 ohci_init_ed(&sc->sc_hw.bulk_start_pc); 320 321 sc->sc_isoc_p_last = 322 ohci_init_ed(&sc->sc_hw.isoc_start_pc); 323 324 for (i = 0; i != OHCI_NO_EDS; i++) { 325 sc->sc_intr_p_last[i] = 326 ohci_init_ed(sc->sc_hw.intr_start_pc + i); 327 } 328 329 /* 330 * the QHs are arranged to give poll intervals that are 331 * powers of 2 times 1ms 332 */ 333 bit = OHCI_NO_EDS / 2; 334 while (bit) { 335 x = bit; 336 while (x & bit) { 337 ohci_ed_t *ed_x; 338 ohci_ed_t *ed_y; 339 340 y = (x ^ bit) | (bit / 2); 341 342 /* 343 * the next QH has half the poll interval 344 */ 345 ed_x = sc->sc_intr_p_last[x]; 346 ed_y = sc->sc_intr_p_last[y]; 347 348 ed_x->next = NULL; 349 ed_x->ed_next = ed_y->ed_self; 350 351 x++; 352 } 353 bit >>= 1; 354 } 355 356 if (1) { 357 358 ohci_ed_t *ed_int; 359 ohci_ed_t *ed_isc; 360 361 ed_int = sc->sc_intr_p_last[0]; 362 ed_isc = sc->sc_isoc_p_last; 363 364 /* the last (1ms) QH */ 365 ed_int->next = ed_isc; 366 ed_int->ed_next = ed_isc->ed_self; 367 } 368 usb2_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 369 370 sc->sc_hcca_p = buf_res.buffer; 371 372 /* 373 * Fill HCCA interrupt table. The bit reversal is to get 374 * the tree set up properly to spread the interrupts. 375 */ 376 for (i = 0; i != OHCI_NO_INTRS; i++) { 377 sc->sc_hcca_p->hcca_interrupt_table[i] = 378 sc->sc_intr_p_last[i | (OHCI_NO_EDS / 2)]->ed_self; 379 } 380 /* flush all cache into memory */ 381 382 usb2_bus_mem_flush_all(&sc->sc_bus, &ohci_iterate_hw_softc); 383 384 /* set up the bus struct */ 385 sc->sc_bus.methods = &ohci_bus_methods; 386 387 usb2_callout_init_mtx(&sc->sc_tmo_rhsc, &sc->sc_bus.bus_mtx, 0); 388 389#if USB_DEBUG 390 if (ohcidebug > 15) { 391 for (i = 0; i != OHCI_NO_EDS; i++) { 392 printf("ed#%d ", i); 393 ohci_dump_ed(sc->sc_intr_p_last[i]); 394 } 395 printf("iso "); 396 ohci_dump_ed(sc->sc_isoc_p_last); 397 } 398#endif 399 400 sc->sc_bus.usbrev = USB_REV_1_0; 401 402 if (ohci_controller_init(sc)) { 403 return (USB_ERR_INVAL); 404 } else { 405 /* catch any lost interrupts */ 406 ohci_do_poll(&sc->sc_bus); 407 return (USB_ERR_NORMAL_COMPLETION); 408 } 409} 410 411/* 412 * shut down the controller when the system is going down 413 */ 414void 415ohci_detach(struct ohci_softc *sc) 416{ 417 USB_BUS_LOCK(&sc->sc_bus); 418 419 usb2_callout_stop(&sc->sc_tmo_rhsc); 420 421 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 422 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 423 424 USB_BUS_UNLOCK(&sc->sc_bus); 425 426 /* XXX let stray task complete */ 427 usb2_pause_mtx(NULL, hz / 20); 428 429 usb2_callout_drain(&sc->sc_tmo_rhsc); 430} 431 432/* NOTE: suspend/resume is called from 433 * interrupt context and cannot sleep! 434 */ 435void 436ohci_suspend(ohci_softc_t *sc) 437{ 438 uint32_t ctl; 439 440 USB_BUS_LOCK(&sc->sc_bus); 441 442#if USB_DEBUG 443 DPRINTF("\n"); 444 if (ohcidebug > 2) { 445 ohci_dumpregs(sc); 446 } 447#endif 448 449 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 450 if (sc->sc_control == 0) { 451 /* 452 * Preserve register values, in case that APM BIOS 453 * does not recover them. 454 */ 455 sc->sc_control = ctl; 456 sc->sc_intre = OREAD4(sc, OHCI_INTERRUPT_ENABLE); 457 } 458 ctl |= OHCI_HCFS_SUSPEND; 459 OWRITE4(sc, OHCI_CONTROL, ctl); 460 461 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 462 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 463 464 USB_BUS_UNLOCK(&sc->sc_bus); 465} 466 467void 468ohci_resume(ohci_softc_t *sc) 469{ 470 uint32_t ctl; 471 472#if USB_DEBUG 473 DPRINTF("\n"); 474 if (ohcidebug > 2) { 475 ohci_dumpregs(sc); 476 } 477#endif 478 /* some broken BIOSes never initialize the Controller chip */ 479 ohci_controller_init(sc); 480 481 USB_BUS_LOCK(&sc->sc_bus); 482 if (sc->sc_intre) { 483 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, 484 sc->sc_intre & (OHCI_ALL_INTRS | OHCI_MIE)); 485 } 486 if (sc->sc_control) 487 ctl = sc->sc_control; 488 else 489 ctl = OREAD4(sc, OHCI_CONTROL); 490 ctl |= OHCI_HCFS_RESUME; 491 OWRITE4(sc, OHCI_CONTROL, ctl); 492 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 493 USB_MS_TO_TICKS(USB_RESUME_DELAY)); 494 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 495 OWRITE4(sc, OHCI_CONTROL, ctl); 496 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 497 USB_MS_TO_TICKS(USB_RESUME_RECOVERY)); 498 sc->sc_control = sc->sc_intre = 0; 499 500 USB_BUS_UNLOCK(&sc->sc_bus); 501 502 /* catch any lost interrupts */ 503 ohci_do_poll(&sc->sc_bus); 504} 505 506#if USB_DEBUG 507static void 508ohci_dumpregs(ohci_softc_t *sc) 509{ 510 struct ohci_hcca *hcca; 511 512 DPRINTF("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 513 OREAD4(sc, OHCI_REVISION), 514 OREAD4(sc, OHCI_CONTROL), 515 OREAD4(sc, OHCI_COMMAND_STATUS)); 516 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 517 OREAD4(sc, OHCI_INTERRUPT_STATUS), 518 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 519 OREAD4(sc, OHCI_INTERRUPT_DISABLE)); 520 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 521 OREAD4(sc, OHCI_HCCA), 522 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 523 OREAD4(sc, OHCI_CONTROL_HEAD_ED)); 524 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 525 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 526 OREAD4(sc, OHCI_BULK_HEAD_ED), 527 OREAD4(sc, OHCI_BULK_CURRENT_ED)); 528 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 529 OREAD4(sc, OHCI_DONE_HEAD), 530 OREAD4(sc, OHCI_FM_INTERVAL), 531 OREAD4(sc, OHCI_FM_REMAINING)); 532 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 533 OREAD4(sc, OHCI_FM_NUMBER), 534 OREAD4(sc, OHCI_PERIODIC_START), 535 OREAD4(sc, OHCI_LS_THRESHOLD)); 536 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x\n", 537 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 538 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 539 OREAD4(sc, OHCI_RH_STATUS)); 540 DPRINTF(" port1=0x%08x port2=0x%08x\n", 541 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 542 OREAD4(sc, OHCI_RH_PORT_STATUS(2))); 543 544 hcca = ohci_get_hcca(sc); 545 546 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x\n", 547 le32toh(hcca->hcca_frame_number), 548 le32toh(hcca->hcca_done_head)); 549} 550static void 551ohci_dump_tds(ohci_td_t *std) 552{ 553 for (; std; std = std->obj_next) { 554 if (ohci_dump_td(std)) { 555 break; 556 } 557 } 558} 559 560static uint8_t 561ohci_dump_td(ohci_td_t *std) 562{ 563 uint32_t td_flags; 564 uint8_t temp; 565 566 usb2_pc_cpu_invalidate(std->page_cache); 567 568 td_flags = le32toh(std->td_flags); 569 temp = (std->td_next == 0); 570 571 printf("TD(%p) at 0x%08x: %s%s%s%s%s delay=%d ec=%d " 572 "cc=%d\ncbp=0x%08x next=0x%08x be=0x%08x\n", 573 std, le32toh(std->td_self), 574 (td_flags & OHCI_TD_R) ? "-R" : "", 575 (td_flags & OHCI_TD_OUT) ? "-OUT" : "", 576 (td_flags & OHCI_TD_IN) ? "-IN" : "", 577 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_1) ? "-TOG1" : "", 578 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_0) ? "-TOG0" : "", 579 OHCI_TD_GET_DI(td_flags), 580 OHCI_TD_GET_EC(td_flags), 581 OHCI_TD_GET_CC(td_flags), 582 le32toh(std->td_cbp), 583 le32toh(std->td_next), 584 le32toh(std->td_be)); 585 586 return (temp); 587} 588 589static uint8_t 590ohci_dump_itd(ohci_itd_t *sitd) 591{ 592 uint32_t itd_flags; 593 uint16_t i; 594 uint8_t temp; 595 596 usb2_pc_cpu_invalidate(sitd->page_cache); 597 598 itd_flags = le32toh(sitd->itd_flags); 599 temp = (sitd->itd_next == 0); 600 601 printf("ITD(%p) at 0x%08x: sf=%d di=%d fc=%d cc=%d\n" 602 "bp0=0x%08x next=0x%08x be=0x%08x\n", 603 sitd, le32toh(sitd->itd_self), 604 OHCI_ITD_GET_SF(itd_flags), 605 OHCI_ITD_GET_DI(itd_flags), 606 OHCI_ITD_GET_FC(itd_flags), 607 OHCI_ITD_GET_CC(itd_flags), 608 le32toh(sitd->itd_bp0), 609 le32toh(sitd->itd_next), 610 le32toh(sitd->itd_be)); 611 for (i = 0; i < OHCI_ITD_NOFFSET; i++) { 612 printf("offs[%d]=0x%04x ", i, 613 (uint32_t)le16toh(sitd->itd_offset[i])); 614 } 615 printf("\n"); 616 617 return (temp); 618} 619 620static void 621ohci_dump_itds(ohci_itd_t *sitd) 622{ 623 for (; sitd; sitd = sitd->obj_next) { 624 if (ohci_dump_itd(sitd)) { 625 break; 626 } 627 } 628} 629 630static void 631ohci_dump_ed(ohci_ed_t *sed) 632{ 633 uint32_t ed_flags; 634 uint32_t ed_headp; 635 636 usb2_pc_cpu_invalidate(sed->page_cache); 637 638 ed_flags = le32toh(sed->ed_flags); 639 ed_headp = le32toh(sed->ed_headp); 640 641 printf("ED(%p) at 0x%08x: addr=%d endpt=%d maxp=%d flags=%s%s%s%s%s\n" 642 "tailp=0x%08x headflags=%s%s headp=0x%08x nexted=0x%08x\n", 643 sed, le32toh(sed->ed_self), 644 OHCI_ED_GET_FA(ed_flags), 645 OHCI_ED_GET_EN(ed_flags), 646 OHCI_ED_GET_MAXP(ed_flags), 647 (ed_flags & OHCI_ED_DIR_OUT) ? "-OUT" : "", 648 (ed_flags & OHCI_ED_DIR_IN) ? "-IN" : "", 649 (ed_flags & OHCI_ED_SPEED) ? "-LOWSPEED" : "", 650 (ed_flags & OHCI_ED_SKIP) ? "-SKIP" : "", 651 (ed_flags & OHCI_ED_FORMAT_ISO) ? "-ISO" : "", 652 le32toh(sed->ed_tailp), 653 (ed_headp & OHCI_HALTED) ? "-HALTED" : "", 654 (ed_headp & OHCI_TOGGLECARRY) ? "-CARRY" : "", 655 le32toh(sed->ed_headp), 656 le32toh(sed->ed_next)); 657} 658 659#endif 660 661static void 662ohci_transfer_intr_enqueue(struct usb2_xfer *xfer) 663{ 664 /* check for early completion */ 665 if (ohci_check_transfer(xfer)) { 666 return; 667 } 668 /* put transfer on interrupt queue */ 669 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 670 671 /* start timeout, if any */ 672 if (xfer->timeout != 0) { 673 usb2_transfer_timeout_ms(xfer, &ohci_timeout, xfer->timeout); 674 } 675} 676 677#define OHCI_APPEND_QH(sed,last) (last) = _ohci_append_qh(sed,last) 678static ohci_ed_t * 679_ohci_append_qh(ohci_ed_t *sed, ohci_ed_t *last) 680{ 681 DPRINTFN(11, "%p to %p\n", sed, last); 682 683 if (sed->prev != NULL) { 684 /* should not happen */ 685 DPRINTFN(0, "ED already linked!\n"); 686 return (last); 687 } 688 /* (sc->sc_bus.bus_mtx) must be locked */ 689 690 sed->next = last->next; 691 sed->ed_next = last->ed_next; 692 sed->ed_tailp = 0; 693 694 sed->prev = last; 695 696 usb2_pc_cpu_flush(sed->page_cache); 697 698 /* 699 * the last->next->prev is never followed: sed->next->prev = sed; 700 */ 701 702 last->next = sed; 703 last->ed_next = sed->ed_self; 704 705 usb2_pc_cpu_flush(last->page_cache); 706 707 return (sed); 708} 709 710#define OHCI_REMOVE_QH(sed,last) (last) = _ohci_remove_qh(sed,last) 711static ohci_ed_t * 712_ohci_remove_qh(ohci_ed_t *sed, ohci_ed_t *last) 713{ 714 DPRINTFN(11, "%p from %p\n", sed, last); 715 716 /* (sc->sc_bus.bus_mtx) must be locked */ 717 718 /* only remove if not removed from a queue */ 719 if (sed->prev) { 720 721 sed->prev->next = sed->next; 722 sed->prev->ed_next = sed->ed_next; 723 724 usb2_pc_cpu_flush(sed->prev->page_cache); 725 726 if (sed->next) { 727 sed->next->prev = sed->prev; 728 usb2_pc_cpu_flush(sed->next->page_cache); 729 } 730 last = ((last == sed) ? sed->prev : last); 731 732 sed->prev = 0; 733 734 usb2_pc_cpu_flush(sed->page_cache); 735 } 736 return (last); 737} 738 739static void 740ohci_isoc_done(struct usb2_xfer *xfer) 741{ 742 uint8_t nframes; 743 uint32_t *plen = xfer->frlengths; 744 volatile uint16_t *olen; 745 uint16_t len = 0; 746 ohci_itd_t *td = xfer->td_transfer_first; 747 748 while (1) { 749 if (td == NULL) { 750 panic("%s:%d: out of TD's\n", 751 __FUNCTION__, __LINE__); 752 } 753#if USB_DEBUG 754 if (ohcidebug > 5) { 755 DPRINTF("isoc TD\n"); 756 ohci_dump_itd(td); 757 } 758#endif 759 usb2_pc_cpu_invalidate(td->page_cache); 760 761 nframes = td->frames; 762 olen = &td->itd_offset[0]; 763 764 if (nframes > 8) { 765 nframes = 8; 766 } 767 while (nframes--) { 768 len = le16toh(*olen); 769 770 if ((len >> 12) == OHCI_CC_NOT_ACCESSED) { 771 len = 0; 772 } else { 773 len &= ((1 << 12) - 1); 774 } 775 776 if (len > *plen) { 777 len = 0;/* invalid length */ 778 } 779 *plen = len; 780 plen++; 781 olen++; 782 } 783 784 if (((void *)td) == xfer->td_transfer_last) { 785 break; 786 } 787 td = td->obj_next; 788 } 789 790 xfer->aframes = xfer->nframes; 791 ohci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 792} 793 794#if USB_DEBUG 795static const char *const 796 ohci_cc_strs[] = 797{ 798 "NO_ERROR", 799 "CRC", 800 "BIT_STUFFING", 801 "DATA_TOGGLE_MISMATCH", 802 803 "STALL", 804 "DEVICE_NOT_RESPONDING", 805 "PID_CHECK_FAILURE", 806 "UNEXPECTED_PID", 807 808 "DATA_OVERRUN", 809 "DATA_UNDERRUN", 810 "BUFFER_OVERRUN", 811 "BUFFER_UNDERRUN", 812 813 "reserved", 814 "reserved", 815 "NOT_ACCESSED", 816 "NOT_ACCESSED" 817}; 818 819#endif 820 821static usb2_error_t 822ohci_non_isoc_done_sub(struct usb2_xfer *xfer) 823{ 824 ohci_td_t *td; 825 ohci_td_t *td_alt_next; 826 uint32_t temp; 827 uint32_t phy_start; 828 uint32_t phy_end; 829 uint32_t td_flags; 830 uint16_t cc; 831 832 td = xfer->td_transfer_cache; 833 td_alt_next = td->alt_next; 834 td_flags = 0; 835 836 if (xfer->aframes != xfer->nframes) { 837 xfer->frlengths[xfer->aframes] = 0; 838 } 839 while (1) { 840 841 usb2_pc_cpu_invalidate(td->page_cache); 842 phy_start = le32toh(td->td_cbp); 843 td_flags = le32toh(td->td_flags); 844 cc = OHCI_TD_GET_CC(td_flags); 845 846 if (phy_start) { 847 /* 848 * short transfer - compute the number of remaining 849 * bytes in the hardware buffer: 850 */ 851 phy_end = le32toh(td->td_be); 852 temp = (OHCI_PAGE(phy_start ^ phy_end) ? 853 (OHCI_PAGE_SIZE + 1) : 0x0001); 854 temp += OHCI_PAGE_OFFSET(phy_end); 855 temp -= OHCI_PAGE_OFFSET(phy_start); 856 857 if (temp > td->len) { 858 /* guard against corruption */ 859 cc = OHCI_CC_STALL; 860 } else if (xfer->aframes != xfer->nframes) { 861 /* 862 * Sum up total transfer length 863 * in "frlengths[]": 864 */ 865 xfer->frlengths[xfer->aframes] += td->len - temp; 866 } 867 } else { 868 if (xfer->aframes != xfer->nframes) { 869 /* transfer was complete */ 870 xfer->frlengths[xfer->aframes] += td->len; 871 } 872 } 873 /* Check for last transfer */ 874 if (((void *)td) == xfer->td_transfer_last) { 875 td = NULL; 876 break; 877 } 878 /* Check transfer status */ 879 if (cc) { 880 /* the transfer is finished */ 881 td = NULL; 882 break; 883 } 884 /* Check for short transfer */ 885 if (phy_start) { 886 if (xfer->flags_int.short_frames_ok) { 887 /* follow alt next */ 888 td = td->alt_next; 889 } else { 890 /* the transfer is finished */ 891 td = NULL; 892 } 893 break; 894 } 895 td = td->obj_next; 896 897 if (td->alt_next != td_alt_next) { 898 /* this USB frame is complete */ 899 break; 900 } 901 } 902 903 /* update transfer cache */ 904 905 xfer->td_transfer_cache = td; 906 907 DPRINTFN(16, "error cc=%d (%s)\n", 908 cc, ohci_cc_strs[cc]); 909 910 return ((cc == 0) ? USB_ERR_NORMAL_COMPLETION : 911 (cc == OHCI_CC_STALL) ? USB_ERR_STALLED : USB_ERR_IOERROR); 912} 913 914static void 915ohci_non_isoc_done(struct usb2_xfer *xfer) 916{ 917 usb2_error_t err = 0; 918 919 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 920 xfer, xfer->pipe); 921 922#if USB_DEBUG 923 if (ohcidebug > 10) { 924 ohci_dump_tds(xfer->td_transfer_first); 925 } 926#endif 927 928 /* reset scanner */ 929 930 xfer->td_transfer_cache = xfer->td_transfer_first; 931 932 if (xfer->flags_int.control_xfr) { 933 934 if (xfer->flags_int.control_hdr) { 935 936 err = ohci_non_isoc_done_sub(xfer); 937 } 938 xfer->aframes = 1; 939 940 if (xfer->td_transfer_cache == NULL) { 941 goto done; 942 } 943 } 944 while (xfer->aframes != xfer->nframes) { 945 946 err = ohci_non_isoc_done_sub(xfer); 947 xfer->aframes++; 948 949 if (xfer->td_transfer_cache == NULL) { 950 goto done; 951 } 952 } 953 954 if (xfer->flags_int.control_xfr && 955 !xfer->flags_int.control_act) { 956 957 err = ohci_non_isoc_done_sub(xfer); 958 } 959done: 960 ohci_device_done(xfer, err); 961} 962 963/*------------------------------------------------------------------------* 964 * ohci_check_transfer_sub 965 *------------------------------------------------------------------------*/ 966static void 967ohci_check_transfer_sub(struct usb2_xfer *xfer) 968{ 969 ohci_td_t *td; 970 ohci_ed_t *ed; 971 uint32_t phy_start; 972 uint32_t td_flags; 973 uint32_t td_next; 974 uint16_t cc; 975 976 td = xfer->td_transfer_cache; 977 978 while (1) { 979 980 usb2_pc_cpu_invalidate(td->page_cache); 981 phy_start = le32toh(td->td_cbp); 982 td_flags = le32toh(td->td_flags); 983 td_next = le32toh(td->td_next); 984 985 /* Check for last transfer */ 986 if (((void *)td) == xfer->td_transfer_last) { 987 /* the transfer is finished */ 988 td = NULL; 989 break; 990 } 991 /* Check transfer status */ 992 cc = OHCI_TD_GET_CC(td_flags); 993 if (cc) { 994 /* the transfer is finished */ 995 td = NULL; 996 break; 997 } 998 /* 999 * Check if we reached the last packet 1000 * or if there is a short packet: 1001 */ 1002 1003 if (((td_next & (~0xF)) == OHCI_TD_NEXT_END) || phy_start) { 1004 /* follow alt next */ 1005 td = td->alt_next; 1006 break; 1007 } 1008 td = td->obj_next; 1009 } 1010 1011 /* update transfer cache */ 1012 1013 xfer->td_transfer_cache = td; 1014 1015 if (td) { 1016 1017 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1018 1019 ed->ed_headp = td->td_self; 1020 usb2_pc_cpu_flush(ed->page_cache); 1021 1022 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1023 } 1024} 1025 1026/*------------------------------------------------------------------------* 1027 * ohci_check_transfer 1028 * 1029 * Return values: 1030 * 0: USB transfer is not finished 1031 * Else: USB transfer is finished 1032 *------------------------------------------------------------------------*/ 1033static uint8_t 1034ohci_check_transfer(struct usb2_xfer *xfer) 1035{ 1036 ohci_ed_t *ed; 1037 uint32_t ed_flags; 1038 uint32_t ed_headp; 1039 uint32_t ed_tailp; 1040 1041 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1042 1043 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1044 1045 usb2_pc_cpu_invalidate(ed->page_cache); 1046 ed_flags = le32toh(ed->ed_flags); 1047 ed_headp = le32toh(ed->ed_headp); 1048 ed_tailp = le32toh(ed->ed_tailp); 1049 1050 if ((ed_flags & OHCI_ED_SKIP) || 1051 (ed_headp & OHCI_HALTED) || 1052 (((ed_headp ^ ed_tailp) & (~0xF)) == 0)) { 1053 if (xfer->pipe->methods == &ohci_device_isoc_methods) { 1054 /* isochronous transfer */ 1055 ohci_isoc_done(xfer); 1056 } else { 1057 if (xfer->flags_int.short_frames_ok) { 1058 ohci_check_transfer_sub(xfer); 1059 if (xfer->td_transfer_cache) { 1060 /* not finished yet */ 1061 return (0); 1062 } 1063 } 1064 /* store data-toggle */ 1065 if (ed_headp & OHCI_TOGGLECARRY) { 1066 xfer->pipe->toggle_next = 1; 1067 } else { 1068 xfer->pipe->toggle_next = 0; 1069 } 1070 1071 /* non-isochronous transfer */ 1072 ohci_non_isoc_done(xfer); 1073 } 1074 return (1); 1075 } 1076 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1077 return (0); 1078} 1079 1080static void 1081ohci_rhsc_enable(ohci_softc_t *sc) 1082{ 1083 DPRINTFN(5, "\n"); 1084 1085 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1086 1087 sc->sc_eintrs |= OHCI_RHSC; 1088 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1089 1090 /* acknowledge any RHSC interrupt */ 1091 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_RHSC); 1092 1093 usb2_sw_transfer(&sc->sc_root_intr, 1094 &ohci_root_intr_done); 1095} 1096 1097static void 1098ohci_interrupt_poll(ohci_softc_t *sc) 1099{ 1100 struct usb2_xfer *xfer; 1101 1102repeat: 1103 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1104 /* 1105 * check if transfer is transferred 1106 */ 1107 if (ohci_check_transfer(xfer)) { 1108 /* queue has been modified */ 1109 goto repeat; 1110 } 1111 } 1112} 1113 1114/*------------------------------------------------------------------------* 1115 * ohci_interrupt - OHCI interrupt handler 1116 * 1117 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1118 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1119 * is present ! 1120 *------------------------------------------------------------------------*/ 1121void 1122ohci_interrupt(ohci_softc_t *sc) 1123{ 1124 struct ohci_hcca *hcca; 1125 uint32_t status; 1126 uint32_t done; 1127 1128 USB_BUS_LOCK(&sc->sc_bus); 1129 1130 hcca = ohci_get_hcca(sc); 1131 1132 DPRINTFN(16, "real interrupt\n"); 1133 1134#if USB_DEBUG 1135 if (ohcidebug > 15) { 1136 ohci_dumpregs(sc); 1137 } 1138#endif 1139 1140 done = le32toh(hcca->hcca_done_head); 1141 1142 /* 1143 * The LSb of done is used to inform the HC Driver that an interrupt 1144 * condition exists for both the Done list and for another event 1145 * recorded in HcInterruptStatus. On an interrupt from the HC, the 1146 * HC Driver checks the HccaDoneHead Value. If this value is 0, then 1147 * the interrupt was caused by other than the HccaDoneHead update 1148 * and the HcInterruptStatus register needs to be accessed to 1149 * determine that exact interrupt cause. If HccaDoneHead is nonzero, 1150 * then a Done list update interrupt is indicated and if the LSb of 1151 * done is nonzero, then an additional interrupt event is indicated 1152 * and HcInterruptStatus should be checked to determine its cause. 1153 */ 1154 if (done != 0) { 1155 status = 0; 1156 1157 if (done & ~OHCI_DONE_INTRS) { 1158 status |= OHCI_WDH; 1159 } 1160 if (done & OHCI_DONE_INTRS) { 1161 status |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 1162 } 1163 hcca->hcca_done_head = 0; 1164 1165 usb2_pc_cpu_flush(&sc->sc_hw.hcca_pc); 1166 } else { 1167 status = OREAD4(sc, OHCI_INTERRUPT_STATUS) & ~OHCI_WDH; 1168 } 1169 1170 status &= ~OHCI_MIE; 1171 if (status == 0) { 1172 /* 1173 * nothing to be done (PCI shared 1174 * interrupt) 1175 */ 1176 goto done; 1177 } 1178 OWRITE4(sc, OHCI_INTERRUPT_STATUS, status); /* Acknowledge */ 1179 1180 status &= sc->sc_eintrs; 1181 if (status == 0) { 1182 goto done; 1183 } 1184 if (status & (OHCI_SO | OHCI_RD | OHCI_UE | OHCI_RHSC)) { 1185#if 0 1186 if (status & OHCI_SO) { 1187 /* XXX do what */ 1188 } 1189#endif 1190 if (status & OHCI_RD) { 1191 printf("%s: resume detect\n", __FUNCTION__); 1192 /* XXX process resume detect */ 1193 } 1194 if (status & OHCI_UE) { 1195 printf("%s: unrecoverable error, " 1196 "controller halted\n", __FUNCTION__); 1197 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1198 /* XXX what else */ 1199 } 1200 if (status & OHCI_RHSC) { 1201 /* 1202 * Disable RHSC interrupt for now, because it will be 1203 * on until the port has been reset. 1204 */ 1205 sc->sc_eintrs &= ~OHCI_RHSC; 1206 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 1207 1208 usb2_sw_transfer(&sc->sc_root_intr, 1209 &ohci_root_intr_done); 1210 1211 /* do not allow RHSC interrupts > 1 per second */ 1212 usb2_callout_reset(&sc->sc_tmo_rhsc, hz, 1213 (void *)&ohci_rhsc_enable, sc); 1214 } 1215 } 1216 status &= ~(OHCI_RHSC | OHCI_WDH | OHCI_SO); 1217 if (status != 0) { 1218 /* Block unprocessed interrupts. XXX */ 1219 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, status); 1220 sc->sc_eintrs &= ~status; 1221 printf("%s: blocking intrs 0x%x\n", 1222 __FUNCTION__, status); 1223 } 1224 /* poll all the USB transfers */ 1225 ohci_interrupt_poll(sc); 1226 1227done: 1228 USB_BUS_UNLOCK(&sc->sc_bus); 1229} 1230 1231/* 1232 * called when a request does not complete 1233 */ 1234static void 1235ohci_timeout(void *arg) 1236{ 1237 struct usb2_xfer *xfer = arg; 1238 1239 DPRINTF("xfer=%p\n", xfer); 1240 1241 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1242 1243 /* transfer is transferred */ 1244 ohci_device_done(xfer, USB_ERR_TIMEOUT); 1245} 1246 1247static void 1248ohci_do_poll(struct usb2_bus *bus) 1249{ 1250 struct ohci_softc *sc = OHCI_BUS2SC(bus); 1251 1252 USB_BUS_LOCK(&sc->sc_bus); 1253 ohci_interrupt_poll(sc); 1254 ohci_root_ctrl_poll(sc); 1255 USB_BUS_UNLOCK(&sc->sc_bus); 1256} 1257 1258static void 1259ohci_setup_standard_chain_sub(struct ohci_std_temp *temp) 1260{ 1261 struct usb2_page_search buf_res; 1262 ohci_td_t *td; 1263 ohci_td_t *td_next; 1264 ohci_td_t *td_alt_next; 1265 uint32_t buf_offset; 1266 uint32_t average; 1267 uint32_t len_old; 1268 uint8_t shortpkt_old; 1269 uint8_t precompute; 1270 1271 td_alt_next = NULL; 1272 buf_offset = 0; 1273 shortpkt_old = temp->shortpkt; 1274 len_old = temp->len; 1275 precompute = 1; 1276 1277 /* software is used to detect short incoming transfers */ 1278 1279 if ((temp->td_flags & htole32(OHCI_TD_DP_MASK)) == htole32(OHCI_TD_IN)) { 1280 temp->td_flags |= htole32(OHCI_TD_R); 1281 } else { 1282 temp->td_flags &= ~htole32(OHCI_TD_R); 1283 } 1284 1285restart: 1286 1287 td = temp->td; 1288 td_next = temp->td_next; 1289 1290 while (1) { 1291 1292 if (temp->len == 0) { 1293 1294 if (temp->shortpkt) { 1295 break; 1296 } 1297 /* send a Zero Length Packet, ZLP, last */ 1298 1299 temp->shortpkt = 1; 1300 average = 0; 1301 1302 } else { 1303 1304 average = temp->average; 1305 1306 if (temp->len < average) { 1307 if (temp->len % temp->max_frame_size) { 1308 temp->shortpkt = 1; 1309 } 1310 average = temp->len; 1311 } 1312 } 1313 1314 if (td_next == NULL) { 1315 panic("%s: out of OHCI transfer descriptors!", __FUNCTION__); 1316 } 1317 /* get next TD */ 1318 1319 td = td_next; 1320 td_next = td->obj_next; 1321 1322 /* check if we are pre-computing */ 1323 1324 if (precompute) { 1325 1326 /* update remaining length */ 1327 1328 temp->len -= average; 1329 1330 continue; 1331 } 1332 /* fill out current TD */ 1333 td->td_flags = temp->td_flags; 1334 1335 /* the next TD uses TOGGLE_CARRY */ 1336 temp->td_flags &= ~htole32(OHCI_TD_TOGGLE_MASK); 1337 1338 if (average == 0) { 1339 1340 td->td_cbp = 0; 1341 td->td_be = ~0; 1342 td->len = 0; 1343 1344 } else { 1345 1346 usb2_get_page(temp->pc, buf_offset, &buf_res); 1347 td->td_cbp = htole32(buf_res.physaddr); 1348 buf_offset += (average - 1); 1349 1350 usb2_get_page(temp->pc, buf_offset, &buf_res); 1351 td->td_be = htole32(buf_res.physaddr); 1352 buf_offset++; 1353 1354 td->len = average; 1355 1356 /* update remaining length */ 1357 1358 temp->len -= average; 1359 } 1360 1361 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1362 /* we need to receive these frames one by one ! */ 1363 td->td_flags &= htole32(~OHCI_TD_INTR_MASK); 1364 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1365 td->td_next = htole32(OHCI_TD_NEXT_END); 1366 } else { 1367 if (td_next) { 1368 /* link the current TD with the next one */ 1369 td->td_next = td_next->td_self; 1370 } 1371 } 1372 1373 td->alt_next = td_alt_next; 1374 1375 usb2_pc_cpu_flush(td->page_cache); 1376 } 1377 1378 if (precompute) { 1379 precompute = 0; 1380 1381 /* setup alt next pointer, if any */ 1382 if (temp->short_frames_ok) { 1383 if (temp->setup_alt_next) { 1384 td_alt_next = td_next; 1385 } 1386 } else { 1387 /* we use this field internally */ 1388 td_alt_next = td_next; 1389 } 1390 1391 /* restore */ 1392 temp->shortpkt = shortpkt_old; 1393 temp->len = len_old; 1394 goto restart; 1395 } 1396 temp->td = td; 1397 temp->td_next = td_next; 1398} 1399 1400static void 1401ohci_setup_standard_chain(struct usb2_xfer *xfer, ohci_ed_t **ed_last) 1402{ 1403 struct ohci_std_temp temp; 1404 struct usb2_pipe_methods *methods; 1405 ohci_ed_t *ed; 1406 ohci_td_t *td; 1407 uint32_t ed_flags; 1408 uint32_t x; 1409 1410 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1411 xfer->address, UE_GET_ADDR(xfer->endpoint), 1412 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 1413 1414 temp.average = xfer->max_usb2_frame_size; 1415 temp.max_frame_size = xfer->max_frame_size; 1416 1417 /* toggle the DMA set we are using */ 1418 xfer->flags_int.curr_dma_set ^= 1; 1419 1420 /* get next DMA set */ 1421 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1422 1423 xfer->td_transfer_first = td; 1424 xfer->td_transfer_cache = td; 1425 1426 temp.td = NULL; 1427 temp.td_next = td; 1428 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1429 temp.short_frames_ok = xfer->flags_int.short_frames_ok; 1430 1431 methods = xfer->pipe->methods; 1432 1433 /* check if we should prepend a setup message */ 1434 1435 if (xfer->flags_int.control_xfr) { 1436 if (xfer->flags_int.control_hdr) { 1437 1438 temp.td_flags = htole32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1439 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1440 1441 temp.len = xfer->frlengths[0]; 1442 temp.pc = xfer->frbuffers + 0; 1443 temp.shortpkt = temp.len ? 1 : 0; 1444 1445 ohci_setup_standard_chain_sub(&temp); 1446 1447 /* 1448 * XXX assume that the setup message is 1449 * contained within one USB packet: 1450 */ 1451 xfer->pipe->toggle_next = 1; 1452 } 1453 x = 1; 1454 } else { 1455 x = 0; 1456 } 1457 temp.td_flags = htole32(OHCI_TD_NOCC | OHCI_TD_NOINTR); 1458 1459 /* set data toggle */ 1460 1461 if (xfer->pipe->toggle_next) { 1462 temp.td_flags |= htole32(OHCI_TD_TOGGLE_1); 1463 } else { 1464 temp.td_flags |= htole32(OHCI_TD_TOGGLE_0); 1465 } 1466 1467 /* set endpoint direction */ 1468 1469 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 1470 temp.td_flags |= htole32(OHCI_TD_IN); 1471 } else { 1472 temp.td_flags |= htole32(OHCI_TD_OUT); 1473 } 1474 1475 while (x != xfer->nframes) { 1476 1477 /* DATA0 / DATA1 message */ 1478 1479 temp.len = xfer->frlengths[x]; 1480 temp.pc = xfer->frbuffers + x; 1481 1482 x++; 1483 1484 if (x == xfer->nframes) { 1485 temp.setup_alt_next = 0; 1486 } 1487 if (temp.len == 0) { 1488 1489 /* make sure that we send an USB packet */ 1490 1491 temp.shortpkt = 0; 1492 1493 } else { 1494 1495 /* regular data transfer */ 1496 1497 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1498 } 1499 1500 ohci_setup_standard_chain_sub(&temp); 1501 } 1502 1503 /* check if we should append a status stage */ 1504 1505 if (xfer->flags_int.control_xfr && 1506 !xfer->flags_int.control_act) { 1507 1508 /* 1509 * Send a DATA1 message and invert the current endpoint 1510 * direction. 1511 */ 1512 1513 /* set endpoint direction and data toggle */ 1514 1515 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 1516 temp.td_flags = htole32(OHCI_TD_OUT | 1517 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1518 } else { 1519 temp.td_flags = htole32(OHCI_TD_IN | 1520 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1521 } 1522 1523 temp.len = 0; 1524 temp.pc = NULL; 1525 temp.shortpkt = 0; 1526 1527 ohci_setup_standard_chain_sub(&temp); 1528 } 1529 td = temp.td; 1530 1531 td->td_next = htole32(OHCI_TD_NEXT_END); 1532 td->td_flags &= ~htole32(OHCI_TD_INTR_MASK); 1533 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1534 1535 usb2_pc_cpu_flush(td->page_cache); 1536 1537 /* must have at least one frame! */ 1538 1539 xfer->td_transfer_last = td; 1540 1541#if USB_DEBUG 1542 if (ohcidebug > 8) { 1543 DPRINTF("nexttog=%d; data before transfer:\n", 1544 xfer->pipe->toggle_next); 1545 ohci_dump_tds(xfer->td_transfer_first); 1546 } 1547#endif 1548 1549 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1550 1551 ed_flags = (OHCI_ED_SET_FA(xfer->address) | 1552 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpoint)) | 1553 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 1554 1555 ed_flags |= (OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD); 1556 1557 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1558 ed_flags |= OHCI_ED_SPEED; 1559 } 1560 ed->ed_flags = htole32(ed_flags); 1561 1562 td = xfer->td_transfer_first; 1563 1564 ed->ed_headp = td->td_self; 1565 1566 if (xfer->xroot->udev->pwr_save.suspended == 0) { 1567 /* the append function will flush the endpoint descriptor */ 1568 OHCI_APPEND_QH(ed, *ed_last); 1569 1570 if (methods == &ohci_device_bulk_methods) { 1571 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1572 1573 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1574 } 1575 if (methods == &ohci_device_ctrl_methods) { 1576 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1577 1578 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1579 } 1580 } else { 1581 usb2_pc_cpu_flush(ed->page_cache); 1582 } 1583} 1584 1585static void 1586ohci_root_intr_done(struct usb2_xfer *xfer, 1587 struct usb2_sw_transfer *std) 1588{ 1589 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1590 uint32_t hstatus; 1591 uint16_t i; 1592 uint16_t m; 1593 1594 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1595 1596 if (std->state != USB_SW_TR_PRE_DATA) { 1597 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1598 /* transfer transferred */ 1599 ohci_device_done(xfer, std->err); 1600 } 1601 goto done; 1602 } 1603 /* setup buffer */ 1604 std->ptr = sc->sc_hub_idata; 1605 std->len = sizeof(sc->sc_hub_idata); 1606 1607 /* clear any old interrupt data */ 1608 bzero(sc->sc_hub_idata, sizeof(sc->sc_hub_idata)); 1609 1610 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1611 DPRINTF("sc=%p xfer=%p hstatus=0x%08x\n", 1612 sc, xfer, hstatus); 1613 1614 /* set bits */ 1615 m = (sc->sc_noport + 1); 1616 if (m > (8 * sizeof(sc->sc_hub_idata))) { 1617 m = (8 * sizeof(sc->sc_hub_idata)); 1618 } 1619 for (i = 1; i < m; i++) { 1620 /* pick out CHANGE bits from the status register */ 1621 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) { 1622 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 1623 DPRINTF("port %d changed\n", i); 1624 } 1625 } 1626done: 1627 return; 1628} 1629 1630/* NOTE: "done" can be run two times in a row, 1631 * from close and from interrupt 1632 */ 1633static void 1634ohci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1635{ 1636 struct usb2_pipe_methods *methods = xfer->pipe->methods; 1637 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1638 ohci_ed_t *ed; 1639 1640 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1641 1642 1643 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1644 xfer, xfer->pipe, error); 1645 1646 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1647 if (ed) { 1648 usb2_pc_cpu_invalidate(ed->page_cache); 1649 } 1650 if (methods == &ohci_device_bulk_methods) { 1651 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 1652 } 1653 if (methods == &ohci_device_ctrl_methods) { 1654 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 1655 } 1656 if (methods == &ohci_device_intr_methods) { 1657 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 1658 } 1659 if (methods == &ohci_device_isoc_methods) { 1660 OHCI_REMOVE_QH(ed, sc->sc_isoc_p_last); 1661 } 1662 xfer->td_transfer_first = NULL; 1663 xfer->td_transfer_last = NULL; 1664 1665 /* dequeue transfer and start next transfer */ 1666 usb2_transfer_done(xfer, error); 1667} 1668 1669/*------------------------------------------------------------------------* 1670 * ohci bulk support 1671 *------------------------------------------------------------------------*/ 1672static void 1673ohci_device_bulk_open(struct usb2_xfer *xfer) 1674{ 1675 return; 1676} 1677 1678static void 1679ohci_device_bulk_close(struct usb2_xfer *xfer) 1680{ 1681 ohci_device_done(xfer, USB_ERR_CANCELLED); 1682} 1683 1684static void 1685ohci_device_bulk_enter(struct usb2_xfer *xfer) 1686{ 1687 return; 1688} 1689 1690static void 1691ohci_device_bulk_start(struct usb2_xfer *xfer) 1692{ 1693 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1694 1695 /* setup TD's and QH */ 1696 ohci_setup_standard_chain(xfer, &sc->sc_bulk_p_last); 1697 1698 /* put transfer on interrupt queue */ 1699 ohci_transfer_intr_enqueue(xfer); 1700} 1701 1702struct usb2_pipe_methods ohci_device_bulk_methods = 1703{ 1704 .open = ohci_device_bulk_open, 1705 .close = ohci_device_bulk_close, 1706 .enter = ohci_device_bulk_enter, 1707 .start = ohci_device_bulk_start, 1708 .enter_is_cancelable = 1, 1709 .start_is_cancelable = 1, 1710}; 1711 1712/*------------------------------------------------------------------------* 1713 * ohci control support 1714 *------------------------------------------------------------------------*/ 1715static void 1716ohci_device_ctrl_open(struct usb2_xfer *xfer) 1717{ 1718 return; 1719} 1720 1721static void 1722ohci_device_ctrl_close(struct usb2_xfer *xfer) 1723{ 1724 ohci_device_done(xfer, USB_ERR_CANCELLED); 1725} 1726 1727static void 1728ohci_device_ctrl_enter(struct usb2_xfer *xfer) 1729{ 1730 return; 1731} 1732 1733static void 1734ohci_device_ctrl_start(struct usb2_xfer *xfer) 1735{ 1736 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1737 1738 /* setup TD's and QH */ 1739 ohci_setup_standard_chain(xfer, &sc->sc_ctrl_p_last); 1740 1741 /* put transfer on interrupt queue */ 1742 ohci_transfer_intr_enqueue(xfer); 1743} 1744 1745struct usb2_pipe_methods ohci_device_ctrl_methods = 1746{ 1747 .open = ohci_device_ctrl_open, 1748 .close = ohci_device_ctrl_close, 1749 .enter = ohci_device_ctrl_enter, 1750 .start = ohci_device_ctrl_start, 1751 .enter_is_cancelable = 1, 1752 .start_is_cancelable = 1, 1753}; 1754 1755/*------------------------------------------------------------------------* 1756 * ohci interrupt support 1757 *------------------------------------------------------------------------*/ 1758static void 1759ohci_device_intr_open(struct usb2_xfer *xfer) 1760{ 1761 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1762 uint16_t best; 1763 uint16_t bit; 1764 uint16_t x; 1765 1766 best = 0; 1767 bit = OHCI_NO_EDS / 2; 1768 while (bit) { 1769 if (xfer->interval >= bit) { 1770 x = bit; 1771 best = bit; 1772 while (x & bit) { 1773 if (sc->sc_intr_stat[x] < 1774 sc->sc_intr_stat[best]) { 1775 best = x; 1776 } 1777 x++; 1778 } 1779 break; 1780 } 1781 bit >>= 1; 1782 } 1783 1784 sc->sc_intr_stat[best]++; 1785 xfer->qh_pos = best; 1786 1787 DPRINTFN(3, "best=%d interval=%d\n", 1788 best, xfer->interval); 1789} 1790 1791static void 1792ohci_device_intr_close(struct usb2_xfer *xfer) 1793{ 1794 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1795 1796 sc->sc_intr_stat[xfer->qh_pos]--; 1797 1798 ohci_device_done(xfer, USB_ERR_CANCELLED); 1799} 1800 1801static void 1802ohci_device_intr_enter(struct usb2_xfer *xfer) 1803{ 1804 return; 1805} 1806 1807static void 1808ohci_device_intr_start(struct usb2_xfer *xfer) 1809{ 1810 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1811 1812 /* setup TD's and QH */ 1813 ohci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 1814 1815 /* put transfer on interrupt queue */ 1816 ohci_transfer_intr_enqueue(xfer); 1817} 1818 1819struct usb2_pipe_methods ohci_device_intr_methods = 1820{ 1821 .open = ohci_device_intr_open, 1822 .close = ohci_device_intr_close, 1823 .enter = ohci_device_intr_enter, 1824 .start = ohci_device_intr_start, 1825 .enter_is_cancelable = 1, 1826 .start_is_cancelable = 1, 1827}; 1828 1829/*------------------------------------------------------------------------* 1830 * ohci isochronous support 1831 *------------------------------------------------------------------------*/ 1832static void 1833ohci_device_isoc_open(struct usb2_xfer *xfer) 1834{ 1835 return; 1836} 1837 1838static void 1839ohci_device_isoc_close(struct usb2_xfer *xfer) 1840{ 1841 /**/ 1842 ohci_device_done(xfer, USB_ERR_CANCELLED); 1843} 1844 1845static void 1846ohci_device_isoc_enter(struct usb2_xfer *xfer) 1847{ 1848 struct usb2_page_search buf_res; 1849 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1850 struct ohci_hcca *hcca; 1851 uint32_t buf_offset; 1852 uint32_t nframes; 1853 uint32_t ed_flags; 1854 uint32_t *plen; 1855 uint16_t itd_offset[OHCI_ITD_NOFFSET]; 1856 uint16_t length; 1857 uint8_t ncur; 1858 ohci_itd_t *td; 1859 ohci_itd_t *td_last = NULL; 1860 ohci_ed_t *ed; 1861 1862 hcca = ohci_get_hcca(sc); 1863 1864 nframes = le32toh(hcca->hcca_frame_number); 1865 1866 DPRINTFN(6, "xfer=%p isoc_next=%u nframes=%u hcca_fn=%u\n", 1867 xfer, xfer->pipe->isoc_next, xfer->nframes, nframes); 1868 1869 if ((xfer->pipe->is_synced == 0) || 1870 (((nframes - xfer->pipe->isoc_next) & 0xFFFF) < xfer->nframes) || 1871 (((xfer->pipe->isoc_next - nframes) & 0xFFFF) >= 128)) { 1872 /* 1873 * If there is data underflow or the pipe queue is empty we 1874 * schedule the transfer a few frames ahead of the current 1875 * frame position. Else two isochronous transfers might 1876 * overlap. 1877 */ 1878 xfer->pipe->isoc_next = (nframes + 3) & 0xFFFF; 1879 xfer->pipe->is_synced = 1; 1880 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 1881 } 1882 /* 1883 * compute how many milliseconds the insertion is ahead of the 1884 * current frame position: 1885 */ 1886 buf_offset = ((xfer->pipe->isoc_next - nframes) & 0xFFFF); 1887 1888 /* 1889 * pre-compute when the isochronous transfer will be finished: 1890 */ 1891 xfer->isoc_time_complete = 1892 (usb2_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 1893 xfer->nframes); 1894 1895 /* get the real number of frames */ 1896 1897 nframes = xfer->nframes; 1898 1899 buf_offset = 0; 1900 1901 plen = xfer->frlengths; 1902 1903 /* toggle the DMA set we are using */ 1904 xfer->flags_int.curr_dma_set ^= 1; 1905 1906 /* get next DMA set */ 1907 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1908 1909 xfer->td_transfer_first = td; 1910 1911 ncur = 0; 1912 length = 0; 1913 1914 while (nframes--) { 1915 if (td == NULL) { 1916 panic("%s:%d: out of TD's\n", 1917 __FUNCTION__, __LINE__); 1918 } 1919 itd_offset[ncur] = length; 1920 buf_offset += *plen; 1921 length += *plen; 1922 plen++; 1923 ncur++; 1924 1925 if ( /* check if the ITD is full */ 1926 (ncur == OHCI_ITD_NOFFSET) || 1927 /* check if we have put more than 4K into the ITD */ 1928 (length & 0xF000) || 1929 /* check if it is the last frame */ 1930 (nframes == 0)) { 1931 1932 /* fill current ITD */ 1933 td->itd_flags = htole32( 1934 OHCI_ITD_NOCC | 1935 OHCI_ITD_SET_SF(xfer->pipe->isoc_next) | 1936 OHCI_ITD_NOINTR | 1937 OHCI_ITD_SET_FC(ncur)); 1938 1939 td->frames = ncur; 1940 xfer->pipe->isoc_next += ncur; 1941 1942 if (length == 0) { 1943 /* all zero */ 1944 td->itd_bp0 = 0; 1945 td->itd_be = ~0; 1946 1947 while (ncur--) { 1948 td->itd_offset[ncur] = 1949 htole16(OHCI_ITD_MK_OFFS(0)); 1950 } 1951 } else { 1952 usb2_get_page(xfer->frbuffers, buf_offset - length, &buf_res); 1953 length = OHCI_PAGE_MASK(buf_res.physaddr); 1954 buf_res.physaddr = 1955 OHCI_PAGE(buf_res.physaddr); 1956 td->itd_bp0 = htole32(buf_res.physaddr); 1957 usb2_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 1958 td->itd_be = htole32(buf_res.physaddr); 1959 1960 while (ncur--) { 1961 itd_offset[ncur] += length; 1962 itd_offset[ncur] = 1963 OHCI_ITD_MK_OFFS(itd_offset[ncur]); 1964 td->itd_offset[ncur] = 1965 htole16(itd_offset[ncur]); 1966 } 1967 } 1968 ncur = 0; 1969 length = 0; 1970 td_last = td; 1971 td = td->obj_next; 1972 1973 if (td) { 1974 /* link the last TD with the next one */ 1975 td_last->itd_next = td->itd_self; 1976 } 1977 usb2_pc_cpu_flush(td_last->page_cache); 1978 } 1979 } 1980 1981 /* update the last TD */ 1982 td_last->itd_flags &= ~htole32(OHCI_ITD_NOINTR); 1983 td_last->itd_flags |= htole32(OHCI_ITD_SET_DI(0)); 1984 td_last->itd_next = 0; 1985 1986 usb2_pc_cpu_flush(td_last->page_cache); 1987 1988 xfer->td_transfer_last = td_last; 1989 1990#if USB_DEBUG 1991 if (ohcidebug > 8) { 1992 DPRINTF("data before transfer:\n"); 1993 ohci_dump_itds(xfer->td_transfer_first); 1994 } 1995#endif 1996 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1997 1998 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) 1999 ed_flags = (OHCI_ED_DIR_IN | OHCI_ED_FORMAT_ISO); 2000 else 2001 ed_flags = (OHCI_ED_DIR_OUT | OHCI_ED_FORMAT_ISO); 2002 2003 ed_flags |= (OHCI_ED_SET_FA(xfer->address) | 2004 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpoint)) | 2005 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 2006 2007 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 2008 ed_flags |= OHCI_ED_SPEED; 2009 } 2010 ed->ed_flags = htole32(ed_flags); 2011 2012 td = xfer->td_transfer_first; 2013 2014 ed->ed_headp = td->itd_self; 2015 2016 /* isochronous transfers are not affected by suspend / resume */ 2017 /* the append function will flush the endpoint descriptor */ 2018 2019 OHCI_APPEND_QH(ed, sc->sc_isoc_p_last); 2020} 2021 2022static void 2023ohci_device_isoc_start(struct usb2_xfer *xfer) 2024{ 2025 /* put transfer on interrupt queue */ 2026 ohci_transfer_intr_enqueue(xfer); 2027} 2028 2029struct usb2_pipe_methods ohci_device_isoc_methods = 2030{ 2031 .open = ohci_device_isoc_open, 2032 .close = ohci_device_isoc_close, 2033 .enter = ohci_device_isoc_enter, 2034 .start = ohci_device_isoc_start, 2035 .enter_is_cancelable = 1, 2036 .start_is_cancelable = 1, 2037}; 2038 2039/*------------------------------------------------------------------------* 2040 * ohci root control support 2041 *------------------------------------------------------------------------* 2042 * simulate a hardware hub by handling 2043 * all the necessary requests 2044 *------------------------------------------------------------------------*/ 2045 2046static void 2047ohci_root_ctrl_open(struct usb2_xfer *xfer) 2048{ 2049 return; 2050} 2051 2052static void 2053ohci_root_ctrl_close(struct usb2_xfer *xfer) 2054{ 2055 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 2056 2057 if (sc->sc_root_ctrl.xfer == xfer) { 2058 sc->sc_root_ctrl.xfer = NULL; 2059 } 2060 ohci_device_done(xfer, USB_ERR_CANCELLED); 2061} 2062 2063/* data structures and routines 2064 * to emulate the root hub: 2065 */ 2066static const 2067struct usb2_device_descriptor ohci_devd = 2068{ 2069 sizeof(struct usb2_device_descriptor), 2070 UDESC_DEVICE, /* type */ 2071 {0x00, 0x01}, /* USB version */ 2072 UDCLASS_HUB, /* class */ 2073 UDSUBCLASS_HUB, /* subclass */ 2074 UDPROTO_FSHUB, /* protocol */ 2075 64, /* max packet */ 2076 {0}, {0}, {0x00, 0x01}, /* device id */ 2077 1, 2, 0, /* string indicies */ 2078 1 /* # of configurations */ 2079}; 2080 2081static const 2082struct ohci_config_desc ohci_confd = 2083{ 2084 .confd = { 2085 .bLength = sizeof(struct usb2_config_descriptor), 2086 .bDescriptorType = UDESC_CONFIG, 2087 .wTotalLength[0] = sizeof(ohci_confd), 2088 .bNumInterface = 1, 2089 .bConfigurationValue = 1, 2090 .iConfiguration = 0, 2091 .bmAttributes = UC_SELF_POWERED, 2092 .bMaxPower = 0, /* max power */ 2093 }, 2094 2095 .ifcd = { 2096 .bLength = sizeof(struct usb2_interface_descriptor), 2097 .bDescriptorType = UDESC_INTERFACE, 2098 .bNumEndpoints = 1, 2099 .bInterfaceClass = UICLASS_HUB, 2100 .bInterfaceSubClass = UISUBCLASS_HUB, 2101 .bInterfaceProtocol = UIPROTO_FSHUB, 2102 }, 2103 2104 .endpd = { 2105 .bLength = sizeof(struct usb2_endpoint_descriptor), 2106 .bDescriptorType = UDESC_ENDPOINT, 2107 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2108 .bmAttributes = UE_INTERRUPT, 2109 .wMaxPacketSize[0] = 32,/* max packet (255 ports) */ 2110 .bInterval = 255, 2111 }, 2112}; 2113 2114static const 2115struct usb2_hub_descriptor ohci_hubd = 2116{ 2117 0, /* dynamic length */ 2118 UDESC_HUB, 2119 0, 2120 {0, 0}, 2121 0, 2122 0, 2123 {0}, 2124}; 2125 2126static void 2127ohci_root_ctrl_enter(struct usb2_xfer *xfer) 2128{ 2129 return; 2130} 2131 2132static void 2133ohci_root_ctrl_start(struct usb2_xfer *xfer) 2134{ 2135 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 2136 2137 sc->sc_root_ctrl.xfer = xfer; 2138 2139 usb2_bus_roothub_exec(xfer->xroot->bus); 2140} 2141 2142static void 2143ohci_root_ctrl_task(struct usb2_bus *bus) 2144{ 2145 ohci_root_ctrl_poll(OHCI_BUS2SC(bus)); 2146} 2147 2148static void 2149ohci_root_ctrl_done(struct usb2_xfer *xfer, 2150 struct usb2_sw_transfer *std) 2151{ 2152 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 2153 char *ptr; 2154 uint32_t port; 2155 uint32_t v; 2156 uint16_t value; 2157 uint16_t index; 2158 uint8_t l; 2159 uint8_t use_polling; 2160 2161 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2162 2163 if (std->state != USB_SW_TR_SETUP) { 2164 if (std->state == USB_SW_TR_PRE_CALLBACK) { 2165 /* transfer transferred */ 2166 ohci_device_done(xfer, std->err); 2167 } 2168 goto done; 2169 } 2170 /* buffer reset */ 2171 std->ptr = sc->sc_hub_desc.temp; 2172 std->len = 0; 2173 2174 value = UGETW(std->req.wValue); 2175 index = UGETW(std->req.wIndex); 2176 2177 use_polling = mtx_owned(xfer->xroot->xfer_mtx) ? 1 : 0; 2178 2179 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2180 "wValue=0x%04x wIndex=0x%04x\n", 2181 std->req.bmRequestType, std->req.bRequest, 2182 UGETW(std->req.wLength), value, index); 2183 2184#define C(x,y) ((x) | ((y) << 8)) 2185 switch (C(std->req.bRequest, std->req.bmRequestType)) { 2186 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2187 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2188 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2189 /* 2190 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2191 * for the integrated root hub. 2192 */ 2193 break; 2194 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2195 std->len = 1; 2196 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2197 break; 2198 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2199 switch (value >> 8) { 2200 case UDESC_DEVICE: 2201 if ((value & 0xff) != 0) { 2202 std->err = USB_ERR_IOERROR; 2203 goto done; 2204 } 2205 std->len = sizeof(ohci_devd); 2206 sc->sc_hub_desc.devd = ohci_devd; 2207 break; 2208 2209 case UDESC_CONFIG: 2210 if ((value & 0xff) != 0) { 2211 std->err = USB_ERR_IOERROR; 2212 goto done; 2213 } 2214 std->len = sizeof(ohci_confd); 2215 std->ptr = USB_ADD_BYTES(&ohci_confd, 0); 2216 break; 2217 2218 case UDESC_STRING: 2219 switch (value & 0xff) { 2220 case 0: /* Language table */ 2221 ptr = "\001"; 2222 break; 2223 2224 case 1: /* Vendor */ 2225 ptr = sc->sc_vendor; 2226 break; 2227 2228 case 2: /* Product */ 2229 ptr = "OHCI root HUB"; 2230 break; 2231 2232 default: 2233 ptr = ""; 2234 break; 2235 } 2236 2237 std->len = usb2_make_str_desc 2238 (sc->sc_hub_desc.temp, 2239 sizeof(sc->sc_hub_desc.temp), 2240 ptr); 2241 break; 2242 2243 default: 2244 std->err = USB_ERR_IOERROR; 2245 goto done; 2246 } 2247 break; 2248 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2249 std->len = 1; 2250 sc->sc_hub_desc.temp[0] = 0; 2251 break; 2252 case C(UR_GET_STATUS, UT_READ_DEVICE): 2253 std->len = 2; 2254 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2255 break; 2256 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2257 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2258 std->len = 2; 2259 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2260 break; 2261 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2262 if (value >= USB_MAX_DEVICES) { 2263 std->err = USB_ERR_IOERROR; 2264 goto done; 2265 } 2266 sc->sc_addr = value; 2267 break; 2268 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2269 if ((value != 0) && (value != 1)) { 2270 std->err = USB_ERR_IOERROR; 2271 goto done; 2272 } 2273 sc->sc_conf = value; 2274 break; 2275 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2276 break; 2277 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2278 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2279 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2280 std->err = USB_ERR_IOERROR; 2281 goto done; 2282 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2283 break; 2284 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2285 break; 2286 /* Hub requests */ 2287 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2288 break; 2289 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2290 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE " 2291 "port=%d feature=%d\n", 2292 index, value); 2293 if ((index < 1) || 2294 (index > sc->sc_noport)) { 2295 std->err = USB_ERR_IOERROR; 2296 goto done; 2297 } 2298 port = OHCI_RH_PORT_STATUS(index); 2299 switch (value) { 2300 case UHF_PORT_ENABLE: 2301 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2302 break; 2303 case UHF_PORT_SUSPEND: 2304 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2305 break; 2306 case UHF_PORT_POWER: 2307 /* Yes, writing to the LOW_SPEED bit clears power. */ 2308 OWRITE4(sc, port, UPS_LOW_SPEED); 2309 break; 2310 case UHF_C_PORT_CONNECTION: 2311 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2312 break; 2313 case UHF_C_PORT_ENABLE: 2314 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2315 break; 2316 case UHF_C_PORT_SUSPEND: 2317 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2318 break; 2319 case UHF_C_PORT_OVER_CURRENT: 2320 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2321 break; 2322 case UHF_C_PORT_RESET: 2323 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2324 break; 2325 default: 2326 std->err = USB_ERR_IOERROR; 2327 goto done; 2328 } 2329 switch (value) { 2330 case UHF_C_PORT_CONNECTION: 2331 case UHF_C_PORT_ENABLE: 2332 case UHF_C_PORT_SUSPEND: 2333 case UHF_C_PORT_OVER_CURRENT: 2334 case UHF_C_PORT_RESET: 2335 /* enable RHSC interrupt if condition is cleared. */ 2336 if ((OREAD4(sc, port) >> 16) == 0) 2337 ohci_rhsc_enable(sc); 2338 break; 2339 default: 2340 break; 2341 } 2342 break; 2343 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2344 if ((value & 0xff) != 0) { 2345 std->err = USB_ERR_IOERROR; 2346 goto done; 2347 } 2348 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2349 2350 sc->sc_hub_desc.hubd = ohci_hubd; 2351 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 2352 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, 2353 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2354 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2355 /* XXX overcurrent */ 2356 ); 2357 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2358 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2359 2360 for (l = 0; l < sc->sc_noport; l++) { 2361 if (v & 1) { 2362 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] |= (1 << (l % 8)); 2363 } 2364 v >>= 1; 2365 } 2366 sc->sc_hub_desc.hubd.bDescLength = 2367 8 + ((sc->sc_noport + 7) / 8); 2368 std->len = sc->sc_hub_desc.hubd.bDescLength; 2369 break; 2370 2371 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2372 std->len = 16; 2373 bzero(sc->sc_hub_desc.temp, 16); 2374 break; 2375 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2376 DPRINTFN(9, "get port status i=%d\n", 2377 index); 2378 if ((index < 1) || 2379 (index > sc->sc_noport)) { 2380 std->err = USB_ERR_IOERROR; 2381 goto done; 2382 } 2383 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2384 DPRINTFN(9, "port status=0x%04x\n", v); 2385 USETW(sc->sc_hub_desc.ps.wPortStatus, v); 2386 USETW(sc->sc_hub_desc.ps.wPortChange, v >> 16); 2387 std->len = sizeof(sc->sc_hub_desc.ps); 2388 break; 2389 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2390 std->err = USB_ERR_IOERROR; 2391 goto done; 2392 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2393 break; 2394 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2395 if ((index < 1) || 2396 (index > sc->sc_noport)) { 2397 std->err = USB_ERR_IOERROR; 2398 goto done; 2399 } 2400 port = OHCI_RH_PORT_STATUS(index); 2401 switch (value) { 2402 case UHF_PORT_ENABLE: 2403 OWRITE4(sc, port, UPS_PORT_ENABLED); 2404 break; 2405 case UHF_PORT_SUSPEND: 2406 OWRITE4(sc, port, UPS_SUSPEND); 2407 break; 2408 case UHF_PORT_RESET: 2409 DPRINTFN(6, "reset port %d\n", index); 2410 OWRITE4(sc, port, UPS_RESET); 2411 for (v = 0;; v++) { 2412 if (v < 12) { 2413 if (use_polling) { 2414 /* polling */ 2415 DELAY(USB_PORT_ROOT_RESET_DELAY * 1000); 2416 } else { 2417 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 2418 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY)); 2419 } 2420 2421 if ((OREAD4(sc, port) & UPS_RESET) == 0) { 2422 break; 2423 } 2424 } else { 2425 std->err = USB_ERR_TIMEOUT; 2426 goto done; 2427 } 2428 } 2429 DPRINTFN(9, "ohci port %d reset, status = 0x%04x\n", 2430 index, OREAD4(sc, port)); 2431 break; 2432 case UHF_PORT_POWER: 2433 DPRINTFN(3, "set port power %d\n", index); 2434 OWRITE4(sc, port, UPS_PORT_POWER); 2435 break; 2436 default: 2437 std->err = USB_ERR_IOERROR; 2438 goto done; 2439 } 2440 break; 2441 default: 2442 std->err = USB_ERR_IOERROR; 2443 goto done; 2444 } 2445done: 2446 return; 2447} 2448 2449static void 2450ohci_root_ctrl_poll(struct ohci_softc *sc) 2451{ 2452 usb2_sw_transfer(&sc->sc_root_ctrl, 2453 &ohci_root_ctrl_done); 2454} 2455 2456struct usb2_pipe_methods ohci_root_ctrl_methods = 2457{ 2458 .open = ohci_root_ctrl_open, 2459 .close = ohci_root_ctrl_close, 2460 .enter = ohci_root_ctrl_enter, 2461 .start = ohci_root_ctrl_start, 2462 .enter_is_cancelable = 1, 2463 .start_is_cancelable = 0, 2464}; 2465 2466/*------------------------------------------------------------------------* 2467 * ohci root interrupt support 2468 *------------------------------------------------------------------------*/ 2469static void 2470ohci_root_intr_open(struct usb2_xfer *xfer) 2471{ 2472 return; 2473} 2474 2475static void 2476ohci_root_intr_close(struct usb2_xfer *xfer) 2477{ 2478 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 2479 2480 if (sc->sc_root_intr.xfer == xfer) { 2481 sc->sc_root_intr.xfer = NULL; 2482 } 2483 ohci_device_done(xfer, USB_ERR_CANCELLED); 2484} 2485 2486static void 2487ohci_root_intr_enter(struct usb2_xfer *xfer) 2488{ 2489 return; 2490} 2491 2492static void 2493ohci_root_intr_start(struct usb2_xfer *xfer) 2494{ 2495 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 2496 2497 sc->sc_root_intr.xfer = xfer; 2498} 2499 2500struct usb2_pipe_methods ohci_root_intr_methods = 2501{ 2502 .open = ohci_root_intr_open, 2503 .close = ohci_root_intr_close, 2504 .enter = ohci_root_intr_enter, 2505 .start = ohci_root_intr_start, 2506 .enter_is_cancelable = 1, 2507 .start_is_cancelable = 1, 2508}; 2509 2510static void 2511ohci_xfer_setup(struct usb2_setup_params *parm) 2512{ 2513 struct usb2_page_search page_info; 2514 struct usb2_page_cache *pc; 2515 ohci_softc_t *sc; 2516 struct usb2_xfer *xfer; 2517 void *last_obj; 2518 uint32_t ntd; 2519 uint32_t nitd; 2520 uint32_t nqh; 2521 uint32_t n; 2522 2523 sc = OHCI_BUS2SC(parm->udev->bus); 2524 xfer = parm->curr_xfer; 2525 2526 parm->hc_max_packet_size = 0x500; 2527 parm->hc_max_packet_count = 1; 2528 parm->hc_max_frame_size = OHCI_PAGE_SIZE; 2529 2530 /* 2531 * calculate ntd and nqh 2532 */ 2533 if (parm->methods == &ohci_device_ctrl_methods) { 2534 xfer->flags_int.bdma_enable = 1; 2535 2536 usb2_transfer_setup_sub(parm); 2537 2538 nitd = 0; 2539 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2540 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 2541 nqh = 1; 2542 2543 } else if (parm->methods == &ohci_device_bulk_methods) { 2544 xfer->flags_int.bdma_enable = 1; 2545 2546 usb2_transfer_setup_sub(parm); 2547 2548 nitd = 0; 2549 ntd = ((2 * xfer->nframes) 2550 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 2551 nqh = 1; 2552 2553 } else if (parm->methods == &ohci_device_intr_methods) { 2554 xfer->flags_int.bdma_enable = 1; 2555 2556 usb2_transfer_setup_sub(parm); 2557 2558 nitd = 0; 2559 ntd = ((2 * xfer->nframes) 2560 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 2561 nqh = 1; 2562 2563 } else if (parm->methods == &ohci_device_isoc_methods) { 2564 xfer->flags_int.bdma_enable = 1; 2565 2566 usb2_transfer_setup_sub(parm); 2567 2568 nitd = ((xfer->max_data_length / OHCI_PAGE_SIZE) + 2569 ((xfer->nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET) + 2570 1 /* EXTRA */ ); 2571 ntd = 0; 2572 nqh = 1; 2573 2574 } else { 2575 2576 usb2_transfer_setup_sub(parm); 2577 2578 nitd = 0; 2579 ntd = 0; 2580 nqh = 0; 2581 } 2582 2583alloc_dma_set: 2584 2585 if (parm->err) { 2586 return; 2587 } 2588 last_obj = NULL; 2589 2590 if (usb2_transfer_setup_sub_malloc( 2591 parm, &pc, sizeof(ohci_td_t), 2592 OHCI_TD_ALIGN, ntd)) { 2593 parm->err = USB_ERR_NOMEM; 2594 return; 2595 } 2596 if (parm->buf) { 2597 for (n = 0; n != ntd; n++) { 2598 ohci_td_t *td; 2599 2600 usb2_get_page(pc + n, 0, &page_info); 2601 2602 td = page_info.buffer; 2603 2604 /* init TD */ 2605 td->td_self = htole32(page_info.physaddr); 2606 td->obj_next = last_obj; 2607 td->page_cache = pc + n; 2608 2609 last_obj = td; 2610 2611 usb2_pc_cpu_flush(pc + n); 2612 } 2613 } 2614 if (usb2_transfer_setup_sub_malloc( 2615 parm, &pc, sizeof(ohci_itd_t), 2616 OHCI_ITD_ALIGN, nitd)) { 2617 parm->err = USB_ERR_NOMEM; 2618 return; 2619 } 2620 if (parm->buf) { 2621 for (n = 0; n != nitd; n++) { 2622 ohci_itd_t *itd; 2623 2624 usb2_get_page(pc + n, 0, &page_info); 2625 2626 itd = page_info.buffer; 2627 2628 /* init TD */ 2629 itd->itd_self = htole32(page_info.physaddr); 2630 itd->obj_next = last_obj; 2631 itd->page_cache = pc + n; 2632 2633 last_obj = itd; 2634 2635 usb2_pc_cpu_flush(pc + n); 2636 } 2637 } 2638 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2639 2640 last_obj = NULL; 2641 2642 if (usb2_transfer_setup_sub_malloc( 2643 parm, &pc, sizeof(ohci_ed_t), 2644 OHCI_ED_ALIGN, nqh)) { 2645 parm->err = USB_ERR_NOMEM; 2646 return; 2647 } 2648 if (parm->buf) { 2649 for (n = 0; n != nqh; n++) { 2650 ohci_ed_t *ed; 2651 2652 usb2_get_page(pc + n, 0, &page_info); 2653 2654 ed = page_info.buffer; 2655 2656 /* init QH */ 2657 ed->ed_self = htole32(page_info.physaddr); 2658 ed->obj_next = last_obj; 2659 ed->page_cache = pc + n; 2660 2661 last_obj = ed; 2662 2663 usb2_pc_cpu_flush(pc + n); 2664 } 2665 } 2666 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 2667 2668 if (!xfer->flags_int.curr_dma_set) { 2669 xfer->flags_int.curr_dma_set = 1; 2670 goto alloc_dma_set; 2671 } 2672} 2673 2674static void 2675ohci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2676 struct usb2_pipe *pipe) 2677{ 2678 ohci_softc_t *sc = OHCI_BUS2SC(udev->bus); 2679 2680 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2681 pipe, udev->address, 2682 edesc->bEndpointAddress, udev->flags.usb2_mode, 2683 sc->sc_addr); 2684 2685 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2686 /* not supported */ 2687 return; 2688 } 2689 if (udev->device_index == sc->sc_addr) { 2690 switch (edesc->bEndpointAddress) { 2691 case USB_CONTROL_ENDPOINT: 2692 pipe->methods = &ohci_root_ctrl_methods; 2693 break; 2694 case UE_DIR_IN | OHCI_INTR_ENDPT: 2695 pipe->methods = &ohci_root_intr_methods; 2696 break; 2697 default: 2698 /* do nothing */ 2699 break; 2700 } 2701 } else { 2702 switch (edesc->bmAttributes & UE_XFERTYPE) { 2703 case UE_CONTROL: 2704 pipe->methods = &ohci_device_ctrl_methods; 2705 break; 2706 case UE_INTERRUPT: 2707 pipe->methods = &ohci_device_intr_methods; 2708 break; 2709 case UE_ISOCHRONOUS: 2710 if (udev->speed == USB_SPEED_FULL) { 2711 pipe->methods = &ohci_device_isoc_methods; 2712 } 2713 break; 2714 case UE_BULK: 2715 if (udev->speed != USB_SPEED_LOW) { 2716 pipe->methods = &ohci_device_bulk_methods; 2717 } 2718 break; 2719 default: 2720 /* do nothing */ 2721 break; 2722 } 2723 } 2724} 2725 2726static void 2727ohci_xfer_unsetup(struct usb2_xfer *xfer) 2728{ 2729 return; 2730} 2731 2732static void 2733ohci_get_dma_delay(struct usb2_bus *bus, uint32_t *pus) 2734{ 2735 /* 2736 * Wait until hardware has finished any possible use of the 2737 * transfer descriptor(s) and QH 2738 */ 2739 *pus = (1125); /* microseconds */ 2740} 2741 2742static void 2743ohci_device_resume(struct usb2_device *udev) 2744{ 2745 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2746 struct usb2_xfer *xfer; 2747 struct usb2_pipe_methods *methods; 2748 ohci_ed_t *ed; 2749 2750 DPRINTF("\n"); 2751 2752 USB_BUS_LOCK(udev->bus); 2753 2754 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2755 2756 if (xfer->xroot->udev == udev) { 2757 2758 methods = xfer->pipe->methods; 2759 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2760 2761 if (methods == &ohci_device_bulk_methods) { 2762 OHCI_APPEND_QH(ed, sc->sc_bulk_p_last); 2763 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2764 } 2765 if (methods == &ohci_device_ctrl_methods) { 2766 OHCI_APPEND_QH(ed, sc->sc_ctrl_p_last); 2767 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2768 } 2769 if (methods == &ohci_device_intr_methods) { 2770 OHCI_APPEND_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2771 } 2772 } 2773 } 2774 2775 USB_BUS_UNLOCK(udev->bus); 2776 2777 return; 2778} 2779 2780static void 2781ohci_device_suspend(struct usb2_device *udev) 2782{ 2783 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2784 struct usb2_xfer *xfer; 2785 struct usb2_pipe_methods *methods; 2786 ohci_ed_t *ed; 2787 2788 DPRINTF("\n"); 2789 2790 USB_BUS_LOCK(udev->bus); 2791 2792 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2793 2794 if (xfer->xroot->udev == udev) { 2795 2796 methods = xfer->pipe->methods; 2797 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2798 2799 if (methods == &ohci_device_bulk_methods) { 2800 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 2801 } 2802 if (methods == &ohci_device_ctrl_methods) { 2803 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 2804 } 2805 if (methods == &ohci_device_intr_methods) { 2806 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2807 } 2808 } 2809 } 2810 2811 USB_BUS_UNLOCK(udev->bus); 2812 2813 return; 2814} 2815 2816static void 2817ohci_set_hw_power(struct usb2_bus *bus) 2818{ 2819 struct ohci_softc *sc = OHCI_BUS2SC(bus); 2820 uint32_t temp; 2821 uint32_t flags; 2822 2823 DPRINTF("\n"); 2824 2825 USB_BUS_LOCK(bus); 2826 2827 flags = bus->hw_power_state; 2828 2829 temp = OREAD4(sc, OHCI_CONTROL); 2830 temp &= ~(OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE); 2831 2832 if (flags & USB_HW_POWER_CONTROL) 2833 temp |= OHCI_CLE; 2834 2835 if (flags & USB_HW_POWER_BULK) 2836 temp |= OHCI_BLE; 2837 2838 if (flags & USB_HW_POWER_INTERRUPT) 2839 temp |= OHCI_PLE; 2840 2841 if (flags & USB_HW_POWER_ISOC) 2842 temp |= OHCI_IE | OHCI_PLE; 2843 2844 OWRITE4(sc, OHCI_CONTROL, temp); 2845 2846 USB_BUS_UNLOCK(bus); 2847 2848 return; 2849} 2850 2851struct usb2_bus_methods ohci_bus_methods = 2852{ 2853 .pipe_init = ohci_pipe_init, 2854 .xfer_setup = ohci_xfer_setup, 2855 .xfer_unsetup = ohci_xfer_unsetup, 2856 .do_poll = ohci_do_poll, 2857 .get_dma_delay = ohci_get_dma_delay, 2858 .device_resume = ohci_device_resume, 2859 .device_suspend = ohci_device_suspend, 2860 .set_hw_power = ohci_set_hw_power, 2861 .roothub_exec = ohci_root_ctrl_task, 2862}; 2863