ohci.c revision 188273
1/*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/usb2/controller/ohci2.c 188273 2009-02-07 06:27:16Z thompsa $"); 30 31/* 32 * USB Open Host Controller driver. 33 * 34 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 35 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 36 */ 37 38#include <dev/usb2/include/usb2_standard.h> 39#include <dev/usb2/include/usb2_mfunc.h> 40#include <dev/usb2/include/usb2_error.h> 41#include <dev/usb2/include/usb2_defs.h> 42 43#define USB_DEBUG_VAR ohcidebug 44 45#include <dev/usb2/core/usb2_core.h> 46#include <dev/usb2/core/usb2_debug.h> 47#include <dev/usb2/core/usb2_busdma.h> 48#include <dev/usb2/core/usb2_process.h> 49#include <dev/usb2/core/usb2_sw_transfer.h> 50#include <dev/usb2/core/usb2_transfer.h> 51#include <dev/usb2/core/usb2_device.h> 52#include <dev/usb2/core/usb2_hub.h> 53#include <dev/usb2/core/usb2_util.h> 54 55#include <dev/usb2/controller/usb2_controller.h> 56#include <dev/usb2/controller/usb2_bus.h> 57#include <dev/usb2/controller/ohci2.h> 58 59#define OHCI_BUS2SC(bus) ((ohci_softc_t *)(((uint8_t *)(bus)) - \ 60 USB_P2U(&(((ohci_softc_t *)0)->sc_bus)))) 61 62#if USB_DEBUG 63static int ohcidebug = 0; 64 65SYSCTL_NODE(_hw_usb2, OID_AUTO, ohci, CTLFLAG_RW, 0, "USB ohci"); 66SYSCTL_INT(_hw_usb2_ohci, OID_AUTO, debug, CTLFLAG_RW, 67 &ohcidebug, 0, "ohci debug level"); 68static void ohci_dumpregs(ohci_softc_t *); 69static void ohci_dump_tds(ohci_td_t *); 70static uint8_t ohci_dump_td(ohci_td_t *); 71static void ohci_dump_ed(ohci_ed_t *); 72static uint8_t ohci_dump_itd(ohci_itd_t *); 73static void ohci_dump_itds(ohci_itd_t *); 74 75#endif 76 77#define OBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 78 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 79#define OWRITE1(sc, r, x) \ 80 do { OBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 81#define OWRITE2(sc, r, x) \ 82 do { OBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 83#define OWRITE4(sc, r, x) \ 84 do { OBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 85#define OREAD1(sc, r) (OBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 86#define OREAD2(sc, r) (OBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 87#define OREAD4(sc, r) (OBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 88 89#define OHCI_INTR_ENDPT 1 90 91extern struct usb2_bus_methods ohci_bus_methods; 92extern struct usb2_pipe_methods ohci_device_bulk_methods; 93extern struct usb2_pipe_methods ohci_device_ctrl_methods; 94extern struct usb2_pipe_methods ohci_device_intr_methods; 95extern struct usb2_pipe_methods ohci_device_isoc_methods; 96extern struct usb2_pipe_methods ohci_root_ctrl_methods; 97extern struct usb2_pipe_methods ohci_root_intr_methods; 98 99static void ohci_root_ctrl_poll(struct ohci_softc *sc); 100static void ohci_do_poll(struct usb2_bus *bus); 101static void ohci_device_done(struct usb2_xfer *xfer, usb2_error_t error); 102 103static usb2_sw_transfer_func_t ohci_root_intr_done; 104static usb2_sw_transfer_func_t ohci_root_ctrl_done; 105static void ohci_timeout(void *arg); 106static uint8_t ohci_check_transfer(struct usb2_xfer *xfer); 107 108struct ohci_std_temp { 109 struct usb2_page_cache *pc; 110 ohci_td_t *td; 111 ohci_td_t *td_next; 112 uint32_t average; 113 uint32_t td_flags; 114 uint32_t len; 115 uint16_t max_frame_size; 116 uint8_t shortpkt; 117 uint8_t setup_alt_next; 118 uint8_t short_frames_ok; 119}; 120 121static struct ohci_hcca * 122ohci_get_hcca(ohci_softc_t *sc) 123{ 124 usb2_pc_cpu_invalidate(&sc->sc_hw.hcca_pc); 125 return (sc->sc_hcca_p); 126} 127 128void 129ohci_iterate_hw_softc(struct usb2_bus *bus, usb2_bus_mem_sub_cb_t *cb) 130{ 131 struct ohci_softc *sc = OHCI_BUS2SC(bus); 132 uint32_t i; 133 134 cb(bus, &sc->sc_hw.hcca_pc, &sc->sc_hw.hcca_pg, 135 sizeof(ohci_hcca_t), OHCI_HCCA_ALIGN); 136 137 cb(bus, &sc->sc_hw.ctrl_start_pc, &sc->sc_hw.ctrl_start_pg, 138 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 139 140 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 141 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 142 143 cb(bus, &sc->sc_hw.isoc_start_pc, &sc->sc_hw.isoc_start_pg, 144 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 145 146 for (i = 0; i != OHCI_NO_EDS; i++) { 147 cb(bus, sc->sc_hw.intr_start_pc + i, sc->sc_hw.intr_start_pg + i, 148 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 149 } 150} 151 152static usb2_error_t 153ohci_controller_init(ohci_softc_t *sc) 154{ 155 struct usb2_page_search buf_res; 156 uint32_t i; 157 uint32_t ctl; 158 uint32_t ival; 159 uint32_t hcr; 160 uint32_t fm; 161 uint32_t per; 162 uint32_t desca; 163 164 /* Determine in what context we are running. */ 165 ctl = OREAD4(sc, OHCI_CONTROL); 166 if (ctl & OHCI_IR) { 167 /* SMM active, request change */ 168 DPRINTF("SMM active, request owner change\n"); 169 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_OCR); 170 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 171 usb2_pause_mtx(NULL, 1); 172 ctl = OREAD4(sc, OHCI_CONTROL); 173 } 174 if (ctl & OHCI_IR) { 175 device_printf(sc->sc_bus.bdev, 176 "SMM does not respond, resetting\n"); 177 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 178 goto reset; 179 } 180 } else { 181 DPRINTF("cold started\n"); 182reset: 183 /* controller was cold started */ 184 usb2_pause_mtx(NULL, USB_BUS_RESET_DELAY); 185 } 186 187 /* 188 * This reset should not be necessary according to the OHCI spec, but 189 * without it some controllers do not start. 190 */ 191 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 192 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 193 194 usb2_pause_mtx(NULL, USB_BUS_RESET_DELAY); 195 196 /* we now own the host controller and the bus has been reset */ 197 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL)); 198 199 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 200 /* nominal time for a reset is 10 us */ 201 for (i = 0; i < 10; i++) { 202 DELAY(10); 203 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 204 if (!hcr) { 205 break; 206 } 207 } 208 if (hcr) { 209 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 210 return (USB_ERR_IOERROR); 211 } 212#if USB_DEBUG 213 if (ohcidebug > 15) { 214 ohci_dumpregs(sc); 215 } 216#endif 217 218 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 219 220 /* set up HC registers */ 221 usb2_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 222 OWRITE4(sc, OHCI_HCCA, buf_res.physaddr); 223 224 usb2_get_page(&sc->sc_hw.ctrl_start_pc, 0, &buf_res); 225 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, buf_res.physaddr); 226 227 usb2_get_page(&sc->sc_hw.bulk_start_pc, 0, &buf_res); 228 OWRITE4(sc, OHCI_BULK_HEAD_ED, buf_res.physaddr); 229 230 /* disable all interrupts and then switch on all desired interrupts */ 231 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 232 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 233 /* switch on desired functional features */ 234 ctl = OREAD4(sc, OHCI_CONTROL); 235 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 236 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 237 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL; 238 /* And finally start it! */ 239 OWRITE4(sc, OHCI_CONTROL, ctl); 240 241 /* 242 * The controller is now OPERATIONAL. Set a some final 243 * registers that should be set earlier, but that the 244 * controller ignores when in the SUSPEND state. 245 */ 246 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 247 fm |= OHCI_FSMPS(ival) | ival; 248 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 249 per = OHCI_PERIODIC(ival); /* 90% periodic */ 250 OWRITE4(sc, OHCI_PERIODIC_START, per); 251 252 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 253 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 254 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 255 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 256 usb2_pause_mtx(NULL, OHCI_ENABLE_POWER_DELAY); 257 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 258 259 /* 260 * The AMD756 requires a delay before re-reading the register, 261 * otherwise it will occasionally report 0 ports. 262 */ 263 sc->sc_noport = 0; 264 for (i = 0; (i < 10) && (sc->sc_noport == 0); i++) { 265 usb2_pause_mtx(NULL, OHCI_READ_DESC_DELAY); 266 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 267 } 268 269#if USB_DEBUG 270 if (ohcidebug > 5) { 271 ohci_dumpregs(sc); 272 } 273#endif 274 return (USB_ERR_NORMAL_COMPLETION); 275} 276 277static struct ohci_ed * 278ohci_init_ed(struct usb2_page_cache *pc) 279{ 280 struct usb2_page_search buf_res; 281 struct ohci_ed *ed; 282 283 usb2_get_page(pc, 0, &buf_res); 284 285 ed = buf_res.buffer; 286 287 ed->ed_self = htole32(buf_res.physaddr); 288 ed->ed_flags = htole32(OHCI_ED_SKIP); 289 ed->page_cache = pc; 290 291 return (ed); 292} 293 294usb2_error_t 295ohci_init(ohci_softc_t *sc) 296{ 297 struct usb2_page_search buf_res; 298 uint16_t i; 299 uint16_t bit; 300 uint16_t x; 301 uint16_t y; 302 303 DPRINTF("start\n"); 304 305 sc->sc_eintrs = OHCI_NORMAL_INTRS; 306 307 /* 308 * Setup all ED's 309 */ 310 311 sc->sc_ctrl_p_last = 312 ohci_init_ed(&sc->sc_hw.ctrl_start_pc); 313 314 sc->sc_bulk_p_last = 315 ohci_init_ed(&sc->sc_hw.bulk_start_pc); 316 317 sc->sc_isoc_p_last = 318 ohci_init_ed(&sc->sc_hw.isoc_start_pc); 319 320 for (i = 0; i != OHCI_NO_EDS; i++) { 321 sc->sc_intr_p_last[i] = 322 ohci_init_ed(sc->sc_hw.intr_start_pc + i); 323 } 324 325 /* 326 * the QHs are arranged to give poll intervals that are 327 * powers of 2 times 1ms 328 */ 329 bit = OHCI_NO_EDS / 2; 330 while (bit) { 331 x = bit; 332 while (x & bit) { 333 ohci_ed_t *ed_x; 334 ohci_ed_t *ed_y; 335 336 y = (x ^ bit) | (bit / 2); 337 338 /* 339 * the next QH has half the poll interval 340 */ 341 ed_x = sc->sc_intr_p_last[x]; 342 ed_y = sc->sc_intr_p_last[y]; 343 344 ed_x->next = NULL; 345 ed_x->ed_next = ed_y->ed_self; 346 347 x++; 348 } 349 bit >>= 1; 350 } 351 352 if (1) { 353 354 ohci_ed_t *ed_int; 355 ohci_ed_t *ed_isc; 356 357 ed_int = sc->sc_intr_p_last[0]; 358 ed_isc = sc->sc_isoc_p_last; 359 360 /* the last (1ms) QH */ 361 ed_int->next = ed_isc; 362 ed_int->ed_next = ed_isc->ed_self; 363 } 364 usb2_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 365 366 sc->sc_hcca_p = buf_res.buffer; 367 368 /* 369 * Fill HCCA interrupt table. The bit reversal is to get 370 * the tree set up properly to spread the interrupts. 371 */ 372 for (i = 0; i != OHCI_NO_INTRS; i++) { 373 sc->sc_hcca_p->hcca_interrupt_table[i] = 374 sc->sc_intr_p_last[i | (OHCI_NO_EDS / 2)]->ed_self; 375 } 376 /* flush all cache into memory */ 377 378 usb2_bus_mem_flush_all(&sc->sc_bus, &ohci_iterate_hw_softc); 379 380 /* set up the bus struct */ 381 sc->sc_bus.methods = &ohci_bus_methods; 382 383 usb2_callout_init_mtx(&sc->sc_tmo_rhsc, &sc->sc_bus.bus_mtx, 0); 384 385#if USB_DEBUG 386 if (ohcidebug > 15) { 387 for (i = 0; i != OHCI_NO_EDS; i++) { 388 printf("ed#%d ", i); 389 ohci_dump_ed(sc->sc_intr_p_last[i]); 390 } 391 printf("iso "); 392 ohci_dump_ed(sc->sc_isoc_p_last); 393 } 394#endif 395 396 sc->sc_bus.usbrev = USB_REV_1_0; 397 398 if (ohci_controller_init(sc)) { 399 return (USB_ERR_INVAL); 400 } else { 401 /* catch any lost interrupts */ 402 ohci_do_poll(&sc->sc_bus); 403 return (USB_ERR_NORMAL_COMPLETION); 404 } 405} 406 407/* 408 * shut down the controller when the system is going down 409 */ 410void 411ohci_detach(struct ohci_softc *sc) 412{ 413 USB_BUS_LOCK(&sc->sc_bus); 414 415 usb2_callout_stop(&sc->sc_tmo_rhsc); 416 417 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 418 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 419 420 /* XXX let stray task complete */ 421 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 50); 422 423 USB_BUS_UNLOCK(&sc->sc_bus); 424 425 usb2_callout_drain(&sc->sc_tmo_rhsc); 426} 427 428/* NOTE: suspend/resume is called from 429 * interrupt context and cannot sleep! 430 */ 431void 432ohci_suspend(ohci_softc_t *sc) 433{ 434 uint32_t ctl; 435 436 USB_BUS_LOCK(&sc->sc_bus); 437 438#if USB_DEBUG 439 DPRINTF("\n"); 440 if (ohcidebug > 2) { 441 ohci_dumpregs(sc); 442 } 443#endif 444 445 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 446 if (sc->sc_control == 0) { 447 /* 448 * Preserve register values, in case that APM BIOS 449 * does not recover them. 450 */ 451 sc->sc_control = ctl; 452 sc->sc_intre = OREAD4(sc, OHCI_INTERRUPT_ENABLE); 453 } 454 ctl |= OHCI_HCFS_SUSPEND; 455 OWRITE4(sc, OHCI_CONTROL, ctl); 456 457 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 458 USB_RESUME_WAIT); 459 460 USB_BUS_UNLOCK(&sc->sc_bus); 461} 462 463void 464ohci_resume(ohci_softc_t *sc) 465{ 466 uint32_t ctl; 467 468#if USB_DEBUG 469 DPRINTF("\n"); 470 if (ohcidebug > 2) { 471 ohci_dumpregs(sc); 472 } 473#endif 474 /* some broken BIOSes never initialize the Controller chip */ 475 ohci_controller_init(sc); 476 477 USB_BUS_LOCK(&sc->sc_bus); 478 if (sc->sc_intre) { 479 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, 480 sc->sc_intre & (OHCI_ALL_INTRS | OHCI_MIE)); 481 } 482 if (sc->sc_control) 483 ctl = sc->sc_control; 484 else 485 ctl = OREAD4(sc, OHCI_CONTROL); 486 ctl |= OHCI_HCFS_RESUME; 487 OWRITE4(sc, OHCI_CONTROL, ctl); 488 usb2_pause_mtx(&sc->sc_bus.bus_mtx, USB_RESUME_DELAY); 489 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 490 OWRITE4(sc, OHCI_CONTROL, ctl); 491 usb2_pause_mtx(&sc->sc_bus.bus_mtx, USB_RESUME_RECOVERY); 492 sc->sc_control = sc->sc_intre = 0; 493 494 USB_BUS_UNLOCK(&sc->sc_bus); 495 496 /* catch any lost interrupts */ 497 ohci_do_poll(&sc->sc_bus); 498} 499 500#if USB_DEBUG 501static void 502ohci_dumpregs(ohci_softc_t *sc) 503{ 504 struct ohci_hcca *hcca; 505 506 DPRINTF("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 507 OREAD4(sc, OHCI_REVISION), 508 OREAD4(sc, OHCI_CONTROL), 509 OREAD4(sc, OHCI_COMMAND_STATUS)); 510 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 511 OREAD4(sc, OHCI_INTERRUPT_STATUS), 512 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 513 OREAD4(sc, OHCI_INTERRUPT_DISABLE)); 514 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 515 OREAD4(sc, OHCI_HCCA), 516 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 517 OREAD4(sc, OHCI_CONTROL_HEAD_ED)); 518 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 519 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 520 OREAD4(sc, OHCI_BULK_HEAD_ED), 521 OREAD4(sc, OHCI_BULK_CURRENT_ED)); 522 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 523 OREAD4(sc, OHCI_DONE_HEAD), 524 OREAD4(sc, OHCI_FM_INTERVAL), 525 OREAD4(sc, OHCI_FM_REMAINING)); 526 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 527 OREAD4(sc, OHCI_FM_NUMBER), 528 OREAD4(sc, OHCI_PERIODIC_START), 529 OREAD4(sc, OHCI_LS_THRESHOLD)); 530 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x\n", 531 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 532 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 533 OREAD4(sc, OHCI_RH_STATUS)); 534 DPRINTF(" port1=0x%08x port2=0x%08x\n", 535 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 536 OREAD4(sc, OHCI_RH_PORT_STATUS(2))); 537 538 hcca = ohci_get_hcca(sc); 539 540 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x\n", 541 le32toh(hcca->hcca_frame_number), 542 le32toh(hcca->hcca_done_head)); 543} 544static void 545ohci_dump_tds(ohci_td_t *std) 546{ 547 for (; std; std = std->obj_next) { 548 if (ohci_dump_td(std)) { 549 break; 550 } 551 } 552} 553 554static uint8_t 555ohci_dump_td(ohci_td_t *std) 556{ 557 uint32_t td_flags; 558 uint8_t temp; 559 560 usb2_pc_cpu_invalidate(std->page_cache); 561 562 td_flags = le32toh(std->td_flags); 563 temp = (std->td_next == 0); 564 565 printf("TD(%p) at 0x%08x: %s%s%s%s%s delay=%d ec=%d " 566 "cc=%d\ncbp=0x%08x next=0x%08x be=0x%08x\n", 567 std, le32toh(std->td_self), 568 (td_flags & OHCI_TD_R) ? "-R" : "", 569 (td_flags & OHCI_TD_OUT) ? "-OUT" : "", 570 (td_flags & OHCI_TD_IN) ? "-IN" : "", 571 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_1) ? "-TOG1" : "", 572 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_0) ? "-TOG0" : "", 573 OHCI_TD_GET_DI(td_flags), 574 OHCI_TD_GET_EC(td_flags), 575 OHCI_TD_GET_CC(td_flags), 576 le32toh(std->td_cbp), 577 le32toh(std->td_next), 578 le32toh(std->td_be)); 579 580 return (temp); 581} 582 583static uint8_t 584ohci_dump_itd(ohci_itd_t *sitd) 585{ 586 uint32_t itd_flags; 587 uint16_t i; 588 uint8_t temp; 589 590 usb2_pc_cpu_invalidate(sitd->page_cache); 591 592 itd_flags = le32toh(sitd->itd_flags); 593 temp = (sitd->itd_next == 0); 594 595 printf("ITD(%p) at 0x%08x: sf=%d di=%d fc=%d cc=%d\n" 596 "bp0=0x%08x next=0x%08x be=0x%08x\n", 597 sitd, le32toh(sitd->itd_self), 598 OHCI_ITD_GET_SF(itd_flags), 599 OHCI_ITD_GET_DI(itd_flags), 600 OHCI_ITD_GET_FC(itd_flags), 601 OHCI_ITD_GET_CC(itd_flags), 602 le32toh(sitd->itd_bp0), 603 le32toh(sitd->itd_next), 604 le32toh(sitd->itd_be)); 605 for (i = 0; i < OHCI_ITD_NOFFSET; i++) { 606 printf("offs[%d]=0x%04x ", i, 607 (uint32_t)le16toh(sitd->itd_offset[i])); 608 } 609 printf("\n"); 610 611 return (temp); 612} 613 614static void 615ohci_dump_itds(ohci_itd_t *sitd) 616{ 617 for (; sitd; sitd = sitd->obj_next) { 618 if (ohci_dump_itd(sitd)) { 619 break; 620 } 621 } 622} 623 624static void 625ohci_dump_ed(ohci_ed_t *sed) 626{ 627 uint32_t ed_flags; 628 uint32_t ed_headp; 629 630 usb2_pc_cpu_invalidate(sed->page_cache); 631 632 ed_flags = le32toh(sed->ed_flags); 633 ed_headp = le32toh(sed->ed_headp); 634 635 printf("ED(%p) at 0x%08x: addr=%d endpt=%d maxp=%d flags=%s%s%s%s%s\n" 636 "tailp=0x%08x headflags=%s%s headp=0x%08x nexted=0x%08x\n", 637 sed, le32toh(sed->ed_self), 638 OHCI_ED_GET_FA(ed_flags), 639 OHCI_ED_GET_EN(ed_flags), 640 OHCI_ED_GET_MAXP(ed_flags), 641 (ed_flags & OHCI_ED_DIR_OUT) ? "-OUT" : "", 642 (ed_flags & OHCI_ED_DIR_IN) ? "-IN" : "", 643 (ed_flags & OHCI_ED_SPEED) ? "-LOWSPEED" : "", 644 (ed_flags & OHCI_ED_SKIP) ? "-SKIP" : "", 645 (ed_flags & OHCI_ED_FORMAT_ISO) ? "-ISO" : "", 646 le32toh(sed->ed_tailp), 647 (ed_headp & OHCI_HALTED) ? "-HALTED" : "", 648 (ed_headp & OHCI_TOGGLECARRY) ? "-CARRY" : "", 649 le32toh(sed->ed_headp), 650 le32toh(sed->ed_next)); 651} 652 653#endif 654 655static void 656ohci_transfer_intr_enqueue(struct usb2_xfer *xfer) 657{ 658 /* check for early completion */ 659 if (ohci_check_transfer(xfer)) { 660 return; 661 } 662 /* put transfer on interrupt queue */ 663 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 664 665 /* start timeout, if any */ 666 if (xfer->timeout != 0) { 667 usb2_transfer_timeout_ms(xfer, &ohci_timeout, xfer->timeout); 668 } 669} 670 671#define OHCI_APPEND_QH(sed,last) (last) = _ohci_append_qh(sed,last) 672static ohci_ed_t * 673_ohci_append_qh(ohci_ed_t *sed, ohci_ed_t *last) 674{ 675 DPRINTFN(11, "%p to %p\n", sed, last); 676 677 if (sed->prev != NULL) { 678 /* should not happen */ 679 DPRINTFN(0, "ED already linked!\n"); 680 return (last); 681 } 682 /* (sc->sc_bus.bus_mtx) must be locked */ 683 684 sed->next = last->next; 685 sed->ed_next = last->ed_next; 686 sed->ed_tailp = 0; 687 688 sed->prev = last; 689 690 usb2_pc_cpu_flush(sed->page_cache); 691 692 /* 693 * the last->next->prev is never followed: sed->next->prev = sed; 694 */ 695 696 last->next = sed; 697 last->ed_next = sed->ed_self; 698 699 usb2_pc_cpu_flush(last->page_cache); 700 701 return (sed); 702} 703 704#define OHCI_REMOVE_QH(sed,last) (last) = _ohci_remove_qh(sed,last) 705static ohci_ed_t * 706_ohci_remove_qh(ohci_ed_t *sed, ohci_ed_t *last) 707{ 708 DPRINTFN(11, "%p from %p\n", sed, last); 709 710 /* (sc->sc_bus.bus_mtx) must be locked */ 711 712 /* only remove if not removed from a queue */ 713 if (sed->prev) { 714 715 sed->prev->next = sed->next; 716 sed->prev->ed_next = sed->ed_next; 717 718 usb2_pc_cpu_flush(sed->prev->page_cache); 719 720 if (sed->next) { 721 sed->next->prev = sed->prev; 722 usb2_pc_cpu_flush(sed->next->page_cache); 723 } 724 last = ((last == sed) ? sed->prev : last); 725 726 sed->prev = 0; 727 728 usb2_pc_cpu_flush(sed->page_cache); 729 } 730 return (last); 731} 732 733static void 734ohci_isoc_done(struct usb2_xfer *xfer) 735{ 736 uint8_t nframes; 737 uint32_t *plen = xfer->frlengths; 738 volatile uint16_t *olen; 739 uint16_t len = 0; 740 ohci_itd_t *td = xfer->td_transfer_first; 741 742 while (1) { 743 if (td == NULL) { 744 panic("%s:%d: out of TD's\n", 745 __FUNCTION__, __LINE__); 746 } 747#if USB_DEBUG 748 if (ohcidebug > 5) { 749 DPRINTF("isoc TD\n"); 750 ohci_dump_itd(td); 751 } 752#endif 753 usb2_pc_cpu_invalidate(td->page_cache); 754 755 nframes = td->frames; 756 olen = &td->itd_offset[0]; 757 758 if (nframes > 8) { 759 nframes = 8; 760 } 761 while (nframes--) { 762 len = le16toh(*olen); 763 764 if ((len >> 12) == OHCI_CC_NOT_ACCESSED) { 765 len = 0; 766 } else { 767 len &= ((1 << 12) - 1); 768 } 769 770 if (len > *plen) { 771 len = 0;/* invalid length */ 772 } 773 *plen = len; 774 plen++; 775 olen++; 776 } 777 778 if (((void *)td) == xfer->td_transfer_last) { 779 break; 780 } 781 td = td->obj_next; 782 } 783 784 xfer->aframes = xfer->nframes; 785 ohci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 786} 787 788#if USB_DEBUG 789static const char *const 790 ohci_cc_strs[] = 791{ 792 "NO_ERROR", 793 "CRC", 794 "BIT_STUFFING", 795 "DATA_TOGGLE_MISMATCH", 796 797 "STALL", 798 "DEVICE_NOT_RESPONDING", 799 "PID_CHECK_FAILURE", 800 "UNEXPECTED_PID", 801 802 "DATA_OVERRUN", 803 "DATA_UNDERRUN", 804 "BUFFER_OVERRUN", 805 "BUFFER_UNDERRUN", 806 807 "reserved", 808 "reserved", 809 "NOT_ACCESSED", 810 "NOT_ACCESSED" 811}; 812 813#endif 814 815static usb2_error_t 816ohci_non_isoc_done_sub(struct usb2_xfer *xfer) 817{ 818 ohci_td_t *td; 819 ohci_td_t *td_alt_next; 820 uint32_t temp; 821 uint32_t phy_start; 822 uint32_t phy_end; 823 uint32_t td_flags; 824 uint16_t cc; 825 826 td = xfer->td_transfer_cache; 827 td_alt_next = td->alt_next; 828 td_flags = 0; 829 830 while (1) { 831 832 usb2_pc_cpu_invalidate(td->page_cache); 833 phy_start = le32toh(td->td_cbp); 834 td_flags = le32toh(td->td_flags); 835 cc = OHCI_TD_GET_CC(td_flags); 836 837 if (phy_start) { 838 /* 839 * short transfer - compute the number of remaining 840 * bytes in the hardware buffer: 841 */ 842 phy_end = le32toh(td->td_be); 843 temp = (OHCI_PAGE(phy_start ^ phy_end) ? 844 (OHCI_PAGE_SIZE + 1) : 0x0001); 845 temp += OHCI_PAGE_OFFSET(phy_end); 846 temp -= OHCI_PAGE_OFFSET(phy_start); 847 848 if (temp > td->len) { 849 /* guard against corruption */ 850 cc = OHCI_CC_STALL; 851 } else if (xfer->aframes != xfer->nframes) { 852 /* 853 * subtract remaining length from 854 * "frlengths[]" 855 */ 856 xfer->frlengths[xfer->aframes] -= temp; 857 } 858 } 859 /* Check for last transfer */ 860 if (((void *)td) == xfer->td_transfer_last) { 861 td = NULL; 862 break; 863 } 864 /* Check transfer status */ 865 if (cc) { 866 /* the transfer is finished */ 867 td = NULL; 868 break; 869 } 870 /* Check for short transfer */ 871 if (phy_start) { 872 if (xfer->flags_int.short_frames_ok) { 873 /* follow alt next */ 874 td = td->alt_next; 875 } else { 876 /* the transfer is finished */ 877 td = NULL; 878 } 879 break; 880 } 881 td = td->obj_next; 882 883 if (td->alt_next != td_alt_next) { 884 /* this USB frame is complete */ 885 break; 886 } 887 } 888 889 /* update transfer cache */ 890 891 xfer->td_transfer_cache = td; 892 893 DPRINTFN(16, "error cc=%d (%s)\n", 894 cc, ohci_cc_strs[cc]); 895 896 return ((cc == 0) ? USB_ERR_NORMAL_COMPLETION : 897 (cc == OHCI_CC_STALL) ? USB_ERR_STALLED : USB_ERR_IOERROR); 898} 899 900static void 901ohci_non_isoc_done(struct usb2_xfer *xfer) 902{ 903 usb2_error_t err = 0; 904 905 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 906 xfer, xfer->pipe); 907 908#if USB_DEBUG 909 if (ohcidebug > 10) { 910 ohci_dump_tds(xfer->td_transfer_first); 911 } 912#endif 913 914 /* reset scanner */ 915 916 xfer->td_transfer_cache = xfer->td_transfer_first; 917 918 if (xfer->flags_int.control_xfr) { 919 920 if (xfer->flags_int.control_hdr) { 921 922 err = ohci_non_isoc_done_sub(xfer); 923 } 924 xfer->aframes = 1; 925 926 if (xfer->td_transfer_cache == NULL) { 927 goto done; 928 } 929 } 930 while (xfer->aframes != xfer->nframes) { 931 932 err = ohci_non_isoc_done_sub(xfer); 933 xfer->aframes++; 934 935 if (xfer->td_transfer_cache == NULL) { 936 goto done; 937 } 938 } 939 940 if (xfer->flags_int.control_xfr && 941 !xfer->flags_int.control_act) { 942 943 err = ohci_non_isoc_done_sub(xfer); 944 } 945done: 946 ohci_device_done(xfer, err); 947} 948 949/*------------------------------------------------------------------------* 950 * ohci_check_transfer_sub 951 *------------------------------------------------------------------------*/ 952static void 953ohci_check_transfer_sub(struct usb2_xfer *xfer) 954{ 955 ohci_td_t *td; 956 ohci_ed_t *ed; 957 uint32_t phy_start; 958 uint32_t td_flags; 959 uint32_t td_next; 960 uint16_t cc; 961 962 td = xfer->td_transfer_cache; 963 964 while (1) { 965 966 usb2_pc_cpu_invalidate(td->page_cache); 967 phy_start = le32toh(td->td_cbp); 968 td_flags = le32toh(td->td_flags); 969 td_next = le32toh(td->td_next); 970 971 /* Check for last transfer */ 972 if (((void *)td) == xfer->td_transfer_last) { 973 /* the transfer is finished */ 974 td = NULL; 975 break; 976 } 977 /* Check transfer status */ 978 cc = OHCI_TD_GET_CC(td_flags); 979 if (cc) { 980 /* the transfer is finished */ 981 td = NULL; 982 break; 983 } 984 /* 985 * Check if we reached the last packet 986 * or if there is a short packet: 987 */ 988 989 if (((td_next & (~0xF)) == OHCI_TD_NEXT_END) || phy_start) { 990 /* follow alt next */ 991 td = td->alt_next; 992 break; 993 } 994 td = td->obj_next; 995 } 996 997 /* update transfer cache */ 998 999 xfer->td_transfer_cache = td; 1000 1001 if (td) { 1002 1003 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1004 1005 ed->ed_headp = td->td_self; 1006 usb2_pc_cpu_flush(ed->page_cache); 1007 1008 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1009 } 1010} 1011 1012/*------------------------------------------------------------------------* 1013 * ohci_check_transfer 1014 * 1015 * Return values: 1016 * 0: USB transfer is not finished 1017 * Else: USB transfer is finished 1018 *------------------------------------------------------------------------*/ 1019static uint8_t 1020ohci_check_transfer(struct usb2_xfer *xfer) 1021{ 1022 ohci_ed_t *ed; 1023 uint32_t ed_flags; 1024 uint32_t ed_headp; 1025 uint32_t ed_tailp; 1026 1027 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1028 1029 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1030 1031 usb2_pc_cpu_invalidate(ed->page_cache); 1032 ed_flags = le32toh(ed->ed_flags); 1033 ed_headp = le32toh(ed->ed_headp); 1034 ed_tailp = le32toh(ed->ed_tailp); 1035 1036 if ((ed_flags & OHCI_ED_SKIP) || 1037 (ed_headp & OHCI_HALTED) || 1038 (((ed_headp ^ ed_tailp) & (~0xF)) == 0)) { 1039 if (xfer->pipe->methods == &ohci_device_isoc_methods) { 1040 /* isochronous transfer */ 1041 ohci_isoc_done(xfer); 1042 } else { 1043 if (xfer->flags_int.short_frames_ok) { 1044 ohci_check_transfer_sub(xfer); 1045 if (xfer->td_transfer_cache) { 1046 /* not finished yet */ 1047 return (0); 1048 } 1049 } 1050 /* store data-toggle */ 1051 if (ed_headp & OHCI_TOGGLECARRY) { 1052 xfer->pipe->toggle_next = 1; 1053 } else { 1054 xfer->pipe->toggle_next = 0; 1055 } 1056 1057 /* non-isochronous transfer */ 1058 ohci_non_isoc_done(xfer); 1059 } 1060 return (1); 1061 } 1062 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1063 return (0); 1064} 1065 1066static void 1067ohci_rhsc_enable(ohci_softc_t *sc) 1068{ 1069 DPRINTFN(5, "\n"); 1070 1071 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1072 1073 sc->sc_eintrs |= OHCI_RHSC; 1074 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1075 1076 /* acknowledge any RHSC interrupt */ 1077 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_RHSC); 1078 1079 usb2_sw_transfer(&sc->sc_root_intr, 1080 &ohci_root_intr_done); 1081} 1082 1083static void 1084ohci_interrupt_poll(ohci_softc_t *sc) 1085{ 1086 struct usb2_xfer *xfer; 1087 1088repeat: 1089 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1090 /* 1091 * check if transfer is transferred 1092 */ 1093 if (ohci_check_transfer(xfer)) { 1094 /* queue has been modified */ 1095 goto repeat; 1096 } 1097 } 1098} 1099 1100/*------------------------------------------------------------------------* 1101 * ohci_interrupt - OHCI interrupt handler 1102 * 1103 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1104 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1105 * is present ! 1106 *------------------------------------------------------------------------*/ 1107void 1108ohci_interrupt(ohci_softc_t *sc) 1109{ 1110 struct ohci_hcca *hcca; 1111 uint32_t status; 1112 uint32_t done; 1113 1114 USB_BUS_LOCK(&sc->sc_bus); 1115 1116 hcca = ohci_get_hcca(sc); 1117 1118 DPRINTFN(16, "real interrupt\n"); 1119 1120#if USB_DEBUG 1121 if (ohcidebug > 15) { 1122 ohci_dumpregs(sc); 1123 } 1124#endif 1125 1126 done = le32toh(hcca->hcca_done_head); 1127 1128 /* 1129 * The LSb of done is used to inform the HC Driver that an interrupt 1130 * condition exists for both the Done list and for another event 1131 * recorded in HcInterruptStatus. On an interrupt from the HC, the 1132 * HC Driver checks the HccaDoneHead Value. If this value is 0, then 1133 * the interrupt was caused by other than the HccaDoneHead update 1134 * and the HcInterruptStatus register needs to be accessed to 1135 * determine that exact interrupt cause. If HccaDoneHead is nonzero, 1136 * then a Done list update interrupt is indicated and if the LSb of 1137 * done is nonzero, then an additional interrupt event is indicated 1138 * and HcInterruptStatus should be checked to determine its cause. 1139 */ 1140 if (done != 0) { 1141 status = 0; 1142 1143 if (done & ~OHCI_DONE_INTRS) { 1144 status |= OHCI_WDH; 1145 } 1146 if (done & OHCI_DONE_INTRS) { 1147 status |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 1148 } 1149 hcca->hcca_done_head = 0; 1150 1151 usb2_pc_cpu_flush(&sc->sc_hw.hcca_pc); 1152 } else { 1153 status = OREAD4(sc, OHCI_INTERRUPT_STATUS) & ~OHCI_WDH; 1154 } 1155 1156 status &= ~OHCI_MIE; 1157 if (status == 0) { 1158 /* 1159 * nothing to be done (PCI shared 1160 * interrupt) 1161 */ 1162 goto done; 1163 } 1164 OWRITE4(sc, OHCI_INTERRUPT_STATUS, status); /* Acknowledge */ 1165 1166 status &= sc->sc_eintrs; 1167 if (status == 0) { 1168 goto done; 1169 } 1170 if (status & (OHCI_SO | OHCI_RD | OHCI_UE | OHCI_RHSC)) { 1171#if 0 1172 if (status & OHCI_SO) { 1173 /* XXX do what */ 1174 } 1175#endif 1176 if (status & OHCI_RD) { 1177 printf("%s: resume detect\n", __FUNCTION__); 1178 /* XXX process resume detect */ 1179 } 1180 if (status & OHCI_UE) { 1181 printf("%s: unrecoverable error, " 1182 "controller halted\n", __FUNCTION__); 1183 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1184 /* XXX what else */ 1185 } 1186 if (status & OHCI_RHSC) { 1187 /* 1188 * Disable RHSC interrupt for now, because it will be 1189 * on until the port has been reset. 1190 */ 1191 sc->sc_eintrs &= ~OHCI_RHSC; 1192 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 1193 1194 usb2_sw_transfer(&sc->sc_root_intr, 1195 &ohci_root_intr_done); 1196 1197 /* do not allow RHSC interrupts > 1 per second */ 1198 usb2_callout_reset(&sc->sc_tmo_rhsc, hz, 1199 (void *)&ohci_rhsc_enable, sc); 1200 } 1201 } 1202 status &= ~(OHCI_RHSC | OHCI_WDH | OHCI_SO); 1203 if (status != 0) { 1204 /* Block unprocessed interrupts. XXX */ 1205 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, status); 1206 sc->sc_eintrs &= ~status; 1207 printf("%s: blocking intrs 0x%x\n", 1208 __FUNCTION__, status); 1209 } 1210 /* poll all the USB transfers */ 1211 ohci_interrupt_poll(sc); 1212 1213done: 1214 USB_BUS_UNLOCK(&sc->sc_bus); 1215} 1216 1217/* 1218 * called when a request does not complete 1219 */ 1220static void 1221ohci_timeout(void *arg) 1222{ 1223 struct usb2_xfer *xfer = arg; 1224 1225 DPRINTF("xfer=%p\n", xfer); 1226 1227 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1228 1229 /* transfer is transferred */ 1230 ohci_device_done(xfer, USB_ERR_TIMEOUT); 1231} 1232 1233static void 1234ohci_do_poll(struct usb2_bus *bus) 1235{ 1236 struct ohci_softc *sc = OHCI_BUS2SC(bus); 1237 1238 USB_BUS_LOCK(&sc->sc_bus); 1239 ohci_interrupt_poll(sc); 1240 ohci_root_ctrl_poll(sc); 1241 USB_BUS_UNLOCK(&sc->sc_bus); 1242} 1243 1244static void 1245ohci_setup_standard_chain_sub(struct ohci_std_temp *temp) 1246{ 1247 struct usb2_page_search buf_res; 1248 ohci_td_t *td; 1249 ohci_td_t *td_next; 1250 ohci_td_t *td_alt_next; 1251 uint32_t buf_offset; 1252 uint32_t average; 1253 uint32_t len_old; 1254 uint8_t shortpkt_old; 1255 uint8_t precompute; 1256 1257 td_alt_next = NULL; 1258 buf_offset = 0; 1259 shortpkt_old = temp->shortpkt; 1260 len_old = temp->len; 1261 precompute = 1; 1262 1263 /* software is used to detect short incoming transfers */ 1264 1265 if ((temp->td_flags & htole32(OHCI_TD_DP_MASK)) == htole32(OHCI_TD_IN)) { 1266 temp->td_flags |= htole32(OHCI_TD_R); 1267 } else { 1268 temp->td_flags &= ~htole32(OHCI_TD_R); 1269 } 1270 1271restart: 1272 1273 td = temp->td; 1274 td_next = temp->td_next; 1275 1276 while (1) { 1277 1278 if (temp->len == 0) { 1279 1280 if (temp->shortpkt) { 1281 break; 1282 } 1283 /* send a Zero Length Packet, ZLP, last */ 1284 1285 temp->shortpkt = 1; 1286 average = 0; 1287 1288 } else { 1289 1290 average = temp->average; 1291 1292 if (temp->len < average) { 1293 if (temp->len % temp->max_frame_size) { 1294 temp->shortpkt = 1; 1295 } 1296 average = temp->len; 1297 } 1298 } 1299 1300 if (td_next == NULL) { 1301 panic("%s: out of OHCI transfer descriptors!", __FUNCTION__); 1302 } 1303 /* get next TD */ 1304 1305 td = td_next; 1306 td_next = td->obj_next; 1307 1308 /* check if we are pre-computing */ 1309 1310 if (precompute) { 1311 1312 /* update remaining length */ 1313 1314 temp->len -= average; 1315 1316 continue; 1317 } 1318 /* fill out current TD */ 1319 td->td_flags = temp->td_flags; 1320 1321 /* the next TD uses TOGGLE_CARRY */ 1322 temp->td_flags &= ~htole32(OHCI_TD_TOGGLE_MASK); 1323 1324 if (average == 0) { 1325 1326 td->td_cbp = 0; 1327 td->td_be = ~0; 1328 td->len = 0; 1329 1330 } else { 1331 1332 usb2_get_page(temp->pc, buf_offset, &buf_res); 1333 td->td_cbp = htole32(buf_res.physaddr); 1334 buf_offset += (average - 1); 1335 1336 usb2_get_page(temp->pc, buf_offset, &buf_res); 1337 td->td_be = htole32(buf_res.physaddr); 1338 buf_offset++; 1339 1340 td->len = average; 1341 1342 /* update remaining length */ 1343 1344 temp->len -= average; 1345 } 1346 1347 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1348 /* we need to receive these frames one by one ! */ 1349 td->td_flags &= htole32(~OHCI_TD_INTR_MASK); 1350 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1351 td->td_next = htole32(OHCI_TD_NEXT_END); 1352 } else { 1353 if (td_next) { 1354 /* link the current TD with the next one */ 1355 td->td_next = td_next->td_self; 1356 } 1357 } 1358 1359 td->alt_next = td_alt_next; 1360 1361 usb2_pc_cpu_flush(td->page_cache); 1362 } 1363 1364 if (precompute) { 1365 precompute = 0; 1366 1367 /* setup alt next pointer, if any */ 1368 if (temp->short_frames_ok) { 1369 if (temp->setup_alt_next) { 1370 td_alt_next = td_next; 1371 } 1372 } else { 1373 /* we use this field internally */ 1374 td_alt_next = td_next; 1375 } 1376 1377 /* restore */ 1378 temp->shortpkt = shortpkt_old; 1379 temp->len = len_old; 1380 goto restart; 1381 } 1382 temp->td = td; 1383 temp->td_next = td_next; 1384} 1385 1386static void 1387ohci_setup_standard_chain(struct usb2_xfer *xfer, ohci_ed_t **ed_last) 1388{ 1389 struct ohci_std_temp temp; 1390 struct usb2_pipe_methods *methods; 1391 ohci_ed_t *ed; 1392 ohci_td_t *td; 1393 uint32_t ed_flags; 1394 uint32_t x; 1395 1396 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1397 xfer->address, UE_GET_ADDR(xfer->endpoint), 1398 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 1399 1400 temp.average = xfer->max_usb2_frame_size; 1401 temp.max_frame_size = xfer->max_frame_size; 1402 1403 /* toggle the DMA set we are using */ 1404 xfer->flags_int.curr_dma_set ^= 1; 1405 1406 /* get next DMA set */ 1407 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1408 1409 xfer->td_transfer_first = td; 1410 xfer->td_transfer_cache = td; 1411 1412 temp.td = NULL; 1413 temp.td_next = td; 1414 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1415 temp.short_frames_ok = xfer->flags_int.short_frames_ok; 1416 1417 methods = xfer->pipe->methods; 1418 1419 /* check if we should prepend a setup message */ 1420 1421 if (xfer->flags_int.control_xfr) { 1422 if (xfer->flags_int.control_hdr) { 1423 1424 temp.td_flags = htole32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1425 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1426 1427 temp.len = xfer->frlengths[0]; 1428 temp.pc = xfer->frbuffers + 0; 1429 temp.shortpkt = temp.len ? 1 : 0; 1430 1431 ohci_setup_standard_chain_sub(&temp); 1432 1433 /* 1434 * XXX assume that the setup message is 1435 * contained within one USB packet: 1436 */ 1437 xfer->pipe->toggle_next = 1; 1438 } 1439 x = 1; 1440 } else { 1441 x = 0; 1442 } 1443 temp.td_flags = htole32(OHCI_TD_NOCC | OHCI_TD_NOINTR); 1444 1445 /* set data toggle */ 1446 1447 if (xfer->pipe->toggle_next) { 1448 temp.td_flags |= htole32(OHCI_TD_TOGGLE_1); 1449 } else { 1450 temp.td_flags |= htole32(OHCI_TD_TOGGLE_0); 1451 } 1452 1453 /* set endpoint direction */ 1454 1455 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 1456 temp.td_flags |= htole32(OHCI_TD_IN); 1457 } else { 1458 temp.td_flags |= htole32(OHCI_TD_OUT); 1459 } 1460 1461 while (x != xfer->nframes) { 1462 1463 /* DATA0 / DATA1 message */ 1464 1465 temp.len = xfer->frlengths[x]; 1466 temp.pc = xfer->frbuffers + x; 1467 1468 x++; 1469 1470 if (x == xfer->nframes) { 1471 temp.setup_alt_next = 0; 1472 } 1473 if (temp.len == 0) { 1474 1475 /* make sure that we send an USB packet */ 1476 1477 temp.shortpkt = 0; 1478 1479 } else { 1480 1481 /* regular data transfer */ 1482 1483 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1484 } 1485 1486 ohci_setup_standard_chain_sub(&temp); 1487 } 1488 1489 /* check if we should append a status stage */ 1490 1491 if (xfer->flags_int.control_xfr && 1492 !xfer->flags_int.control_act) { 1493 1494 /* 1495 * Send a DATA1 message and invert the current endpoint 1496 * direction. 1497 */ 1498 1499 /* set endpoint direction and data toggle */ 1500 1501 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 1502 temp.td_flags = htole32(OHCI_TD_OUT | 1503 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1504 } else { 1505 temp.td_flags = htole32(OHCI_TD_IN | 1506 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1507 } 1508 1509 temp.len = 0; 1510 temp.pc = NULL; 1511 temp.shortpkt = 0; 1512 1513 ohci_setup_standard_chain_sub(&temp); 1514 } 1515 td = temp.td; 1516 1517 td->td_next = htole32(OHCI_TD_NEXT_END); 1518 td->td_flags &= ~htole32(OHCI_TD_INTR_MASK); 1519 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1520 1521 usb2_pc_cpu_flush(td->page_cache); 1522 1523 /* must have at least one frame! */ 1524 1525 xfer->td_transfer_last = td; 1526 1527#if USB_DEBUG 1528 if (ohcidebug > 8) { 1529 DPRINTF("nexttog=%d; data before transfer:\n", 1530 xfer->pipe->toggle_next); 1531 ohci_dump_tds(xfer->td_transfer_first); 1532 } 1533#endif 1534 1535 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1536 1537 ed_flags = (OHCI_ED_SET_FA(xfer->address) | 1538 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpoint)) | 1539 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 1540 1541 ed_flags |= (OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD); 1542 1543 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1544 ed_flags |= OHCI_ED_SPEED; 1545 } 1546 ed->ed_flags = htole32(ed_flags); 1547 1548 td = xfer->td_transfer_first; 1549 1550 ed->ed_headp = td->td_self; 1551 1552 if (xfer->xroot->udev->pwr_save.suspended == 0) { 1553 /* the append function will flush the endpoint descriptor */ 1554 OHCI_APPEND_QH(ed, *ed_last); 1555 1556 if (methods == &ohci_device_bulk_methods) { 1557 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1558 1559 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1560 } 1561 if (methods == &ohci_device_ctrl_methods) { 1562 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1563 1564 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1565 } 1566 } else { 1567 usb2_pc_cpu_flush(ed->page_cache); 1568 } 1569} 1570 1571static void 1572ohci_root_intr_done(struct usb2_xfer *xfer, 1573 struct usb2_sw_transfer *std) 1574{ 1575 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1576 uint32_t hstatus; 1577 uint16_t i; 1578 uint16_t m; 1579 1580 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1581 1582 if (std->state != USB_SW_TR_PRE_DATA) { 1583 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1584 /* transfer transferred */ 1585 ohci_device_done(xfer, std->err); 1586 } 1587 goto done; 1588 } 1589 /* setup buffer */ 1590 std->ptr = sc->sc_hub_idata; 1591 std->len = sizeof(sc->sc_hub_idata); 1592 1593 /* clear any old interrupt data */ 1594 bzero(sc->sc_hub_idata, sizeof(sc->sc_hub_idata)); 1595 1596 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1597 DPRINTF("sc=%p xfer=%p hstatus=0x%08x\n", 1598 sc, xfer, hstatus); 1599 1600 /* set bits */ 1601 m = (sc->sc_noport + 1); 1602 if (m > (8 * sizeof(sc->sc_hub_idata))) { 1603 m = (8 * sizeof(sc->sc_hub_idata)); 1604 } 1605 for (i = 1; i < m; i++) { 1606 /* pick out CHANGE bits from the status register */ 1607 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) { 1608 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 1609 DPRINTF("port %d changed\n", i); 1610 } 1611 } 1612done: 1613 return; 1614} 1615 1616/* NOTE: "done" can be run two times in a row, 1617 * from close and from interrupt 1618 */ 1619static void 1620ohci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1621{ 1622 struct usb2_pipe_methods *methods = xfer->pipe->methods; 1623 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1624 ohci_ed_t *ed; 1625 1626 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1627 1628 1629 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1630 xfer, xfer->pipe, error); 1631 1632 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1633 if (ed) { 1634 usb2_pc_cpu_invalidate(ed->page_cache); 1635 } 1636 if (methods == &ohci_device_bulk_methods) { 1637 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 1638 } 1639 if (methods == &ohci_device_ctrl_methods) { 1640 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 1641 } 1642 if (methods == &ohci_device_intr_methods) { 1643 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 1644 } 1645 if (methods == &ohci_device_isoc_methods) { 1646 OHCI_REMOVE_QH(ed, sc->sc_isoc_p_last); 1647 } 1648 xfer->td_transfer_first = NULL; 1649 xfer->td_transfer_last = NULL; 1650 1651 /* dequeue transfer and start next transfer */ 1652 usb2_transfer_done(xfer, error); 1653} 1654 1655/*------------------------------------------------------------------------* 1656 * ohci bulk support 1657 *------------------------------------------------------------------------*/ 1658static void 1659ohci_device_bulk_open(struct usb2_xfer *xfer) 1660{ 1661 return; 1662} 1663 1664static void 1665ohci_device_bulk_close(struct usb2_xfer *xfer) 1666{ 1667 ohci_device_done(xfer, USB_ERR_CANCELLED); 1668} 1669 1670static void 1671ohci_device_bulk_enter(struct usb2_xfer *xfer) 1672{ 1673 return; 1674} 1675 1676static void 1677ohci_device_bulk_start(struct usb2_xfer *xfer) 1678{ 1679 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1680 1681 /* setup TD's and QH */ 1682 ohci_setup_standard_chain(xfer, &sc->sc_bulk_p_last); 1683 1684 /* put transfer on interrupt queue */ 1685 ohci_transfer_intr_enqueue(xfer); 1686} 1687 1688struct usb2_pipe_methods ohci_device_bulk_methods = 1689{ 1690 .open = ohci_device_bulk_open, 1691 .close = ohci_device_bulk_close, 1692 .enter = ohci_device_bulk_enter, 1693 .start = ohci_device_bulk_start, 1694 .enter_is_cancelable = 1, 1695 .start_is_cancelable = 1, 1696}; 1697 1698/*------------------------------------------------------------------------* 1699 * ohci control support 1700 *------------------------------------------------------------------------*/ 1701static void 1702ohci_device_ctrl_open(struct usb2_xfer *xfer) 1703{ 1704 return; 1705} 1706 1707static void 1708ohci_device_ctrl_close(struct usb2_xfer *xfer) 1709{ 1710 ohci_device_done(xfer, USB_ERR_CANCELLED); 1711} 1712 1713static void 1714ohci_device_ctrl_enter(struct usb2_xfer *xfer) 1715{ 1716 return; 1717} 1718 1719static void 1720ohci_device_ctrl_start(struct usb2_xfer *xfer) 1721{ 1722 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1723 1724 /* setup TD's and QH */ 1725 ohci_setup_standard_chain(xfer, &sc->sc_ctrl_p_last); 1726 1727 /* put transfer on interrupt queue */ 1728 ohci_transfer_intr_enqueue(xfer); 1729} 1730 1731struct usb2_pipe_methods ohci_device_ctrl_methods = 1732{ 1733 .open = ohci_device_ctrl_open, 1734 .close = ohci_device_ctrl_close, 1735 .enter = ohci_device_ctrl_enter, 1736 .start = ohci_device_ctrl_start, 1737 .enter_is_cancelable = 1, 1738 .start_is_cancelable = 1, 1739}; 1740 1741/*------------------------------------------------------------------------* 1742 * ohci interrupt support 1743 *------------------------------------------------------------------------*/ 1744static void 1745ohci_device_intr_open(struct usb2_xfer *xfer) 1746{ 1747 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1748 uint16_t best; 1749 uint16_t bit; 1750 uint16_t x; 1751 1752 best = 0; 1753 bit = OHCI_NO_EDS / 2; 1754 while (bit) { 1755 if (xfer->interval >= bit) { 1756 x = bit; 1757 best = bit; 1758 while (x & bit) { 1759 if (sc->sc_intr_stat[x] < 1760 sc->sc_intr_stat[best]) { 1761 best = x; 1762 } 1763 x++; 1764 } 1765 break; 1766 } 1767 bit >>= 1; 1768 } 1769 1770 sc->sc_intr_stat[best]++; 1771 xfer->qh_pos = best; 1772 1773 DPRINTFN(3, "best=%d interval=%d\n", 1774 best, xfer->interval); 1775} 1776 1777static void 1778ohci_device_intr_close(struct usb2_xfer *xfer) 1779{ 1780 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1781 1782 sc->sc_intr_stat[xfer->qh_pos]--; 1783 1784 ohci_device_done(xfer, USB_ERR_CANCELLED); 1785} 1786 1787static void 1788ohci_device_intr_enter(struct usb2_xfer *xfer) 1789{ 1790 return; 1791} 1792 1793static void 1794ohci_device_intr_start(struct usb2_xfer *xfer) 1795{ 1796 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1797 1798 /* setup TD's and QH */ 1799 ohci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 1800 1801 /* put transfer on interrupt queue */ 1802 ohci_transfer_intr_enqueue(xfer); 1803} 1804 1805struct usb2_pipe_methods ohci_device_intr_methods = 1806{ 1807 .open = ohci_device_intr_open, 1808 .close = ohci_device_intr_close, 1809 .enter = ohci_device_intr_enter, 1810 .start = ohci_device_intr_start, 1811 .enter_is_cancelable = 1, 1812 .start_is_cancelable = 1, 1813}; 1814 1815/*------------------------------------------------------------------------* 1816 * ohci isochronous support 1817 *------------------------------------------------------------------------*/ 1818static void 1819ohci_device_isoc_open(struct usb2_xfer *xfer) 1820{ 1821 return; 1822} 1823 1824static void 1825ohci_device_isoc_close(struct usb2_xfer *xfer) 1826{ 1827 /**/ 1828 ohci_device_done(xfer, USB_ERR_CANCELLED); 1829} 1830 1831static void 1832ohci_device_isoc_enter(struct usb2_xfer *xfer) 1833{ 1834 struct usb2_page_search buf_res; 1835 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1836 struct ohci_hcca *hcca; 1837 uint32_t buf_offset; 1838 uint32_t nframes; 1839 uint32_t ed_flags; 1840 uint32_t *plen; 1841 uint16_t itd_offset[OHCI_ITD_NOFFSET]; 1842 uint16_t length; 1843 uint8_t ncur; 1844 ohci_itd_t *td; 1845 ohci_itd_t *td_last = NULL; 1846 ohci_ed_t *ed; 1847 1848 hcca = ohci_get_hcca(sc); 1849 1850 nframes = le32toh(hcca->hcca_frame_number); 1851 1852 DPRINTFN(6, "xfer=%p isoc_next=%u nframes=%u hcca_fn=%u\n", 1853 xfer, xfer->pipe->isoc_next, xfer->nframes, nframes); 1854 1855 if ((xfer->pipe->is_synced == 0) || 1856 (((nframes - xfer->pipe->isoc_next) & 0xFFFF) < xfer->nframes) || 1857 (((xfer->pipe->isoc_next - nframes) & 0xFFFF) >= 128)) { 1858 /* 1859 * If there is data underflow or the pipe queue is empty we 1860 * schedule the transfer a few frames ahead of the current 1861 * frame position. Else two isochronous transfers might 1862 * overlap. 1863 */ 1864 xfer->pipe->isoc_next = (nframes + 3) & 0xFFFF; 1865 xfer->pipe->is_synced = 1; 1866 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 1867 } 1868 /* 1869 * compute how many milliseconds the insertion is ahead of the 1870 * current frame position: 1871 */ 1872 buf_offset = ((xfer->pipe->isoc_next - nframes) & 0xFFFF); 1873 1874 /* 1875 * pre-compute when the isochronous transfer will be finished: 1876 */ 1877 xfer->isoc_time_complete = 1878 (usb2_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 1879 xfer->nframes); 1880 1881 /* get the real number of frames */ 1882 1883 nframes = xfer->nframes; 1884 1885 buf_offset = 0; 1886 1887 plen = xfer->frlengths; 1888 1889 /* toggle the DMA set we are using */ 1890 xfer->flags_int.curr_dma_set ^= 1; 1891 1892 /* get next DMA set */ 1893 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1894 1895 xfer->td_transfer_first = td; 1896 1897 ncur = 0; 1898 length = 0; 1899 1900 while (nframes--) { 1901 if (td == NULL) { 1902 panic("%s:%d: out of TD's\n", 1903 __FUNCTION__, __LINE__); 1904 } 1905 itd_offset[ncur] = length; 1906 buf_offset += *plen; 1907 length += *plen; 1908 plen++; 1909 ncur++; 1910 1911 if ( /* check if the ITD is full */ 1912 (ncur == OHCI_ITD_NOFFSET) || 1913 /* check if we have put more than 4K into the ITD */ 1914 (length & 0xF000) || 1915 /* check if it is the last frame */ 1916 (nframes == 0)) { 1917 1918 /* fill current ITD */ 1919 td->itd_flags = htole32( 1920 OHCI_ITD_NOCC | 1921 OHCI_ITD_SET_SF(xfer->pipe->isoc_next) | 1922 OHCI_ITD_NOINTR | 1923 OHCI_ITD_SET_FC(ncur)); 1924 1925 td->frames = ncur; 1926 xfer->pipe->isoc_next += ncur; 1927 1928 if (length == 0) { 1929 /* all zero */ 1930 td->itd_bp0 = 0; 1931 td->itd_be = ~0; 1932 1933 while (ncur--) { 1934 td->itd_offset[ncur] = 1935 htole16(OHCI_ITD_MK_OFFS(0)); 1936 } 1937 } else { 1938 usb2_get_page(xfer->frbuffers, buf_offset - length, &buf_res); 1939 length = OHCI_PAGE_MASK(buf_res.physaddr); 1940 buf_res.physaddr = 1941 OHCI_PAGE(buf_res.physaddr); 1942 td->itd_bp0 = htole32(buf_res.physaddr); 1943 usb2_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 1944 td->itd_be = htole32(buf_res.physaddr); 1945 1946 while (ncur--) { 1947 itd_offset[ncur] += length; 1948 itd_offset[ncur] = 1949 OHCI_ITD_MK_OFFS(itd_offset[ncur]); 1950 td->itd_offset[ncur] = 1951 htole16(itd_offset[ncur]); 1952 } 1953 } 1954 ncur = 0; 1955 length = 0; 1956 td_last = td; 1957 td = td->obj_next; 1958 1959 if (td) { 1960 /* link the last TD with the next one */ 1961 td_last->itd_next = td->itd_self; 1962 } 1963 usb2_pc_cpu_flush(td_last->page_cache); 1964 } 1965 } 1966 1967 /* update the last TD */ 1968 td_last->itd_flags &= ~htole32(OHCI_ITD_NOINTR); 1969 td_last->itd_flags |= htole32(OHCI_ITD_SET_DI(0)); 1970 td_last->itd_next = 0; 1971 1972 usb2_pc_cpu_flush(td_last->page_cache); 1973 1974 xfer->td_transfer_last = td_last; 1975 1976#if USB_DEBUG 1977 if (ohcidebug > 8) { 1978 DPRINTF("data before transfer:\n"); 1979 ohci_dump_itds(xfer->td_transfer_first); 1980 } 1981#endif 1982 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1983 1984 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) 1985 ed_flags = (OHCI_ED_DIR_IN | OHCI_ED_FORMAT_ISO); 1986 else 1987 ed_flags = (OHCI_ED_DIR_OUT | OHCI_ED_FORMAT_ISO); 1988 1989 ed_flags |= (OHCI_ED_SET_FA(xfer->address) | 1990 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpoint)) | 1991 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 1992 1993 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1994 ed_flags |= OHCI_ED_SPEED; 1995 } 1996 ed->ed_flags = htole32(ed_flags); 1997 1998 td = xfer->td_transfer_first; 1999 2000 ed->ed_headp = td->itd_self; 2001 2002 /* isochronous transfers are not affected by suspend / resume */ 2003 /* the append function will flush the endpoint descriptor */ 2004 2005 OHCI_APPEND_QH(ed, sc->sc_isoc_p_last); 2006} 2007 2008static void 2009ohci_device_isoc_start(struct usb2_xfer *xfer) 2010{ 2011 /* put transfer on interrupt queue */ 2012 ohci_transfer_intr_enqueue(xfer); 2013} 2014 2015struct usb2_pipe_methods ohci_device_isoc_methods = 2016{ 2017 .open = ohci_device_isoc_open, 2018 .close = ohci_device_isoc_close, 2019 .enter = ohci_device_isoc_enter, 2020 .start = ohci_device_isoc_start, 2021 .enter_is_cancelable = 1, 2022 .start_is_cancelable = 1, 2023}; 2024 2025/*------------------------------------------------------------------------* 2026 * ohci root control support 2027 *------------------------------------------------------------------------* 2028 * simulate a hardware hub by handling 2029 * all the necessary requests 2030 *------------------------------------------------------------------------*/ 2031 2032static void 2033ohci_root_ctrl_open(struct usb2_xfer *xfer) 2034{ 2035 return; 2036} 2037 2038static void 2039ohci_root_ctrl_close(struct usb2_xfer *xfer) 2040{ 2041 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 2042 2043 if (sc->sc_root_ctrl.xfer == xfer) { 2044 sc->sc_root_ctrl.xfer = NULL; 2045 } 2046 ohci_device_done(xfer, USB_ERR_CANCELLED); 2047} 2048 2049/* data structures and routines 2050 * to emulate the root hub: 2051 */ 2052static const 2053struct usb2_device_descriptor ohci_devd = 2054{ 2055 sizeof(struct usb2_device_descriptor), 2056 UDESC_DEVICE, /* type */ 2057 {0x00, 0x01}, /* USB version */ 2058 UDCLASS_HUB, /* class */ 2059 UDSUBCLASS_HUB, /* subclass */ 2060 UDPROTO_FSHUB, /* protocol */ 2061 64, /* max packet */ 2062 {0}, {0}, {0x00, 0x01}, /* device id */ 2063 1, 2, 0, /* string indicies */ 2064 1 /* # of configurations */ 2065}; 2066 2067static const 2068struct ohci_config_desc ohci_confd = 2069{ 2070 .confd = { 2071 .bLength = sizeof(struct usb2_config_descriptor), 2072 .bDescriptorType = UDESC_CONFIG, 2073 .wTotalLength[0] = sizeof(ohci_confd), 2074 .bNumInterface = 1, 2075 .bConfigurationValue = 1, 2076 .iConfiguration = 0, 2077 .bmAttributes = UC_SELF_POWERED, 2078 .bMaxPower = 0, /* max power */ 2079 }, 2080 2081 .ifcd = { 2082 .bLength = sizeof(struct usb2_interface_descriptor), 2083 .bDescriptorType = UDESC_INTERFACE, 2084 .bNumEndpoints = 1, 2085 .bInterfaceClass = UICLASS_HUB, 2086 .bInterfaceSubClass = UISUBCLASS_HUB, 2087 .bInterfaceProtocol = UIPROTO_FSHUB, 2088 }, 2089 2090 .endpd = { 2091 .bLength = sizeof(struct usb2_endpoint_descriptor), 2092 .bDescriptorType = UDESC_ENDPOINT, 2093 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2094 .bmAttributes = UE_INTERRUPT, 2095 .wMaxPacketSize[0] = 32,/* max packet (255 ports) */ 2096 .bInterval = 255, 2097 }, 2098}; 2099 2100static const 2101struct usb2_hub_descriptor ohci_hubd = 2102{ 2103 0, /* dynamic length */ 2104 UDESC_HUB, 2105 0, 2106 {0, 0}, 2107 0, 2108 0, 2109 {0}, 2110}; 2111 2112static void 2113ohci_root_ctrl_enter(struct usb2_xfer *xfer) 2114{ 2115 return; 2116} 2117 2118static void 2119ohci_root_ctrl_start(struct usb2_xfer *xfer) 2120{ 2121 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 2122 2123 sc->sc_root_ctrl.xfer = xfer; 2124 2125 usb2_bus_roothub_exec(xfer->xroot->bus); 2126} 2127 2128static void 2129ohci_root_ctrl_task(struct usb2_bus *bus) 2130{ 2131 ohci_root_ctrl_poll(OHCI_BUS2SC(bus)); 2132} 2133 2134static void 2135ohci_root_ctrl_done(struct usb2_xfer *xfer, 2136 struct usb2_sw_transfer *std) 2137{ 2138 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 2139 char *ptr; 2140 uint32_t port; 2141 uint32_t v; 2142 uint16_t value; 2143 uint16_t index; 2144 uint8_t l; 2145 uint8_t use_polling; 2146 2147 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2148 2149 if (std->state != USB_SW_TR_SETUP) { 2150 if (std->state == USB_SW_TR_PRE_CALLBACK) { 2151 /* transfer transferred */ 2152 ohci_device_done(xfer, std->err); 2153 } 2154 goto done; 2155 } 2156 /* buffer reset */ 2157 std->ptr = sc->sc_hub_desc.temp; 2158 std->len = 0; 2159 2160 value = UGETW(std->req.wValue); 2161 index = UGETW(std->req.wIndex); 2162 2163 use_polling = mtx_owned(xfer->xroot->xfer_mtx) ? 1 : 0; 2164 2165 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2166 "wValue=0x%04x wIndex=0x%04x\n", 2167 std->req.bmRequestType, std->req.bRequest, 2168 UGETW(std->req.wLength), value, index); 2169 2170#define C(x,y) ((x) | ((y) << 8)) 2171 switch (C(std->req.bRequest, std->req.bmRequestType)) { 2172 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2173 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2174 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2175 /* 2176 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2177 * for the integrated root hub. 2178 */ 2179 break; 2180 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2181 std->len = 1; 2182 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2183 break; 2184 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2185 switch (value >> 8) { 2186 case UDESC_DEVICE: 2187 if ((value & 0xff) != 0) { 2188 std->err = USB_ERR_IOERROR; 2189 goto done; 2190 } 2191 std->len = sizeof(ohci_devd); 2192 sc->sc_hub_desc.devd = ohci_devd; 2193 break; 2194 2195 case UDESC_CONFIG: 2196 if ((value & 0xff) != 0) { 2197 std->err = USB_ERR_IOERROR; 2198 goto done; 2199 } 2200 std->len = sizeof(ohci_confd); 2201 std->ptr = USB_ADD_BYTES(&ohci_confd, 0); 2202 break; 2203 2204 case UDESC_STRING: 2205 switch (value & 0xff) { 2206 case 0: /* Language table */ 2207 ptr = "\001"; 2208 break; 2209 2210 case 1: /* Vendor */ 2211 ptr = sc->sc_vendor; 2212 break; 2213 2214 case 2: /* Product */ 2215 ptr = "OHCI root HUB"; 2216 break; 2217 2218 default: 2219 ptr = ""; 2220 break; 2221 } 2222 2223 std->len = usb2_make_str_desc 2224 (sc->sc_hub_desc.temp, 2225 sizeof(sc->sc_hub_desc.temp), 2226 ptr); 2227 break; 2228 2229 default: 2230 std->err = USB_ERR_IOERROR; 2231 goto done; 2232 } 2233 break; 2234 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2235 std->len = 1; 2236 sc->sc_hub_desc.temp[0] = 0; 2237 break; 2238 case C(UR_GET_STATUS, UT_READ_DEVICE): 2239 std->len = 2; 2240 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2241 break; 2242 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2243 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2244 std->len = 2; 2245 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2246 break; 2247 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2248 if (value >= USB_MAX_DEVICES) { 2249 std->err = USB_ERR_IOERROR; 2250 goto done; 2251 } 2252 sc->sc_addr = value; 2253 break; 2254 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2255 if ((value != 0) && (value != 1)) { 2256 std->err = USB_ERR_IOERROR; 2257 goto done; 2258 } 2259 sc->sc_conf = value; 2260 break; 2261 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2262 break; 2263 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2264 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2265 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2266 std->err = USB_ERR_IOERROR; 2267 goto done; 2268 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2269 break; 2270 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2271 break; 2272 /* Hub requests */ 2273 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2274 break; 2275 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2276 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE " 2277 "port=%d feature=%d\n", 2278 index, value); 2279 if ((index < 1) || 2280 (index > sc->sc_noport)) { 2281 std->err = USB_ERR_IOERROR; 2282 goto done; 2283 } 2284 port = OHCI_RH_PORT_STATUS(index); 2285 switch (value) { 2286 case UHF_PORT_ENABLE: 2287 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2288 break; 2289 case UHF_PORT_SUSPEND: 2290 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2291 break; 2292 case UHF_PORT_POWER: 2293 /* Yes, writing to the LOW_SPEED bit clears power. */ 2294 OWRITE4(sc, port, UPS_LOW_SPEED); 2295 break; 2296 case UHF_C_PORT_CONNECTION: 2297 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2298 break; 2299 case UHF_C_PORT_ENABLE: 2300 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2301 break; 2302 case UHF_C_PORT_SUSPEND: 2303 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2304 break; 2305 case UHF_C_PORT_OVER_CURRENT: 2306 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2307 break; 2308 case UHF_C_PORT_RESET: 2309 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2310 break; 2311 default: 2312 std->err = USB_ERR_IOERROR; 2313 goto done; 2314 } 2315 switch (value) { 2316 case UHF_C_PORT_CONNECTION: 2317 case UHF_C_PORT_ENABLE: 2318 case UHF_C_PORT_SUSPEND: 2319 case UHF_C_PORT_OVER_CURRENT: 2320 case UHF_C_PORT_RESET: 2321 /* enable RHSC interrupt if condition is cleared. */ 2322 if ((OREAD4(sc, port) >> 16) == 0) 2323 ohci_rhsc_enable(sc); 2324 break; 2325 default: 2326 break; 2327 } 2328 break; 2329 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2330 if ((value & 0xff) != 0) { 2331 std->err = USB_ERR_IOERROR; 2332 goto done; 2333 } 2334 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2335 2336 sc->sc_hub_desc.hubd = ohci_hubd; 2337 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 2338 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, 2339 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2340 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2341 /* XXX overcurrent */ 2342 ); 2343 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2344 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2345 2346 for (l = 0; l < sc->sc_noport; l++) { 2347 if (v & 1) { 2348 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] |= (1 << (l % 8)); 2349 } 2350 v >>= 1; 2351 } 2352 sc->sc_hub_desc.hubd.bDescLength = 2353 8 + ((sc->sc_noport + 7) / 8); 2354 std->len = sc->sc_hub_desc.hubd.bDescLength; 2355 break; 2356 2357 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2358 std->len = 16; 2359 bzero(sc->sc_hub_desc.temp, 16); 2360 break; 2361 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2362 DPRINTFN(9, "get port status i=%d\n", 2363 index); 2364 if ((index < 1) || 2365 (index > sc->sc_noport)) { 2366 std->err = USB_ERR_IOERROR; 2367 goto done; 2368 } 2369 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2370 DPRINTFN(9, "port status=0x%04x\n", v); 2371 USETW(sc->sc_hub_desc.ps.wPortStatus, v); 2372 USETW(sc->sc_hub_desc.ps.wPortChange, v >> 16); 2373 std->len = sizeof(sc->sc_hub_desc.ps); 2374 break; 2375 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2376 std->err = USB_ERR_IOERROR; 2377 goto done; 2378 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2379 break; 2380 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2381 if ((index < 1) || 2382 (index > sc->sc_noport)) { 2383 std->err = USB_ERR_IOERROR; 2384 goto done; 2385 } 2386 port = OHCI_RH_PORT_STATUS(index); 2387 switch (value) { 2388 case UHF_PORT_ENABLE: 2389 OWRITE4(sc, port, UPS_PORT_ENABLED); 2390 break; 2391 case UHF_PORT_SUSPEND: 2392 OWRITE4(sc, port, UPS_SUSPEND); 2393 break; 2394 case UHF_PORT_RESET: 2395 DPRINTFN(6, "reset port %d\n", index); 2396 OWRITE4(sc, port, UPS_RESET); 2397 for (v = 0;; v++) { 2398 if (v < 12) { 2399 if (use_polling) { 2400 /* polling */ 2401 DELAY(USB_PORT_ROOT_RESET_DELAY * 1000); 2402 } else { 2403 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 2404 USB_PORT_ROOT_RESET_DELAY); 2405 } 2406 2407 if ((OREAD4(sc, port) & UPS_RESET) == 0) { 2408 break; 2409 } 2410 } else { 2411 std->err = USB_ERR_TIMEOUT; 2412 goto done; 2413 } 2414 } 2415 DPRINTFN(9, "ohci port %d reset, status = 0x%04x\n", 2416 index, OREAD4(sc, port)); 2417 break; 2418 case UHF_PORT_POWER: 2419 DPRINTFN(3, "set port power %d\n", index); 2420 OWRITE4(sc, port, UPS_PORT_POWER); 2421 break; 2422 default: 2423 std->err = USB_ERR_IOERROR; 2424 goto done; 2425 } 2426 break; 2427 default: 2428 std->err = USB_ERR_IOERROR; 2429 goto done; 2430 } 2431done: 2432 return; 2433} 2434 2435static void 2436ohci_root_ctrl_poll(struct ohci_softc *sc) 2437{ 2438 usb2_sw_transfer(&sc->sc_root_ctrl, 2439 &ohci_root_ctrl_done); 2440} 2441 2442struct usb2_pipe_methods ohci_root_ctrl_methods = 2443{ 2444 .open = ohci_root_ctrl_open, 2445 .close = ohci_root_ctrl_close, 2446 .enter = ohci_root_ctrl_enter, 2447 .start = ohci_root_ctrl_start, 2448 .enter_is_cancelable = 1, 2449 .start_is_cancelable = 0, 2450}; 2451 2452/*------------------------------------------------------------------------* 2453 * ohci root interrupt support 2454 *------------------------------------------------------------------------*/ 2455static void 2456ohci_root_intr_open(struct usb2_xfer *xfer) 2457{ 2458 return; 2459} 2460 2461static void 2462ohci_root_intr_close(struct usb2_xfer *xfer) 2463{ 2464 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 2465 2466 if (sc->sc_root_intr.xfer == xfer) { 2467 sc->sc_root_intr.xfer = NULL; 2468 } 2469 ohci_device_done(xfer, USB_ERR_CANCELLED); 2470} 2471 2472static void 2473ohci_root_intr_enter(struct usb2_xfer *xfer) 2474{ 2475 return; 2476} 2477 2478static void 2479ohci_root_intr_start(struct usb2_xfer *xfer) 2480{ 2481 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 2482 2483 sc->sc_root_intr.xfer = xfer; 2484} 2485 2486struct usb2_pipe_methods ohci_root_intr_methods = 2487{ 2488 .open = ohci_root_intr_open, 2489 .close = ohci_root_intr_close, 2490 .enter = ohci_root_intr_enter, 2491 .start = ohci_root_intr_start, 2492 .enter_is_cancelable = 1, 2493 .start_is_cancelable = 1, 2494}; 2495 2496static void 2497ohci_xfer_setup(struct usb2_setup_params *parm) 2498{ 2499 struct usb2_page_search page_info; 2500 struct usb2_page_cache *pc; 2501 ohci_softc_t *sc; 2502 struct usb2_xfer *xfer; 2503 void *last_obj; 2504 uint32_t ntd; 2505 uint32_t nitd; 2506 uint32_t nqh; 2507 uint32_t n; 2508 2509 sc = OHCI_BUS2SC(parm->udev->bus); 2510 xfer = parm->curr_xfer; 2511 2512 parm->hc_max_packet_size = 0x500; 2513 parm->hc_max_packet_count = 1; 2514 parm->hc_max_frame_size = OHCI_PAGE_SIZE; 2515 2516 /* 2517 * calculate ntd and nqh 2518 */ 2519 if (parm->methods == &ohci_device_ctrl_methods) { 2520 xfer->flags_int.bdma_enable = 1; 2521 2522 usb2_transfer_setup_sub(parm); 2523 2524 nitd = 0; 2525 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2526 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 2527 nqh = 1; 2528 2529 } else if (parm->methods == &ohci_device_bulk_methods) { 2530 xfer->flags_int.bdma_enable = 1; 2531 2532 usb2_transfer_setup_sub(parm); 2533 2534 nitd = 0; 2535 ntd = ((2 * xfer->nframes) 2536 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 2537 nqh = 1; 2538 2539 } else if (parm->methods == &ohci_device_intr_methods) { 2540 xfer->flags_int.bdma_enable = 1; 2541 2542 usb2_transfer_setup_sub(parm); 2543 2544 nitd = 0; 2545 ntd = ((2 * xfer->nframes) 2546 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 2547 nqh = 1; 2548 2549 } else if (parm->methods == &ohci_device_isoc_methods) { 2550 xfer->flags_int.bdma_enable = 1; 2551 2552 usb2_transfer_setup_sub(parm); 2553 2554 nitd = ((xfer->max_data_length / OHCI_PAGE_SIZE) + 2555 ((xfer->nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET) + 2556 1 /* EXTRA */ ); 2557 ntd = 0; 2558 nqh = 1; 2559 2560 } else { 2561 2562 usb2_transfer_setup_sub(parm); 2563 2564 nitd = 0; 2565 ntd = 0; 2566 nqh = 0; 2567 } 2568 2569alloc_dma_set: 2570 2571 if (parm->err) { 2572 return; 2573 } 2574 last_obj = NULL; 2575 2576 if (usb2_transfer_setup_sub_malloc( 2577 parm, &pc, sizeof(ohci_td_t), 2578 OHCI_TD_ALIGN, ntd)) { 2579 parm->err = USB_ERR_NOMEM; 2580 return; 2581 } 2582 if (parm->buf) { 2583 for (n = 0; n != ntd; n++) { 2584 ohci_td_t *td; 2585 2586 usb2_get_page(pc + n, 0, &page_info); 2587 2588 td = page_info.buffer; 2589 2590 /* init TD */ 2591 td->td_self = htole32(page_info.physaddr); 2592 td->obj_next = last_obj; 2593 td->page_cache = pc + n; 2594 2595 last_obj = td; 2596 2597 usb2_pc_cpu_flush(pc + n); 2598 } 2599 } 2600 if (usb2_transfer_setup_sub_malloc( 2601 parm, &pc, sizeof(ohci_itd_t), 2602 OHCI_ITD_ALIGN, nitd)) { 2603 parm->err = USB_ERR_NOMEM; 2604 return; 2605 } 2606 if (parm->buf) { 2607 for (n = 0; n != nitd; n++) { 2608 ohci_itd_t *itd; 2609 2610 usb2_get_page(pc + n, 0, &page_info); 2611 2612 itd = page_info.buffer; 2613 2614 /* init TD */ 2615 itd->itd_self = htole32(page_info.physaddr); 2616 itd->obj_next = last_obj; 2617 itd->page_cache = pc + n; 2618 2619 last_obj = itd; 2620 2621 usb2_pc_cpu_flush(pc + n); 2622 } 2623 } 2624 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2625 2626 last_obj = NULL; 2627 2628 if (usb2_transfer_setup_sub_malloc( 2629 parm, &pc, sizeof(ohci_ed_t), 2630 OHCI_ED_ALIGN, nqh)) { 2631 parm->err = USB_ERR_NOMEM; 2632 return; 2633 } 2634 if (parm->buf) { 2635 for (n = 0; n != nqh; n++) { 2636 ohci_ed_t *ed; 2637 2638 usb2_get_page(pc + n, 0, &page_info); 2639 2640 ed = page_info.buffer; 2641 2642 /* init QH */ 2643 ed->ed_self = htole32(page_info.physaddr); 2644 ed->obj_next = last_obj; 2645 ed->page_cache = pc + n; 2646 2647 last_obj = ed; 2648 2649 usb2_pc_cpu_flush(pc + n); 2650 } 2651 } 2652 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 2653 2654 if (!xfer->flags_int.curr_dma_set) { 2655 xfer->flags_int.curr_dma_set = 1; 2656 goto alloc_dma_set; 2657 } 2658} 2659 2660static void 2661ohci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2662 struct usb2_pipe *pipe) 2663{ 2664 ohci_softc_t *sc = OHCI_BUS2SC(udev->bus); 2665 2666 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2667 pipe, udev->address, 2668 edesc->bEndpointAddress, udev->flags.usb2_mode, 2669 sc->sc_addr); 2670 2671 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2672 /* not supported */ 2673 return; 2674 } 2675 if (udev->device_index == sc->sc_addr) { 2676 switch (edesc->bEndpointAddress) { 2677 case USB_CONTROL_ENDPOINT: 2678 pipe->methods = &ohci_root_ctrl_methods; 2679 break; 2680 case UE_DIR_IN | OHCI_INTR_ENDPT: 2681 pipe->methods = &ohci_root_intr_methods; 2682 break; 2683 default: 2684 /* do nothing */ 2685 break; 2686 } 2687 } else { 2688 switch (edesc->bmAttributes & UE_XFERTYPE) { 2689 case UE_CONTROL: 2690 pipe->methods = &ohci_device_ctrl_methods; 2691 break; 2692 case UE_INTERRUPT: 2693 pipe->methods = &ohci_device_intr_methods; 2694 break; 2695 case UE_ISOCHRONOUS: 2696 if (udev->speed == USB_SPEED_FULL) { 2697 pipe->methods = &ohci_device_isoc_methods; 2698 } 2699 break; 2700 case UE_BULK: 2701 if (udev->speed != USB_SPEED_LOW) { 2702 pipe->methods = &ohci_device_bulk_methods; 2703 } 2704 break; 2705 default: 2706 /* do nothing */ 2707 break; 2708 } 2709 } 2710} 2711 2712static void 2713ohci_xfer_unsetup(struct usb2_xfer *xfer) 2714{ 2715 return; 2716} 2717 2718static void 2719ohci_get_dma_delay(struct usb2_bus *bus, uint32_t *pus) 2720{ 2721 /* 2722 * Wait until hardware has finished any possible use of the 2723 * transfer descriptor(s) and QH 2724 */ 2725 *pus = (1125); /* microseconds */ 2726} 2727 2728static void 2729ohci_device_resume(struct usb2_device *udev) 2730{ 2731 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2732 struct usb2_xfer *xfer; 2733 struct usb2_pipe_methods *methods; 2734 ohci_ed_t *ed; 2735 2736 DPRINTF("\n"); 2737 2738 USB_BUS_LOCK(udev->bus); 2739 2740 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2741 2742 if (xfer->xroot->udev == udev) { 2743 2744 methods = xfer->pipe->methods; 2745 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2746 2747 if (methods == &ohci_device_bulk_methods) { 2748 OHCI_APPEND_QH(ed, sc->sc_bulk_p_last); 2749 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2750 } 2751 if (methods == &ohci_device_ctrl_methods) { 2752 OHCI_APPEND_QH(ed, sc->sc_ctrl_p_last); 2753 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2754 } 2755 if (methods == &ohci_device_intr_methods) { 2756 OHCI_APPEND_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2757 } 2758 } 2759 } 2760 2761 USB_BUS_UNLOCK(udev->bus); 2762 2763 return; 2764} 2765 2766static void 2767ohci_device_suspend(struct usb2_device *udev) 2768{ 2769 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2770 struct usb2_xfer *xfer; 2771 struct usb2_pipe_methods *methods; 2772 ohci_ed_t *ed; 2773 2774 DPRINTF("\n"); 2775 2776 USB_BUS_LOCK(udev->bus); 2777 2778 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2779 2780 if (xfer->xroot->udev == udev) { 2781 2782 methods = xfer->pipe->methods; 2783 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2784 2785 if (methods == &ohci_device_bulk_methods) { 2786 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 2787 } 2788 if (methods == &ohci_device_ctrl_methods) { 2789 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 2790 } 2791 if (methods == &ohci_device_intr_methods) { 2792 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2793 } 2794 } 2795 } 2796 2797 USB_BUS_UNLOCK(udev->bus); 2798 2799 return; 2800} 2801 2802static void 2803ohci_set_hw_power(struct usb2_bus *bus) 2804{ 2805 struct ohci_softc *sc = OHCI_BUS2SC(bus); 2806 uint32_t temp; 2807 uint32_t flags; 2808 2809 DPRINTF("\n"); 2810 2811 USB_BUS_LOCK(bus); 2812 2813 flags = bus->hw_power_state; 2814 2815 temp = OREAD4(sc, OHCI_CONTROL); 2816 temp &= ~(OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE); 2817 2818 if (flags & USB_HW_POWER_CONTROL) 2819 temp |= OHCI_CLE; 2820 2821 if (flags & USB_HW_POWER_BULK) 2822 temp |= OHCI_BLE; 2823 2824 if (flags & USB_HW_POWER_INTERRUPT) 2825 temp |= OHCI_PLE; 2826 2827 if (flags & USB_HW_POWER_ISOC) 2828 temp |= OHCI_IE | OHCI_PLE; 2829 2830 OWRITE4(sc, OHCI_CONTROL, temp); 2831 2832 USB_BUS_UNLOCK(bus); 2833 2834 return; 2835} 2836 2837struct usb2_bus_methods ohci_bus_methods = 2838{ 2839 .pipe_init = ohci_pipe_init, 2840 .xfer_setup = ohci_xfer_setup, 2841 .xfer_unsetup = ohci_xfer_unsetup, 2842 .do_poll = ohci_do_poll, 2843 .get_dma_delay = ohci_get_dma_delay, 2844 .device_resume = ohci_device_resume, 2845 .device_suspend = ohci_device_suspend, 2846 .set_hw_power = ohci_set_hw_power, 2847 .roothub_exec = ohci_root_ctrl_task, 2848}; 2849