ohci.c revision 187172
1/*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/usb2/controller/ohci2.c 187172 2009-01-13 19:03:01Z thompsa $"); 30 31/* 32 * USB Open Host Controller driver. 33 * 34 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 35 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 36 */ 37 38#include <dev/usb2/include/usb2_standard.h> 39#include <dev/usb2/include/usb2_mfunc.h> 40#include <dev/usb2/include/usb2_error.h> 41#include <dev/usb2/include/usb2_defs.h> 42 43#define USB_DEBUG_VAR ohcidebug 44 45#include <dev/usb2/core/usb2_core.h> 46#include <dev/usb2/core/usb2_debug.h> 47#include <dev/usb2/core/usb2_busdma.h> 48#include <dev/usb2/core/usb2_process.h> 49#include <dev/usb2/core/usb2_sw_transfer.h> 50#include <dev/usb2/core/usb2_transfer.h> 51#include <dev/usb2/core/usb2_device.h> 52#include <dev/usb2/core/usb2_hub.h> 53#include <dev/usb2/core/usb2_util.h> 54 55#include <dev/usb2/controller/usb2_controller.h> 56#include <dev/usb2/controller/usb2_bus.h> 57#include <dev/usb2/controller/ohci2.h> 58 59#define OHCI_BUS2SC(bus) ((ohci_softc_t *)(((uint8_t *)(bus)) - \ 60 USB_P2U(&(((ohci_softc_t *)0)->sc_bus)))) 61 62#if USB_DEBUG 63static int ohcidebug = 0; 64 65SYSCTL_NODE(_hw_usb2, OID_AUTO, ohci, CTLFLAG_RW, 0, "USB ohci"); 66SYSCTL_INT(_hw_usb2_ohci, OID_AUTO, debug, CTLFLAG_RW, 67 &ohcidebug, 0, "ohci debug level"); 68static void ohci_dumpregs(ohci_softc_t *); 69static void ohci_dump_tds(ohci_td_t *); 70static uint8_t ohci_dump_td(ohci_td_t *); 71static void ohci_dump_ed(ohci_ed_t *); 72static uint8_t ohci_dump_itd(ohci_itd_t *); 73static void ohci_dump_itds(ohci_itd_t *); 74 75#endif 76 77#define OBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 78 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 79#define OWRITE1(sc, r, x) \ 80 do { OBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 81#define OWRITE2(sc, r, x) \ 82 do { OBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 83#define OWRITE4(sc, r, x) \ 84 do { OBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 85#define OREAD1(sc, r) (OBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 86#define OREAD2(sc, r) (OBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 87#define OREAD4(sc, r) (OBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 88 89#define OHCI_INTR_ENDPT 1 90 91extern struct usb2_bus_methods ohci_bus_methods; 92extern struct usb2_pipe_methods ohci_device_bulk_methods; 93extern struct usb2_pipe_methods ohci_device_ctrl_methods; 94extern struct usb2_pipe_methods ohci_device_intr_methods; 95extern struct usb2_pipe_methods ohci_device_isoc_methods; 96extern struct usb2_pipe_methods ohci_root_ctrl_methods; 97extern struct usb2_pipe_methods ohci_root_intr_methods; 98 99static void ohci_root_ctrl_poll(struct ohci_softc *sc); 100static void ohci_do_poll(struct usb2_bus *bus); 101static void ohci_device_done(struct usb2_xfer *xfer, usb2_error_t error); 102 103static usb2_sw_transfer_func_t ohci_root_intr_done; 104static usb2_sw_transfer_func_t ohci_root_ctrl_done; 105static void ohci_timeout(void *arg); 106static uint8_t ohci_check_transfer(struct usb2_xfer *xfer); 107 108struct ohci_std_temp { 109 struct usb2_page_cache *pc; 110 ohci_td_t *td; 111 ohci_td_t *td_next; 112 uint32_t average; 113 uint32_t td_flags; 114 uint32_t len; 115 uint16_t max_frame_size; 116 uint8_t shortpkt; 117 uint8_t setup_alt_next; 118 uint8_t short_frames_ok; 119}; 120 121static struct ohci_hcca * 122ohci_get_hcca(ohci_softc_t *sc) 123{ 124 usb2_pc_cpu_invalidate(&sc->sc_hw.hcca_pc); 125 return (sc->sc_hcca_p); 126} 127 128void 129ohci_iterate_hw_softc(struct usb2_bus *bus, usb2_bus_mem_sub_cb_t *cb) 130{ 131 struct ohci_softc *sc = OHCI_BUS2SC(bus); 132 uint32_t i; 133 134 cb(bus, &sc->sc_hw.hcca_pc, &sc->sc_hw.hcca_pg, 135 sizeof(ohci_hcca_t), OHCI_HCCA_ALIGN); 136 137 cb(bus, &sc->sc_hw.ctrl_start_pc, &sc->sc_hw.ctrl_start_pg, 138 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 139 140 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 141 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 142 143 cb(bus, &sc->sc_hw.isoc_start_pc, &sc->sc_hw.isoc_start_pg, 144 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 145 146 for (i = 0; i != OHCI_NO_EDS; i++) { 147 cb(bus, sc->sc_hw.intr_start_pc + i, sc->sc_hw.intr_start_pg + i, 148 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 149 } 150} 151 152static usb2_error_t 153ohci_controller_init(ohci_softc_t *sc) 154{ 155 struct usb2_page_search buf_res; 156 uint32_t i; 157 uint32_t ctl; 158 uint32_t ival; 159 uint32_t hcr; 160 uint32_t fm; 161 uint32_t per; 162 uint32_t desca; 163 164 /* Determine in what context we are running. */ 165 ctl = OREAD4(sc, OHCI_CONTROL); 166 if (ctl & OHCI_IR) { 167 /* SMM active, request change */ 168 DPRINTF("SMM active, request owner change\n"); 169 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_OCR); 170 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 171 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1); 172 ctl = OREAD4(sc, OHCI_CONTROL); 173 } 174 if (ctl & OHCI_IR) { 175 device_printf(sc->sc_bus.bdev, 176 "SMM does not respond, resetting\n"); 177 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 178 goto reset; 179 } 180 } else { 181 DPRINTF("cold started\n"); 182reset: 183 /* controller was cold started */ 184 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 185 USB_BUS_RESET_DELAY); 186 } 187 188 /* 189 * This reset should not be necessary according to the OHCI spec, but 190 * without it some controllers do not start. 191 */ 192 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 193 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 194 195 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 196 USB_BUS_RESET_DELAY); 197 198 /* we now own the host controller and the bus has been reset */ 199 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL)); 200 201 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 202 /* nominal time for a reset is 10 us */ 203 for (i = 0; i < 10; i++) { 204 DELAY(10); 205 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 206 if (!hcr) { 207 break; 208 } 209 } 210 if (hcr) { 211 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 212 return (USB_ERR_IOERROR); 213 } 214#if USB_DEBUG 215 if (ohcidebug > 15) { 216 ohci_dumpregs(sc); 217 } 218#endif 219 220 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 221 222 /* set up HC registers */ 223 usb2_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 224 OWRITE4(sc, OHCI_HCCA, buf_res.physaddr); 225 226 usb2_get_page(&sc->sc_hw.ctrl_start_pc, 0, &buf_res); 227 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, buf_res.physaddr); 228 229 usb2_get_page(&sc->sc_hw.bulk_start_pc, 0, &buf_res); 230 OWRITE4(sc, OHCI_BULK_HEAD_ED, buf_res.physaddr); 231 232 /* disable all interrupts and then switch on all desired interrupts */ 233 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 234 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 235 /* switch on desired functional features */ 236 ctl = OREAD4(sc, OHCI_CONTROL); 237 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 238 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 239 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL; 240 /* And finally start it! */ 241 OWRITE4(sc, OHCI_CONTROL, ctl); 242 243 /* 244 * The controller is now OPERATIONAL. Set a some final 245 * registers that should be set earlier, but that the 246 * controller ignores when in the SUSPEND state. 247 */ 248 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 249 fm |= OHCI_FSMPS(ival) | ival; 250 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 251 per = OHCI_PERIODIC(ival); /* 90% periodic */ 252 OWRITE4(sc, OHCI_PERIODIC_START, per); 253 254 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 255 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 256 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 257 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 258 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 259 OHCI_ENABLE_POWER_DELAY); 260 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 261 262 /* 263 * The AMD756 requires a delay before re-reading the register, 264 * otherwise it will occasionally report 0 ports. 265 */ 266 sc->sc_noport = 0; 267 for (i = 0; (i < 10) && (sc->sc_noport == 0); i++) { 268 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 269 OHCI_READ_DESC_DELAY); 270 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 271 } 272 273#if USB_DEBUG 274 if (ohcidebug > 5) { 275 ohci_dumpregs(sc); 276 } 277#endif 278 return (USB_ERR_NORMAL_COMPLETION); 279} 280 281static struct ohci_ed * 282ohci_init_ed(struct usb2_page_cache *pc) 283{ 284 struct usb2_page_search buf_res; 285 struct ohci_ed *ed; 286 287 usb2_get_page(pc, 0, &buf_res); 288 289 ed = buf_res.buffer; 290 291 ed->ed_self = htole32(buf_res.physaddr); 292 ed->ed_flags = htole32(OHCI_ED_SKIP); 293 ed->page_cache = pc; 294 295 return (ed); 296} 297 298usb2_error_t 299ohci_init(ohci_softc_t *sc) 300{ 301 struct usb2_page_search buf_res; 302 uint16_t i; 303 uint16_t bit; 304 uint16_t x; 305 uint16_t y; 306 307 USB_BUS_LOCK(&sc->sc_bus); 308 309 DPRINTF("start\n"); 310 311 sc->sc_eintrs = OHCI_NORMAL_INTRS; 312 313 /* 314 * Setup all ED's 315 */ 316 317 sc->sc_ctrl_p_last = 318 ohci_init_ed(&sc->sc_hw.ctrl_start_pc); 319 320 sc->sc_bulk_p_last = 321 ohci_init_ed(&sc->sc_hw.bulk_start_pc); 322 323 sc->sc_isoc_p_last = 324 ohci_init_ed(&sc->sc_hw.isoc_start_pc); 325 326 for (i = 0; i != OHCI_NO_EDS; i++) { 327 sc->sc_intr_p_last[i] = 328 ohci_init_ed(sc->sc_hw.intr_start_pc + i); 329 } 330 331 /* 332 * the QHs are arranged to give poll intervals that are 333 * powers of 2 times 1ms 334 */ 335 bit = OHCI_NO_EDS / 2; 336 while (bit) { 337 x = bit; 338 while (x & bit) { 339 ohci_ed_t *ed_x; 340 ohci_ed_t *ed_y; 341 342 y = (x ^ bit) | (bit / 2); 343 344 /* 345 * the next QH has half the poll interval 346 */ 347 ed_x = sc->sc_intr_p_last[x]; 348 ed_y = sc->sc_intr_p_last[y]; 349 350 ed_x->next = NULL; 351 ed_x->ed_next = ed_y->ed_self; 352 353 x++; 354 } 355 bit >>= 1; 356 } 357 358 if (1) { 359 360 ohci_ed_t *ed_int; 361 ohci_ed_t *ed_isc; 362 363 ed_int = sc->sc_intr_p_last[0]; 364 ed_isc = sc->sc_isoc_p_last; 365 366 /* the last (1ms) QH */ 367 ed_int->next = ed_isc; 368 ed_int->ed_next = ed_isc->ed_self; 369 } 370 usb2_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 371 372 sc->sc_hcca_p = buf_res.buffer; 373 374 /* 375 * Fill HCCA interrupt table. The bit reversal is to get 376 * the tree set up properly to spread the interrupts. 377 */ 378 for (i = 0; i != OHCI_NO_INTRS; i++) { 379 sc->sc_hcca_p->hcca_interrupt_table[i] = 380 sc->sc_intr_p_last[i | (OHCI_NO_EDS / 2)]->ed_self; 381 } 382 /* flush all cache into memory */ 383 384 usb2_bus_mem_flush_all(&sc->sc_bus, &ohci_iterate_hw_softc); 385 386 /* set up the bus struct */ 387 sc->sc_bus.methods = &ohci_bus_methods; 388 389 usb2_callout_init_mtx(&sc->sc_tmo_rhsc, &sc->sc_bus.bus_mtx, 0); 390 391#if USB_DEBUG 392 if (ohcidebug > 15) { 393 for (i = 0; i != OHCI_NO_EDS; i++) { 394 printf("ed#%d ", i); 395 ohci_dump_ed(sc->sc_intr_p_last[i]); 396 } 397 printf("iso "); 398 ohci_dump_ed(sc->sc_isoc_p_last); 399 } 400#endif 401 402 sc->sc_bus.usbrev = USB_REV_1_0; 403 404 if (ohci_controller_init(sc)) { 405 USB_BUS_UNLOCK(&sc->sc_bus); 406 return (USB_ERR_INVAL); 407 } else { 408 USB_BUS_UNLOCK(&sc->sc_bus); 409 /* catch any lost interrupts */ 410 ohci_do_poll(&sc->sc_bus); 411 return (USB_ERR_NORMAL_COMPLETION); 412 } 413} 414 415/* 416 * shut down the controller when the system is going down 417 */ 418void 419ohci_detach(struct ohci_softc *sc) 420{ 421 USB_BUS_LOCK(&sc->sc_bus); 422 423 usb2_callout_stop(&sc->sc_tmo_rhsc); 424 425 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 426 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 427 428 /* XXX let stray task complete */ 429 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 50); 430 431 USB_BUS_UNLOCK(&sc->sc_bus); 432 433 usb2_callout_drain(&sc->sc_tmo_rhsc); 434} 435 436/* NOTE: suspend/resume is called from 437 * interrupt context and cannot sleep! 438 */ 439void 440ohci_suspend(ohci_softc_t *sc) 441{ 442 uint32_t ctl; 443 444 USB_BUS_LOCK(&sc->sc_bus); 445 446#if USB_DEBUG 447 DPRINTF("\n"); 448 if (ohcidebug > 2) { 449 ohci_dumpregs(sc); 450 } 451#endif 452 453 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 454 if (sc->sc_control == 0) { 455 /* 456 * Preserve register values, in case that APM BIOS 457 * does not recover them. 458 */ 459 sc->sc_control = ctl; 460 sc->sc_intre = OREAD4(sc, OHCI_INTERRUPT_ENABLE); 461 } 462 ctl |= OHCI_HCFS_SUSPEND; 463 OWRITE4(sc, OHCI_CONTROL, ctl); 464 465 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 466 USB_RESUME_WAIT); 467 468 USB_BUS_UNLOCK(&sc->sc_bus); 469} 470 471void 472ohci_resume(ohci_softc_t *sc) 473{ 474 uint32_t ctl; 475 476 USB_BUS_LOCK(&sc->sc_bus); 477 478#if USB_DEBUG 479 DPRINTF("\n"); 480 if (ohcidebug > 2) { 481 ohci_dumpregs(sc); 482 } 483#endif 484 /* some broken BIOSes never initialize the Controller chip */ 485 ohci_controller_init(sc); 486 487 if (sc->sc_intre) { 488 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, 489 sc->sc_intre & (OHCI_ALL_INTRS | OHCI_MIE)); 490 } 491 if (sc->sc_control) 492 ctl = sc->sc_control; 493 else 494 ctl = OREAD4(sc, OHCI_CONTROL); 495 ctl |= OHCI_HCFS_RESUME; 496 OWRITE4(sc, OHCI_CONTROL, ctl); 497 usb2_pause_mtx(&sc->sc_bus.bus_mtx, USB_RESUME_DELAY); 498 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 499 OWRITE4(sc, OHCI_CONTROL, ctl); 500 usb2_pause_mtx(&sc->sc_bus.bus_mtx, USB_RESUME_RECOVERY); 501 sc->sc_control = sc->sc_intre = 0; 502 503 USB_BUS_UNLOCK(&sc->sc_bus); 504 505 /* catch any lost interrupts */ 506 ohci_do_poll(&sc->sc_bus); 507} 508 509#if USB_DEBUG 510static void 511ohci_dumpregs(ohci_softc_t *sc) 512{ 513 struct ohci_hcca *hcca; 514 515 DPRINTF("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 516 OREAD4(sc, OHCI_REVISION), 517 OREAD4(sc, OHCI_CONTROL), 518 OREAD4(sc, OHCI_COMMAND_STATUS)); 519 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 520 OREAD4(sc, OHCI_INTERRUPT_STATUS), 521 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 522 OREAD4(sc, OHCI_INTERRUPT_DISABLE)); 523 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 524 OREAD4(sc, OHCI_HCCA), 525 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 526 OREAD4(sc, OHCI_CONTROL_HEAD_ED)); 527 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 528 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 529 OREAD4(sc, OHCI_BULK_HEAD_ED), 530 OREAD4(sc, OHCI_BULK_CURRENT_ED)); 531 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 532 OREAD4(sc, OHCI_DONE_HEAD), 533 OREAD4(sc, OHCI_FM_INTERVAL), 534 OREAD4(sc, OHCI_FM_REMAINING)); 535 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 536 OREAD4(sc, OHCI_FM_NUMBER), 537 OREAD4(sc, OHCI_PERIODIC_START), 538 OREAD4(sc, OHCI_LS_THRESHOLD)); 539 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x\n", 540 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 541 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 542 OREAD4(sc, OHCI_RH_STATUS)); 543 DPRINTF(" port1=0x%08x port2=0x%08x\n", 544 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 545 OREAD4(sc, OHCI_RH_PORT_STATUS(2))); 546 547 hcca = ohci_get_hcca(sc); 548 549 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x\n", 550 le32toh(hcca->hcca_frame_number), 551 le32toh(hcca->hcca_done_head)); 552} 553static void 554ohci_dump_tds(ohci_td_t *std) 555{ 556 for (; std; std = std->obj_next) { 557 if (ohci_dump_td(std)) { 558 break; 559 } 560 } 561} 562 563static uint8_t 564ohci_dump_td(ohci_td_t *std) 565{ 566 uint32_t td_flags; 567 uint8_t temp; 568 569 usb2_pc_cpu_invalidate(std->page_cache); 570 571 td_flags = le32toh(std->td_flags); 572 temp = (std->td_next == 0); 573 574 printf("TD(%p) at 0x%08x: %s%s%s%s%s delay=%d ec=%d " 575 "cc=%d\ncbp=0x%08x next=0x%08x be=0x%08x\n", 576 std, le32toh(std->td_self), 577 (td_flags & OHCI_TD_R) ? "-R" : "", 578 (td_flags & OHCI_TD_OUT) ? "-OUT" : "", 579 (td_flags & OHCI_TD_IN) ? "-IN" : "", 580 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_1) ? "-TOG1" : "", 581 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_0) ? "-TOG0" : "", 582 OHCI_TD_GET_DI(td_flags), 583 OHCI_TD_GET_EC(td_flags), 584 OHCI_TD_GET_CC(td_flags), 585 le32toh(std->td_cbp), 586 le32toh(std->td_next), 587 le32toh(std->td_be)); 588 589 return (temp); 590} 591 592static uint8_t 593ohci_dump_itd(ohci_itd_t *sitd) 594{ 595 uint32_t itd_flags; 596 uint16_t i; 597 uint8_t temp; 598 599 usb2_pc_cpu_invalidate(sitd->page_cache); 600 601 itd_flags = le32toh(sitd->itd_flags); 602 temp = (sitd->itd_next == 0); 603 604 printf("ITD(%p) at 0x%08x: sf=%d di=%d fc=%d cc=%d\n" 605 "bp0=0x%08x next=0x%08x be=0x%08x\n", 606 sitd, le32toh(sitd->itd_self), 607 OHCI_ITD_GET_SF(itd_flags), 608 OHCI_ITD_GET_DI(itd_flags), 609 OHCI_ITD_GET_FC(itd_flags), 610 OHCI_ITD_GET_CC(itd_flags), 611 le32toh(sitd->itd_bp0), 612 le32toh(sitd->itd_next), 613 le32toh(sitd->itd_be)); 614 for (i = 0; i < OHCI_ITD_NOFFSET; i++) { 615 printf("offs[%d]=0x%04x ", i, 616 (uint32_t)le16toh(sitd->itd_offset[i])); 617 } 618 printf("\n"); 619 620 return (temp); 621} 622 623static void 624ohci_dump_itds(ohci_itd_t *sitd) 625{ 626 for (; sitd; sitd = sitd->obj_next) { 627 if (ohci_dump_itd(sitd)) { 628 break; 629 } 630 } 631} 632 633static void 634ohci_dump_ed(ohci_ed_t *sed) 635{ 636 uint32_t ed_flags; 637 uint32_t ed_headp; 638 639 usb2_pc_cpu_invalidate(sed->page_cache); 640 641 ed_flags = le32toh(sed->ed_flags); 642 ed_headp = le32toh(sed->ed_headp); 643 644 printf("ED(%p) at 0x%08x: addr=%d endpt=%d maxp=%d flags=%s%s%s%s%s\n" 645 "tailp=0x%08x headflags=%s%s headp=0x%08x nexted=0x%08x\n", 646 sed, le32toh(sed->ed_self), 647 OHCI_ED_GET_FA(ed_flags), 648 OHCI_ED_GET_EN(ed_flags), 649 OHCI_ED_GET_MAXP(ed_flags), 650 (ed_flags & OHCI_ED_DIR_OUT) ? "-OUT" : "", 651 (ed_flags & OHCI_ED_DIR_IN) ? "-IN" : "", 652 (ed_flags & OHCI_ED_SPEED) ? "-LOWSPEED" : "", 653 (ed_flags & OHCI_ED_SKIP) ? "-SKIP" : "", 654 (ed_flags & OHCI_ED_FORMAT_ISO) ? "-ISO" : "", 655 le32toh(sed->ed_tailp), 656 (ed_headp & OHCI_HALTED) ? "-HALTED" : "", 657 (ed_headp & OHCI_TOGGLECARRY) ? "-CARRY" : "", 658 le32toh(sed->ed_headp), 659 le32toh(sed->ed_next)); 660} 661 662#endif 663 664static void 665ohci_transfer_intr_enqueue(struct usb2_xfer *xfer) 666{ 667 /* check for early completion */ 668 if (ohci_check_transfer(xfer)) { 669 return; 670 } 671 /* put transfer on interrupt queue */ 672 usb2_transfer_enqueue(&xfer->udev->bus->intr_q, xfer); 673 674 /* start timeout, if any */ 675 if (xfer->timeout != 0) { 676 usb2_transfer_timeout_ms(xfer, &ohci_timeout, xfer->timeout); 677 } 678} 679 680#define OHCI_APPEND_QH(sed,last) (last) = _ohci_append_qh(sed,last) 681static ohci_ed_t * 682_ohci_append_qh(ohci_ed_t *sed, ohci_ed_t *last) 683{ 684 DPRINTFN(11, "%p to %p\n", sed, last); 685 686 if (sed->prev != NULL) { 687 /* should not happen */ 688 DPRINTFN(0, "ED already linked!\n"); 689 return (last); 690 } 691 /* (sc->sc_bus.bus_mtx) must be locked */ 692 693 sed->next = last->next; 694 sed->ed_next = last->ed_next; 695 sed->ed_tailp = 0; 696 697 sed->prev = last; 698 699 usb2_pc_cpu_flush(sed->page_cache); 700 701 /* 702 * the last->next->prev is never followed: sed->next->prev = sed; 703 */ 704 705 last->next = sed; 706 last->ed_next = sed->ed_self; 707 708 usb2_pc_cpu_flush(last->page_cache); 709 710 return (sed); 711} 712 713#define OHCI_REMOVE_QH(sed,last) (last) = _ohci_remove_qh(sed,last) 714static ohci_ed_t * 715_ohci_remove_qh(ohci_ed_t *sed, ohci_ed_t *last) 716{ 717 DPRINTFN(11, "%p from %p\n", sed, last); 718 719 /* (sc->sc_bus.bus_mtx) must be locked */ 720 721 /* only remove if not removed from a queue */ 722 if (sed->prev) { 723 724 sed->prev->next = sed->next; 725 sed->prev->ed_next = sed->ed_next; 726 727 usb2_pc_cpu_flush(sed->prev->page_cache); 728 729 if (sed->next) { 730 sed->next->prev = sed->prev; 731 usb2_pc_cpu_flush(sed->next->page_cache); 732 } 733 last = ((last == sed) ? sed->prev : last); 734 735 sed->prev = 0; 736 737 usb2_pc_cpu_flush(sed->page_cache); 738 } 739 return (last); 740} 741 742static void 743ohci_isoc_done(struct usb2_xfer *xfer) 744{ 745 uint8_t nframes; 746 uint32_t *plen = xfer->frlengths; 747 volatile uint16_t *olen; 748 uint16_t len = 0; 749 ohci_itd_t *td = xfer->td_transfer_first; 750 751 while (1) { 752 if (td == NULL) { 753 panic("%s:%d: out of TD's\n", 754 __FUNCTION__, __LINE__); 755 } 756#if USB_DEBUG 757 if (ohcidebug > 5) { 758 DPRINTF("isoc TD\n"); 759 ohci_dump_itd(td); 760 } 761#endif 762 usb2_pc_cpu_invalidate(td->page_cache); 763 764 nframes = td->frames; 765 olen = &td->itd_offset[0]; 766 767 if (nframes > 8) { 768 nframes = 8; 769 } 770 while (nframes--) { 771 len = le16toh(*olen); 772 773 if ((len >> 12) == OHCI_CC_NOT_ACCESSED) { 774 len = 0; 775 } else { 776 len &= ((1 << 12) - 1); 777 } 778 779 if (len > *plen) { 780 len = 0;/* invalid length */ 781 } 782 *plen = len; 783 plen++; 784 olen++; 785 } 786 787 if (((void *)td) == xfer->td_transfer_last) { 788 break; 789 } 790 td = td->obj_next; 791 } 792 793 xfer->aframes = xfer->nframes; 794 ohci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 795} 796 797#if USB_DEBUG 798static const char *const 799 ohci_cc_strs[] = 800{ 801 "NO_ERROR", 802 "CRC", 803 "BIT_STUFFING", 804 "DATA_TOGGLE_MISMATCH", 805 806 "STALL", 807 "DEVICE_NOT_RESPONDING", 808 "PID_CHECK_FAILURE", 809 "UNEXPECTED_PID", 810 811 "DATA_OVERRUN", 812 "DATA_UNDERRUN", 813 "BUFFER_OVERRUN", 814 "BUFFER_UNDERRUN", 815 816 "reserved", 817 "reserved", 818 "NOT_ACCESSED", 819 "NOT_ACCESSED" 820}; 821 822#endif 823 824static usb2_error_t 825ohci_non_isoc_done_sub(struct usb2_xfer *xfer) 826{ 827 ohci_td_t *td; 828 ohci_td_t *td_alt_next; 829 uint32_t temp; 830 uint32_t phy_start; 831 uint32_t phy_end; 832 uint32_t td_flags; 833 uint16_t cc; 834 835 td = xfer->td_transfer_cache; 836 td_alt_next = td->alt_next; 837 td_flags = 0; 838 839 while (1) { 840 841 usb2_pc_cpu_invalidate(td->page_cache); 842 phy_start = le32toh(td->td_cbp); 843 td_flags = le32toh(td->td_flags); 844 cc = OHCI_TD_GET_CC(td_flags); 845 846 if (phy_start) { 847 /* 848 * short transfer - compute the number of remaining 849 * bytes in the hardware buffer: 850 */ 851 phy_end = le32toh(td->td_be); 852 temp = (OHCI_PAGE(phy_start ^ phy_end) ? 853 (OHCI_PAGE_SIZE + 1) : 0x0001); 854 temp += OHCI_PAGE_OFFSET(phy_end); 855 temp -= OHCI_PAGE_OFFSET(phy_start); 856 857 if (temp > td->len) { 858 /* guard against corruption */ 859 cc = OHCI_CC_STALL; 860 } else if (xfer->aframes != xfer->nframes) { 861 /* 862 * subtract remaining length from 863 * "frlengths[]" 864 */ 865 xfer->frlengths[xfer->aframes] -= temp; 866 } 867 } 868 /* Check for last transfer */ 869 if (((void *)td) == xfer->td_transfer_last) { 870 td = NULL; 871 break; 872 } 873 /* Check transfer status */ 874 if (cc) { 875 /* the transfer is finished */ 876 td = NULL; 877 break; 878 } 879 /* Check for short transfer */ 880 if (phy_start) { 881 if (xfer->flags_int.short_frames_ok) { 882 /* follow alt next */ 883 td = td->alt_next; 884 } else { 885 /* the transfer is finished */ 886 td = NULL; 887 } 888 break; 889 } 890 td = td->obj_next; 891 892 if (td->alt_next != td_alt_next) { 893 /* this USB frame is complete */ 894 break; 895 } 896 } 897 898 /* update transfer cache */ 899 900 xfer->td_transfer_cache = td; 901 902 DPRINTFN(16, "error cc=%d (%s)\n", 903 cc, ohci_cc_strs[cc]); 904 905 return ((cc == 0) ? USB_ERR_NORMAL_COMPLETION : 906 (cc == OHCI_CC_STALL) ? USB_ERR_STALLED : USB_ERR_IOERROR); 907} 908 909static void 910ohci_non_isoc_done(struct usb2_xfer *xfer) 911{ 912 usb2_error_t err = 0; 913 914 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 915 xfer, xfer->pipe); 916 917#if USB_DEBUG 918 if (ohcidebug > 10) { 919 ohci_dump_tds(xfer->td_transfer_first); 920 } 921#endif 922 923 /* reset scanner */ 924 925 xfer->td_transfer_cache = xfer->td_transfer_first; 926 927 if (xfer->flags_int.control_xfr) { 928 929 if (xfer->flags_int.control_hdr) { 930 931 err = ohci_non_isoc_done_sub(xfer); 932 } 933 xfer->aframes = 1; 934 935 if (xfer->td_transfer_cache == NULL) { 936 goto done; 937 } 938 } 939 while (xfer->aframes != xfer->nframes) { 940 941 err = ohci_non_isoc_done_sub(xfer); 942 xfer->aframes++; 943 944 if (xfer->td_transfer_cache == NULL) { 945 goto done; 946 } 947 } 948 949 if (xfer->flags_int.control_xfr && 950 !xfer->flags_int.control_act) { 951 952 err = ohci_non_isoc_done_sub(xfer); 953 } 954done: 955 ohci_device_done(xfer, err); 956} 957 958/*------------------------------------------------------------------------* 959 * ohci_check_transfer_sub 960 *------------------------------------------------------------------------*/ 961static void 962ohci_check_transfer_sub(struct usb2_xfer *xfer) 963{ 964 ohci_td_t *td; 965 ohci_ed_t *ed; 966 uint32_t phy_start; 967 uint32_t td_flags; 968 uint32_t td_next; 969 uint16_t cc; 970 971 td = xfer->td_transfer_cache; 972 973 while (1) { 974 975 usb2_pc_cpu_invalidate(td->page_cache); 976 phy_start = le32toh(td->td_cbp); 977 td_flags = le32toh(td->td_flags); 978 td_next = le32toh(td->td_next); 979 980 /* Check for last transfer */ 981 if (((void *)td) == xfer->td_transfer_last) { 982 /* the transfer is finished */ 983 td = NULL; 984 break; 985 } 986 /* Check transfer status */ 987 cc = OHCI_TD_GET_CC(td_flags); 988 if (cc) { 989 /* the transfer is finished */ 990 td = NULL; 991 break; 992 } 993 /* 994 * Check if we reached the last packet 995 * or if there is a short packet: 996 */ 997 998 if (((td_next & (~0xF)) == OHCI_TD_NEXT_END) || phy_start) { 999 /* follow alt next */ 1000 td = td->alt_next; 1001 break; 1002 } 1003 td = td->obj_next; 1004 } 1005 1006 /* update transfer cache */ 1007 1008 xfer->td_transfer_cache = td; 1009 1010 if (td) { 1011 1012 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1013 1014 ed->ed_headp = td->td_self; 1015 usb2_pc_cpu_flush(ed->page_cache); 1016 1017 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1018 } 1019} 1020 1021/*------------------------------------------------------------------------* 1022 * ohci_check_transfer 1023 * 1024 * Return values: 1025 * 0: USB transfer is not finished 1026 * Else: USB transfer is finished 1027 *------------------------------------------------------------------------*/ 1028static uint8_t 1029ohci_check_transfer(struct usb2_xfer *xfer) 1030{ 1031 ohci_ed_t *ed; 1032 uint32_t ed_flags; 1033 uint32_t ed_headp; 1034 uint32_t ed_tailp; 1035 1036 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1037 1038 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1039 1040 usb2_pc_cpu_invalidate(ed->page_cache); 1041 ed_flags = le32toh(ed->ed_flags); 1042 ed_headp = le32toh(ed->ed_headp); 1043 ed_tailp = le32toh(ed->ed_tailp); 1044 1045 if ((ed_flags & OHCI_ED_SKIP) || 1046 (ed_headp & OHCI_HALTED) || 1047 (((ed_headp ^ ed_tailp) & (~0xF)) == 0)) { 1048 if (xfer->pipe->methods == &ohci_device_isoc_methods) { 1049 /* isochronous transfer */ 1050 ohci_isoc_done(xfer); 1051 } else { 1052 if (xfer->flags_int.short_frames_ok) { 1053 ohci_check_transfer_sub(xfer); 1054 if (xfer->td_transfer_cache) { 1055 /* not finished yet */ 1056 return (0); 1057 } 1058 } 1059 /* store data-toggle */ 1060 if (ed_headp & OHCI_TOGGLECARRY) { 1061 xfer->pipe->toggle_next = 1; 1062 } else { 1063 xfer->pipe->toggle_next = 0; 1064 } 1065 1066 /* non-isochronous transfer */ 1067 ohci_non_isoc_done(xfer); 1068 } 1069 return (1); 1070 } 1071 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1072 return (0); 1073} 1074 1075static void 1076ohci_rhsc_enable(ohci_softc_t *sc) 1077{ 1078 DPRINTFN(5, "\n"); 1079 1080 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1081 1082 sc->sc_eintrs |= OHCI_RHSC; 1083 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1084 1085 /* acknowledge any RHSC interrupt */ 1086 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_RHSC); 1087 1088 usb2_sw_transfer(&sc->sc_root_intr, 1089 &ohci_root_intr_done); 1090} 1091 1092static void 1093ohci_interrupt_poll(ohci_softc_t *sc) 1094{ 1095 struct usb2_xfer *xfer; 1096 1097repeat: 1098 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1099 /* 1100 * check if transfer is transferred 1101 */ 1102 if (ohci_check_transfer(xfer)) { 1103 /* queue has been modified */ 1104 goto repeat; 1105 } 1106 } 1107} 1108 1109/*------------------------------------------------------------------------* 1110 * ohci_interrupt - OHCI interrupt handler 1111 * 1112 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1113 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1114 * is present ! 1115 *------------------------------------------------------------------------*/ 1116void 1117ohci_interrupt(ohci_softc_t *sc) 1118{ 1119 struct ohci_hcca *hcca; 1120 uint32_t status; 1121 uint32_t done; 1122 1123 USB_BUS_LOCK(&sc->sc_bus); 1124 1125 hcca = ohci_get_hcca(sc); 1126 1127 DPRINTFN(16, "real interrupt\n"); 1128 1129#if USB_DEBUG 1130 if (ohcidebug > 15) { 1131 ohci_dumpregs(sc); 1132 } 1133#endif 1134 1135 done = le32toh(hcca->hcca_done_head); 1136 1137 /* 1138 * The LSb of done is used to inform the HC Driver that an interrupt 1139 * condition exists for both the Done list and for another event 1140 * recorded in HcInterruptStatus. On an interrupt from the HC, the 1141 * HC Driver checks the HccaDoneHead Value. If this value is 0, then 1142 * the interrupt was caused by other than the HccaDoneHead update 1143 * and the HcInterruptStatus register needs to be accessed to 1144 * determine that exact interrupt cause. If HccaDoneHead is nonzero, 1145 * then a Done list update interrupt is indicated and if the LSb of 1146 * done is nonzero, then an additional interrupt event is indicated 1147 * and HcInterruptStatus should be checked to determine its cause. 1148 */ 1149 if (done != 0) { 1150 status = 0; 1151 1152 if (done & ~OHCI_DONE_INTRS) { 1153 status |= OHCI_WDH; 1154 } 1155 if (done & OHCI_DONE_INTRS) { 1156 status |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 1157 } 1158 hcca->hcca_done_head = 0; 1159 1160 usb2_pc_cpu_flush(&sc->sc_hw.hcca_pc); 1161 } else { 1162 status = OREAD4(sc, OHCI_INTERRUPT_STATUS) & ~OHCI_WDH; 1163 } 1164 1165 status &= ~OHCI_MIE; 1166 if (status == 0) { 1167 /* 1168 * nothing to be done (PCI shared 1169 * interrupt) 1170 */ 1171 goto done; 1172 } 1173 OWRITE4(sc, OHCI_INTERRUPT_STATUS, status); /* Acknowledge */ 1174 1175 status &= sc->sc_eintrs; 1176 if (status == 0) { 1177 goto done; 1178 } 1179 if (status & (OHCI_SO | OHCI_RD | OHCI_UE | OHCI_RHSC)) { 1180#if 0 1181 if (status & OHCI_SO) { 1182 /* XXX do what */ 1183 } 1184#endif 1185 if (status & OHCI_RD) { 1186 printf("%s: resume detect\n", __FUNCTION__); 1187 /* XXX process resume detect */ 1188 } 1189 if (status & OHCI_UE) { 1190 printf("%s: unrecoverable error, " 1191 "controller halted\n", __FUNCTION__); 1192 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1193 /* XXX what else */ 1194 } 1195 if (status & OHCI_RHSC) { 1196 /* 1197 * Disable RHSC interrupt for now, because it will be 1198 * on until the port has been reset. 1199 */ 1200 sc->sc_eintrs &= ~OHCI_RHSC; 1201 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 1202 1203 usb2_sw_transfer(&sc->sc_root_intr, 1204 &ohci_root_intr_done); 1205 1206 /* do not allow RHSC interrupts > 1 per second */ 1207 usb2_callout_reset(&sc->sc_tmo_rhsc, hz, 1208 (void *)&ohci_rhsc_enable, sc); 1209 } 1210 } 1211 status &= ~(OHCI_RHSC | OHCI_WDH | OHCI_SO); 1212 if (status != 0) { 1213 /* Block unprocessed interrupts. XXX */ 1214 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, status); 1215 sc->sc_eintrs &= ~status; 1216 printf("%s: blocking intrs 0x%x\n", 1217 __FUNCTION__, status); 1218 } 1219 /* poll all the USB transfers */ 1220 ohci_interrupt_poll(sc); 1221 1222done: 1223 USB_BUS_UNLOCK(&sc->sc_bus); 1224} 1225 1226/* 1227 * called when a request does not complete 1228 */ 1229static void 1230ohci_timeout(void *arg) 1231{ 1232 struct usb2_xfer *xfer = arg; 1233 1234 DPRINTF("xfer=%p\n", xfer); 1235 1236 USB_BUS_LOCK_ASSERT(xfer->udev->bus, MA_OWNED); 1237 1238 /* transfer is transferred */ 1239 ohci_device_done(xfer, USB_ERR_TIMEOUT); 1240} 1241 1242static void 1243ohci_do_poll(struct usb2_bus *bus) 1244{ 1245 struct ohci_softc *sc = OHCI_BUS2SC(bus); 1246 1247 USB_BUS_LOCK(&sc->sc_bus); 1248 ohci_interrupt_poll(sc); 1249 ohci_root_ctrl_poll(sc); 1250 USB_BUS_UNLOCK(&sc->sc_bus); 1251} 1252 1253static void 1254ohci_setup_standard_chain_sub(struct ohci_std_temp *temp) 1255{ 1256 struct usb2_page_search buf_res; 1257 ohci_td_t *td; 1258 ohci_td_t *td_next; 1259 ohci_td_t *td_alt_next; 1260 uint32_t buf_offset; 1261 uint32_t average; 1262 uint32_t len_old; 1263 uint8_t shortpkt_old; 1264 uint8_t precompute; 1265 1266 td_alt_next = NULL; 1267 buf_offset = 0; 1268 shortpkt_old = temp->shortpkt; 1269 len_old = temp->len; 1270 precompute = 1; 1271 1272 /* software is used to detect short incoming transfers */ 1273 1274 if ((temp->td_flags & htole32(OHCI_TD_DP_MASK)) == htole32(OHCI_TD_IN)) { 1275 temp->td_flags |= htole32(OHCI_TD_R); 1276 } else { 1277 temp->td_flags &= ~htole32(OHCI_TD_R); 1278 } 1279 1280restart: 1281 1282 td = temp->td; 1283 td_next = temp->td_next; 1284 1285 while (1) { 1286 1287 if (temp->len == 0) { 1288 1289 if (temp->shortpkt) { 1290 break; 1291 } 1292 /* send a Zero Length Packet, ZLP, last */ 1293 1294 temp->shortpkt = 1; 1295 average = 0; 1296 1297 } else { 1298 1299 average = temp->average; 1300 1301 if (temp->len < average) { 1302 if (temp->len % temp->max_frame_size) { 1303 temp->shortpkt = 1; 1304 } 1305 average = temp->len; 1306 } 1307 } 1308 1309 if (td_next == NULL) { 1310 panic("%s: out of OHCI transfer descriptors!", __FUNCTION__); 1311 } 1312 /* get next TD */ 1313 1314 td = td_next; 1315 td_next = td->obj_next; 1316 1317 /* check if we are pre-computing */ 1318 1319 if (precompute) { 1320 1321 /* update remaining length */ 1322 1323 temp->len -= average; 1324 1325 continue; 1326 } 1327 /* fill out current TD */ 1328 td->td_flags = temp->td_flags; 1329 1330 /* the next TD uses TOGGLE_CARRY */ 1331 temp->td_flags &= ~htole32(OHCI_TD_TOGGLE_MASK); 1332 1333 if (average == 0) { 1334 1335 td->td_cbp = 0; 1336 td->td_be = ~0; 1337 td->len = 0; 1338 1339 } else { 1340 1341 usb2_get_page(temp->pc, buf_offset, &buf_res); 1342 td->td_cbp = htole32(buf_res.physaddr); 1343 buf_offset += (average - 1); 1344 1345 usb2_get_page(temp->pc, buf_offset, &buf_res); 1346 td->td_be = htole32(buf_res.physaddr); 1347 buf_offset++; 1348 1349 td->len = average; 1350 1351 /* update remaining length */ 1352 1353 temp->len -= average; 1354 } 1355 1356 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1357 /* we need to receive these frames one by one ! */ 1358 td->td_flags &= htole32(~OHCI_TD_INTR_MASK); 1359 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1360 td->td_next = htole32(OHCI_TD_NEXT_END); 1361 } else { 1362 if (td_next) { 1363 /* link the current TD with the next one */ 1364 td->td_next = td_next->td_self; 1365 } 1366 } 1367 1368 td->alt_next = td_alt_next; 1369 1370 usb2_pc_cpu_flush(td->page_cache); 1371 } 1372 1373 if (precompute) { 1374 precompute = 0; 1375 1376 /* setup alt next pointer, if any */ 1377 if (temp->short_frames_ok) { 1378 if (temp->setup_alt_next) { 1379 td_alt_next = td_next; 1380 } 1381 } else { 1382 /* we use this field internally */ 1383 td_alt_next = td_next; 1384 } 1385 1386 /* restore */ 1387 temp->shortpkt = shortpkt_old; 1388 temp->len = len_old; 1389 goto restart; 1390 } 1391 temp->td = td; 1392 temp->td_next = td_next; 1393} 1394 1395static void 1396ohci_setup_standard_chain(struct usb2_xfer *xfer, ohci_ed_t **ed_last) 1397{ 1398 struct ohci_std_temp temp; 1399 struct usb2_pipe_methods *methods; 1400 ohci_ed_t *ed; 1401 ohci_td_t *td; 1402 uint32_t ed_flags; 1403 uint32_t x; 1404 1405 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1406 xfer->address, UE_GET_ADDR(xfer->endpoint), 1407 xfer->sumlen, usb2_get_speed(xfer->udev)); 1408 1409 temp.average = xfer->max_usb2_frame_size; 1410 temp.max_frame_size = xfer->max_frame_size; 1411 1412 /* toggle the DMA set we are using */ 1413 xfer->flags_int.curr_dma_set ^= 1; 1414 1415 /* get next DMA set */ 1416 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1417 1418 xfer->td_transfer_first = td; 1419 xfer->td_transfer_cache = td; 1420 1421 temp.td = NULL; 1422 temp.td_next = td; 1423 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1424 temp.short_frames_ok = xfer->flags_int.short_frames_ok; 1425 1426 methods = xfer->pipe->methods; 1427 1428 /* check if we should prepend a setup message */ 1429 1430 if (xfer->flags_int.control_xfr) { 1431 if (xfer->flags_int.control_hdr) { 1432 1433 temp.td_flags = htole32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1434 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1435 1436 temp.len = xfer->frlengths[0]; 1437 temp.pc = xfer->frbuffers + 0; 1438 temp.shortpkt = temp.len ? 1 : 0; 1439 1440 ohci_setup_standard_chain_sub(&temp); 1441 1442 /* 1443 * XXX assume that the setup message is 1444 * contained within one USB packet: 1445 */ 1446 xfer->pipe->toggle_next = 1; 1447 } 1448 x = 1; 1449 } else { 1450 x = 0; 1451 } 1452 temp.td_flags = htole32(OHCI_TD_NOCC | OHCI_TD_NOINTR); 1453 1454 /* set data toggle */ 1455 1456 if (xfer->pipe->toggle_next) { 1457 temp.td_flags |= htole32(OHCI_TD_TOGGLE_1); 1458 } else { 1459 temp.td_flags |= htole32(OHCI_TD_TOGGLE_0); 1460 } 1461 1462 /* set endpoint direction */ 1463 1464 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 1465 temp.td_flags |= htole32(OHCI_TD_IN); 1466 } else { 1467 temp.td_flags |= htole32(OHCI_TD_OUT); 1468 } 1469 1470 while (x != xfer->nframes) { 1471 1472 /* DATA0 / DATA1 message */ 1473 1474 temp.len = xfer->frlengths[x]; 1475 temp.pc = xfer->frbuffers + x; 1476 1477 x++; 1478 1479 if (x == xfer->nframes) { 1480 temp.setup_alt_next = 0; 1481 } 1482 if (temp.len == 0) { 1483 1484 /* make sure that we send an USB packet */ 1485 1486 temp.shortpkt = 0; 1487 1488 } else { 1489 1490 /* regular data transfer */ 1491 1492 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1493 } 1494 1495 ohci_setup_standard_chain_sub(&temp); 1496 } 1497 1498 /* check if we should append a status stage */ 1499 1500 if (xfer->flags_int.control_xfr && 1501 !xfer->flags_int.control_act) { 1502 1503 /* 1504 * Send a DATA1 message and invert the current endpoint 1505 * direction. 1506 */ 1507 1508 /* set endpoint direction and data toggle */ 1509 1510 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 1511 temp.td_flags = htole32(OHCI_TD_OUT | 1512 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1513 } else { 1514 temp.td_flags = htole32(OHCI_TD_IN | 1515 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1516 } 1517 1518 temp.len = 0; 1519 temp.pc = NULL; 1520 temp.shortpkt = 0; 1521 1522 ohci_setup_standard_chain_sub(&temp); 1523 } 1524 td = temp.td; 1525 1526 td->td_next = htole32(OHCI_TD_NEXT_END); 1527 td->td_flags &= ~htole32(OHCI_TD_INTR_MASK); 1528 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1529 1530 usb2_pc_cpu_flush(td->page_cache); 1531 1532 /* must have at least one frame! */ 1533 1534 xfer->td_transfer_last = td; 1535 1536#if USB_DEBUG 1537 if (ohcidebug > 8) { 1538 DPRINTF("nexttog=%d; data before transfer:\n", 1539 xfer->pipe->toggle_next); 1540 ohci_dump_tds(xfer->td_transfer_first); 1541 } 1542#endif 1543 1544 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1545 1546 ed_flags = (OHCI_ED_SET_FA(xfer->address) | 1547 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpoint)) | 1548 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 1549 1550 ed_flags |= (OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD); 1551 1552 if (xfer->udev->speed == USB_SPEED_LOW) { 1553 ed_flags |= OHCI_ED_SPEED; 1554 } 1555 ed->ed_flags = htole32(ed_flags); 1556 1557 td = xfer->td_transfer_first; 1558 1559 ed->ed_headp = td->td_self; 1560 1561 if (xfer->udev->pwr_save.suspended == 0) { 1562 /* the append function will flush the endpoint descriptor */ 1563 OHCI_APPEND_QH(ed, *ed_last); 1564 1565 if (methods == &ohci_device_bulk_methods) { 1566 ohci_softc_t *sc = xfer->usb2_sc; 1567 1568 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1569 } 1570 if (methods == &ohci_device_ctrl_methods) { 1571 ohci_softc_t *sc = xfer->usb2_sc; 1572 1573 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1574 } 1575 } else { 1576 usb2_pc_cpu_flush(ed->page_cache); 1577 } 1578} 1579 1580static void 1581ohci_root_intr_done(struct usb2_xfer *xfer, 1582 struct usb2_sw_transfer *std) 1583{ 1584 ohci_softc_t *sc = xfer->usb2_sc; 1585 uint32_t hstatus; 1586 uint16_t i; 1587 uint16_t m; 1588 1589 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1590 1591 if (std->state != USB_SW_TR_PRE_DATA) { 1592 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1593 /* transfer transferred */ 1594 ohci_device_done(xfer, std->err); 1595 } 1596 goto done; 1597 } 1598 /* setup buffer */ 1599 std->ptr = sc->sc_hub_idata; 1600 std->len = sizeof(sc->sc_hub_idata); 1601 1602 /* clear any old interrupt data */ 1603 bzero(sc->sc_hub_idata, sizeof(sc->sc_hub_idata)); 1604 1605 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1606 DPRINTF("sc=%p xfer=%p hstatus=0x%08x\n", 1607 sc, xfer, hstatus); 1608 1609 /* set bits */ 1610 m = (sc->sc_noport + 1); 1611 if (m > (8 * sizeof(sc->sc_hub_idata))) { 1612 m = (8 * sizeof(sc->sc_hub_idata)); 1613 } 1614 for (i = 1; i < m; i++) { 1615 /* pick out CHANGE bits from the status register */ 1616 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) { 1617 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 1618 DPRINTF("port %d changed\n", i); 1619 } 1620 } 1621done: 1622 return; 1623} 1624 1625/* NOTE: "done" can be run two times in a row, 1626 * from close and from interrupt 1627 */ 1628static void 1629ohci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1630{ 1631 struct usb2_pipe_methods *methods = xfer->pipe->methods; 1632 ohci_softc_t *sc = xfer->usb2_sc; 1633 ohci_ed_t *ed; 1634 1635 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1636 1637 1638 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1639 xfer, xfer->pipe, error); 1640 1641 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1642 if (ed) { 1643 usb2_pc_cpu_invalidate(ed->page_cache); 1644 } 1645 if (methods == &ohci_device_bulk_methods) { 1646 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 1647 } 1648 if (methods == &ohci_device_ctrl_methods) { 1649 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 1650 } 1651 if (methods == &ohci_device_intr_methods) { 1652 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 1653 } 1654 if (methods == &ohci_device_isoc_methods) { 1655 OHCI_REMOVE_QH(ed, sc->sc_isoc_p_last); 1656 } 1657 xfer->td_transfer_first = NULL; 1658 xfer->td_transfer_last = NULL; 1659 1660 /* dequeue transfer and start next transfer */ 1661 usb2_transfer_done(xfer, error); 1662} 1663 1664/*------------------------------------------------------------------------* 1665 * ohci bulk support 1666 *------------------------------------------------------------------------*/ 1667static void 1668ohci_device_bulk_open(struct usb2_xfer *xfer) 1669{ 1670 return; 1671} 1672 1673static void 1674ohci_device_bulk_close(struct usb2_xfer *xfer) 1675{ 1676 ohci_device_done(xfer, USB_ERR_CANCELLED); 1677} 1678 1679static void 1680ohci_device_bulk_enter(struct usb2_xfer *xfer) 1681{ 1682 return; 1683} 1684 1685static void 1686ohci_device_bulk_start(struct usb2_xfer *xfer) 1687{ 1688 ohci_softc_t *sc = xfer->usb2_sc; 1689 1690 /* setup TD's and QH */ 1691 ohci_setup_standard_chain(xfer, &sc->sc_bulk_p_last); 1692 1693 /* put transfer on interrupt queue */ 1694 ohci_transfer_intr_enqueue(xfer); 1695} 1696 1697struct usb2_pipe_methods ohci_device_bulk_methods = 1698{ 1699 .open = ohci_device_bulk_open, 1700 .close = ohci_device_bulk_close, 1701 .enter = ohci_device_bulk_enter, 1702 .start = ohci_device_bulk_start, 1703 .enter_is_cancelable = 1, 1704 .start_is_cancelable = 1, 1705}; 1706 1707/*------------------------------------------------------------------------* 1708 * ohci control support 1709 *------------------------------------------------------------------------*/ 1710static void 1711ohci_device_ctrl_open(struct usb2_xfer *xfer) 1712{ 1713 return; 1714} 1715 1716static void 1717ohci_device_ctrl_close(struct usb2_xfer *xfer) 1718{ 1719 ohci_device_done(xfer, USB_ERR_CANCELLED); 1720} 1721 1722static void 1723ohci_device_ctrl_enter(struct usb2_xfer *xfer) 1724{ 1725 return; 1726} 1727 1728static void 1729ohci_device_ctrl_start(struct usb2_xfer *xfer) 1730{ 1731 ohci_softc_t *sc = xfer->usb2_sc; 1732 1733 /* setup TD's and QH */ 1734 ohci_setup_standard_chain(xfer, &sc->sc_ctrl_p_last); 1735 1736 /* put transfer on interrupt queue */ 1737 ohci_transfer_intr_enqueue(xfer); 1738} 1739 1740struct usb2_pipe_methods ohci_device_ctrl_methods = 1741{ 1742 .open = ohci_device_ctrl_open, 1743 .close = ohci_device_ctrl_close, 1744 .enter = ohci_device_ctrl_enter, 1745 .start = ohci_device_ctrl_start, 1746 .enter_is_cancelable = 1, 1747 .start_is_cancelable = 1, 1748}; 1749 1750/*------------------------------------------------------------------------* 1751 * ohci interrupt support 1752 *------------------------------------------------------------------------*/ 1753static void 1754ohci_device_intr_open(struct usb2_xfer *xfer) 1755{ 1756 ohci_softc_t *sc = xfer->usb2_sc; 1757 uint16_t best; 1758 uint16_t bit; 1759 uint16_t x; 1760 1761 best = 0; 1762 bit = OHCI_NO_EDS / 2; 1763 while (bit) { 1764 if (xfer->interval >= bit) { 1765 x = bit; 1766 best = bit; 1767 while (x & bit) { 1768 if (sc->sc_intr_stat[x] < 1769 sc->sc_intr_stat[best]) { 1770 best = x; 1771 } 1772 x++; 1773 } 1774 break; 1775 } 1776 bit >>= 1; 1777 } 1778 1779 sc->sc_intr_stat[best]++; 1780 xfer->qh_pos = best; 1781 1782 DPRINTFN(3, "best=%d interval=%d\n", 1783 best, xfer->interval); 1784} 1785 1786static void 1787ohci_device_intr_close(struct usb2_xfer *xfer) 1788{ 1789 ohci_softc_t *sc = xfer->usb2_sc; 1790 1791 sc->sc_intr_stat[xfer->qh_pos]--; 1792 1793 ohci_device_done(xfer, USB_ERR_CANCELLED); 1794} 1795 1796static void 1797ohci_device_intr_enter(struct usb2_xfer *xfer) 1798{ 1799 return; 1800} 1801 1802static void 1803ohci_device_intr_start(struct usb2_xfer *xfer) 1804{ 1805 ohci_softc_t *sc = xfer->usb2_sc; 1806 1807 /* setup TD's and QH */ 1808 ohci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 1809 1810 /* put transfer on interrupt queue */ 1811 ohci_transfer_intr_enqueue(xfer); 1812} 1813 1814struct usb2_pipe_methods ohci_device_intr_methods = 1815{ 1816 .open = ohci_device_intr_open, 1817 .close = ohci_device_intr_close, 1818 .enter = ohci_device_intr_enter, 1819 .start = ohci_device_intr_start, 1820 .enter_is_cancelable = 1, 1821 .start_is_cancelable = 1, 1822}; 1823 1824/*------------------------------------------------------------------------* 1825 * ohci isochronous support 1826 *------------------------------------------------------------------------*/ 1827static void 1828ohci_device_isoc_open(struct usb2_xfer *xfer) 1829{ 1830 return; 1831} 1832 1833static void 1834ohci_device_isoc_close(struct usb2_xfer *xfer) 1835{ 1836 /**/ 1837 ohci_device_done(xfer, USB_ERR_CANCELLED); 1838} 1839 1840static void 1841ohci_device_isoc_enter(struct usb2_xfer *xfer) 1842{ 1843 struct usb2_page_search buf_res; 1844 ohci_softc_t *sc = xfer->usb2_sc; 1845 struct ohci_hcca *hcca; 1846 uint32_t buf_offset; 1847 uint32_t nframes; 1848 uint32_t ed_flags; 1849 uint32_t *plen; 1850 uint16_t itd_offset[OHCI_ITD_NOFFSET]; 1851 uint16_t length; 1852 uint8_t ncur; 1853 ohci_itd_t *td; 1854 ohci_itd_t *td_last = NULL; 1855 ohci_ed_t *ed; 1856 1857 hcca = ohci_get_hcca(sc); 1858 1859 nframes = le32toh(hcca->hcca_frame_number); 1860 1861 DPRINTFN(6, "xfer=%p isoc_next=%u nframes=%u hcca_fn=%u\n", 1862 xfer, xfer->pipe->isoc_next, xfer->nframes, nframes); 1863 1864 if ((xfer->pipe->is_synced == 0) || 1865 (((nframes - xfer->pipe->isoc_next) & 0xFFFF) < xfer->nframes) || 1866 (((xfer->pipe->isoc_next - nframes) & 0xFFFF) >= 128)) { 1867 /* 1868 * If there is data underflow or the pipe queue is empty we 1869 * schedule the transfer a few frames ahead of the current 1870 * frame position. Else two isochronous transfers might 1871 * overlap. 1872 */ 1873 xfer->pipe->isoc_next = (nframes + 3) & 0xFFFF; 1874 xfer->pipe->is_synced = 1; 1875 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 1876 } 1877 /* 1878 * compute how many milliseconds the insertion is ahead of the 1879 * current frame position: 1880 */ 1881 buf_offset = ((xfer->pipe->isoc_next - nframes) & 0xFFFF); 1882 1883 /* 1884 * pre-compute when the isochronous transfer will be finished: 1885 */ 1886 xfer->isoc_time_complete = 1887 (usb2_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 1888 xfer->nframes); 1889 1890 /* get the real number of frames */ 1891 1892 nframes = xfer->nframes; 1893 1894 buf_offset = 0; 1895 1896 plen = xfer->frlengths; 1897 1898 /* toggle the DMA set we are using */ 1899 xfer->flags_int.curr_dma_set ^= 1; 1900 1901 /* get next DMA set */ 1902 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1903 1904 xfer->td_transfer_first = td; 1905 1906 ncur = 0; 1907 length = 0; 1908 1909 while (nframes--) { 1910 if (td == NULL) { 1911 panic("%s:%d: out of TD's\n", 1912 __FUNCTION__, __LINE__); 1913 } 1914 itd_offset[ncur] = length; 1915 buf_offset += *plen; 1916 length += *plen; 1917 plen++; 1918 ncur++; 1919 1920 if ( /* check if the ITD is full */ 1921 (ncur == OHCI_ITD_NOFFSET) || 1922 /* check if we have put more than 4K into the ITD */ 1923 (length & 0xF000) || 1924 /* check if it is the last frame */ 1925 (nframes == 0)) { 1926 1927 /* fill current ITD */ 1928 td->itd_flags = htole32( 1929 OHCI_ITD_NOCC | 1930 OHCI_ITD_SET_SF(xfer->pipe->isoc_next) | 1931 OHCI_ITD_NOINTR | 1932 OHCI_ITD_SET_FC(ncur)); 1933 1934 td->frames = ncur; 1935 xfer->pipe->isoc_next += ncur; 1936 1937 if (length == 0) { 1938 /* all zero */ 1939 td->itd_bp0 = 0; 1940 td->itd_be = ~0; 1941 1942 while (ncur--) { 1943 td->itd_offset[ncur] = 1944 htole16(OHCI_ITD_MK_OFFS(0)); 1945 } 1946 } else { 1947 usb2_get_page(xfer->frbuffers, buf_offset - length, &buf_res); 1948 length = OHCI_PAGE_MASK(buf_res.physaddr); 1949 buf_res.physaddr = 1950 OHCI_PAGE(buf_res.physaddr); 1951 td->itd_bp0 = htole32(buf_res.physaddr); 1952 usb2_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 1953 td->itd_be = htole32(buf_res.physaddr); 1954 1955 while (ncur--) { 1956 itd_offset[ncur] += length; 1957 itd_offset[ncur] = 1958 OHCI_ITD_MK_OFFS(itd_offset[ncur]); 1959 td->itd_offset[ncur] = 1960 htole16(itd_offset[ncur]); 1961 } 1962 } 1963 ncur = 0; 1964 length = 0; 1965 td_last = td; 1966 td = td->obj_next; 1967 1968 if (td) { 1969 /* link the last TD with the next one */ 1970 td_last->itd_next = td->itd_self; 1971 } 1972 usb2_pc_cpu_flush(td_last->page_cache); 1973 } 1974 } 1975 1976 /* update the last TD */ 1977 td_last->itd_flags &= ~htole32(OHCI_ITD_NOINTR); 1978 td_last->itd_flags |= htole32(OHCI_ITD_SET_DI(0)); 1979 td_last->itd_next = 0; 1980 1981 usb2_pc_cpu_flush(td_last->page_cache); 1982 1983 xfer->td_transfer_last = td_last; 1984 1985#if USB_DEBUG 1986 if (ohcidebug > 8) { 1987 DPRINTF("data before transfer:\n"); 1988 ohci_dump_itds(xfer->td_transfer_first); 1989 } 1990#endif 1991 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1992 1993 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) 1994 ed_flags = (OHCI_ED_DIR_IN | OHCI_ED_FORMAT_ISO); 1995 else 1996 ed_flags = (OHCI_ED_DIR_OUT | OHCI_ED_FORMAT_ISO); 1997 1998 ed_flags |= (OHCI_ED_SET_FA(xfer->address) | 1999 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpoint)) | 2000 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 2001 2002 if (xfer->udev->speed == USB_SPEED_LOW) { 2003 ed_flags |= OHCI_ED_SPEED; 2004 } 2005 ed->ed_flags = htole32(ed_flags); 2006 2007 td = xfer->td_transfer_first; 2008 2009 ed->ed_headp = td->itd_self; 2010 2011 /* isochronous transfers are not affected by suspend / resume */ 2012 /* the append function will flush the endpoint descriptor */ 2013 2014 OHCI_APPEND_QH(ed, sc->sc_isoc_p_last); 2015} 2016 2017static void 2018ohci_device_isoc_start(struct usb2_xfer *xfer) 2019{ 2020 /* put transfer on interrupt queue */ 2021 ohci_transfer_intr_enqueue(xfer); 2022} 2023 2024struct usb2_pipe_methods ohci_device_isoc_methods = 2025{ 2026 .open = ohci_device_isoc_open, 2027 .close = ohci_device_isoc_close, 2028 .enter = ohci_device_isoc_enter, 2029 .start = ohci_device_isoc_start, 2030 .enter_is_cancelable = 1, 2031 .start_is_cancelable = 1, 2032}; 2033 2034/*------------------------------------------------------------------------* 2035 * ohci root control support 2036 *------------------------------------------------------------------------* 2037 * simulate a hardware hub by handling 2038 * all the necessary requests 2039 *------------------------------------------------------------------------*/ 2040 2041static void 2042ohci_root_ctrl_open(struct usb2_xfer *xfer) 2043{ 2044 return; 2045} 2046 2047static void 2048ohci_root_ctrl_close(struct usb2_xfer *xfer) 2049{ 2050 ohci_softc_t *sc = xfer->usb2_sc; 2051 2052 if (sc->sc_root_ctrl.xfer == xfer) { 2053 sc->sc_root_ctrl.xfer = NULL; 2054 } 2055 ohci_device_done(xfer, USB_ERR_CANCELLED); 2056} 2057 2058/* data structures and routines 2059 * to emulate the root hub: 2060 */ 2061static const 2062struct usb2_device_descriptor ohci_devd = 2063{ 2064 sizeof(struct usb2_device_descriptor), 2065 UDESC_DEVICE, /* type */ 2066 {0x00, 0x01}, /* USB version */ 2067 UDCLASS_HUB, /* class */ 2068 UDSUBCLASS_HUB, /* subclass */ 2069 UDPROTO_FSHUB, /* protocol */ 2070 64, /* max packet */ 2071 {0}, {0}, {0x00, 0x01}, /* device id */ 2072 1, 2, 0, /* string indicies */ 2073 1 /* # of configurations */ 2074}; 2075 2076static const 2077struct ohci_config_desc ohci_confd = 2078{ 2079 .confd = { 2080 .bLength = sizeof(struct usb2_config_descriptor), 2081 .bDescriptorType = UDESC_CONFIG, 2082 .wTotalLength[0] = sizeof(ohci_confd), 2083 .bNumInterface = 1, 2084 .bConfigurationValue = 1, 2085 .iConfiguration = 0, 2086 .bmAttributes = UC_SELF_POWERED, 2087 .bMaxPower = 0, /* max power */ 2088 }, 2089 2090 .ifcd = { 2091 .bLength = sizeof(struct usb2_interface_descriptor), 2092 .bDescriptorType = UDESC_INTERFACE, 2093 .bNumEndpoints = 1, 2094 .bInterfaceClass = UICLASS_HUB, 2095 .bInterfaceSubClass = UISUBCLASS_HUB, 2096 .bInterfaceProtocol = UIPROTO_FSHUB, 2097 }, 2098 2099 .endpd = { 2100 .bLength = sizeof(struct usb2_endpoint_descriptor), 2101 .bDescriptorType = UDESC_ENDPOINT, 2102 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2103 .bmAttributes = UE_INTERRUPT, 2104 .wMaxPacketSize[0] = 32,/* max packet (255 ports) */ 2105 .bInterval = 255, 2106 }, 2107}; 2108 2109static const 2110struct usb2_hub_descriptor ohci_hubd = 2111{ 2112 0, /* dynamic length */ 2113 UDESC_HUB, 2114 0, 2115 {0, 0}, 2116 0, 2117 0, 2118 {0}, 2119}; 2120 2121static void 2122ohci_root_ctrl_enter(struct usb2_xfer *xfer) 2123{ 2124 return; 2125} 2126 2127static void 2128ohci_root_ctrl_start(struct usb2_xfer *xfer) 2129{ 2130 ohci_softc_t *sc = xfer->usb2_sc; 2131 2132 sc->sc_root_ctrl.xfer = xfer; 2133 2134 usb2_bus_roothub_exec(xfer->udev->bus); 2135} 2136 2137static void 2138ohci_root_ctrl_task(struct usb2_bus *bus) 2139{ 2140 ohci_root_ctrl_poll(OHCI_BUS2SC(bus)); 2141} 2142 2143static void 2144ohci_root_ctrl_done(struct usb2_xfer *xfer, 2145 struct usb2_sw_transfer *std) 2146{ 2147 ohci_softc_t *sc = xfer->usb2_sc; 2148 char *ptr; 2149 uint32_t port; 2150 uint32_t v; 2151 uint16_t value; 2152 uint16_t index; 2153 uint8_t l; 2154 uint8_t use_polling; 2155 2156 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2157 2158 if (std->state != USB_SW_TR_SETUP) { 2159 if (std->state == USB_SW_TR_PRE_CALLBACK) { 2160 /* transfer transferred */ 2161 ohci_device_done(xfer, std->err); 2162 } 2163 goto done; 2164 } 2165 /* buffer reset */ 2166 std->ptr = sc->sc_hub_desc.temp; 2167 std->len = 0; 2168 2169 value = UGETW(std->req.wValue); 2170 index = UGETW(std->req.wIndex); 2171 2172 use_polling = mtx_owned(xfer->xfer_mtx) ? 1 : 0; 2173 2174 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2175 "wValue=0x%04x wIndex=0x%04x\n", 2176 std->req.bmRequestType, std->req.bRequest, 2177 UGETW(std->req.wLength), value, index); 2178 2179#define C(x,y) ((x) | ((y) << 8)) 2180 switch (C(std->req.bRequest, std->req.bmRequestType)) { 2181 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2182 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2183 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2184 /* 2185 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2186 * for the integrated root hub. 2187 */ 2188 break; 2189 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2190 std->len = 1; 2191 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2192 break; 2193 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2194 switch (value >> 8) { 2195 case UDESC_DEVICE: 2196 if ((value & 0xff) != 0) { 2197 std->err = USB_ERR_IOERROR; 2198 goto done; 2199 } 2200 std->len = sizeof(ohci_devd); 2201 sc->sc_hub_desc.devd = ohci_devd; 2202 break; 2203 2204 case UDESC_CONFIG: 2205 if ((value & 0xff) != 0) { 2206 std->err = USB_ERR_IOERROR; 2207 goto done; 2208 } 2209 std->len = sizeof(ohci_confd); 2210 std->ptr = USB_ADD_BYTES(&ohci_confd, 0); 2211 break; 2212 2213 case UDESC_STRING: 2214 switch (value & 0xff) { 2215 case 0: /* Language table */ 2216 ptr = "\001"; 2217 break; 2218 2219 case 1: /* Vendor */ 2220 ptr = sc->sc_vendor; 2221 break; 2222 2223 case 2: /* Product */ 2224 ptr = "OHCI root HUB"; 2225 break; 2226 2227 default: 2228 ptr = ""; 2229 break; 2230 } 2231 2232 std->len = usb2_make_str_desc 2233 (sc->sc_hub_desc.temp, 2234 sizeof(sc->sc_hub_desc.temp), 2235 ptr); 2236 break; 2237 2238 default: 2239 std->err = USB_ERR_IOERROR; 2240 goto done; 2241 } 2242 break; 2243 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2244 std->len = 1; 2245 sc->sc_hub_desc.temp[0] = 0; 2246 break; 2247 case C(UR_GET_STATUS, UT_READ_DEVICE): 2248 std->len = 2; 2249 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2250 break; 2251 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2252 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2253 std->len = 2; 2254 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2255 break; 2256 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2257 if (value >= USB_MAX_DEVICES) { 2258 std->err = USB_ERR_IOERROR; 2259 goto done; 2260 } 2261 sc->sc_addr = value; 2262 break; 2263 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2264 if ((value != 0) && (value != 1)) { 2265 std->err = USB_ERR_IOERROR; 2266 goto done; 2267 } 2268 sc->sc_conf = value; 2269 break; 2270 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2271 break; 2272 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2273 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2274 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2275 std->err = USB_ERR_IOERROR; 2276 goto done; 2277 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2278 break; 2279 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2280 break; 2281 /* Hub requests */ 2282 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2283 break; 2284 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2285 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE " 2286 "port=%d feature=%d\n", 2287 index, value); 2288 if ((index < 1) || 2289 (index > sc->sc_noport)) { 2290 std->err = USB_ERR_IOERROR; 2291 goto done; 2292 } 2293 port = OHCI_RH_PORT_STATUS(index); 2294 switch (value) { 2295 case UHF_PORT_ENABLE: 2296 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2297 break; 2298 case UHF_PORT_SUSPEND: 2299 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2300 break; 2301 case UHF_PORT_POWER: 2302 /* Yes, writing to the LOW_SPEED bit clears power. */ 2303 OWRITE4(sc, port, UPS_LOW_SPEED); 2304 break; 2305 case UHF_C_PORT_CONNECTION: 2306 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2307 break; 2308 case UHF_C_PORT_ENABLE: 2309 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2310 break; 2311 case UHF_C_PORT_SUSPEND: 2312 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2313 break; 2314 case UHF_C_PORT_OVER_CURRENT: 2315 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2316 break; 2317 case UHF_C_PORT_RESET: 2318 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2319 break; 2320 default: 2321 std->err = USB_ERR_IOERROR; 2322 goto done; 2323 } 2324 switch (value) { 2325 case UHF_C_PORT_CONNECTION: 2326 case UHF_C_PORT_ENABLE: 2327 case UHF_C_PORT_SUSPEND: 2328 case UHF_C_PORT_OVER_CURRENT: 2329 case UHF_C_PORT_RESET: 2330 /* enable RHSC interrupt if condition is cleared. */ 2331 if ((OREAD4(sc, port) >> 16) == 0) 2332 ohci_rhsc_enable(sc); 2333 break; 2334 default: 2335 break; 2336 } 2337 break; 2338 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2339 if ((value & 0xff) != 0) { 2340 std->err = USB_ERR_IOERROR; 2341 goto done; 2342 } 2343 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2344 2345 sc->sc_hub_desc.hubd = ohci_hubd; 2346 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 2347 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, 2348 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2349 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2350 /* XXX overcurrent */ 2351 ); 2352 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2353 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2354 2355 for (l = 0; l < sc->sc_noport; l++) { 2356 if (v & 1) { 2357 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] |= (1 << (l % 8)); 2358 } 2359 v >>= 1; 2360 } 2361 sc->sc_hub_desc.hubd.bDescLength = 2362 8 + ((sc->sc_noport + 7) / 8); 2363 std->len = sc->sc_hub_desc.hubd.bDescLength; 2364 break; 2365 2366 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2367 std->len = 16; 2368 bzero(sc->sc_hub_desc.temp, 16); 2369 break; 2370 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2371 DPRINTFN(9, "get port status i=%d\n", 2372 index); 2373 if ((index < 1) || 2374 (index > sc->sc_noport)) { 2375 std->err = USB_ERR_IOERROR; 2376 goto done; 2377 } 2378 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2379 DPRINTFN(9, "port status=0x%04x\n", v); 2380 USETW(sc->sc_hub_desc.ps.wPortStatus, v); 2381 USETW(sc->sc_hub_desc.ps.wPortChange, v >> 16); 2382 std->len = sizeof(sc->sc_hub_desc.ps); 2383 break; 2384 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2385 std->err = USB_ERR_IOERROR; 2386 goto done; 2387 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2388 break; 2389 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2390 if ((index < 1) || 2391 (index > sc->sc_noport)) { 2392 std->err = USB_ERR_IOERROR; 2393 goto done; 2394 } 2395 port = OHCI_RH_PORT_STATUS(index); 2396 switch (value) { 2397 case UHF_PORT_ENABLE: 2398 OWRITE4(sc, port, UPS_PORT_ENABLED); 2399 break; 2400 case UHF_PORT_SUSPEND: 2401 OWRITE4(sc, port, UPS_SUSPEND); 2402 break; 2403 case UHF_PORT_RESET: 2404 DPRINTFN(6, "reset port %d\n", index); 2405 OWRITE4(sc, port, UPS_RESET); 2406 for (v = 0;; v++) { 2407 if (v < 12) { 2408 if (use_polling) { 2409 /* polling */ 2410 DELAY(USB_PORT_ROOT_RESET_DELAY * 1000); 2411 } else { 2412 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 2413 USB_PORT_ROOT_RESET_DELAY); 2414 } 2415 2416 if ((OREAD4(sc, port) & UPS_RESET) == 0) { 2417 break; 2418 } 2419 } else { 2420 std->err = USB_ERR_TIMEOUT; 2421 goto done; 2422 } 2423 } 2424 DPRINTFN(9, "ohci port %d reset, status = 0x%04x\n", 2425 index, OREAD4(sc, port)); 2426 break; 2427 case UHF_PORT_POWER: 2428 DPRINTFN(3, "set port power %d\n", index); 2429 OWRITE4(sc, port, UPS_PORT_POWER); 2430 break; 2431 default: 2432 std->err = USB_ERR_IOERROR; 2433 goto done; 2434 } 2435 break; 2436 default: 2437 std->err = USB_ERR_IOERROR; 2438 goto done; 2439 } 2440done: 2441 return; 2442} 2443 2444static void 2445ohci_root_ctrl_poll(struct ohci_softc *sc) 2446{ 2447 usb2_sw_transfer(&sc->sc_root_ctrl, 2448 &ohci_root_ctrl_done); 2449} 2450 2451struct usb2_pipe_methods ohci_root_ctrl_methods = 2452{ 2453 .open = ohci_root_ctrl_open, 2454 .close = ohci_root_ctrl_close, 2455 .enter = ohci_root_ctrl_enter, 2456 .start = ohci_root_ctrl_start, 2457 .enter_is_cancelable = 1, 2458 .start_is_cancelable = 0, 2459}; 2460 2461/*------------------------------------------------------------------------* 2462 * ohci root interrupt support 2463 *------------------------------------------------------------------------*/ 2464static void 2465ohci_root_intr_open(struct usb2_xfer *xfer) 2466{ 2467 return; 2468} 2469 2470static void 2471ohci_root_intr_close(struct usb2_xfer *xfer) 2472{ 2473 ohci_softc_t *sc = xfer->usb2_sc; 2474 2475 if (sc->sc_root_intr.xfer == xfer) { 2476 sc->sc_root_intr.xfer = NULL; 2477 } 2478 ohci_device_done(xfer, USB_ERR_CANCELLED); 2479} 2480 2481static void 2482ohci_root_intr_enter(struct usb2_xfer *xfer) 2483{ 2484 return; 2485} 2486 2487static void 2488ohci_root_intr_start(struct usb2_xfer *xfer) 2489{ 2490 ohci_softc_t *sc = xfer->usb2_sc; 2491 2492 sc->sc_root_intr.xfer = xfer; 2493} 2494 2495struct usb2_pipe_methods ohci_root_intr_methods = 2496{ 2497 .open = ohci_root_intr_open, 2498 .close = ohci_root_intr_close, 2499 .enter = ohci_root_intr_enter, 2500 .start = ohci_root_intr_start, 2501 .enter_is_cancelable = 1, 2502 .start_is_cancelable = 1, 2503}; 2504 2505static void 2506ohci_xfer_setup(struct usb2_setup_params *parm) 2507{ 2508 struct usb2_page_search page_info; 2509 struct usb2_page_cache *pc; 2510 ohci_softc_t *sc; 2511 struct usb2_xfer *xfer; 2512 void *last_obj; 2513 uint32_t ntd; 2514 uint32_t nitd; 2515 uint32_t nqh; 2516 uint32_t n; 2517 2518 sc = OHCI_BUS2SC(parm->udev->bus); 2519 xfer = parm->curr_xfer; 2520 2521 /* 2522 * setup xfer 2523 */ 2524 xfer->usb2_sc = sc; 2525 2526 parm->hc_max_packet_size = 0x500; 2527 parm->hc_max_packet_count = 1; 2528 parm->hc_max_frame_size = OHCI_PAGE_SIZE; 2529 2530 /* 2531 * calculate ntd and nqh 2532 */ 2533 if (parm->methods == &ohci_device_ctrl_methods) { 2534 xfer->flags_int.bdma_enable = 1; 2535 2536 usb2_transfer_setup_sub(parm); 2537 2538 nitd = 0; 2539 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2540 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 2541 nqh = 1; 2542 2543 } else if (parm->methods == &ohci_device_bulk_methods) { 2544 xfer->flags_int.bdma_enable = 1; 2545 2546 usb2_transfer_setup_sub(parm); 2547 2548 nitd = 0; 2549 ntd = ((2 * xfer->nframes) 2550 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 2551 nqh = 1; 2552 2553 } else if (parm->methods == &ohci_device_intr_methods) { 2554 xfer->flags_int.bdma_enable = 1; 2555 2556 usb2_transfer_setup_sub(parm); 2557 2558 nitd = 0; 2559 ntd = ((2 * xfer->nframes) 2560 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 2561 nqh = 1; 2562 2563 } else if (parm->methods == &ohci_device_isoc_methods) { 2564 xfer->flags_int.bdma_enable = 1; 2565 2566 usb2_transfer_setup_sub(parm); 2567 2568 nitd = ((xfer->max_data_length / OHCI_PAGE_SIZE) + 2569 ((xfer->nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET) + 2570 1 /* EXTRA */ ); 2571 ntd = 0; 2572 nqh = 1; 2573 2574 } else { 2575 2576 usb2_transfer_setup_sub(parm); 2577 2578 nitd = 0; 2579 ntd = 0; 2580 nqh = 0; 2581 } 2582 2583alloc_dma_set: 2584 2585 if (parm->err) { 2586 return; 2587 } 2588 last_obj = NULL; 2589 2590 if (usb2_transfer_setup_sub_malloc( 2591 parm, &pc, sizeof(ohci_td_t), 2592 OHCI_TD_ALIGN, ntd)) { 2593 parm->err = USB_ERR_NOMEM; 2594 return; 2595 } 2596 if (parm->buf) { 2597 for (n = 0; n != ntd; n++) { 2598 ohci_td_t *td; 2599 2600 usb2_get_page(pc + n, 0, &page_info); 2601 2602 td = page_info.buffer; 2603 2604 /* init TD */ 2605 td->td_self = htole32(page_info.physaddr); 2606 td->obj_next = last_obj; 2607 td->page_cache = pc + n; 2608 2609 last_obj = td; 2610 2611 usb2_pc_cpu_flush(pc + n); 2612 } 2613 } 2614 if (usb2_transfer_setup_sub_malloc( 2615 parm, &pc, sizeof(ohci_itd_t), 2616 OHCI_ITD_ALIGN, nitd)) { 2617 parm->err = USB_ERR_NOMEM; 2618 return; 2619 } 2620 if (parm->buf) { 2621 for (n = 0; n != nitd; n++) { 2622 ohci_itd_t *itd; 2623 2624 usb2_get_page(pc + n, 0, &page_info); 2625 2626 itd = page_info.buffer; 2627 2628 /* init TD */ 2629 itd->itd_self = htole32(page_info.physaddr); 2630 itd->obj_next = last_obj; 2631 itd->page_cache = pc + n; 2632 2633 last_obj = itd; 2634 2635 usb2_pc_cpu_flush(pc + n); 2636 } 2637 } 2638 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2639 2640 last_obj = NULL; 2641 2642 if (usb2_transfer_setup_sub_malloc( 2643 parm, &pc, sizeof(ohci_ed_t), 2644 OHCI_ED_ALIGN, nqh)) { 2645 parm->err = USB_ERR_NOMEM; 2646 return; 2647 } 2648 if (parm->buf) { 2649 for (n = 0; n != nqh; n++) { 2650 ohci_ed_t *ed; 2651 2652 usb2_get_page(pc + n, 0, &page_info); 2653 2654 ed = page_info.buffer; 2655 2656 /* init QH */ 2657 ed->ed_self = htole32(page_info.physaddr); 2658 ed->obj_next = last_obj; 2659 ed->page_cache = pc + n; 2660 2661 last_obj = ed; 2662 2663 usb2_pc_cpu_flush(pc + n); 2664 } 2665 } 2666 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 2667 2668 if (!xfer->flags_int.curr_dma_set) { 2669 xfer->flags_int.curr_dma_set = 1; 2670 goto alloc_dma_set; 2671 } 2672} 2673 2674static void 2675ohci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2676 struct usb2_pipe *pipe) 2677{ 2678 ohci_softc_t *sc = OHCI_BUS2SC(udev->bus); 2679 2680 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2681 pipe, udev->address, 2682 edesc->bEndpointAddress, udev->flags.usb2_mode, 2683 sc->sc_addr); 2684 2685 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2686 /* not supported */ 2687 return; 2688 } 2689 if (udev->device_index == sc->sc_addr) { 2690 switch (edesc->bEndpointAddress) { 2691 case USB_CONTROL_ENDPOINT: 2692 pipe->methods = &ohci_root_ctrl_methods; 2693 break; 2694 case UE_DIR_IN | OHCI_INTR_ENDPT: 2695 pipe->methods = &ohci_root_intr_methods; 2696 break; 2697 default: 2698 /* do nothing */ 2699 break; 2700 } 2701 } else { 2702 switch (edesc->bmAttributes & UE_XFERTYPE) { 2703 case UE_CONTROL: 2704 pipe->methods = &ohci_device_ctrl_methods; 2705 break; 2706 case UE_INTERRUPT: 2707 pipe->methods = &ohci_device_intr_methods; 2708 break; 2709 case UE_ISOCHRONOUS: 2710 if (udev->speed == USB_SPEED_FULL) { 2711 pipe->methods = &ohci_device_isoc_methods; 2712 } 2713 break; 2714 case UE_BULK: 2715 if (udev->speed != USB_SPEED_LOW) { 2716 pipe->methods = &ohci_device_bulk_methods; 2717 } 2718 break; 2719 default: 2720 /* do nothing */ 2721 break; 2722 } 2723 } 2724} 2725 2726static void 2727ohci_xfer_unsetup(struct usb2_xfer *xfer) 2728{ 2729 return; 2730} 2731 2732static void 2733ohci_get_dma_delay(struct usb2_bus *bus, uint32_t *pus) 2734{ 2735 /* 2736 * Wait until hardware has finished any possible use of the 2737 * transfer descriptor(s) and QH 2738 */ 2739 *pus = (1125); /* microseconds */ 2740} 2741 2742static void 2743ohci_device_resume(struct usb2_device *udev) 2744{ 2745 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2746 struct usb2_xfer *xfer; 2747 struct usb2_pipe_methods *methods; 2748 ohci_ed_t *ed; 2749 2750 DPRINTF("\n"); 2751 2752 USB_BUS_LOCK(udev->bus); 2753 2754 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2755 2756 if (xfer->udev == udev) { 2757 2758 methods = xfer->pipe->methods; 2759 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2760 2761 if (methods == &ohci_device_bulk_methods) { 2762 OHCI_APPEND_QH(ed, sc->sc_bulk_p_last); 2763 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2764 } 2765 if (methods == &ohci_device_ctrl_methods) { 2766 OHCI_APPEND_QH(ed, sc->sc_ctrl_p_last); 2767 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2768 } 2769 if (methods == &ohci_device_intr_methods) { 2770 OHCI_APPEND_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2771 } 2772 } 2773 } 2774 2775 USB_BUS_UNLOCK(udev->bus); 2776 2777 return; 2778} 2779 2780static void 2781ohci_device_suspend(struct usb2_device *udev) 2782{ 2783 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2784 struct usb2_xfer *xfer; 2785 struct usb2_pipe_methods *methods; 2786 ohci_ed_t *ed; 2787 2788 DPRINTF("\n"); 2789 2790 USB_BUS_LOCK(udev->bus); 2791 2792 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2793 2794 if (xfer->udev == udev) { 2795 2796 methods = xfer->pipe->methods; 2797 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2798 2799 if (methods == &ohci_device_bulk_methods) { 2800 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 2801 } 2802 if (methods == &ohci_device_ctrl_methods) { 2803 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 2804 } 2805 if (methods == &ohci_device_intr_methods) { 2806 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2807 } 2808 } 2809 } 2810 2811 USB_BUS_UNLOCK(udev->bus); 2812 2813 return; 2814} 2815 2816static void 2817ohci_set_hw_power(struct usb2_bus *bus) 2818{ 2819 struct ohci_softc *sc = OHCI_BUS2SC(bus); 2820 uint32_t temp; 2821 uint32_t flags; 2822 2823 DPRINTF("\n"); 2824 2825 USB_BUS_LOCK(bus); 2826 2827 flags = bus->hw_power_state; 2828 2829 temp = OREAD4(sc, OHCI_CONTROL); 2830 temp &= ~(OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE); 2831 2832 if (flags & USB_HW_POWER_CONTROL) 2833 temp |= OHCI_CLE; 2834 2835 if (flags & USB_HW_POWER_BULK) 2836 temp |= OHCI_BLE; 2837 2838 if (flags & USB_HW_POWER_INTERRUPT) 2839 temp |= OHCI_PLE; 2840 2841 if (flags & USB_HW_POWER_ISOC) 2842 temp |= OHCI_IE | OHCI_PLE; 2843 2844 OWRITE4(sc, OHCI_CONTROL, temp); 2845 2846 USB_BUS_UNLOCK(bus); 2847 2848 return; 2849} 2850 2851struct usb2_bus_methods ohci_bus_methods = 2852{ 2853 .pipe_init = ohci_pipe_init, 2854 .xfer_setup = ohci_xfer_setup, 2855 .xfer_unsetup = ohci_xfer_unsetup, 2856 .do_poll = ohci_do_poll, 2857 .get_dma_delay = ohci_get_dma_delay, 2858 .device_resume = ohci_device_resume, 2859 .device_suspend = ohci_device_suspend, 2860 .set_hw_power = ohci_set_hw_power, 2861 .roothub_exec = ohci_root_ctrl_task, 2862}; 2863