ohci.c revision 186730
1/*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/usb2/controller/ohci2.c 186730 2009-01-04 00:12:01Z alfred $"); 30 31/* 32 * USB Open Host Controller driver. 33 * 34 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 35 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 36 */ 37 38#include <dev/usb2/include/usb2_standard.h> 39#include <dev/usb2/include/usb2_mfunc.h> 40#include <dev/usb2/include/usb2_error.h> 41#include <dev/usb2/include/usb2_defs.h> 42 43#define USB_DEBUG_VAR ohcidebug 44#define usb2_config_td_cc ohci_config_copy 45#define usb2_config_td_softc ohci_softc 46 47#include <dev/usb2/core/usb2_core.h> 48#include <dev/usb2/core/usb2_debug.h> 49#include <dev/usb2/core/usb2_busdma.h> 50#include <dev/usb2/core/usb2_process.h> 51#include <dev/usb2/core/usb2_config_td.h> 52#include <dev/usb2/core/usb2_sw_transfer.h> 53#include <dev/usb2/core/usb2_transfer.h> 54#include <dev/usb2/core/usb2_device.h> 55#include <dev/usb2/core/usb2_hub.h> 56#include <dev/usb2/core/usb2_util.h> 57 58#include <dev/usb2/controller/usb2_controller.h> 59#include <dev/usb2/controller/usb2_bus.h> 60#include <dev/usb2/controller/ohci2.h> 61 62#define OHCI_BUS2SC(bus) ((ohci_softc_t *)(((uint8_t *)(bus)) - \ 63 USB_P2U(&(((ohci_softc_t *)0)->sc_bus)))) 64 65#if USB_DEBUG 66static int ohcidebug = 0; 67 68SYSCTL_NODE(_hw_usb2, OID_AUTO, ohci, CTLFLAG_RW, 0, "USB ohci"); 69SYSCTL_INT(_hw_usb2_ohci, OID_AUTO, debug, CTLFLAG_RW, 70 &ohcidebug, 0, "ohci debug level"); 71static void ohci_dumpregs(ohci_softc_t *); 72static void ohci_dump_tds(ohci_td_t *); 73static uint8_t ohci_dump_td(ohci_td_t *); 74static void ohci_dump_ed(ohci_ed_t *); 75static uint8_t ohci_dump_itd(ohci_itd_t *); 76static void ohci_dump_itds(ohci_itd_t *); 77 78#endif 79 80#define OBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 81 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 82#define OWRITE1(sc, r, x) \ 83 do { OBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 84#define OWRITE2(sc, r, x) \ 85 do { OBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 86#define OWRITE4(sc, r, x) \ 87 do { OBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 88#define OREAD1(sc, r) (OBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 89#define OREAD2(sc, r) (OBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 90#define OREAD4(sc, r) (OBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 91 92#define OHCI_INTR_ENDPT 1 93 94extern struct usb2_bus_methods ohci_bus_methods; 95extern struct usb2_pipe_methods ohci_device_bulk_methods; 96extern struct usb2_pipe_methods ohci_device_ctrl_methods; 97extern struct usb2_pipe_methods ohci_device_intr_methods; 98extern struct usb2_pipe_methods ohci_device_isoc_methods; 99extern struct usb2_pipe_methods ohci_root_ctrl_methods; 100extern struct usb2_pipe_methods ohci_root_intr_methods; 101 102static usb2_config_td_command_t ohci_root_ctrl_task; 103static void ohci_root_ctrl_poll(struct ohci_softc *sc); 104static void ohci_do_poll(struct usb2_bus *bus); 105static void ohci_device_done(struct usb2_xfer *xfer, usb2_error_t error); 106 107static usb2_sw_transfer_func_t ohci_root_intr_done; 108static usb2_sw_transfer_func_t ohci_root_ctrl_done; 109static void ohci_timeout(void *arg); 110static uint8_t ohci_check_transfer(struct usb2_xfer *xfer); 111 112struct ohci_std_temp { 113 struct usb2_page_cache *pc; 114 ohci_td_t *td; 115 ohci_td_t *td_next; 116 uint32_t average; 117 uint32_t td_flags; 118 uint32_t len; 119 uint16_t max_frame_size; 120 uint8_t shortpkt; 121 uint8_t setup_alt_next; 122 uint8_t short_frames_ok; 123}; 124 125static struct ohci_hcca * 126ohci_get_hcca(ohci_softc_t *sc) 127{ 128 usb2_pc_cpu_invalidate(&sc->sc_hw.hcca_pc); 129 return (sc->sc_hcca_p); 130} 131 132void 133ohci_iterate_hw_softc(struct usb2_bus *bus, usb2_bus_mem_sub_cb_t *cb) 134{ 135 struct ohci_softc *sc = OHCI_BUS2SC(bus); 136 uint32_t i; 137 138 cb(bus, &sc->sc_hw.hcca_pc, &sc->sc_hw.hcca_pg, 139 sizeof(ohci_hcca_t), OHCI_HCCA_ALIGN); 140 141 cb(bus, &sc->sc_hw.ctrl_start_pc, &sc->sc_hw.ctrl_start_pg, 142 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 143 144 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 145 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 146 147 cb(bus, &sc->sc_hw.isoc_start_pc, &sc->sc_hw.isoc_start_pg, 148 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 149 150 for (i = 0; i != OHCI_NO_EDS; i++) { 151 cb(bus, sc->sc_hw.intr_start_pc + i, sc->sc_hw.intr_start_pg + i, 152 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 153 } 154} 155 156static usb2_error_t 157ohci_controller_init(ohci_softc_t *sc) 158{ 159 struct usb2_page_search buf_res; 160 uint32_t i; 161 uint32_t ctl; 162 uint32_t ival; 163 uint32_t hcr; 164 uint32_t fm; 165 uint32_t per; 166 uint32_t desca; 167 168 /* Determine in what context we are running. */ 169 ctl = OREAD4(sc, OHCI_CONTROL); 170 if (ctl & OHCI_IR) { 171 /* SMM active, request change */ 172 DPRINTF("SMM active, request owner change\n"); 173 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_OCR); 174 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 175 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1); 176 ctl = OREAD4(sc, OHCI_CONTROL); 177 } 178 if (ctl & OHCI_IR) { 179 device_printf(sc->sc_bus.bdev, 180 "SMM does not respond, resetting\n"); 181 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 182 goto reset; 183 } 184 } else { 185 DPRINTF("cold started\n"); 186reset: 187 /* controller was cold started */ 188 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 189 USB_BUS_RESET_DELAY); 190 } 191 192 /* 193 * This reset should not be necessary according to the OHCI spec, but 194 * without it some controllers do not start. 195 */ 196 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 197 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 198 199 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 200 USB_BUS_RESET_DELAY); 201 202 /* we now own the host controller and the bus has been reset */ 203 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL)); 204 205 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 206 /* nominal time for a reset is 10 us */ 207 for (i = 0; i < 10; i++) { 208 DELAY(10); 209 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 210 if (!hcr) { 211 break; 212 } 213 } 214 if (hcr) { 215 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 216 return (USB_ERR_IOERROR); 217 } 218#if USB_DEBUG 219 if (ohcidebug > 15) { 220 ohci_dumpregs(sc); 221 } 222#endif 223 224 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 225 226 /* set up HC registers */ 227 usb2_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 228 OWRITE4(sc, OHCI_HCCA, buf_res.physaddr); 229 230 usb2_get_page(&sc->sc_hw.ctrl_start_pc, 0, &buf_res); 231 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, buf_res.physaddr); 232 233 usb2_get_page(&sc->sc_hw.bulk_start_pc, 0, &buf_res); 234 OWRITE4(sc, OHCI_BULK_HEAD_ED, buf_res.physaddr); 235 236 /* disable all interrupts and then switch on all desired interrupts */ 237 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 238 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 239 /* switch on desired functional features */ 240 ctl = OREAD4(sc, OHCI_CONTROL); 241 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 242 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 243 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL; 244 /* And finally start it! */ 245 OWRITE4(sc, OHCI_CONTROL, ctl); 246 247 /* 248 * The controller is now OPERATIONAL. Set a some final 249 * registers that should be set earlier, but that the 250 * controller ignores when in the SUSPEND state. 251 */ 252 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 253 fm |= OHCI_FSMPS(ival) | ival; 254 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 255 per = OHCI_PERIODIC(ival); /* 90% periodic */ 256 OWRITE4(sc, OHCI_PERIODIC_START, per); 257 258 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 259 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 260 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 261 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 262 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 263 OHCI_ENABLE_POWER_DELAY); 264 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 265 266 /* 267 * The AMD756 requires a delay before re-reading the register, 268 * otherwise it will occasionally report 0 ports. 269 */ 270 sc->sc_noport = 0; 271 for (i = 0; (i < 10) && (sc->sc_noport == 0); i++) { 272 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 273 OHCI_READ_DESC_DELAY); 274 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 275 } 276 277#if USB_DEBUG 278 if (ohcidebug > 5) { 279 ohci_dumpregs(sc); 280 } 281#endif 282 return (USB_ERR_NORMAL_COMPLETION); 283} 284 285static struct ohci_ed * 286ohci_init_ed(struct usb2_page_cache *pc) 287{ 288 struct usb2_page_search buf_res; 289 struct ohci_ed *ed; 290 291 usb2_get_page(pc, 0, &buf_res); 292 293 ed = buf_res.buffer; 294 295 ed->ed_self = htole32(buf_res.physaddr); 296 ed->ed_flags = htole32(OHCI_ED_SKIP); 297 ed->page_cache = pc; 298 299 return (ed); 300} 301 302usb2_error_t 303ohci_init(ohci_softc_t *sc) 304{ 305 struct usb2_page_search buf_res; 306 uint16_t i; 307 uint16_t bit; 308 uint16_t x; 309 uint16_t y; 310 311 USB_BUS_LOCK(&sc->sc_bus); 312 313 DPRINTF("start\n"); 314 315 sc->sc_eintrs = OHCI_NORMAL_INTRS; 316 317 /* 318 * Setup all ED's 319 */ 320 321 sc->sc_ctrl_p_last = 322 ohci_init_ed(&sc->sc_hw.ctrl_start_pc); 323 324 sc->sc_bulk_p_last = 325 ohci_init_ed(&sc->sc_hw.bulk_start_pc); 326 327 sc->sc_isoc_p_last = 328 ohci_init_ed(&sc->sc_hw.isoc_start_pc); 329 330 for (i = 0; i != OHCI_NO_EDS; i++) { 331 sc->sc_intr_p_last[i] = 332 ohci_init_ed(sc->sc_hw.intr_start_pc + i); 333 } 334 335 /* 336 * the QHs are arranged to give poll intervals that are 337 * powers of 2 times 1ms 338 */ 339 bit = OHCI_NO_EDS / 2; 340 while (bit) { 341 x = bit; 342 while (x & bit) { 343 ohci_ed_t *ed_x; 344 ohci_ed_t *ed_y; 345 346 y = (x ^ bit) | (bit / 2); 347 348 /* 349 * the next QH has half the poll interval 350 */ 351 ed_x = sc->sc_intr_p_last[x]; 352 ed_y = sc->sc_intr_p_last[y]; 353 354 ed_x->next = NULL; 355 ed_x->ed_next = ed_y->ed_self; 356 357 x++; 358 } 359 bit >>= 1; 360 } 361 362 if (1) { 363 364 ohci_ed_t *ed_int; 365 ohci_ed_t *ed_isc; 366 367 ed_int = sc->sc_intr_p_last[0]; 368 ed_isc = sc->sc_isoc_p_last; 369 370 /* the last (1ms) QH */ 371 ed_int->next = ed_isc; 372 ed_int->ed_next = ed_isc->ed_self; 373 } 374 usb2_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 375 376 sc->sc_hcca_p = buf_res.buffer; 377 378 /* 379 * Fill HCCA interrupt table. The bit reversal is to get 380 * the tree set up properly to spread the interrupts. 381 */ 382 for (i = 0; i != OHCI_NO_INTRS; i++) { 383 sc->sc_hcca_p->hcca_interrupt_table[i] = 384 sc->sc_intr_p_last[i | (OHCI_NO_EDS / 2)]->ed_self; 385 } 386 /* flush all cache into memory */ 387 388 usb2_bus_mem_flush_all(&sc->sc_bus, &ohci_iterate_hw_softc); 389 390 /* set up the bus struct */ 391 sc->sc_bus.methods = &ohci_bus_methods; 392 393 usb2_callout_init_mtx(&sc->sc_tmo_rhsc, &sc->sc_bus.bus_mtx, 0); 394 395#if USB_DEBUG 396 if (ohcidebug > 15) { 397 for (i = 0; i != OHCI_NO_EDS; i++) { 398 printf("ed#%d ", i); 399 ohci_dump_ed(sc->sc_intr_p_last[i]); 400 } 401 printf("iso "); 402 ohci_dump_ed(sc->sc_isoc_p_last); 403 } 404#endif 405 406 sc->sc_bus.usbrev = USB_REV_1_0; 407 408 if (ohci_controller_init(sc)) { 409 USB_BUS_UNLOCK(&sc->sc_bus); 410 return (USB_ERR_INVAL); 411 } else { 412 USB_BUS_UNLOCK(&sc->sc_bus); 413 /* catch any lost interrupts */ 414 ohci_do_poll(&sc->sc_bus); 415 return (USB_ERR_NORMAL_COMPLETION); 416 } 417} 418 419/* 420 * shut down the controller when the system is going down 421 */ 422void 423ohci_detach(struct ohci_softc *sc) 424{ 425 USB_BUS_LOCK(&sc->sc_bus); 426 427 usb2_callout_stop(&sc->sc_tmo_rhsc); 428 429 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 430 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 431 432 /* XXX let stray task complete */ 433 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 50); 434 435 USB_BUS_UNLOCK(&sc->sc_bus); 436 437 usb2_callout_drain(&sc->sc_tmo_rhsc); 438} 439 440/* NOTE: suspend/resume is called from 441 * interrupt context and cannot sleep! 442 */ 443void 444ohci_suspend(ohci_softc_t *sc) 445{ 446 uint32_t ctl; 447 448 USB_BUS_LOCK(&sc->sc_bus); 449 450#if USB_DEBUG 451 DPRINTF("\n"); 452 if (ohcidebug > 2) { 453 ohci_dumpregs(sc); 454 } 455#endif 456 457 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 458 if (sc->sc_control == 0) { 459 /* 460 * Preserve register values, in case that APM BIOS 461 * does not recover them. 462 */ 463 sc->sc_control = ctl; 464 sc->sc_intre = OREAD4(sc, OHCI_INTERRUPT_ENABLE); 465 } 466 ctl |= OHCI_HCFS_SUSPEND; 467 OWRITE4(sc, OHCI_CONTROL, ctl); 468 469 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 470 USB_RESUME_WAIT); 471 472 USB_BUS_UNLOCK(&sc->sc_bus); 473} 474 475void 476ohci_resume(ohci_softc_t *sc) 477{ 478 uint32_t ctl; 479 480 USB_BUS_LOCK(&sc->sc_bus); 481 482#if USB_DEBUG 483 DPRINTF("\n"); 484 if (ohcidebug > 2) { 485 ohci_dumpregs(sc); 486 } 487#endif 488 /* some broken BIOSes never initialize the Controller chip */ 489 ohci_controller_init(sc); 490 491 if (sc->sc_intre) { 492 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, 493 sc->sc_intre & (OHCI_ALL_INTRS | OHCI_MIE)); 494 } 495 if (sc->sc_control) 496 ctl = sc->sc_control; 497 else 498 ctl = OREAD4(sc, OHCI_CONTROL); 499 ctl |= OHCI_HCFS_RESUME; 500 OWRITE4(sc, OHCI_CONTROL, ctl); 501 usb2_pause_mtx(&sc->sc_bus.bus_mtx, USB_RESUME_DELAY); 502 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 503 OWRITE4(sc, OHCI_CONTROL, ctl); 504 usb2_pause_mtx(&sc->sc_bus.bus_mtx, USB_RESUME_RECOVERY); 505 sc->sc_control = sc->sc_intre = 0; 506 507 USB_BUS_UNLOCK(&sc->sc_bus); 508 509 /* catch any lost interrupts */ 510 ohci_do_poll(&sc->sc_bus); 511} 512 513#if USB_DEBUG 514static void 515ohci_dumpregs(ohci_softc_t *sc) 516{ 517 struct ohci_hcca *hcca; 518 519 DPRINTF("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 520 OREAD4(sc, OHCI_REVISION), 521 OREAD4(sc, OHCI_CONTROL), 522 OREAD4(sc, OHCI_COMMAND_STATUS)); 523 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 524 OREAD4(sc, OHCI_INTERRUPT_STATUS), 525 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 526 OREAD4(sc, OHCI_INTERRUPT_DISABLE)); 527 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 528 OREAD4(sc, OHCI_HCCA), 529 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 530 OREAD4(sc, OHCI_CONTROL_HEAD_ED)); 531 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 532 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 533 OREAD4(sc, OHCI_BULK_HEAD_ED), 534 OREAD4(sc, OHCI_BULK_CURRENT_ED)); 535 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 536 OREAD4(sc, OHCI_DONE_HEAD), 537 OREAD4(sc, OHCI_FM_INTERVAL), 538 OREAD4(sc, OHCI_FM_REMAINING)); 539 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 540 OREAD4(sc, OHCI_FM_NUMBER), 541 OREAD4(sc, OHCI_PERIODIC_START), 542 OREAD4(sc, OHCI_LS_THRESHOLD)); 543 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x\n", 544 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 545 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 546 OREAD4(sc, OHCI_RH_STATUS)); 547 DPRINTF(" port1=0x%08x port2=0x%08x\n", 548 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 549 OREAD4(sc, OHCI_RH_PORT_STATUS(2))); 550 551 hcca = ohci_get_hcca(sc); 552 553 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x\n", 554 le32toh(hcca->hcca_frame_number), 555 le32toh(hcca->hcca_done_head)); 556} 557static void 558ohci_dump_tds(ohci_td_t *std) 559{ 560 for (; std; std = std->obj_next) { 561 if (ohci_dump_td(std)) { 562 break; 563 } 564 } 565} 566 567static uint8_t 568ohci_dump_td(ohci_td_t *std) 569{ 570 uint32_t td_flags; 571 uint8_t temp; 572 573 usb2_pc_cpu_invalidate(std->page_cache); 574 575 td_flags = le32toh(std->td_flags); 576 temp = (std->td_next == 0); 577 578 printf("TD(%p) at 0x%08x: %s%s%s%s%s delay=%d ec=%d " 579 "cc=%d\ncbp=0x%08x next=0x%08x be=0x%08x\n", 580 std, le32toh(std->td_self), 581 (td_flags & OHCI_TD_R) ? "-R" : "", 582 (td_flags & OHCI_TD_OUT) ? "-OUT" : "", 583 (td_flags & OHCI_TD_IN) ? "-IN" : "", 584 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_1) ? "-TOG1" : "", 585 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_0) ? "-TOG0" : "", 586 OHCI_TD_GET_DI(td_flags), 587 OHCI_TD_GET_EC(td_flags), 588 OHCI_TD_GET_CC(td_flags), 589 le32toh(std->td_cbp), 590 le32toh(std->td_next), 591 le32toh(std->td_be)); 592 593 return (temp); 594} 595 596static uint8_t 597ohci_dump_itd(ohci_itd_t *sitd) 598{ 599 uint32_t itd_flags; 600 uint16_t i; 601 uint8_t temp; 602 603 usb2_pc_cpu_invalidate(sitd->page_cache); 604 605 itd_flags = le32toh(sitd->itd_flags); 606 temp = (sitd->itd_next == 0); 607 608 printf("ITD(%p) at 0x%08x: sf=%d di=%d fc=%d cc=%d\n" 609 "bp0=0x%08x next=0x%08x be=0x%08x\n", 610 sitd, le32toh(sitd->itd_self), 611 OHCI_ITD_GET_SF(itd_flags), 612 OHCI_ITD_GET_DI(itd_flags), 613 OHCI_ITD_GET_FC(itd_flags), 614 OHCI_ITD_GET_CC(itd_flags), 615 le32toh(sitd->itd_bp0), 616 le32toh(sitd->itd_next), 617 le32toh(sitd->itd_be)); 618 for (i = 0; i < OHCI_ITD_NOFFSET; i++) { 619 printf("offs[%d]=0x%04x ", i, 620 (uint32_t)le16toh(sitd->itd_offset[i])); 621 } 622 printf("\n"); 623 624 return (temp); 625} 626 627static void 628ohci_dump_itds(ohci_itd_t *sitd) 629{ 630 for (; sitd; sitd = sitd->obj_next) { 631 if (ohci_dump_itd(sitd)) { 632 break; 633 } 634 } 635} 636 637static void 638ohci_dump_ed(ohci_ed_t *sed) 639{ 640 uint32_t ed_flags; 641 uint32_t ed_headp; 642 643 usb2_pc_cpu_invalidate(sed->page_cache); 644 645 ed_flags = le32toh(sed->ed_flags); 646 ed_headp = le32toh(sed->ed_headp); 647 648 printf("ED(%p) at 0x%08x: addr=%d endpt=%d maxp=%d flags=%s%s%s%s%s\n" 649 "tailp=0x%08x headflags=%s%s headp=0x%08x nexted=0x%08x\n", 650 sed, le32toh(sed->ed_self), 651 OHCI_ED_GET_FA(ed_flags), 652 OHCI_ED_GET_EN(ed_flags), 653 OHCI_ED_GET_MAXP(ed_flags), 654 (ed_flags & OHCI_ED_DIR_OUT) ? "-OUT" : "", 655 (ed_flags & OHCI_ED_DIR_IN) ? "-IN" : "", 656 (ed_flags & OHCI_ED_SPEED) ? "-LOWSPEED" : "", 657 (ed_flags & OHCI_ED_SKIP) ? "-SKIP" : "", 658 (ed_flags & OHCI_ED_FORMAT_ISO) ? "-ISO" : "", 659 le32toh(sed->ed_tailp), 660 (ed_headp & OHCI_HALTED) ? "-HALTED" : "", 661 (ed_headp & OHCI_TOGGLECARRY) ? "-CARRY" : "", 662 le32toh(sed->ed_headp), 663 le32toh(sed->ed_next)); 664} 665 666#endif 667 668static void 669ohci_transfer_intr_enqueue(struct usb2_xfer *xfer) 670{ 671 /* check for early completion */ 672 if (ohci_check_transfer(xfer)) { 673 return; 674 } 675 /* put transfer on interrupt queue */ 676 usb2_transfer_enqueue(&xfer->udev->bus->intr_q, xfer); 677 678 /* start timeout, if any */ 679 if (xfer->timeout != 0) { 680 usb2_transfer_timeout_ms(xfer, &ohci_timeout, xfer->timeout); 681 } 682} 683 684#define OHCI_APPEND_QH(sed,last) (last) = _ohci_append_qh(sed,last) 685static ohci_ed_t * 686_ohci_append_qh(ohci_ed_t *sed, ohci_ed_t *last) 687{ 688 DPRINTFN(11, "%p to %p\n", sed, last); 689 690 if (sed->prev != NULL) { 691 /* should not happen */ 692 DPRINTFN(0, "ED already linked!\n"); 693 return (last); 694 } 695 /* (sc->sc_bus.bus_mtx) must be locked */ 696 697 sed->next = last->next; 698 sed->ed_next = last->ed_next; 699 sed->ed_tailp = 0; 700 701 sed->prev = last; 702 703 usb2_pc_cpu_flush(sed->page_cache); 704 705 /* 706 * the last->next->prev is never followed: sed->next->prev = sed; 707 */ 708 709 last->next = sed; 710 last->ed_next = sed->ed_self; 711 712 usb2_pc_cpu_flush(last->page_cache); 713 714 return (sed); 715} 716 717#define OHCI_REMOVE_QH(sed,last) (last) = _ohci_remove_qh(sed,last) 718static ohci_ed_t * 719_ohci_remove_qh(ohci_ed_t *sed, ohci_ed_t *last) 720{ 721 DPRINTFN(11, "%p from %p\n", sed, last); 722 723 /* (sc->sc_bus.bus_mtx) must be locked */ 724 725 /* only remove if not removed from a queue */ 726 if (sed->prev) { 727 728 sed->prev->next = sed->next; 729 sed->prev->ed_next = sed->ed_next; 730 731 usb2_pc_cpu_flush(sed->prev->page_cache); 732 733 if (sed->next) { 734 sed->next->prev = sed->prev; 735 usb2_pc_cpu_flush(sed->next->page_cache); 736 } 737 last = ((last == sed) ? sed->prev : last); 738 739 sed->prev = 0; 740 741 usb2_pc_cpu_flush(sed->page_cache); 742 } 743 return (last); 744} 745 746static void 747ohci_isoc_done(struct usb2_xfer *xfer) 748{ 749 uint8_t nframes; 750 uint32_t *plen = xfer->frlengths; 751 volatile uint16_t *olen; 752 uint16_t len = 0; 753 ohci_itd_t *td = xfer->td_transfer_first; 754 755 while (1) { 756 if (td == NULL) { 757 panic("%s:%d: out of TD's\n", 758 __FUNCTION__, __LINE__); 759 } 760#if USB_DEBUG 761 if (ohcidebug > 5) { 762 DPRINTF("isoc TD\n"); 763 ohci_dump_itd(td); 764 } 765#endif 766 usb2_pc_cpu_invalidate(td->page_cache); 767 768 nframes = td->frames; 769 olen = &td->itd_offset[0]; 770 771 if (nframes > 8) { 772 nframes = 8; 773 } 774 while (nframes--) { 775 len = le16toh(*olen); 776 777 if ((len >> 12) == OHCI_CC_NOT_ACCESSED) { 778 len = 0; 779 } else { 780 len &= ((1 << 12) - 1); 781 } 782 783 if (len > *plen) { 784 len = 0;/* invalid length */ 785 } 786 *plen = len; 787 plen++; 788 olen++; 789 } 790 791 if (((void *)td) == xfer->td_transfer_last) { 792 break; 793 } 794 td = td->obj_next; 795 } 796 797 xfer->aframes = xfer->nframes; 798 ohci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 799} 800 801#if USB_DEBUG 802static const char *const 803 ohci_cc_strs[] = 804{ 805 "NO_ERROR", 806 "CRC", 807 "BIT_STUFFING", 808 "DATA_TOGGLE_MISMATCH", 809 810 "STALL", 811 "DEVICE_NOT_RESPONDING", 812 "PID_CHECK_FAILURE", 813 "UNEXPECTED_PID", 814 815 "DATA_OVERRUN", 816 "DATA_UNDERRUN", 817 "BUFFER_OVERRUN", 818 "BUFFER_UNDERRUN", 819 820 "reserved", 821 "reserved", 822 "NOT_ACCESSED", 823 "NOT_ACCESSED" 824}; 825 826#endif 827 828static usb2_error_t 829ohci_non_isoc_done_sub(struct usb2_xfer *xfer) 830{ 831 ohci_td_t *td; 832 ohci_td_t *td_alt_next; 833 uint32_t temp; 834 uint32_t phy_start; 835 uint32_t phy_end; 836 uint32_t td_flags; 837 uint16_t cc; 838 839 td = xfer->td_transfer_cache; 840 td_alt_next = td->alt_next; 841 td_flags = 0; 842 843 while (1) { 844 845 usb2_pc_cpu_invalidate(td->page_cache); 846 phy_start = le32toh(td->td_cbp); 847 td_flags = le32toh(td->td_flags); 848 cc = OHCI_TD_GET_CC(td_flags); 849 850 if (phy_start) { 851 /* 852 * short transfer - compute the number of remaining 853 * bytes in the hardware buffer: 854 */ 855 phy_end = le32toh(td->td_be); 856 temp = (OHCI_PAGE(phy_start ^ phy_end) ? 857 (OHCI_PAGE_SIZE + 1) : 0x0001); 858 temp += OHCI_PAGE_OFFSET(phy_end); 859 temp -= OHCI_PAGE_OFFSET(phy_start); 860 861 if (temp > td->len) { 862 /* guard against corruption */ 863 cc = OHCI_CC_STALL; 864 } else if (xfer->aframes != xfer->nframes) { 865 /* 866 * subtract remaining length from 867 * "frlengths[]" 868 */ 869 xfer->frlengths[xfer->aframes] -= temp; 870 } 871 } 872 /* Check for last transfer */ 873 if (((void *)td) == xfer->td_transfer_last) { 874 td = NULL; 875 break; 876 } 877 /* Check transfer status */ 878 if (cc) { 879 /* the transfer is finished */ 880 td = NULL; 881 break; 882 } 883 /* Check for short transfer */ 884 if (phy_start) { 885 if (xfer->flags_int.short_frames_ok) { 886 /* follow alt next */ 887 td = td->alt_next; 888 } else { 889 /* the transfer is finished */ 890 td = NULL; 891 } 892 break; 893 } 894 td = td->obj_next; 895 896 if (td->alt_next != td_alt_next) { 897 /* this USB frame is complete */ 898 break; 899 } 900 } 901 902 /* update transfer cache */ 903 904 xfer->td_transfer_cache = td; 905 906 DPRINTFN(16, "error cc=%d (%s)\n", 907 cc, ohci_cc_strs[cc]); 908 909 return ((cc == 0) ? USB_ERR_NORMAL_COMPLETION : 910 (cc == OHCI_CC_STALL) ? USB_ERR_STALLED : USB_ERR_IOERROR); 911} 912 913static void 914ohci_non_isoc_done(struct usb2_xfer *xfer) 915{ 916 usb2_error_t err = 0; 917 918 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 919 xfer, xfer->pipe); 920 921#if USB_DEBUG 922 if (ohcidebug > 10) { 923 ohci_dump_tds(xfer->td_transfer_first); 924 } 925#endif 926 927 /* reset scanner */ 928 929 xfer->td_transfer_cache = xfer->td_transfer_first; 930 931 if (xfer->flags_int.control_xfr) { 932 933 if (xfer->flags_int.control_hdr) { 934 935 err = ohci_non_isoc_done_sub(xfer); 936 } 937 xfer->aframes = 1; 938 939 if (xfer->td_transfer_cache == NULL) { 940 goto done; 941 } 942 } 943 while (xfer->aframes != xfer->nframes) { 944 945 err = ohci_non_isoc_done_sub(xfer); 946 xfer->aframes++; 947 948 if (xfer->td_transfer_cache == NULL) { 949 goto done; 950 } 951 } 952 953 if (xfer->flags_int.control_xfr && 954 !xfer->flags_int.control_act) { 955 956 err = ohci_non_isoc_done_sub(xfer); 957 } 958done: 959 ohci_device_done(xfer, err); 960} 961 962/*------------------------------------------------------------------------* 963 * ohci_check_transfer_sub 964 *------------------------------------------------------------------------*/ 965static void 966ohci_check_transfer_sub(struct usb2_xfer *xfer) 967{ 968 ohci_td_t *td; 969 ohci_ed_t *ed; 970 uint32_t phy_start; 971 uint32_t td_flags; 972 uint32_t td_next; 973 uint16_t cc; 974 975 td = xfer->td_transfer_cache; 976 977 while (1) { 978 979 usb2_pc_cpu_invalidate(td->page_cache); 980 phy_start = le32toh(td->td_cbp); 981 td_flags = le32toh(td->td_flags); 982 td_next = le32toh(td->td_next); 983 984 /* Check for last transfer */ 985 if (((void *)td) == xfer->td_transfer_last) { 986 /* the transfer is finished */ 987 td = NULL; 988 break; 989 } 990 /* Check transfer status */ 991 cc = OHCI_TD_GET_CC(td_flags); 992 if (cc) { 993 /* the transfer is finished */ 994 td = NULL; 995 break; 996 } 997 /* 998 * Check if we reached the last packet 999 * or if there is a short packet: 1000 */ 1001 1002 if (((td_next & (~0xF)) == OHCI_TD_NEXT_END) || phy_start) { 1003 /* follow alt next */ 1004 td = td->alt_next; 1005 break; 1006 } 1007 td = td->obj_next; 1008 } 1009 1010 /* update transfer cache */ 1011 1012 xfer->td_transfer_cache = td; 1013 1014 if (td) { 1015 1016 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1017 1018 ed->ed_headp = td->td_self; 1019 usb2_pc_cpu_flush(ed->page_cache); 1020 1021 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1022 } 1023} 1024 1025/*------------------------------------------------------------------------* 1026 * ohci_check_transfer 1027 * 1028 * Return values: 1029 * 0: USB transfer is not finished 1030 * Else: USB transfer is finished 1031 *------------------------------------------------------------------------*/ 1032static uint8_t 1033ohci_check_transfer(struct usb2_xfer *xfer) 1034{ 1035 ohci_ed_t *ed; 1036 uint32_t ed_flags; 1037 uint32_t ed_headp; 1038 uint32_t ed_tailp; 1039 1040 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1041 1042 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1043 1044 usb2_pc_cpu_invalidate(ed->page_cache); 1045 ed_flags = le32toh(ed->ed_flags); 1046 ed_headp = le32toh(ed->ed_headp); 1047 ed_tailp = le32toh(ed->ed_tailp); 1048 1049 if ((ed_flags & OHCI_ED_SKIP) || 1050 (ed_headp & OHCI_HALTED) || 1051 (((ed_headp ^ ed_tailp) & (~0xF)) == 0)) { 1052 if (xfer->pipe->methods == &ohci_device_isoc_methods) { 1053 /* isochronous transfer */ 1054 ohci_isoc_done(xfer); 1055 } else { 1056 if (xfer->flags_int.short_frames_ok) { 1057 ohci_check_transfer_sub(xfer); 1058 if (xfer->td_transfer_cache) { 1059 /* not finished yet */ 1060 return (0); 1061 } 1062 } 1063 /* store data-toggle */ 1064 if (ed_headp & OHCI_TOGGLECARRY) { 1065 xfer->pipe->toggle_next = 1; 1066 } else { 1067 xfer->pipe->toggle_next = 0; 1068 } 1069 1070 /* non-isochronous transfer */ 1071 ohci_non_isoc_done(xfer); 1072 } 1073 return (1); 1074 } 1075 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1076 return (0); 1077} 1078 1079static void 1080ohci_rhsc_enable(ohci_softc_t *sc) 1081{ 1082 DPRINTFN(5, "\n"); 1083 1084 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1085 1086 sc->sc_eintrs |= OHCI_RHSC; 1087 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1088 1089 /* acknowledge any RHSC interrupt */ 1090 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_RHSC); 1091 1092 usb2_sw_transfer(&sc->sc_root_intr, 1093 &ohci_root_intr_done); 1094} 1095 1096static void 1097ohci_interrupt_poll(ohci_softc_t *sc) 1098{ 1099 struct usb2_xfer *xfer; 1100 1101repeat: 1102 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1103 /* 1104 * check if transfer is transferred 1105 */ 1106 if (ohci_check_transfer(xfer)) { 1107 /* queue has been modified */ 1108 goto repeat; 1109 } 1110 } 1111} 1112 1113/*------------------------------------------------------------------------* 1114 * ohci_interrupt - OHCI interrupt handler 1115 * 1116 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1117 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1118 * is present ! 1119 *------------------------------------------------------------------------*/ 1120void 1121ohci_interrupt(ohci_softc_t *sc) 1122{ 1123 struct ohci_hcca *hcca; 1124 uint32_t status; 1125 uint32_t done; 1126 1127 USB_BUS_LOCK(&sc->sc_bus); 1128 1129 hcca = ohci_get_hcca(sc); 1130 1131 DPRINTFN(16, "real interrupt\n"); 1132 1133#if USB_DEBUG 1134 if (ohcidebug > 15) { 1135 ohci_dumpregs(sc); 1136 } 1137#endif 1138 1139 done = le32toh(hcca->hcca_done_head); 1140 1141 /* 1142 * The LSb of done is used to inform the HC Driver that an interrupt 1143 * condition exists for both the Done list and for another event 1144 * recorded in HcInterruptStatus. On an interrupt from the HC, the 1145 * HC Driver checks the HccaDoneHead Value. If this value is 0, then 1146 * the interrupt was caused by other than the HccaDoneHead update 1147 * and the HcInterruptStatus register needs to be accessed to 1148 * determine that exact interrupt cause. If HccaDoneHead is nonzero, 1149 * then a Done list update interrupt is indicated and if the LSb of 1150 * done is nonzero, then an additional interrupt event is indicated 1151 * and HcInterruptStatus should be checked to determine its cause. 1152 */ 1153 if (done != 0) { 1154 status = 0; 1155 1156 if (done & ~OHCI_DONE_INTRS) { 1157 status |= OHCI_WDH; 1158 } 1159 if (done & OHCI_DONE_INTRS) { 1160 status |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 1161 } 1162 hcca->hcca_done_head = 0; 1163 1164 usb2_pc_cpu_flush(&sc->sc_hw.hcca_pc); 1165 } else { 1166 status = OREAD4(sc, OHCI_INTERRUPT_STATUS) & ~OHCI_WDH; 1167 } 1168 1169 status &= ~OHCI_MIE; 1170 if (status == 0) { 1171 /* 1172 * nothing to be done (PCI shared 1173 * interrupt) 1174 */ 1175 goto done; 1176 } 1177 OWRITE4(sc, OHCI_INTERRUPT_STATUS, status); /* Acknowledge */ 1178 1179 status &= sc->sc_eintrs; 1180 if (status == 0) { 1181 goto done; 1182 } 1183 if (status & (OHCI_SO | OHCI_RD | OHCI_UE | OHCI_RHSC)) { 1184#if 0 1185 if (status & OHCI_SO) { 1186 /* XXX do what */ 1187 } 1188#endif 1189 if (status & OHCI_RD) { 1190 printf("%s: resume detect\n", __FUNCTION__); 1191 /* XXX process resume detect */ 1192 } 1193 if (status & OHCI_UE) { 1194 printf("%s: unrecoverable error, " 1195 "controller halted\n", __FUNCTION__); 1196 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1197 /* XXX what else */ 1198 } 1199 if (status & OHCI_RHSC) { 1200 /* 1201 * Disable RHSC interrupt for now, because it will be 1202 * on until the port has been reset. 1203 */ 1204 sc->sc_eintrs &= ~OHCI_RHSC; 1205 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 1206 1207 usb2_sw_transfer(&sc->sc_root_intr, 1208 &ohci_root_intr_done); 1209 1210 /* do not allow RHSC interrupts > 1 per second */ 1211 usb2_callout_reset(&sc->sc_tmo_rhsc, hz, 1212 (void *)&ohci_rhsc_enable, sc); 1213 } 1214 } 1215 status &= ~(OHCI_RHSC | OHCI_WDH | OHCI_SO); 1216 if (status != 0) { 1217 /* Block unprocessed interrupts. XXX */ 1218 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, status); 1219 sc->sc_eintrs &= ~status; 1220 printf("%s: blocking intrs 0x%x\n", 1221 __FUNCTION__, status); 1222 } 1223 /* poll all the USB transfers */ 1224 ohci_interrupt_poll(sc); 1225 1226done: 1227 USB_BUS_UNLOCK(&sc->sc_bus); 1228} 1229 1230/* 1231 * called when a request does not complete 1232 */ 1233static void 1234ohci_timeout(void *arg) 1235{ 1236 struct usb2_xfer *xfer = arg; 1237 1238 DPRINTF("xfer=%p\n", xfer); 1239 1240 USB_BUS_LOCK_ASSERT(xfer->udev->bus, MA_OWNED); 1241 1242 /* transfer is transferred */ 1243 ohci_device_done(xfer, USB_ERR_TIMEOUT); 1244} 1245 1246static void 1247ohci_do_poll(struct usb2_bus *bus) 1248{ 1249 struct ohci_softc *sc = OHCI_BUS2SC(bus); 1250 1251 USB_BUS_LOCK(&sc->sc_bus); 1252 ohci_interrupt_poll(sc); 1253 ohci_root_ctrl_poll(sc); 1254 USB_BUS_UNLOCK(&sc->sc_bus); 1255} 1256 1257static void 1258ohci_setup_standard_chain_sub(struct ohci_std_temp *temp) 1259{ 1260 struct usb2_page_search buf_res; 1261 ohci_td_t *td; 1262 ohci_td_t *td_next; 1263 ohci_td_t *td_alt_next; 1264 uint32_t buf_offset; 1265 uint32_t average; 1266 uint32_t len_old; 1267 uint8_t shortpkt_old; 1268 uint8_t precompute; 1269 1270 td_alt_next = NULL; 1271 buf_offset = 0; 1272 shortpkt_old = temp->shortpkt; 1273 len_old = temp->len; 1274 precompute = 1; 1275 1276 /* software is used to detect short incoming transfers */ 1277 1278 if ((temp->td_flags & htole32(OHCI_TD_DP_MASK)) == htole32(OHCI_TD_IN)) { 1279 temp->td_flags |= htole32(OHCI_TD_R); 1280 } else { 1281 temp->td_flags &= ~htole32(OHCI_TD_R); 1282 } 1283 1284restart: 1285 1286 td = temp->td; 1287 td_next = temp->td_next; 1288 1289 while (1) { 1290 1291 if (temp->len == 0) { 1292 1293 if (temp->shortpkt) { 1294 break; 1295 } 1296 /* send a Zero Length Packet, ZLP, last */ 1297 1298 temp->shortpkt = 1; 1299 average = 0; 1300 1301 } else { 1302 1303 average = temp->average; 1304 1305 if (temp->len < average) { 1306 if (temp->len % temp->max_frame_size) { 1307 temp->shortpkt = 1; 1308 } 1309 average = temp->len; 1310 } 1311 } 1312 1313 if (td_next == NULL) { 1314 panic("%s: out of OHCI transfer descriptors!", __FUNCTION__); 1315 } 1316 /* get next TD */ 1317 1318 td = td_next; 1319 td_next = td->obj_next; 1320 1321 /* check if we are pre-computing */ 1322 1323 if (precompute) { 1324 1325 /* update remaining length */ 1326 1327 temp->len -= average; 1328 1329 continue; 1330 } 1331 /* fill out current TD */ 1332 td->td_flags = temp->td_flags; 1333 1334 /* the next TD uses TOGGLE_CARRY */ 1335 temp->td_flags &= ~htole32(OHCI_TD_TOGGLE_MASK); 1336 1337 if (average == 0) { 1338 1339 td->td_cbp = 0; 1340 td->td_be = ~0; 1341 td->len = 0; 1342 1343 } else { 1344 1345 usb2_get_page(temp->pc, buf_offset, &buf_res); 1346 td->td_cbp = htole32(buf_res.physaddr); 1347 buf_offset += (average - 1); 1348 1349 usb2_get_page(temp->pc, buf_offset, &buf_res); 1350 td->td_be = htole32(buf_res.physaddr); 1351 buf_offset++; 1352 1353 td->len = average; 1354 1355 /* update remaining length */ 1356 1357 temp->len -= average; 1358 } 1359 1360 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1361 /* we need to receive these frames one by one ! */ 1362 td->td_flags &= htole32(~OHCI_TD_INTR_MASK); 1363 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1364 td->td_next = htole32(OHCI_TD_NEXT_END); 1365 } else { 1366 if (td_next) { 1367 /* link the current TD with the next one */ 1368 td->td_next = td_next->td_self; 1369 } 1370 } 1371 1372 td->alt_next = td_alt_next; 1373 1374 usb2_pc_cpu_flush(td->page_cache); 1375 } 1376 1377 if (precompute) { 1378 precompute = 0; 1379 1380 /* setup alt next pointer, if any */ 1381 if (temp->short_frames_ok) { 1382 if (temp->setup_alt_next) { 1383 td_alt_next = td_next; 1384 } 1385 } else { 1386 /* we use this field internally */ 1387 td_alt_next = td_next; 1388 } 1389 1390 /* restore */ 1391 temp->shortpkt = shortpkt_old; 1392 temp->len = len_old; 1393 goto restart; 1394 } 1395 temp->td = td; 1396 temp->td_next = td_next; 1397} 1398 1399static void 1400ohci_setup_standard_chain(struct usb2_xfer *xfer, ohci_ed_t **ed_last) 1401{ 1402 struct ohci_std_temp temp; 1403 struct usb2_pipe_methods *methods; 1404 ohci_ed_t *ed; 1405 ohci_td_t *td; 1406 uint32_t ed_flags; 1407 uint32_t x; 1408 1409 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1410 xfer->address, UE_GET_ADDR(xfer->endpoint), 1411 xfer->sumlen, usb2_get_speed(xfer->udev)); 1412 1413 temp.average = xfer->max_usb2_frame_size; 1414 temp.max_frame_size = xfer->max_frame_size; 1415 1416 /* toggle the DMA set we are using */ 1417 xfer->flags_int.curr_dma_set ^= 1; 1418 1419 /* get next DMA set */ 1420 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1421 1422 xfer->td_transfer_first = td; 1423 xfer->td_transfer_cache = td; 1424 1425 temp.td = NULL; 1426 temp.td_next = td; 1427 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1428 temp.short_frames_ok = xfer->flags_int.short_frames_ok; 1429 1430 methods = xfer->pipe->methods; 1431 1432 /* check if we should prepend a setup message */ 1433 1434 if (xfer->flags_int.control_xfr) { 1435 if (xfer->flags_int.control_hdr) { 1436 1437 temp.td_flags = htole32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1438 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1439 1440 temp.len = xfer->frlengths[0]; 1441 temp.pc = xfer->frbuffers + 0; 1442 temp.shortpkt = temp.len ? 1 : 0; 1443 1444 ohci_setup_standard_chain_sub(&temp); 1445 1446 /* 1447 * XXX assume that the setup message is 1448 * contained within one USB packet: 1449 */ 1450 xfer->pipe->toggle_next = 1; 1451 } 1452 x = 1; 1453 } else { 1454 x = 0; 1455 } 1456 temp.td_flags = htole32(OHCI_TD_NOCC | OHCI_TD_NOINTR); 1457 1458 /* set data toggle */ 1459 1460 if (xfer->pipe->toggle_next) { 1461 temp.td_flags |= htole32(OHCI_TD_TOGGLE_1); 1462 } else { 1463 temp.td_flags |= htole32(OHCI_TD_TOGGLE_0); 1464 } 1465 1466 /* set endpoint direction */ 1467 1468 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 1469 temp.td_flags |= htole32(OHCI_TD_IN); 1470 } else { 1471 temp.td_flags |= htole32(OHCI_TD_OUT); 1472 } 1473 1474 while (x != xfer->nframes) { 1475 1476 /* DATA0 / DATA1 message */ 1477 1478 temp.len = xfer->frlengths[x]; 1479 temp.pc = xfer->frbuffers + x; 1480 1481 x++; 1482 1483 if (x == xfer->nframes) { 1484 temp.setup_alt_next = 0; 1485 } 1486 if (temp.len == 0) { 1487 1488 /* make sure that we send an USB packet */ 1489 1490 temp.shortpkt = 0; 1491 1492 } else { 1493 1494 /* regular data transfer */ 1495 1496 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1497 } 1498 1499 ohci_setup_standard_chain_sub(&temp); 1500 } 1501 1502 /* check if we should append a status stage */ 1503 1504 if (xfer->flags_int.control_xfr && 1505 !xfer->flags_int.control_act) { 1506 1507 /* 1508 * Send a DATA1 message and invert the current endpoint 1509 * direction. 1510 */ 1511 1512 /* set endpoint direction and data toggle */ 1513 1514 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 1515 temp.td_flags = htole32(OHCI_TD_OUT | 1516 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1517 } else { 1518 temp.td_flags = htole32(OHCI_TD_IN | 1519 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1520 } 1521 1522 temp.len = 0; 1523 temp.pc = NULL; 1524 temp.shortpkt = 0; 1525 1526 ohci_setup_standard_chain_sub(&temp); 1527 } 1528 td = temp.td; 1529 1530 td->td_next = htole32(OHCI_TD_NEXT_END); 1531 td->td_flags &= ~htole32(OHCI_TD_INTR_MASK); 1532 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1533 1534 usb2_pc_cpu_flush(td->page_cache); 1535 1536 /* must have at least one frame! */ 1537 1538 xfer->td_transfer_last = td; 1539 1540#if USB_DEBUG 1541 if (ohcidebug > 8) { 1542 DPRINTF("nexttog=%d; data before transfer:\n", 1543 xfer->pipe->toggle_next); 1544 ohci_dump_tds(xfer->td_transfer_first); 1545 } 1546#endif 1547 1548 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1549 1550 ed_flags = (OHCI_ED_SET_FA(xfer->address) | 1551 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpoint)) | 1552 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 1553 1554 ed_flags |= (OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD); 1555 1556 if (xfer->udev->speed == USB_SPEED_LOW) { 1557 ed_flags |= OHCI_ED_SPEED; 1558 } 1559 ed->ed_flags = htole32(ed_flags); 1560 1561 usb2_pc_cpu_flush(ed->page_cache); 1562 1563 td = xfer->td_transfer_first; 1564 1565 ed->ed_headp = td->td_self; 1566 1567 if (xfer->udev->pwr_save.suspended == 0) { 1568 OHCI_APPEND_QH(ed, *ed_last); 1569 1570 if (methods == &ohci_device_bulk_methods) { 1571 ohci_softc_t *sc = xfer->usb2_sc; 1572 1573 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1574 } 1575 if (methods == &ohci_device_ctrl_methods) { 1576 ohci_softc_t *sc = xfer->usb2_sc; 1577 1578 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1579 } 1580 } else { 1581 usb2_pc_cpu_flush(ed->page_cache); 1582 } 1583} 1584 1585static void 1586ohci_root_intr_done(struct usb2_xfer *xfer, 1587 struct usb2_sw_transfer *std) 1588{ 1589 ohci_softc_t *sc = xfer->usb2_sc; 1590 uint32_t hstatus; 1591 uint16_t i; 1592 uint16_t m; 1593 1594 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1595 1596 if (std->state != USB_SW_TR_PRE_DATA) { 1597 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1598 /* transfer transferred */ 1599 ohci_device_done(xfer, std->err); 1600 } 1601 goto done; 1602 } 1603 /* setup buffer */ 1604 std->ptr = sc->sc_hub_idata; 1605 std->len = sizeof(sc->sc_hub_idata); 1606 1607 /* clear any old interrupt data */ 1608 bzero(sc->sc_hub_idata, sizeof(sc->sc_hub_idata)); 1609 1610 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1611 DPRINTF("sc=%p xfer=%p hstatus=0x%08x\n", 1612 sc, xfer, hstatus); 1613 1614 /* set bits */ 1615 m = (sc->sc_noport + 1); 1616 if (m > (8 * sizeof(sc->sc_hub_idata))) { 1617 m = (8 * sizeof(sc->sc_hub_idata)); 1618 } 1619 for (i = 1; i < m; i++) { 1620 /* pick out CHANGE bits from the status register */ 1621 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) { 1622 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 1623 DPRINTF("port %d changed\n", i); 1624 } 1625 } 1626done: 1627 return; 1628} 1629 1630/* NOTE: "done" can be run two times in a row, 1631 * from close and from interrupt 1632 */ 1633static void 1634ohci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1635{ 1636 struct usb2_pipe_methods *methods = xfer->pipe->methods; 1637 ohci_softc_t *sc = xfer->usb2_sc; 1638 ohci_ed_t *ed; 1639 1640 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1641 1642 1643 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1644 xfer, xfer->pipe, error); 1645 1646 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1647 if (ed) { 1648 usb2_pc_cpu_invalidate(ed->page_cache); 1649 } 1650 if (methods == &ohci_device_bulk_methods) { 1651 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 1652 } 1653 if (methods == &ohci_device_ctrl_methods) { 1654 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 1655 } 1656 if (methods == &ohci_device_intr_methods) { 1657 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 1658 } 1659 if (methods == &ohci_device_isoc_methods) { 1660 OHCI_REMOVE_QH(ed, sc->sc_isoc_p_last); 1661 } 1662 xfer->td_transfer_first = NULL; 1663 xfer->td_transfer_last = NULL; 1664 1665 /* dequeue transfer and start next transfer */ 1666 usb2_transfer_done(xfer, error); 1667} 1668 1669/*------------------------------------------------------------------------* 1670 * ohci bulk support 1671 *------------------------------------------------------------------------*/ 1672static void 1673ohci_device_bulk_open(struct usb2_xfer *xfer) 1674{ 1675 return; 1676} 1677 1678static void 1679ohci_device_bulk_close(struct usb2_xfer *xfer) 1680{ 1681 ohci_device_done(xfer, USB_ERR_CANCELLED); 1682} 1683 1684static void 1685ohci_device_bulk_enter(struct usb2_xfer *xfer) 1686{ 1687 return; 1688} 1689 1690static void 1691ohci_device_bulk_start(struct usb2_xfer *xfer) 1692{ 1693 ohci_softc_t *sc = xfer->usb2_sc; 1694 1695 /* setup TD's and QH */ 1696 ohci_setup_standard_chain(xfer, &sc->sc_bulk_p_last); 1697 1698 /* put transfer on interrupt queue */ 1699 ohci_transfer_intr_enqueue(xfer); 1700} 1701 1702struct usb2_pipe_methods ohci_device_bulk_methods = 1703{ 1704 .open = ohci_device_bulk_open, 1705 .close = ohci_device_bulk_close, 1706 .enter = ohci_device_bulk_enter, 1707 .start = ohci_device_bulk_start, 1708 .enter_is_cancelable = 1, 1709 .start_is_cancelable = 1, 1710}; 1711 1712/*------------------------------------------------------------------------* 1713 * ohci control support 1714 *------------------------------------------------------------------------*/ 1715static void 1716ohci_device_ctrl_open(struct usb2_xfer *xfer) 1717{ 1718 return; 1719} 1720 1721static void 1722ohci_device_ctrl_close(struct usb2_xfer *xfer) 1723{ 1724 ohci_device_done(xfer, USB_ERR_CANCELLED); 1725} 1726 1727static void 1728ohci_device_ctrl_enter(struct usb2_xfer *xfer) 1729{ 1730 return; 1731} 1732 1733static void 1734ohci_device_ctrl_start(struct usb2_xfer *xfer) 1735{ 1736 ohci_softc_t *sc = xfer->usb2_sc; 1737 1738 /* setup TD's and QH */ 1739 ohci_setup_standard_chain(xfer, &sc->sc_ctrl_p_last); 1740 1741 /* put transfer on interrupt queue */ 1742 ohci_transfer_intr_enqueue(xfer); 1743} 1744 1745struct usb2_pipe_methods ohci_device_ctrl_methods = 1746{ 1747 .open = ohci_device_ctrl_open, 1748 .close = ohci_device_ctrl_close, 1749 .enter = ohci_device_ctrl_enter, 1750 .start = ohci_device_ctrl_start, 1751 .enter_is_cancelable = 1, 1752 .start_is_cancelable = 1, 1753}; 1754 1755/*------------------------------------------------------------------------* 1756 * ohci interrupt support 1757 *------------------------------------------------------------------------*/ 1758static void 1759ohci_device_intr_open(struct usb2_xfer *xfer) 1760{ 1761 ohci_softc_t *sc = xfer->usb2_sc; 1762 uint16_t best; 1763 uint16_t bit; 1764 uint16_t x; 1765 1766 best = 0; 1767 bit = OHCI_NO_EDS / 2; 1768 while (bit) { 1769 if (xfer->interval >= bit) { 1770 x = bit; 1771 best = bit; 1772 while (x & bit) { 1773 if (sc->sc_intr_stat[x] < 1774 sc->sc_intr_stat[best]) { 1775 best = x; 1776 } 1777 x++; 1778 } 1779 break; 1780 } 1781 bit >>= 1; 1782 } 1783 1784 sc->sc_intr_stat[best]++; 1785 xfer->qh_pos = best; 1786 1787 DPRINTFN(3, "best=%d interval=%d\n", 1788 best, xfer->interval); 1789} 1790 1791static void 1792ohci_device_intr_close(struct usb2_xfer *xfer) 1793{ 1794 ohci_softc_t *sc = xfer->usb2_sc; 1795 1796 sc->sc_intr_stat[xfer->qh_pos]--; 1797 1798 ohci_device_done(xfer, USB_ERR_CANCELLED); 1799} 1800 1801static void 1802ohci_device_intr_enter(struct usb2_xfer *xfer) 1803{ 1804 return; 1805} 1806 1807static void 1808ohci_device_intr_start(struct usb2_xfer *xfer) 1809{ 1810 ohci_softc_t *sc = xfer->usb2_sc; 1811 1812 /* setup TD's and QH */ 1813 ohci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 1814 1815 /* put transfer on interrupt queue */ 1816 ohci_transfer_intr_enqueue(xfer); 1817} 1818 1819struct usb2_pipe_methods ohci_device_intr_methods = 1820{ 1821 .open = ohci_device_intr_open, 1822 .close = ohci_device_intr_close, 1823 .enter = ohci_device_intr_enter, 1824 .start = ohci_device_intr_start, 1825 .enter_is_cancelable = 1, 1826 .start_is_cancelable = 1, 1827}; 1828 1829/*------------------------------------------------------------------------* 1830 * ohci isochronous support 1831 *------------------------------------------------------------------------*/ 1832static void 1833ohci_device_isoc_open(struct usb2_xfer *xfer) 1834{ 1835 return; 1836} 1837 1838static void 1839ohci_device_isoc_close(struct usb2_xfer *xfer) 1840{ 1841 /**/ 1842 ohci_device_done(xfer, USB_ERR_CANCELLED); 1843} 1844 1845static void 1846ohci_device_isoc_enter(struct usb2_xfer *xfer) 1847{ 1848 struct usb2_page_search buf_res; 1849 ohci_softc_t *sc = xfer->usb2_sc; 1850 struct ohci_hcca *hcca; 1851 uint32_t buf_offset; 1852 uint32_t nframes; 1853 uint32_t ed_flags; 1854 uint32_t *plen; 1855 uint16_t itd_offset[OHCI_ITD_NOFFSET]; 1856 uint16_t length; 1857 uint8_t ncur; 1858 ohci_itd_t *td; 1859 ohci_itd_t *td_last = NULL; 1860 ohci_ed_t *ed; 1861 1862 hcca = ohci_get_hcca(sc); 1863 1864 nframes = le32toh(hcca->hcca_frame_number); 1865 1866 DPRINTFN(6, "xfer=%p isoc_next=%u nframes=%u hcca_fn=%u\n", 1867 xfer, xfer->pipe->isoc_next, xfer->nframes, nframes); 1868 1869 if ((xfer->pipe->is_synced == 0) || 1870 (((nframes - xfer->pipe->isoc_next) & 0xFFFF) < xfer->nframes) || 1871 (((xfer->pipe->isoc_next - nframes) & 0xFFFF) >= 128)) { 1872 /* 1873 * If there is data underflow or the pipe queue is empty we 1874 * schedule the transfer a few frames ahead of the current 1875 * frame position. Else two isochronous transfers might 1876 * overlap. 1877 */ 1878 xfer->pipe->isoc_next = (nframes + 3) & 0xFFFF; 1879 xfer->pipe->is_synced = 1; 1880 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 1881 } 1882 /* 1883 * compute how many milliseconds the insertion is ahead of the 1884 * current frame position: 1885 */ 1886 buf_offset = ((xfer->pipe->isoc_next - nframes) & 0xFFFF); 1887 1888 /* 1889 * pre-compute when the isochronous transfer will be finished: 1890 */ 1891 xfer->isoc_time_complete = 1892 (usb2_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 1893 xfer->nframes); 1894 1895 /* get the real number of frames */ 1896 1897 nframes = xfer->nframes; 1898 1899 buf_offset = 0; 1900 1901 plen = xfer->frlengths; 1902 1903 /* toggle the DMA set we are using */ 1904 xfer->flags_int.curr_dma_set ^= 1; 1905 1906 /* get next DMA set */ 1907 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1908 1909 xfer->td_transfer_first = td; 1910 1911 ncur = 0; 1912 length = 0; 1913 1914 while (nframes--) { 1915 if (td == NULL) { 1916 panic("%s:%d: out of TD's\n", 1917 __FUNCTION__, __LINE__); 1918 } 1919 itd_offset[ncur] = length; 1920 buf_offset += *plen; 1921 length += *plen; 1922 plen++; 1923 ncur++; 1924 1925 if ( /* check if the ITD is full */ 1926 (ncur == OHCI_ITD_NOFFSET) || 1927 /* check if we have put more than 4K into the ITD */ 1928 (length & 0xF000) || 1929 /* check if it is the last frame */ 1930 (nframes == 0)) { 1931 1932 /* fill current ITD */ 1933 td->itd_flags = htole32( 1934 OHCI_ITD_NOCC | 1935 OHCI_ITD_SET_SF(xfer->pipe->isoc_next) | 1936 OHCI_ITD_NOINTR | 1937 OHCI_ITD_SET_FC(ncur)); 1938 1939 td->frames = ncur; 1940 xfer->pipe->isoc_next += ncur; 1941 1942 if (length == 0) { 1943 /* all zero */ 1944 td->itd_bp0 = 0; 1945 td->itd_be = ~0; 1946 1947 while (ncur--) { 1948 td->itd_offset[ncur] = 1949 htole16(OHCI_ITD_MK_OFFS(0)); 1950 } 1951 } else { 1952 usb2_get_page(xfer->frbuffers, buf_offset - length, &buf_res); 1953 length = OHCI_PAGE_MASK(buf_res.physaddr); 1954 buf_res.physaddr = 1955 OHCI_PAGE(buf_res.physaddr); 1956 td->itd_bp0 = htole32(buf_res.physaddr); 1957 usb2_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 1958 td->itd_be = htole32(buf_res.physaddr); 1959 1960 while (ncur--) { 1961 itd_offset[ncur] += length; 1962 itd_offset[ncur] = 1963 OHCI_ITD_MK_OFFS(itd_offset[ncur]); 1964 td->itd_offset[ncur] = 1965 htole16(itd_offset[ncur]); 1966 } 1967 } 1968 ncur = 0; 1969 length = 0; 1970 td_last = td; 1971 td = td->obj_next; 1972 1973 if (td) { 1974 /* link the last TD with the next one */ 1975 td_last->itd_next = td->itd_self; 1976 } 1977 usb2_pc_cpu_flush(td_last->page_cache); 1978 } 1979 } 1980 1981 /* update the last TD */ 1982 td_last->itd_flags &= ~htole32(OHCI_ITD_NOINTR); 1983 td_last->itd_flags |= htole32(OHCI_ITD_SET_DI(0)); 1984 td_last->itd_next = 0; 1985 1986 usb2_pc_cpu_flush(td_last->page_cache); 1987 1988 xfer->td_transfer_last = td_last; 1989 1990#if USB_DEBUG 1991 if (ohcidebug > 8) { 1992 DPRINTF("data before transfer:\n"); 1993 ohci_dump_itds(xfer->td_transfer_first); 1994 } 1995#endif 1996 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1997 1998 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) 1999 ed_flags = (OHCI_ED_DIR_IN | OHCI_ED_FORMAT_ISO); 2000 else 2001 ed_flags = (OHCI_ED_DIR_OUT | OHCI_ED_FORMAT_ISO); 2002 2003 ed_flags |= (OHCI_ED_SET_FA(xfer->address) | 2004 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpoint)) | 2005 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 2006 2007 if (xfer->udev->speed == USB_SPEED_LOW) { 2008 ed_flags |= OHCI_ED_SPEED; 2009 } 2010 ed->ed_flags = htole32(ed_flags); 2011 2012 usb2_pc_cpu_flush(ed->page_cache); 2013 2014 td = xfer->td_transfer_first; 2015 2016 ed->ed_headp = td->itd_self; 2017 2018 /* isochronous transfers are not affected by suspend / resume */ 2019 2020 OHCI_APPEND_QH(ed, sc->sc_isoc_p_last); 2021} 2022 2023static void 2024ohci_device_isoc_start(struct usb2_xfer *xfer) 2025{ 2026 /* put transfer on interrupt queue */ 2027 ohci_transfer_intr_enqueue(xfer); 2028} 2029 2030struct usb2_pipe_methods ohci_device_isoc_methods = 2031{ 2032 .open = ohci_device_isoc_open, 2033 .close = ohci_device_isoc_close, 2034 .enter = ohci_device_isoc_enter, 2035 .start = ohci_device_isoc_start, 2036 .enter_is_cancelable = 1, 2037 .start_is_cancelable = 1, 2038}; 2039 2040/*------------------------------------------------------------------------* 2041 * ohci root control support 2042 *------------------------------------------------------------------------* 2043 * simulate a hardware hub by handling 2044 * all the necessary requests 2045 *------------------------------------------------------------------------*/ 2046 2047static void 2048ohci_root_ctrl_open(struct usb2_xfer *xfer) 2049{ 2050 return; 2051} 2052 2053static void 2054ohci_root_ctrl_close(struct usb2_xfer *xfer) 2055{ 2056 ohci_softc_t *sc = xfer->usb2_sc; 2057 2058 if (sc->sc_root_ctrl.xfer == xfer) { 2059 sc->sc_root_ctrl.xfer = NULL; 2060 } 2061 ohci_device_done(xfer, USB_ERR_CANCELLED); 2062} 2063 2064/* data structures and routines 2065 * to emulate the root hub: 2066 */ 2067static const 2068struct usb2_device_descriptor ohci_devd = 2069{ 2070 sizeof(struct usb2_device_descriptor), 2071 UDESC_DEVICE, /* type */ 2072 {0x00, 0x01}, /* USB version */ 2073 UDCLASS_HUB, /* class */ 2074 UDSUBCLASS_HUB, /* subclass */ 2075 UDPROTO_FSHUB, /* protocol */ 2076 64, /* max packet */ 2077 {0}, {0}, {0x00, 0x01}, /* device id */ 2078 1, 2, 0, /* string indicies */ 2079 1 /* # of configurations */ 2080}; 2081 2082static const 2083struct ohci_config_desc ohci_confd = 2084{ 2085 .confd = { 2086 .bLength = sizeof(struct usb2_config_descriptor), 2087 .bDescriptorType = UDESC_CONFIG, 2088 .wTotalLength[0] = sizeof(ohci_confd), 2089 .bNumInterface = 1, 2090 .bConfigurationValue = 1, 2091 .iConfiguration = 0, 2092 .bmAttributes = UC_SELF_POWERED, 2093 .bMaxPower = 0, /* max power */ 2094 }, 2095 2096 .ifcd = { 2097 .bLength = sizeof(struct usb2_interface_descriptor), 2098 .bDescriptorType = UDESC_INTERFACE, 2099 .bNumEndpoints = 1, 2100 .bInterfaceClass = UICLASS_HUB, 2101 .bInterfaceSubClass = UISUBCLASS_HUB, 2102 .bInterfaceProtocol = UIPROTO_FSHUB, 2103 }, 2104 2105 .endpd = { 2106 .bLength = sizeof(struct usb2_endpoint_descriptor), 2107 .bDescriptorType = UDESC_ENDPOINT, 2108 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2109 .bmAttributes = UE_INTERRUPT, 2110 .wMaxPacketSize[0] = 32,/* max packet (255 ports) */ 2111 .bInterval = 255, 2112 }, 2113}; 2114 2115static const 2116struct usb2_hub_descriptor ohci_hubd = 2117{ 2118 0, /* dynamic length */ 2119 UDESC_HUB, 2120 0, 2121 {0, 0}, 2122 0, 2123 0, 2124 {0}, 2125}; 2126 2127static void 2128ohci_root_ctrl_enter(struct usb2_xfer *xfer) 2129{ 2130 return; 2131} 2132 2133static void 2134ohci_root_ctrl_start(struct usb2_xfer *xfer) 2135{ 2136 ohci_softc_t *sc = xfer->usb2_sc; 2137 2138 sc->sc_root_ctrl.xfer = xfer; 2139 2140 usb2_config_td_queue_command 2141 (&sc->sc_config_td, NULL, &ohci_root_ctrl_task, 0, 0); 2142} 2143 2144static void 2145ohci_root_ctrl_task(struct ohci_softc *sc, 2146 struct ohci_config_copy *cc, uint16_t refcount) 2147{ 2148 ohci_root_ctrl_poll(sc); 2149} 2150 2151static void 2152ohci_root_ctrl_done(struct usb2_xfer *xfer, 2153 struct usb2_sw_transfer *std) 2154{ 2155 ohci_softc_t *sc = xfer->usb2_sc; 2156 char *ptr; 2157 uint32_t port; 2158 uint32_t v; 2159 uint16_t value; 2160 uint16_t index; 2161 uint8_t l; 2162 uint8_t use_polling; 2163 2164 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2165 2166 if (std->state != USB_SW_TR_SETUP) { 2167 if (std->state == USB_SW_TR_PRE_CALLBACK) { 2168 /* transfer transferred */ 2169 ohci_device_done(xfer, std->err); 2170 } 2171 goto done; 2172 } 2173 /* buffer reset */ 2174 std->ptr = sc->sc_hub_desc.temp; 2175 std->len = 0; 2176 2177 value = UGETW(std->req.wValue); 2178 index = UGETW(std->req.wIndex); 2179 2180 use_polling = mtx_owned(xfer->xfer_mtx) ? 1 : 0; 2181 2182 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2183 "wValue=0x%04x wIndex=0x%04x\n", 2184 std->req.bmRequestType, std->req.bRequest, 2185 UGETW(std->req.wLength), value, index); 2186 2187#define C(x,y) ((x) | ((y) << 8)) 2188 switch (C(std->req.bRequest, std->req.bmRequestType)) { 2189 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2190 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2191 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2192 /* 2193 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2194 * for the integrated root hub. 2195 */ 2196 break; 2197 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2198 std->len = 1; 2199 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2200 break; 2201 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2202 switch (value >> 8) { 2203 case UDESC_DEVICE: 2204 if ((value & 0xff) != 0) { 2205 std->err = USB_ERR_IOERROR; 2206 goto done; 2207 } 2208 std->len = sizeof(ohci_devd); 2209 sc->sc_hub_desc.devd = ohci_devd; 2210 break; 2211 2212 case UDESC_CONFIG: 2213 if ((value & 0xff) != 0) { 2214 std->err = USB_ERR_IOERROR; 2215 goto done; 2216 } 2217 std->len = sizeof(ohci_confd); 2218 std->ptr = USB_ADD_BYTES(&ohci_confd, 0); 2219 break; 2220 2221 case UDESC_STRING: 2222 switch (value & 0xff) { 2223 case 0: /* Language table */ 2224 ptr = "\001"; 2225 break; 2226 2227 case 1: /* Vendor */ 2228 ptr = sc->sc_vendor; 2229 break; 2230 2231 case 2: /* Product */ 2232 ptr = "OHCI root HUB"; 2233 break; 2234 2235 default: 2236 ptr = ""; 2237 break; 2238 } 2239 2240 std->len = usb2_make_str_desc 2241 (sc->sc_hub_desc.temp, 2242 sizeof(sc->sc_hub_desc.temp), 2243 ptr); 2244 break; 2245 2246 default: 2247 std->err = USB_ERR_IOERROR; 2248 goto done; 2249 } 2250 break; 2251 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2252 std->len = 1; 2253 sc->sc_hub_desc.temp[0] = 0; 2254 break; 2255 case C(UR_GET_STATUS, UT_READ_DEVICE): 2256 std->len = 2; 2257 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2258 break; 2259 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2260 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2261 std->len = 2; 2262 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2263 break; 2264 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2265 if (value >= USB_MAX_DEVICES) { 2266 std->err = USB_ERR_IOERROR; 2267 goto done; 2268 } 2269 sc->sc_addr = value; 2270 break; 2271 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2272 if ((value != 0) && (value != 1)) { 2273 std->err = USB_ERR_IOERROR; 2274 goto done; 2275 } 2276 sc->sc_conf = value; 2277 break; 2278 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2279 break; 2280 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2281 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2282 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2283 std->err = USB_ERR_IOERROR; 2284 goto done; 2285 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2286 break; 2287 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2288 break; 2289 /* Hub requests */ 2290 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2291 break; 2292 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2293 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE " 2294 "port=%d feature=%d\n", 2295 index, value); 2296 if ((index < 1) || 2297 (index > sc->sc_noport)) { 2298 std->err = USB_ERR_IOERROR; 2299 goto done; 2300 } 2301 port = OHCI_RH_PORT_STATUS(index); 2302 switch (value) { 2303 case UHF_PORT_ENABLE: 2304 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2305 break; 2306 case UHF_PORT_SUSPEND: 2307 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2308 break; 2309 case UHF_PORT_POWER: 2310 /* Yes, writing to the LOW_SPEED bit clears power. */ 2311 OWRITE4(sc, port, UPS_LOW_SPEED); 2312 break; 2313 case UHF_C_PORT_CONNECTION: 2314 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2315 break; 2316 case UHF_C_PORT_ENABLE: 2317 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2318 break; 2319 case UHF_C_PORT_SUSPEND: 2320 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2321 break; 2322 case UHF_C_PORT_OVER_CURRENT: 2323 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2324 break; 2325 case UHF_C_PORT_RESET: 2326 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2327 break; 2328 default: 2329 std->err = USB_ERR_IOERROR; 2330 goto done; 2331 } 2332 switch (value) { 2333 case UHF_C_PORT_CONNECTION: 2334 case UHF_C_PORT_ENABLE: 2335 case UHF_C_PORT_SUSPEND: 2336 case UHF_C_PORT_OVER_CURRENT: 2337 case UHF_C_PORT_RESET: 2338 /* enable RHSC interrupt if condition is cleared. */ 2339 if ((OREAD4(sc, port) >> 16) == 0) 2340 ohci_rhsc_enable(sc); 2341 break; 2342 default: 2343 break; 2344 } 2345 break; 2346 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2347 if ((value & 0xff) != 0) { 2348 std->err = USB_ERR_IOERROR; 2349 goto done; 2350 } 2351 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2352 2353 sc->sc_hub_desc.hubd = ohci_hubd; 2354 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 2355 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, 2356 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2357 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2358 /* XXX overcurrent */ 2359 ); 2360 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2361 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2362 2363 for (l = 0; l < sc->sc_noport; l++) { 2364 if (v & 1) { 2365 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] |= (1 << (l % 8)); 2366 } 2367 v >>= 1; 2368 } 2369 sc->sc_hub_desc.hubd.bDescLength = 2370 8 + ((sc->sc_noport + 7) / 8); 2371 std->len = sc->sc_hub_desc.hubd.bDescLength; 2372 break; 2373 2374 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2375 std->len = 16; 2376 bzero(sc->sc_hub_desc.temp, 16); 2377 break; 2378 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2379 DPRINTFN(9, "get port status i=%d\n", 2380 index); 2381 if ((index < 1) || 2382 (index > sc->sc_noport)) { 2383 std->err = USB_ERR_IOERROR; 2384 goto done; 2385 } 2386 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2387 DPRINTFN(9, "port status=0x%04x\n", v); 2388 USETW(sc->sc_hub_desc.ps.wPortStatus, v); 2389 USETW(sc->sc_hub_desc.ps.wPortChange, v >> 16); 2390 std->len = sizeof(sc->sc_hub_desc.ps); 2391 break; 2392 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2393 std->err = USB_ERR_IOERROR; 2394 goto done; 2395 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2396 break; 2397 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2398 if ((index < 1) || 2399 (index > sc->sc_noport)) { 2400 std->err = USB_ERR_IOERROR; 2401 goto done; 2402 } 2403 port = OHCI_RH_PORT_STATUS(index); 2404 switch (value) { 2405 case UHF_PORT_ENABLE: 2406 OWRITE4(sc, port, UPS_PORT_ENABLED); 2407 break; 2408 case UHF_PORT_SUSPEND: 2409 OWRITE4(sc, port, UPS_SUSPEND); 2410 break; 2411 case UHF_PORT_RESET: 2412 DPRINTFN(6, "reset port %d\n", index); 2413 OWRITE4(sc, port, UPS_RESET); 2414 for (v = 0;; v++) { 2415 if (v < 12) { 2416 if (use_polling) { 2417 /* polling */ 2418 DELAY(USB_PORT_ROOT_RESET_DELAY * 1000); 2419 } else { 2420 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 2421 USB_PORT_ROOT_RESET_DELAY); 2422 } 2423 2424 if ((OREAD4(sc, port) & UPS_RESET) == 0) { 2425 break; 2426 } 2427 } else { 2428 std->err = USB_ERR_TIMEOUT; 2429 goto done; 2430 } 2431 } 2432 DPRINTFN(9, "ohci port %d reset, status = 0x%04x\n", 2433 index, OREAD4(sc, port)); 2434 break; 2435 case UHF_PORT_POWER: 2436 DPRINTFN(3, "set port power %d\n", index); 2437 OWRITE4(sc, port, UPS_PORT_POWER); 2438 break; 2439 default: 2440 std->err = USB_ERR_IOERROR; 2441 goto done; 2442 } 2443 break; 2444 default: 2445 std->err = USB_ERR_IOERROR; 2446 goto done; 2447 } 2448done: 2449 return; 2450} 2451 2452static void 2453ohci_root_ctrl_poll(struct ohci_softc *sc) 2454{ 2455 usb2_sw_transfer(&sc->sc_root_ctrl, 2456 &ohci_root_ctrl_done); 2457} 2458 2459struct usb2_pipe_methods ohci_root_ctrl_methods = 2460{ 2461 .open = ohci_root_ctrl_open, 2462 .close = ohci_root_ctrl_close, 2463 .enter = ohci_root_ctrl_enter, 2464 .start = ohci_root_ctrl_start, 2465 .enter_is_cancelable = 1, 2466 .start_is_cancelable = 0, 2467}; 2468 2469/*------------------------------------------------------------------------* 2470 * ohci root interrupt support 2471 *------------------------------------------------------------------------*/ 2472static void 2473ohci_root_intr_open(struct usb2_xfer *xfer) 2474{ 2475 return; 2476} 2477 2478static void 2479ohci_root_intr_close(struct usb2_xfer *xfer) 2480{ 2481 ohci_softc_t *sc = xfer->usb2_sc; 2482 2483 if (sc->sc_root_intr.xfer == xfer) { 2484 sc->sc_root_intr.xfer = NULL; 2485 } 2486 ohci_device_done(xfer, USB_ERR_CANCELLED); 2487} 2488 2489static void 2490ohci_root_intr_enter(struct usb2_xfer *xfer) 2491{ 2492 return; 2493} 2494 2495static void 2496ohci_root_intr_start(struct usb2_xfer *xfer) 2497{ 2498 ohci_softc_t *sc = xfer->usb2_sc; 2499 2500 sc->sc_root_intr.xfer = xfer; 2501} 2502 2503struct usb2_pipe_methods ohci_root_intr_methods = 2504{ 2505 .open = ohci_root_intr_open, 2506 .close = ohci_root_intr_close, 2507 .enter = ohci_root_intr_enter, 2508 .start = ohci_root_intr_start, 2509 .enter_is_cancelable = 1, 2510 .start_is_cancelable = 1, 2511}; 2512 2513static void 2514ohci_xfer_setup(struct usb2_setup_params *parm) 2515{ 2516 struct usb2_page_search page_info; 2517 struct usb2_page_cache *pc; 2518 ohci_softc_t *sc; 2519 struct usb2_xfer *xfer; 2520 void *last_obj; 2521 uint32_t ntd; 2522 uint32_t nitd; 2523 uint32_t nqh; 2524 uint32_t n; 2525 2526 sc = OHCI_BUS2SC(parm->udev->bus); 2527 xfer = parm->curr_xfer; 2528 2529 /* 2530 * setup xfer 2531 */ 2532 xfer->usb2_sc = sc; 2533 2534 parm->hc_max_packet_size = 0x500; 2535 parm->hc_max_packet_count = 1; 2536 parm->hc_max_frame_size = OHCI_PAGE_SIZE; 2537 2538 /* 2539 * calculate ntd and nqh 2540 */ 2541 if (parm->methods == &ohci_device_ctrl_methods) { 2542 xfer->flags_int.bdma_enable = 1; 2543 2544 usb2_transfer_setup_sub(parm); 2545 2546 nitd = 0; 2547 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2548 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 2549 nqh = 1; 2550 2551 } else if (parm->methods == &ohci_device_bulk_methods) { 2552 xfer->flags_int.bdma_enable = 1; 2553 2554 usb2_transfer_setup_sub(parm); 2555 2556 nitd = 0; 2557 ntd = ((2 * xfer->nframes) 2558 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 2559 nqh = 1; 2560 2561 } else if (parm->methods == &ohci_device_intr_methods) { 2562 xfer->flags_int.bdma_enable = 1; 2563 2564 usb2_transfer_setup_sub(parm); 2565 2566 nitd = 0; 2567 ntd = ((2 * xfer->nframes) 2568 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 2569 nqh = 1; 2570 2571 } else if (parm->methods == &ohci_device_isoc_methods) { 2572 xfer->flags_int.bdma_enable = 1; 2573 2574 usb2_transfer_setup_sub(parm); 2575 2576 nitd = ((xfer->max_data_length / OHCI_PAGE_SIZE) + 2577 ((xfer->nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET) + 2578 1 /* EXTRA */ ); 2579 ntd = 0; 2580 nqh = 1; 2581 2582 } else { 2583 2584 usb2_transfer_setup_sub(parm); 2585 2586 nitd = 0; 2587 ntd = 0; 2588 nqh = 0; 2589 } 2590 2591alloc_dma_set: 2592 2593 if (parm->err) { 2594 return; 2595 } 2596 last_obj = NULL; 2597 2598 if (usb2_transfer_setup_sub_malloc( 2599 parm, &pc, sizeof(ohci_td_t), 2600 OHCI_TD_ALIGN, ntd)) { 2601 parm->err = USB_ERR_NOMEM; 2602 return; 2603 } 2604 if (parm->buf) { 2605 for (n = 0; n != ntd; n++) { 2606 ohci_td_t *td; 2607 2608 usb2_get_page(pc + n, 0, &page_info); 2609 2610 td = page_info.buffer; 2611 2612 /* init TD */ 2613 td->td_self = htole32(page_info.physaddr); 2614 td->obj_next = last_obj; 2615 td->page_cache = pc + n; 2616 2617 last_obj = td; 2618 2619 usb2_pc_cpu_flush(pc + n); 2620 } 2621 } 2622 if (usb2_transfer_setup_sub_malloc( 2623 parm, &pc, sizeof(ohci_itd_t), 2624 OHCI_ITD_ALIGN, nitd)) { 2625 parm->err = USB_ERR_NOMEM; 2626 return; 2627 } 2628 if (parm->buf) { 2629 for (n = 0; n != nitd; n++) { 2630 ohci_itd_t *itd; 2631 2632 usb2_get_page(pc + n, 0, &page_info); 2633 2634 itd = page_info.buffer; 2635 2636 /* init TD */ 2637 itd->itd_self = htole32(page_info.physaddr); 2638 itd->obj_next = last_obj; 2639 itd->page_cache = pc + n; 2640 2641 last_obj = itd; 2642 2643 usb2_pc_cpu_flush(pc + n); 2644 } 2645 } 2646 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2647 2648 last_obj = NULL; 2649 2650 if (usb2_transfer_setup_sub_malloc( 2651 parm, &pc, sizeof(ohci_ed_t), 2652 OHCI_ED_ALIGN, nqh)) { 2653 parm->err = USB_ERR_NOMEM; 2654 return; 2655 } 2656 if (parm->buf) { 2657 for (n = 0; n != nqh; n++) { 2658 ohci_ed_t *ed; 2659 2660 usb2_get_page(pc + n, 0, &page_info); 2661 2662 ed = page_info.buffer; 2663 2664 /* init QH */ 2665 ed->ed_self = htole32(page_info.physaddr); 2666 ed->obj_next = last_obj; 2667 ed->page_cache = pc + n; 2668 2669 last_obj = ed; 2670 2671 usb2_pc_cpu_flush(pc + n); 2672 } 2673 } 2674 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 2675 2676 if (!xfer->flags_int.curr_dma_set) { 2677 xfer->flags_int.curr_dma_set = 1; 2678 goto alloc_dma_set; 2679 } 2680} 2681 2682static void 2683ohci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2684 struct usb2_pipe *pipe) 2685{ 2686 ohci_softc_t *sc = OHCI_BUS2SC(udev->bus); 2687 2688 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2689 pipe, udev->address, 2690 edesc->bEndpointAddress, udev->flags.usb2_mode, 2691 sc->sc_addr); 2692 2693 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2694 /* not supported */ 2695 return; 2696 } 2697 if (udev->device_index == sc->sc_addr) { 2698 switch (edesc->bEndpointAddress) { 2699 case USB_CONTROL_ENDPOINT: 2700 pipe->methods = &ohci_root_ctrl_methods; 2701 break; 2702 case UE_DIR_IN | OHCI_INTR_ENDPT: 2703 pipe->methods = &ohci_root_intr_methods; 2704 break; 2705 default: 2706 /* do nothing */ 2707 break; 2708 } 2709 } else { 2710 switch (edesc->bmAttributes & UE_XFERTYPE) { 2711 case UE_CONTROL: 2712 pipe->methods = &ohci_device_ctrl_methods; 2713 break; 2714 case UE_INTERRUPT: 2715 pipe->methods = &ohci_device_intr_methods; 2716 break; 2717 case UE_ISOCHRONOUS: 2718 if (udev->speed == USB_SPEED_FULL) { 2719 pipe->methods = &ohci_device_isoc_methods; 2720 } 2721 break; 2722 case UE_BULK: 2723 if (udev->speed != USB_SPEED_LOW) { 2724 pipe->methods = &ohci_device_bulk_methods; 2725 } 2726 break; 2727 default: 2728 /* do nothing */ 2729 break; 2730 } 2731 } 2732} 2733 2734static void 2735ohci_xfer_unsetup(struct usb2_xfer *xfer) 2736{ 2737 return; 2738} 2739 2740static void 2741ohci_get_dma_delay(struct usb2_bus *bus, uint32_t *pus) 2742{ 2743 /* 2744 * Wait until hardware has finished any possible use of the 2745 * transfer descriptor(s) and QH 2746 */ 2747 *pus = (1125); /* microseconds */ 2748} 2749 2750static void 2751ohci_device_resume(struct usb2_device *udev) 2752{ 2753 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2754 struct usb2_xfer *xfer; 2755 struct usb2_pipe_methods *methods; 2756 ohci_ed_t *ed; 2757 2758 DPRINTF("\n"); 2759 2760 USB_BUS_LOCK(udev->bus); 2761 2762 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2763 2764 if (xfer->udev == udev) { 2765 2766 methods = xfer->pipe->methods; 2767 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2768 2769 if (methods == &ohci_device_bulk_methods) { 2770 OHCI_APPEND_QH(ed, sc->sc_bulk_p_last); 2771 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2772 } 2773 if (methods == &ohci_device_ctrl_methods) { 2774 OHCI_APPEND_QH(ed, sc->sc_ctrl_p_last); 2775 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2776 } 2777 if (methods == &ohci_device_intr_methods) { 2778 OHCI_APPEND_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2779 } 2780 } 2781 } 2782 2783 USB_BUS_UNLOCK(udev->bus); 2784 2785 return; 2786} 2787 2788static void 2789ohci_device_suspend(struct usb2_device *udev) 2790{ 2791 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2792 struct usb2_xfer *xfer; 2793 struct usb2_pipe_methods *methods; 2794 ohci_ed_t *ed; 2795 2796 DPRINTF("\n"); 2797 2798 USB_BUS_LOCK(udev->bus); 2799 2800 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2801 2802 if (xfer->udev == udev) { 2803 2804 methods = xfer->pipe->methods; 2805 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2806 2807 if (methods == &ohci_device_bulk_methods) { 2808 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 2809 } 2810 if (methods == &ohci_device_ctrl_methods) { 2811 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 2812 } 2813 if (methods == &ohci_device_intr_methods) { 2814 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2815 } 2816 } 2817 } 2818 2819 USB_BUS_UNLOCK(udev->bus); 2820 2821 return; 2822} 2823 2824static void 2825ohci_set_hw_power(struct usb2_bus *bus) 2826{ 2827 struct ohci_softc *sc = OHCI_BUS2SC(bus); 2828 uint32_t temp; 2829 uint32_t flags; 2830 2831 DPRINTF("\n"); 2832 2833 USB_BUS_LOCK(bus); 2834 2835 flags = bus->hw_power_state; 2836 2837 temp = OREAD4(sc, OHCI_CONTROL); 2838 temp &= ~(OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE); 2839 2840 if (flags & USB_HW_POWER_CONTROL) 2841 temp |= OHCI_CLE; 2842 2843 if (flags & USB_HW_POWER_BULK) 2844 temp |= OHCI_BLE; 2845 2846 if (flags & USB_HW_POWER_INTERRUPT) 2847 temp |= OHCI_PLE; 2848 2849 if (flags & USB_HW_POWER_ISOC) 2850 temp |= OHCI_IE | OHCI_PLE; 2851 2852 OWRITE4(sc, OHCI_CONTROL, temp); 2853 2854 USB_BUS_UNLOCK(bus); 2855 2856 return; 2857} 2858 2859struct usb2_bus_methods ohci_bus_methods = 2860{ 2861 .pipe_init = ohci_pipe_init, 2862 .xfer_setup = ohci_xfer_setup, 2863 .xfer_unsetup = ohci_xfer_unsetup, 2864 .do_poll = ohci_do_poll, 2865 .get_dma_delay = ohci_get_dma_delay, 2866 .device_resume = ohci_device_resume, 2867 .device_suspend = ohci_device_suspend, 2868 .set_hw_power = ohci_set_hw_power, 2869}; 2870