ohci.c revision 193644
1/*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/usb/controller/ohci.c 193644 2009-06-07 19:41:11Z thompsa $"); 30 31/* 32 * USB Open Host Controller driver. 33 * 34 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 35 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 36 */ 37 38#include <dev/usb/usb.h> 39#include <dev/usb/usb_mfunc.h> 40#include <dev/usb/usb_error.h> 41 42#define USB_DEBUG_VAR ohcidebug 43 44#include <dev/usb/usb_core.h> 45#include <dev/usb/usb_debug.h> 46#include <dev/usb/usb_busdma.h> 47#include <dev/usb/usb_process.h> 48#include <dev/usb/usb_transfer.h> 49#include <dev/usb/usb_device.h> 50#include <dev/usb/usb_hub.h> 51#include <dev/usb/usb_util.h> 52 53#include <dev/usb/usb_controller.h> 54#include <dev/usb/usb_bus.h> 55#include <dev/usb/controller/ohci.h> 56 57#define OHCI_BUS2SC(bus) \ 58 ((ohci_softc_t *)(((uint8_t *)(bus)) - \ 59 ((uint8_t *)&(((ohci_softc_t *)0)->sc_bus)))) 60 61#if USB_DEBUG 62static int ohcidebug = 0; 63 64SYSCTL_NODE(_hw_usb, OID_AUTO, ohci, CTLFLAG_RW, 0, "USB ohci"); 65SYSCTL_INT(_hw_usb_ohci, OID_AUTO, debug, CTLFLAG_RW, 66 &ohcidebug, 0, "ohci debug level"); 67static void ohci_dumpregs(ohci_softc_t *); 68static void ohci_dump_tds(ohci_td_t *); 69static uint8_t ohci_dump_td(ohci_td_t *); 70static void ohci_dump_ed(ohci_ed_t *); 71static uint8_t ohci_dump_itd(ohci_itd_t *); 72static void ohci_dump_itds(ohci_itd_t *); 73 74#endif 75 76#define OBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 77 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 78#define OWRITE1(sc, r, x) \ 79 do { OBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 80#define OWRITE2(sc, r, x) \ 81 do { OBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 82#define OWRITE4(sc, r, x) \ 83 do { OBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 84#define OREAD1(sc, r) (OBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 85#define OREAD2(sc, r) (OBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 86#define OREAD4(sc, r) (OBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 87 88#define OHCI_INTR_ENDPT 1 89 90extern struct usb_bus_methods ohci_bus_methods; 91extern struct usb_pipe_methods ohci_device_bulk_methods; 92extern struct usb_pipe_methods ohci_device_ctrl_methods; 93extern struct usb_pipe_methods ohci_device_intr_methods; 94extern struct usb_pipe_methods ohci_device_isoc_methods; 95 96static void ohci_do_poll(struct usb_bus *bus); 97static void ohci_device_done(struct usb_xfer *xfer, usb_error_t error); 98static void ohci_timeout(void *arg); 99static uint8_t ohci_check_transfer(struct usb_xfer *xfer); 100static void ohci_root_intr(ohci_softc_t *sc); 101 102struct ohci_std_temp { 103 struct usb_page_cache *pc; 104 ohci_td_t *td; 105 ohci_td_t *td_next; 106 uint32_t average; 107 uint32_t td_flags; 108 uint32_t len; 109 uint16_t max_frame_size; 110 uint8_t shortpkt; 111 uint8_t setup_alt_next; 112 uint8_t last_frame; 113}; 114 115static struct ohci_hcca * 116ohci_get_hcca(ohci_softc_t *sc) 117{ 118 usb2_pc_cpu_invalidate(&sc->sc_hw.hcca_pc); 119 return (sc->sc_hcca_p); 120} 121 122void 123ohci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 124{ 125 struct ohci_softc *sc = OHCI_BUS2SC(bus); 126 uint32_t i; 127 128 cb(bus, &sc->sc_hw.hcca_pc, &sc->sc_hw.hcca_pg, 129 sizeof(ohci_hcca_t), OHCI_HCCA_ALIGN); 130 131 cb(bus, &sc->sc_hw.ctrl_start_pc, &sc->sc_hw.ctrl_start_pg, 132 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 133 134 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 135 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 136 137 cb(bus, &sc->sc_hw.isoc_start_pc, &sc->sc_hw.isoc_start_pg, 138 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 139 140 for (i = 0; i != OHCI_NO_EDS; i++) { 141 cb(bus, sc->sc_hw.intr_start_pc + i, sc->sc_hw.intr_start_pg + i, 142 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 143 } 144} 145 146static usb_error_t 147ohci_controller_init(ohci_softc_t *sc) 148{ 149 struct usb_page_search buf_res; 150 uint32_t i; 151 uint32_t ctl; 152 uint32_t ival; 153 uint32_t hcr; 154 uint32_t fm; 155 uint32_t per; 156 uint32_t desca; 157 158 /* Determine in what context we are running. */ 159 ctl = OREAD4(sc, OHCI_CONTROL); 160 if (ctl & OHCI_IR) { 161 /* SMM active, request change */ 162 DPRINTF("SMM active, request owner change\n"); 163 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_OCR); 164 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 165 usb2_pause_mtx(NULL, hz / 1000); 166 ctl = OREAD4(sc, OHCI_CONTROL); 167 } 168 if (ctl & OHCI_IR) { 169 device_printf(sc->sc_bus.bdev, 170 "SMM does not respond, resetting\n"); 171 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 172 goto reset; 173 } 174 } else { 175 DPRINTF("cold started\n"); 176reset: 177 /* controller was cold started */ 178 usb2_pause_mtx(NULL, 179 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 180 } 181 182 /* 183 * This reset should not be necessary according to the OHCI spec, but 184 * without it some controllers do not start. 185 */ 186 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 187 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 188 189 usb2_pause_mtx(NULL, 190 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 191 192 /* we now own the host controller and the bus has been reset */ 193 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL)); 194 195 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 196 /* nominal time for a reset is 10 us */ 197 for (i = 0; i < 10; i++) { 198 DELAY(10); 199 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 200 if (!hcr) { 201 break; 202 } 203 } 204 if (hcr) { 205 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 206 return (USB_ERR_IOERROR); 207 } 208#if USB_DEBUG 209 if (ohcidebug > 15) { 210 ohci_dumpregs(sc); 211 } 212#endif 213 214 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 215 216 /* set up HC registers */ 217 usb2_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 218 OWRITE4(sc, OHCI_HCCA, buf_res.physaddr); 219 220 usb2_get_page(&sc->sc_hw.ctrl_start_pc, 0, &buf_res); 221 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, buf_res.physaddr); 222 223 usb2_get_page(&sc->sc_hw.bulk_start_pc, 0, &buf_res); 224 OWRITE4(sc, OHCI_BULK_HEAD_ED, buf_res.physaddr); 225 226 /* disable all interrupts and then switch on all desired interrupts */ 227 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 228 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 229 /* switch on desired functional features */ 230 ctl = OREAD4(sc, OHCI_CONTROL); 231 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 232 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 233 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL; 234 /* And finally start it! */ 235 OWRITE4(sc, OHCI_CONTROL, ctl); 236 237 /* 238 * The controller is now OPERATIONAL. Set a some final 239 * registers that should be set earlier, but that the 240 * controller ignores when in the SUSPEND state. 241 */ 242 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 243 fm |= OHCI_FSMPS(ival) | ival; 244 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 245 per = OHCI_PERIODIC(ival); /* 90% periodic */ 246 OWRITE4(sc, OHCI_PERIODIC_START, per); 247 248 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 249 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 250 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 251 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 252 usb2_pause_mtx(NULL, 253 USB_MS_TO_TICKS(OHCI_ENABLE_POWER_DELAY)); 254 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 255 256 /* 257 * The AMD756 requires a delay before re-reading the register, 258 * otherwise it will occasionally report 0 ports. 259 */ 260 sc->sc_noport = 0; 261 for (i = 0; (i < 10) && (sc->sc_noport == 0); i++) { 262 usb2_pause_mtx(NULL, 263 USB_MS_TO_TICKS(OHCI_READ_DESC_DELAY)); 264 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 265 } 266 267#if USB_DEBUG 268 if (ohcidebug > 5) { 269 ohci_dumpregs(sc); 270 } 271#endif 272 return (USB_ERR_NORMAL_COMPLETION); 273} 274 275static struct ohci_ed * 276ohci_init_ed(struct usb_page_cache *pc) 277{ 278 struct usb_page_search buf_res; 279 struct ohci_ed *ed; 280 281 usb2_get_page(pc, 0, &buf_res); 282 283 ed = buf_res.buffer; 284 285 ed->ed_self = htole32(buf_res.physaddr); 286 ed->ed_flags = htole32(OHCI_ED_SKIP); 287 ed->page_cache = pc; 288 289 return (ed); 290} 291 292usb_error_t 293ohci_init(ohci_softc_t *sc) 294{ 295 struct usb_page_search buf_res; 296 uint16_t i; 297 uint16_t bit; 298 uint16_t x; 299 uint16_t y; 300 301 DPRINTF("start\n"); 302 303 sc->sc_eintrs = OHCI_NORMAL_INTRS; 304 305 /* 306 * Setup all ED's 307 */ 308 309 sc->sc_ctrl_p_last = 310 ohci_init_ed(&sc->sc_hw.ctrl_start_pc); 311 312 sc->sc_bulk_p_last = 313 ohci_init_ed(&sc->sc_hw.bulk_start_pc); 314 315 sc->sc_isoc_p_last = 316 ohci_init_ed(&sc->sc_hw.isoc_start_pc); 317 318 for (i = 0; i != OHCI_NO_EDS; i++) { 319 sc->sc_intr_p_last[i] = 320 ohci_init_ed(sc->sc_hw.intr_start_pc + i); 321 } 322 323 /* 324 * the QHs are arranged to give poll intervals that are 325 * powers of 2 times 1ms 326 */ 327 bit = OHCI_NO_EDS / 2; 328 while (bit) { 329 x = bit; 330 while (x & bit) { 331 ohci_ed_t *ed_x; 332 ohci_ed_t *ed_y; 333 334 y = (x ^ bit) | (bit / 2); 335 336 /* 337 * the next QH has half the poll interval 338 */ 339 ed_x = sc->sc_intr_p_last[x]; 340 ed_y = sc->sc_intr_p_last[y]; 341 342 ed_x->next = NULL; 343 ed_x->ed_next = ed_y->ed_self; 344 345 x++; 346 } 347 bit >>= 1; 348 } 349 350 if (1) { 351 352 ohci_ed_t *ed_int; 353 ohci_ed_t *ed_isc; 354 355 ed_int = sc->sc_intr_p_last[0]; 356 ed_isc = sc->sc_isoc_p_last; 357 358 /* the last (1ms) QH */ 359 ed_int->next = ed_isc; 360 ed_int->ed_next = ed_isc->ed_self; 361 } 362 usb2_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 363 364 sc->sc_hcca_p = buf_res.buffer; 365 366 /* 367 * Fill HCCA interrupt table. The bit reversal is to get 368 * the tree set up properly to spread the interrupts. 369 */ 370 for (i = 0; i != OHCI_NO_INTRS; i++) { 371 sc->sc_hcca_p->hcca_interrupt_table[i] = 372 sc->sc_intr_p_last[i | (OHCI_NO_EDS / 2)]->ed_self; 373 } 374 /* flush all cache into memory */ 375 376 usb2_bus_mem_flush_all(&sc->sc_bus, &ohci_iterate_hw_softc); 377 378 /* set up the bus struct */ 379 sc->sc_bus.methods = &ohci_bus_methods; 380 381 usb2_callout_init_mtx(&sc->sc_tmo_rhsc, &sc->sc_bus.bus_mtx, 0); 382 383#if USB_DEBUG 384 if (ohcidebug > 15) { 385 for (i = 0; i != OHCI_NO_EDS; i++) { 386 printf("ed#%d ", i); 387 ohci_dump_ed(sc->sc_intr_p_last[i]); 388 } 389 printf("iso "); 390 ohci_dump_ed(sc->sc_isoc_p_last); 391 } 392#endif 393 394 sc->sc_bus.usbrev = USB_REV_1_0; 395 396 if (ohci_controller_init(sc)) { 397 return (USB_ERR_INVAL); 398 } else { 399 /* catch any lost interrupts */ 400 ohci_do_poll(&sc->sc_bus); 401 return (USB_ERR_NORMAL_COMPLETION); 402 } 403} 404 405/* 406 * shut down the controller when the system is going down 407 */ 408void 409ohci_detach(struct ohci_softc *sc) 410{ 411 USB_BUS_LOCK(&sc->sc_bus); 412 413 usb2_callout_stop(&sc->sc_tmo_rhsc); 414 415 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 416 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 417 418 USB_BUS_UNLOCK(&sc->sc_bus); 419 420 /* XXX let stray task complete */ 421 usb2_pause_mtx(NULL, hz / 20); 422 423 usb2_callout_drain(&sc->sc_tmo_rhsc); 424} 425 426/* NOTE: suspend/resume is called from 427 * interrupt context and cannot sleep! 428 */ 429void 430ohci_suspend(ohci_softc_t *sc) 431{ 432 uint32_t ctl; 433 434 USB_BUS_LOCK(&sc->sc_bus); 435 436#if USB_DEBUG 437 DPRINTF("\n"); 438 if (ohcidebug > 2) { 439 ohci_dumpregs(sc); 440 } 441#endif 442 443 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 444 if (sc->sc_control == 0) { 445 /* 446 * Preserve register values, in case that APM BIOS 447 * does not recover them. 448 */ 449 sc->sc_control = ctl; 450 sc->sc_intre = OREAD4(sc, OHCI_INTERRUPT_ENABLE); 451 } 452 ctl |= OHCI_HCFS_SUSPEND; 453 OWRITE4(sc, OHCI_CONTROL, ctl); 454 455 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 456 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 457 458 USB_BUS_UNLOCK(&sc->sc_bus); 459} 460 461void 462ohci_resume(ohci_softc_t *sc) 463{ 464 uint32_t ctl; 465 466#if USB_DEBUG 467 DPRINTF("\n"); 468 if (ohcidebug > 2) { 469 ohci_dumpregs(sc); 470 } 471#endif 472 /* some broken BIOSes never initialize the Controller chip */ 473 ohci_controller_init(sc); 474 475 USB_BUS_LOCK(&sc->sc_bus); 476 if (sc->sc_intre) { 477 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, 478 sc->sc_intre & (OHCI_ALL_INTRS | OHCI_MIE)); 479 } 480 if (sc->sc_control) 481 ctl = sc->sc_control; 482 else 483 ctl = OREAD4(sc, OHCI_CONTROL); 484 ctl |= OHCI_HCFS_RESUME; 485 OWRITE4(sc, OHCI_CONTROL, ctl); 486 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 487 USB_MS_TO_TICKS(USB_RESUME_DELAY)); 488 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 489 OWRITE4(sc, OHCI_CONTROL, ctl); 490 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 491 USB_MS_TO_TICKS(USB_RESUME_RECOVERY)); 492 sc->sc_control = sc->sc_intre = 0; 493 494 USB_BUS_UNLOCK(&sc->sc_bus); 495 496 /* catch any lost interrupts */ 497 ohci_do_poll(&sc->sc_bus); 498} 499 500#if USB_DEBUG 501static void 502ohci_dumpregs(ohci_softc_t *sc) 503{ 504 struct ohci_hcca *hcca; 505 506 DPRINTF("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 507 OREAD4(sc, OHCI_REVISION), 508 OREAD4(sc, OHCI_CONTROL), 509 OREAD4(sc, OHCI_COMMAND_STATUS)); 510 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 511 OREAD4(sc, OHCI_INTERRUPT_STATUS), 512 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 513 OREAD4(sc, OHCI_INTERRUPT_DISABLE)); 514 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 515 OREAD4(sc, OHCI_HCCA), 516 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 517 OREAD4(sc, OHCI_CONTROL_HEAD_ED)); 518 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 519 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 520 OREAD4(sc, OHCI_BULK_HEAD_ED), 521 OREAD4(sc, OHCI_BULK_CURRENT_ED)); 522 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 523 OREAD4(sc, OHCI_DONE_HEAD), 524 OREAD4(sc, OHCI_FM_INTERVAL), 525 OREAD4(sc, OHCI_FM_REMAINING)); 526 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 527 OREAD4(sc, OHCI_FM_NUMBER), 528 OREAD4(sc, OHCI_PERIODIC_START), 529 OREAD4(sc, OHCI_LS_THRESHOLD)); 530 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x\n", 531 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 532 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 533 OREAD4(sc, OHCI_RH_STATUS)); 534 DPRINTF(" port1=0x%08x port2=0x%08x\n", 535 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 536 OREAD4(sc, OHCI_RH_PORT_STATUS(2))); 537 538 hcca = ohci_get_hcca(sc); 539 540 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x\n", 541 le32toh(hcca->hcca_frame_number), 542 le32toh(hcca->hcca_done_head)); 543} 544static void 545ohci_dump_tds(ohci_td_t *std) 546{ 547 for (; std; std = std->obj_next) { 548 if (ohci_dump_td(std)) { 549 break; 550 } 551 } 552} 553 554static uint8_t 555ohci_dump_td(ohci_td_t *std) 556{ 557 uint32_t td_flags; 558 uint8_t temp; 559 560 usb2_pc_cpu_invalidate(std->page_cache); 561 562 td_flags = le32toh(std->td_flags); 563 temp = (std->td_next == 0); 564 565 printf("TD(%p) at 0x%08x: %s%s%s%s%s delay=%d ec=%d " 566 "cc=%d\ncbp=0x%08x next=0x%08x be=0x%08x\n", 567 std, le32toh(std->td_self), 568 (td_flags & OHCI_TD_R) ? "-R" : "", 569 (td_flags & OHCI_TD_OUT) ? "-OUT" : "", 570 (td_flags & OHCI_TD_IN) ? "-IN" : "", 571 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_1) ? "-TOG1" : "", 572 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_0) ? "-TOG0" : "", 573 OHCI_TD_GET_DI(td_flags), 574 OHCI_TD_GET_EC(td_flags), 575 OHCI_TD_GET_CC(td_flags), 576 le32toh(std->td_cbp), 577 le32toh(std->td_next), 578 le32toh(std->td_be)); 579 580 return (temp); 581} 582 583static uint8_t 584ohci_dump_itd(ohci_itd_t *sitd) 585{ 586 uint32_t itd_flags; 587 uint16_t i; 588 uint8_t temp; 589 590 usb2_pc_cpu_invalidate(sitd->page_cache); 591 592 itd_flags = le32toh(sitd->itd_flags); 593 temp = (sitd->itd_next == 0); 594 595 printf("ITD(%p) at 0x%08x: sf=%d di=%d fc=%d cc=%d\n" 596 "bp0=0x%08x next=0x%08x be=0x%08x\n", 597 sitd, le32toh(sitd->itd_self), 598 OHCI_ITD_GET_SF(itd_flags), 599 OHCI_ITD_GET_DI(itd_flags), 600 OHCI_ITD_GET_FC(itd_flags), 601 OHCI_ITD_GET_CC(itd_flags), 602 le32toh(sitd->itd_bp0), 603 le32toh(sitd->itd_next), 604 le32toh(sitd->itd_be)); 605 for (i = 0; i < OHCI_ITD_NOFFSET; i++) { 606 printf("offs[%d]=0x%04x ", i, 607 (uint32_t)le16toh(sitd->itd_offset[i])); 608 } 609 printf("\n"); 610 611 return (temp); 612} 613 614static void 615ohci_dump_itds(ohci_itd_t *sitd) 616{ 617 for (; sitd; sitd = sitd->obj_next) { 618 if (ohci_dump_itd(sitd)) { 619 break; 620 } 621 } 622} 623 624static void 625ohci_dump_ed(ohci_ed_t *sed) 626{ 627 uint32_t ed_flags; 628 uint32_t ed_headp; 629 630 usb2_pc_cpu_invalidate(sed->page_cache); 631 632 ed_flags = le32toh(sed->ed_flags); 633 ed_headp = le32toh(sed->ed_headp); 634 635 printf("ED(%p) at 0x%08x: addr=%d endpt=%d maxp=%d flags=%s%s%s%s%s\n" 636 "tailp=0x%08x headflags=%s%s headp=0x%08x nexted=0x%08x\n", 637 sed, le32toh(sed->ed_self), 638 OHCI_ED_GET_FA(ed_flags), 639 OHCI_ED_GET_EN(ed_flags), 640 OHCI_ED_GET_MAXP(ed_flags), 641 (ed_flags & OHCI_ED_DIR_OUT) ? "-OUT" : "", 642 (ed_flags & OHCI_ED_DIR_IN) ? "-IN" : "", 643 (ed_flags & OHCI_ED_SPEED) ? "-LOWSPEED" : "", 644 (ed_flags & OHCI_ED_SKIP) ? "-SKIP" : "", 645 (ed_flags & OHCI_ED_FORMAT_ISO) ? "-ISO" : "", 646 le32toh(sed->ed_tailp), 647 (ed_headp & OHCI_HALTED) ? "-HALTED" : "", 648 (ed_headp & OHCI_TOGGLECARRY) ? "-CARRY" : "", 649 le32toh(sed->ed_headp), 650 le32toh(sed->ed_next)); 651} 652 653#endif 654 655static void 656ohci_transfer_intr_enqueue(struct usb_xfer *xfer) 657{ 658 /* check for early completion */ 659 if (ohci_check_transfer(xfer)) { 660 return; 661 } 662 /* put transfer on interrupt queue */ 663 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 664 665 /* start timeout, if any */ 666 if (xfer->timeout != 0) { 667 usb2_transfer_timeout_ms(xfer, &ohci_timeout, xfer->timeout); 668 } 669} 670 671#define OHCI_APPEND_QH(sed,last) (last) = _ohci_append_qh(sed,last) 672static ohci_ed_t * 673_ohci_append_qh(ohci_ed_t *sed, ohci_ed_t *last) 674{ 675 DPRINTFN(11, "%p to %p\n", sed, last); 676 677 if (sed->prev != NULL) { 678 /* should not happen */ 679 DPRINTFN(0, "ED already linked!\n"); 680 return (last); 681 } 682 /* (sc->sc_bus.bus_mtx) must be locked */ 683 684 sed->next = last->next; 685 sed->ed_next = last->ed_next; 686 sed->ed_tailp = 0; 687 688 sed->prev = last; 689 690 usb2_pc_cpu_flush(sed->page_cache); 691 692 /* 693 * the last->next->prev is never followed: sed->next->prev = sed; 694 */ 695 696 last->next = sed; 697 last->ed_next = sed->ed_self; 698 699 usb2_pc_cpu_flush(last->page_cache); 700 701 return (sed); 702} 703 704#define OHCI_REMOVE_QH(sed,last) (last) = _ohci_remove_qh(sed,last) 705static ohci_ed_t * 706_ohci_remove_qh(ohci_ed_t *sed, ohci_ed_t *last) 707{ 708 DPRINTFN(11, "%p from %p\n", sed, last); 709 710 /* (sc->sc_bus.bus_mtx) must be locked */ 711 712 /* only remove if not removed from a queue */ 713 if (sed->prev) { 714 715 sed->prev->next = sed->next; 716 sed->prev->ed_next = sed->ed_next; 717 718 usb2_pc_cpu_flush(sed->prev->page_cache); 719 720 if (sed->next) { 721 sed->next->prev = sed->prev; 722 usb2_pc_cpu_flush(sed->next->page_cache); 723 } 724 last = ((last == sed) ? sed->prev : last); 725 726 sed->prev = 0; 727 728 usb2_pc_cpu_flush(sed->page_cache); 729 } 730 return (last); 731} 732 733static void 734ohci_isoc_done(struct usb_xfer *xfer) 735{ 736 uint8_t nframes; 737 uint32_t *plen = xfer->frlengths; 738 volatile uint16_t *olen; 739 uint16_t len = 0; 740 ohci_itd_t *td = xfer->td_transfer_first; 741 742 while (1) { 743 if (td == NULL) { 744 panic("%s:%d: out of TD's\n", 745 __FUNCTION__, __LINE__); 746 } 747#if USB_DEBUG 748 if (ohcidebug > 5) { 749 DPRINTF("isoc TD\n"); 750 ohci_dump_itd(td); 751 } 752#endif 753 usb2_pc_cpu_invalidate(td->page_cache); 754 755 nframes = td->frames; 756 olen = &td->itd_offset[0]; 757 758 if (nframes > 8) { 759 nframes = 8; 760 } 761 while (nframes--) { 762 len = le16toh(*olen); 763 764 if ((len >> 12) == OHCI_CC_NOT_ACCESSED) { 765 len = 0; 766 } else { 767 len &= ((1 << 12) - 1); 768 } 769 770 if (len > *plen) { 771 len = 0;/* invalid length */ 772 } 773 *plen = len; 774 plen++; 775 olen++; 776 } 777 778 if (((void *)td) == xfer->td_transfer_last) { 779 break; 780 } 781 td = td->obj_next; 782 } 783 784 xfer->aframes = xfer->nframes; 785 ohci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 786} 787 788#if USB_DEBUG 789static const char *const 790 ohci_cc_strs[] = 791{ 792 "NO_ERROR", 793 "CRC", 794 "BIT_STUFFING", 795 "DATA_TOGGLE_MISMATCH", 796 797 "STALL", 798 "DEVICE_NOT_RESPONDING", 799 "PID_CHECK_FAILURE", 800 "UNEXPECTED_PID", 801 802 "DATA_OVERRUN", 803 "DATA_UNDERRUN", 804 "BUFFER_OVERRUN", 805 "BUFFER_UNDERRUN", 806 807 "reserved", 808 "reserved", 809 "NOT_ACCESSED", 810 "NOT_ACCESSED" 811}; 812 813#endif 814 815static usb_error_t 816ohci_non_isoc_done_sub(struct usb_xfer *xfer) 817{ 818 ohci_td_t *td; 819 ohci_td_t *td_alt_next; 820 uint32_t temp; 821 uint32_t phy_start; 822 uint32_t phy_end; 823 uint32_t td_flags; 824 uint16_t cc; 825 826 td = xfer->td_transfer_cache; 827 td_alt_next = td->alt_next; 828 td_flags = 0; 829 830 if (xfer->aframes != xfer->nframes) { 831 xfer->frlengths[xfer->aframes] = 0; 832 } 833 while (1) { 834 835 usb2_pc_cpu_invalidate(td->page_cache); 836 phy_start = le32toh(td->td_cbp); 837 td_flags = le32toh(td->td_flags); 838 cc = OHCI_TD_GET_CC(td_flags); 839 840 if (phy_start) { 841 /* 842 * short transfer - compute the number of remaining 843 * bytes in the hardware buffer: 844 */ 845 phy_end = le32toh(td->td_be); 846 temp = (OHCI_PAGE(phy_start ^ phy_end) ? 847 (OHCI_PAGE_SIZE + 1) : 0x0001); 848 temp += OHCI_PAGE_OFFSET(phy_end); 849 temp -= OHCI_PAGE_OFFSET(phy_start); 850 851 if (temp > td->len) { 852 /* guard against corruption */ 853 cc = OHCI_CC_STALL; 854 } else if (xfer->aframes != xfer->nframes) { 855 /* 856 * Sum up total transfer length 857 * in "frlengths[]": 858 */ 859 xfer->frlengths[xfer->aframes] += td->len - temp; 860 } 861 } else { 862 if (xfer->aframes != xfer->nframes) { 863 /* transfer was complete */ 864 xfer->frlengths[xfer->aframes] += td->len; 865 } 866 } 867 /* Check for last transfer */ 868 if (((void *)td) == xfer->td_transfer_last) { 869 td = NULL; 870 break; 871 } 872 /* Check transfer status */ 873 if (cc) { 874 /* the transfer is finished */ 875 td = NULL; 876 break; 877 } 878 /* Check for short transfer */ 879 if (phy_start) { 880 if (xfer->flags_int.short_frames_ok) { 881 /* follow alt next */ 882 td = td->alt_next; 883 } else { 884 /* the transfer is finished */ 885 td = NULL; 886 } 887 break; 888 } 889 td = td->obj_next; 890 891 if (td->alt_next != td_alt_next) { 892 /* this USB frame is complete */ 893 break; 894 } 895 } 896 897 /* update transfer cache */ 898 899 xfer->td_transfer_cache = td; 900 901 DPRINTFN(16, "error cc=%d (%s)\n", 902 cc, ohci_cc_strs[cc]); 903 904 return ((cc == 0) ? USB_ERR_NORMAL_COMPLETION : 905 (cc == OHCI_CC_STALL) ? USB_ERR_STALLED : USB_ERR_IOERROR); 906} 907 908static void 909ohci_non_isoc_done(struct usb_xfer *xfer) 910{ 911 usb_error_t err = 0; 912 913 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 914 xfer, xfer->endpoint); 915 916#if USB_DEBUG 917 if (ohcidebug > 10) { 918 ohci_dump_tds(xfer->td_transfer_first); 919 } 920#endif 921 922 /* reset scanner */ 923 924 xfer->td_transfer_cache = xfer->td_transfer_first; 925 926 if (xfer->flags_int.control_xfr) { 927 928 if (xfer->flags_int.control_hdr) { 929 930 err = ohci_non_isoc_done_sub(xfer); 931 } 932 xfer->aframes = 1; 933 934 if (xfer->td_transfer_cache == NULL) { 935 goto done; 936 } 937 } 938 while (xfer->aframes != xfer->nframes) { 939 940 err = ohci_non_isoc_done_sub(xfer); 941 xfer->aframes++; 942 943 if (xfer->td_transfer_cache == NULL) { 944 goto done; 945 } 946 } 947 948 if (xfer->flags_int.control_xfr && 949 !xfer->flags_int.control_act) { 950 951 err = ohci_non_isoc_done_sub(xfer); 952 } 953done: 954 ohci_device_done(xfer, err); 955} 956 957/*------------------------------------------------------------------------* 958 * ohci_check_transfer_sub 959 *------------------------------------------------------------------------*/ 960static void 961ohci_check_transfer_sub(struct usb_xfer *xfer) 962{ 963 ohci_td_t *td; 964 ohci_ed_t *ed; 965 uint32_t phy_start; 966 uint32_t td_flags; 967 uint32_t td_next; 968 uint16_t cc; 969 970 td = xfer->td_transfer_cache; 971 972 while (1) { 973 974 usb2_pc_cpu_invalidate(td->page_cache); 975 phy_start = le32toh(td->td_cbp); 976 td_flags = le32toh(td->td_flags); 977 td_next = le32toh(td->td_next); 978 979 /* Check for last transfer */ 980 if (((void *)td) == xfer->td_transfer_last) { 981 /* the transfer is finished */ 982 td = NULL; 983 break; 984 } 985 /* Check transfer status */ 986 cc = OHCI_TD_GET_CC(td_flags); 987 if (cc) { 988 /* the transfer is finished */ 989 td = NULL; 990 break; 991 } 992 /* 993 * Check if we reached the last packet 994 * or if there is a short packet: 995 */ 996 997 if (((td_next & (~0xF)) == OHCI_TD_NEXT_END) || phy_start) { 998 /* follow alt next */ 999 td = td->alt_next; 1000 break; 1001 } 1002 td = td->obj_next; 1003 } 1004 1005 /* update transfer cache */ 1006 1007 xfer->td_transfer_cache = td; 1008 1009 if (td) { 1010 1011 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1012 1013 ed->ed_headp = td->td_self; 1014 usb2_pc_cpu_flush(ed->page_cache); 1015 1016 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1017 1018 /* 1019 * Make sure that the OHCI re-scans the schedule by 1020 * writing the BLF and CLF bits: 1021 */ 1022 1023 if (xfer->xroot->udev->flags.self_suspended) { 1024 /* nothing to do */ 1025 } else if (xfer->endpoint->methods == &ohci_device_bulk_methods) { 1026 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1027 1028 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1029 } else if (xfer->endpoint->methods == &ohci_device_ctrl_methods) { 1030 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1031 1032 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1033 } 1034 } 1035} 1036 1037/*------------------------------------------------------------------------* 1038 * ohci_check_transfer 1039 * 1040 * Return values: 1041 * 0: USB transfer is not finished 1042 * Else: USB transfer is finished 1043 *------------------------------------------------------------------------*/ 1044static uint8_t 1045ohci_check_transfer(struct usb_xfer *xfer) 1046{ 1047 ohci_ed_t *ed; 1048 uint32_t ed_headp; 1049 uint32_t ed_tailp; 1050 1051 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1052 1053 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1054 1055 usb2_pc_cpu_invalidate(ed->page_cache); 1056 ed_headp = le32toh(ed->ed_headp); 1057 ed_tailp = le32toh(ed->ed_tailp); 1058 1059 if ((ed_headp & OHCI_HALTED) || 1060 (((ed_headp ^ ed_tailp) & (~0xF)) == 0)) { 1061 if (xfer->endpoint->methods == &ohci_device_isoc_methods) { 1062 /* isochronous transfer */ 1063 ohci_isoc_done(xfer); 1064 } else { 1065 if (xfer->flags_int.short_frames_ok) { 1066 ohci_check_transfer_sub(xfer); 1067 if (xfer->td_transfer_cache) { 1068 /* not finished yet */ 1069 return (0); 1070 } 1071 } 1072 /* store data-toggle */ 1073 if (ed_headp & OHCI_TOGGLECARRY) { 1074 xfer->endpoint->toggle_next = 1; 1075 } else { 1076 xfer->endpoint->toggle_next = 0; 1077 } 1078 1079 /* non-isochronous transfer */ 1080 ohci_non_isoc_done(xfer); 1081 } 1082 return (1); 1083 } 1084 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1085 return (0); 1086} 1087 1088static void 1089ohci_rhsc_enable(ohci_softc_t *sc) 1090{ 1091 DPRINTFN(5, "\n"); 1092 1093 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1094 1095 sc->sc_eintrs |= OHCI_RHSC; 1096 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1097 1098 /* acknowledge any RHSC interrupt */ 1099 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_RHSC); 1100 1101 ohci_root_intr(sc); 1102} 1103 1104static void 1105ohci_interrupt_poll(ohci_softc_t *sc) 1106{ 1107 struct usb_xfer *xfer; 1108 1109repeat: 1110 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1111 /* 1112 * check if transfer is transferred 1113 */ 1114 if (ohci_check_transfer(xfer)) { 1115 /* queue has been modified */ 1116 goto repeat; 1117 } 1118 } 1119} 1120 1121/*------------------------------------------------------------------------* 1122 * ohci_interrupt - OHCI interrupt handler 1123 * 1124 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1125 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1126 * is present ! 1127 *------------------------------------------------------------------------*/ 1128void 1129ohci_interrupt(ohci_softc_t *sc) 1130{ 1131 struct ohci_hcca *hcca; 1132 uint32_t status; 1133 uint32_t done; 1134 1135 USB_BUS_LOCK(&sc->sc_bus); 1136 1137 hcca = ohci_get_hcca(sc); 1138 1139 DPRINTFN(16, "real interrupt\n"); 1140 1141#if USB_DEBUG 1142 if (ohcidebug > 15) { 1143 ohci_dumpregs(sc); 1144 } 1145#endif 1146 1147 done = le32toh(hcca->hcca_done_head); 1148 1149 /* 1150 * The LSb of done is used to inform the HC Driver that an interrupt 1151 * condition exists for both the Done list and for another event 1152 * recorded in HcInterruptStatus. On an interrupt from the HC, the 1153 * HC Driver checks the HccaDoneHead Value. If this value is 0, then 1154 * the interrupt was caused by other than the HccaDoneHead update 1155 * and the HcInterruptStatus register needs to be accessed to 1156 * determine that exact interrupt cause. If HccaDoneHead is nonzero, 1157 * then a Done list update interrupt is indicated and if the LSb of 1158 * done is nonzero, then an additional interrupt event is indicated 1159 * and HcInterruptStatus should be checked to determine its cause. 1160 */ 1161 if (done != 0) { 1162 status = 0; 1163 1164 if (done & ~OHCI_DONE_INTRS) { 1165 status |= OHCI_WDH; 1166 } 1167 if (done & OHCI_DONE_INTRS) { 1168 status |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 1169 } 1170 hcca->hcca_done_head = 0; 1171 1172 usb2_pc_cpu_flush(&sc->sc_hw.hcca_pc); 1173 } else { 1174 status = OREAD4(sc, OHCI_INTERRUPT_STATUS) & ~OHCI_WDH; 1175 } 1176 1177 status &= ~OHCI_MIE; 1178 if (status == 0) { 1179 /* 1180 * nothing to be done (PCI shared 1181 * interrupt) 1182 */ 1183 goto done; 1184 } 1185 OWRITE4(sc, OHCI_INTERRUPT_STATUS, status); /* Acknowledge */ 1186 1187 status &= sc->sc_eintrs; 1188 if (status == 0) { 1189 goto done; 1190 } 1191 if (status & (OHCI_SO | OHCI_RD | OHCI_UE | OHCI_RHSC)) { 1192#if 0 1193 if (status & OHCI_SO) { 1194 /* XXX do what */ 1195 } 1196#endif 1197 if (status & OHCI_RD) { 1198 printf("%s: resume detect\n", __FUNCTION__); 1199 /* XXX process resume detect */ 1200 } 1201 if (status & OHCI_UE) { 1202 printf("%s: unrecoverable error, " 1203 "controller halted\n", __FUNCTION__); 1204 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1205 /* XXX what else */ 1206 } 1207 if (status & OHCI_RHSC) { 1208 /* 1209 * Disable RHSC interrupt for now, because it will be 1210 * on until the port has been reset. 1211 */ 1212 sc->sc_eintrs &= ~OHCI_RHSC; 1213 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 1214 1215 ohci_root_intr(sc); 1216 1217 /* do not allow RHSC interrupts > 1 per second */ 1218 usb2_callout_reset(&sc->sc_tmo_rhsc, hz, 1219 (void *)&ohci_rhsc_enable, sc); 1220 } 1221 } 1222 status &= ~(OHCI_RHSC | OHCI_WDH | OHCI_SO); 1223 if (status != 0) { 1224 /* Block unprocessed interrupts. XXX */ 1225 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, status); 1226 sc->sc_eintrs &= ~status; 1227 printf("%s: blocking intrs 0x%x\n", 1228 __FUNCTION__, status); 1229 } 1230 /* poll all the USB transfers */ 1231 ohci_interrupt_poll(sc); 1232 1233done: 1234 USB_BUS_UNLOCK(&sc->sc_bus); 1235} 1236 1237/* 1238 * called when a request does not complete 1239 */ 1240static void 1241ohci_timeout(void *arg) 1242{ 1243 struct usb_xfer *xfer = arg; 1244 1245 DPRINTF("xfer=%p\n", xfer); 1246 1247 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1248 1249 /* transfer is transferred */ 1250 ohci_device_done(xfer, USB_ERR_TIMEOUT); 1251} 1252 1253static void 1254ohci_do_poll(struct usb_bus *bus) 1255{ 1256 struct ohci_softc *sc = OHCI_BUS2SC(bus); 1257 1258 USB_BUS_LOCK(&sc->sc_bus); 1259 ohci_interrupt_poll(sc); 1260 USB_BUS_UNLOCK(&sc->sc_bus); 1261} 1262 1263static void 1264ohci_setup_standard_chain_sub(struct ohci_std_temp *temp) 1265{ 1266 struct usb_page_search buf_res; 1267 ohci_td_t *td; 1268 ohci_td_t *td_next; 1269 ohci_td_t *td_alt_next; 1270 uint32_t buf_offset; 1271 uint32_t average; 1272 uint32_t len_old; 1273 uint8_t shortpkt_old; 1274 uint8_t precompute; 1275 1276 td_alt_next = NULL; 1277 buf_offset = 0; 1278 shortpkt_old = temp->shortpkt; 1279 len_old = temp->len; 1280 precompute = 1; 1281 1282 /* software is used to detect short incoming transfers */ 1283 1284 if ((temp->td_flags & htole32(OHCI_TD_DP_MASK)) == htole32(OHCI_TD_IN)) { 1285 temp->td_flags |= htole32(OHCI_TD_R); 1286 } else { 1287 temp->td_flags &= ~htole32(OHCI_TD_R); 1288 } 1289 1290restart: 1291 1292 td = temp->td; 1293 td_next = temp->td_next; 1294 1295 while (1) { 1296 1297 if (temp->len == 0) { 1298 1299 if (temp->shortpkt) { 1300 break; 1301 } 1302 /* send a Zero Length Packet, ZLP, last */ 1303 1304 temp->shortpkt = 1; 1305 average = 0; 1306 1307 } else { 1308 1309 average = temp->average; 1310 1311 if (temp->len < average) { 1312 if (temp->len % temp->max_frame_size) { 1313 temp->shortpkt = 1; 1314 } 1315 average = temp->len; 1316 } 1317 } 1318 1319 if (td_next == NULL) { 1320 panic("%s: out of OHCI transfer descriptors!", __FUNCTION__); 1321 } 1322 /* get next TD */ 1323 1324 td = td_next; 1325 td_next = td->obj_next; 1326 1327 /* check if we are pre-computing */ 1328 1329 if (precompute) { 1330 1331 /* update remaining length */ 1332 1333 temp->len -= average; 1334 1335 continue; 1336 } 1337 /* fill out current TD */ 1338 td->td_flags = temp->td_flags; 1339 1340 /* the next TD uses TOGGLE_CARRY */ 1341 temp->td_flags &= ~htole32(OHCI_TD_TOGGLE_MASK); 1342 1343 if (average == 0) { 1344 /* 1345 * The buffer start and end phys addresses should be 1346 * 0x0 for a zero length packet. 1347 */ 1348 td->td_cbp = 0; 1349 td->td_be = 0; 1350 td->len = 0; 1351 1352 } else { 1353 1354 usb2_get_page(temp->pc, buf_offset, &buf_res); 1355 td->td_cbp = htole32(buf_res.physaddr); 1356 buf_offset += (average - 1); 1357 1358 usb2_get_page(temp->pc, buf_offset, &buf_res); 1359 td->td_be = htole32(buf_res.physaddr); 1360 buf_offset++; 1361 1362 td->len = average; 1363 1364 /* update remaining length */ 1365 1366 temp->len -= average; 1367 } 1368 1369 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1370 /* we need to receive these frames one by one ! */ 1371 td->td_flags &= htole32(~OHCI_TD_INTR_MASK); 1372 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1373 td->td_next = htole32(OHCI_TD_NEXT_END); 1374 } else { 1375 if (td_next) { 1376 /* link the current TD with the next one */ 1377 td->td_next = td_next->td_self; 1378 } 1379 } 1380 1381 td->alt_next = td_alt_next; 1382 1383 usb2_pc_cpu_flush(td->page_cache); 1384 } 1385 1386 if (precompute) { 1387 precompute = 0; 1388 1389 /* setup alt next pointer, if any */ 1390 if (temp->last_frame) { 1391 /* no alternate next */ 1392 td_alt_next = NULL; 1393 } else { 1394 /* we use this field internally */ 1395 td_alt_next = td_next; 1396 } 1397 1398 /* restore */ 1399 temp->shortpkt = shortpkt_old; 1400 temp->len = len_old; 1401 goto restart; 1402 } 1403 temp->td = td; 1404 temp->td_next = td_next; 1405} 1406 1407static void 1408ohci_setup_standard_chain(struct usb_xfer *xfer, ohci_ed_t **ed_last) 1409{ 1410 struct ohci_std_temp temp; 1411 struct usb_pipe_methods *methods; 1412 ohci_ed_t *ed; 1413 ohci_td_t *td; 1414 uint32_t ed_flags; 1415 uint32_t x; 1416 1417 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1418 xfer->address, UE_GET_ADDR(xfer->endpointno), 1419 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 1420 1421 temp.average = xfer->max_hc_frame_size; 1422 temp.max_frame_size = xfer->max_frame_size; 1423 1424 /* toggle the DMA set we are using */ 1425 xfer->flags_int.curr_dma_set ^= 1; 1426 1427 /* get next DMA set */ 1428 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1429 1430 xfer->td_transfer_first = td; 1431 xfer->td_transfer_cache = td; 1432 1433 temp.td = NULL; 1434 temp.td_next = td; 1435 temp.last_frame = 0; 1436 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1437 1438 methods = xfer->endpoint->methods; 1439 1440 /* check if we should prepend a setup message */ 1441 1442 if (xfer->flags_int.control_xfr) { 1443 if (xfer->flags_int.control_hdr) { 1444 1445 temp.td_flags = htole32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1446 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1447 1448 temp.len = xfer->frlengths[0]; 1449 temp.pc = xfer->frbuffers + 0; 1450 temp.shortpkt = temp.len ? 1 : 0; 1451 /* check for last frame */ 1452 if (xfer->nframes == 1) { 1453 /* no STATUS stage yet, SETUP is last */ 1454 if (xfer->flags_int.control_act) { 1455 temp.last_frame = 1; 1456 temp.setup_alt_next = 0; 1457 } 1458 } 1459 ohci_setup_standard_chain_sub(&temp); 1460 1461 /* 1462 * XXX assume that the setup message is 1463 * contained within one USB packet: 1464 */ 1465 xfer->endpoint->toggle_next = 1; 1466 } 1467 x = 1; 1468 } else { 1469 x = 0; 1470 } 1471 temp.td_flags = htole32(OHCI_TD_NOCC | OHCI_TD_NOINTR); 1472 1473 /* set data toggle */ 1474 1475 if (xfer->endpoint->toggle_next) { 1476 temp.td_flags |= htole32(OHCI_TD_TOGGLE_1); 1477 } else { 1478 temp.td_flags |= htole32(OHCI_TD_TOGGLE_0); 1479 } 1480 1481 /* set endpoint direction */ 1482 1483 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 1484 temp.td_flags |= htole32(OHCI_TD_IN); 1485 } else { 1486 temp.td_flags |= htole32(OHCI_TD_OUT); 1487 } 1488 1489 while (x != xfer->nframes) { 1490 1491 /* DATA0 / DATA1 message */ 1492 1493 temp.len = xfer->frlengths[x]; 1494 temp.pc = xfer->frbuffers + x; 1495 1496 x++; 1497 1498 if (x == xfer->nframes) { 1499 if (xfer->flags_int.control_xfr) { 1500 /* no STATUS stage yet, DATA is last */ 1501 if (xfer->flags_int.control_act) { 1502 temp.last_frame = 1; 1503 temp.setup_alt_next = 0; 1504 } 1505 } else { 1506 temp.last_frame = 1; 1507 temp.setup_alt_next = 0; 1508 } 1509 } 1510 if (temp.len == 0) { 1511 1512 /* make sure that we send an USB packet */ 1513 1514 temp.shortpkt = 0; 1515 1516 } else { 1517 1518 /* regular data transfer */ 1519 1520 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1521 } 1522 1523 ohci_setup_standard_chain_sub(&temp); 1524 } 1525 1526 /* check if we should append a status stage */ 1527 1528 if (xfer->flags_int.control_xfr && 1529 !xfer->flags_int.control_act) { 1530 1531 /* 1532 * Send a DATA1 message and invert the current endpoint 1533 * direction. 1534 */ 1535 1536 /* set endpoint direction and data toggle */ 1537 1538 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 1539 temp.td_flags = htole32(OHCI_TD_OUT | 1540 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1541 } else { 1542 temp.td_flags = htole32(OHCI_TD_IN | 1543 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1544 } 1545 1546 temp.len = 0; 1547 temp.pc = NULL; 1548 temp.shortpkt = 0; 1549 temp.last_frame = 1; 1550 temp.setup_alt_next = 0; 1551 1552 ohci_setup_standard_chain_sub(&temp); 1553 } 1554 td = temp.td; 1555 1556 /* Ensure that last TD is terminating: */ 1557 td->td_next = htole32(OHCI_TD_NEXT_END); 1558 td->td_flags &= ~htole32(OHCI_TD_INTR_MASK); 1559 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1560 1561 usb2_pc_cpu_flush(td->page_cache); 1562 1563 /* must have at least one frame! */ 1564 1565 xfer->td_transfer_last = td; 1566 1567#if USB_DEBUG 1568 if (ohcidebug > 8) { 1569 DPRINTF("nexttog=%d; data before transfer:\n", 1570 xfer->endpoint->toggle_next); 1571 ohci_dump_tds(xfer->td_transfer_first); 1572 } 1573#endif 1574 1575 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1576 1577 ed_flags = (OHCI_ED_SET_FA(xfer->address) | 1578 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpointno)) | 1579 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 1580 1581 ed_flags |= (OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD); 1582 1583 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1584 ed_flags |= OHCI_ED_SPEED; 1585 } 1586 ed->ed_flags = htole32(ed_flags); 1587 1588 td = xfer->td_transfer_first; 1589 1590 ed->ed_headp = td->td_self; 1591 1592 if (xfer->xroot->udev->flags.self_suspended == 0) { 1593 /* the append function will flush the endpoint descriptor */ 1594 OHCI_APPEND_QH(ed, *ed_last); 1595 1596 if (methods == &ohci_device_bulk_methods) { 1597 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1598 1599 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1600 } 1601 if (methods == &ohci_device_ctrl_methods) { 1602 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1603 1604 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1605 } 1606 } else { 1607 usb2_pc_cpu_flush(ed->page_cache); 1608 } 1609} 1610 1611static void 1612ohci_root_intr(ohci_softc_t *sc) 1613{ 1614 uint32_t hstatus; 1615 uint16_t i; 1616 uint16_t m; 1617 1618 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1619 1620 /* clear any old interrupt data */ 1621 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 1622 1623 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1624 DPRINTF("sc=%p hstatus=0x%08x\n", 1625 sc, hstatus); 1626 1627 /* set bits */ 1628 m = (sc->sc_noport + 1); 1629 if (m > (8 * sizeof(sc->sc_hub_idata))) { 1630 m = (8 * sizeof(sc->sc_hub_idata)); 1631 } 1632 for (i = 1; i < m; i++) { 1633 /* pick out CHANGE bits from the status register */ 1634 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) { 1635 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 1636 DPRINTF("port %d changed\n", i); 1637 } 1638 } 1639 1640 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1641 sizeof(sc->sc_hub_idata)); 1642} 1643 1644/* NOTE: "done" can be run two times in a row, 1645 * from close and from interrupt 1646 */ 1647static void 1648ohci_device_done(struct usb_xfer *xfer, usb_error_t error) 1649{ 1650 struct usb_pipe_methods *methods = xfer->endpoint->methods; 1651 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1652 ohci_ed_t *ed; 1653 1654 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1655 1656 1657 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1658 xfer, xfer->endpoint, error); 1659 1660 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1661 if (ed) { 1662 usb2_pc_cpu_invalidate(ed->page_cache); 1663 } 1664 if (methods == &ohci_device_bulk_methods) { 1665 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 1666 } 1667 if (methods == &ohci_device_ctrl_methods) { 1668 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 1669 } 1670 if (methods == &ohci_device_intr_methods) { 1671 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 1672 } 1673 if (methods == &ohci_device_isoc_methods) { 1674 OHCI_REMOVE_QH(ed, sc->sc_isoc_p_last); 1675 } 1676 xfer->td_transfer_first = NULL; 1677 xfer->td_transfer_last = NULL; 1678 1679 /* dequeue transfer and start next transfer */ 1680 usb2_transfer_done(xfer, error); 1681} 1682 1683/*------------------------------------------------------------------------* 1684 * ohci bulk support 1685 *------------------------------------------------------------------------*/ 1686static void 1687ohci_device_bulk_open(struct usb_xfer *xfer) 1688{ 1689 return; 1690} 1691 1692static void 1693ohci_device_bulk_close(struct usb_xfer *xfer) 1694{ 1695 ohci_device_done(xfer, USB_ERR_CANCELLED); 1696} 1697 1698static void 1699ohci_device_bulk_enter(struct usb_xfer *xfer) 1700{ 1701 return; 1702} 1703 1704static void 1705ohci_device_bulk_start(struct usb_xfer *xfer) 1706{ 1707 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1708 1709 /* setup TD's and QH */ 1710 ohci_setup_standard_chain(xfer, &sc->sc_bulk_p_last); 1711 1712 /* put transfer on interrupt queue */ 1713 ohci_transfer_intr_enqueue(xfer); 1714} 1715 1716struct usb_pipe_methods ohci_device_bulk_methods = 1717{ 1718 .open = ohci_device_bulk_open, 1719 .close = ohci_device_bulk_close, 1720 .enter = ohci_device_bulk_enter, 1721 .start = ohci_device_bulk_start, 1722}; 1723 1724/*------------------------------------------------------------------------* 1725 * ohci control support 1726 *------------------------------------------------------------------------*/ 1727static void 1728ohci_device_ctrl_open(struct usb_xfer *xfer) 1729{ 1730 return; 1731} 1732 1733static void 1734ohci_device_ctrl_close(struct usb_xfer *xfer) 1735{ 1736 ohci_device_done(xfer, USB_ERR_CANCELLED); 1737} 1738 1739static void 1740ohci_device_ctrl_enter(struct usb_xfer *xfer) 1741{ 1742 return; 1743} 1744 1745static void 1746ohci_device_ctrl_start(struct usb_xfer *xfer) 1747{ 1748 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1749 1750 /* setup TD's and QH */ 1751 ohci_setup_standard_chain(xfer, &sc->sc_ctrl_p_last); 1752 1753 /* put transfer on interrupt queue */ 1754 ohci_transfer_intr_enqueue(xfer); 1755} 1756 1757struct usb_pipe_methods ohci_device_ctrl_methods = 1758{ 1759 .open = ohci_device_ctrl_open, 1760 .close = ohci_device_ctrl_close, 1761 .enter = ohci_device_ctrl_enter, 1762 .start = ohci_device_ctrl_start, 1763}; 1764 1765/*------------------------------------------------------------------------* 1766 * ohci interrupt support 1767 *------------------------------------------------------------------------*/ 1768static void 1769ohci_device_intr_open(struct usb_xfer *xfer) 1770{ 1771 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1772 uint16_t best; 1773 uint16_t bit; 1774 uint16_t x; 1775 1776 best = 0; 1777 bit = OHCI_NO_EDS / 2; 1778 while (bit) { 1779 if (xfer->interval >= bit) { 1780 x = bit; 1781 best = bit; 1782 while (x & bit) { 1783 if (sc->sc_intr_stat[x] < 1784 sc->sc_intr_stat[best]) { 1785 best = x; 1786 } 1787 x++; 1788 } 1789 break; 1790 } 1791 bit >>= 1; 1792 } 1793 1794 sc->sc_intr_stat[best]++; 1795 xfer->qh_pos = best; 1796 1797 DPRINTFN(3, "best=%d interval=%d\n", 1798 best, xfer->interval); 1799} 1800 1801static void 1802ohci_device_intr_close(struct usb_xfer *xfer) 1803{ 1804 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1805 1806 sc->sc_intr_stat[xfer->qh_pos]--; 1807 1808 ohci_device_done(xfer, USB_ERR_CANCELLED); 1809} 1810 1811static void 1812ohci_device_intr_enter(struct usb_xfer *xfer) 1813{ 1814 return; 1815} 1816 1817static void 1818ohci_device_intr_start(struct usb_xfer *xfer) 1819{ 1820 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1821 1822 /* setup TD's and QH */ 1823 ohci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 1824 1825 /* put transfer on interrupt queue */ 1826 ohci_transfer_intr_enqueue(xfer); 1827} 1828 1829struct usb_pipe_methods ohci_device_intr_methods = 1830{ 1831 .open = ohci_device_intr_open, 1832 .close = ohci_device_intr_close, 1833 .enter = ohci_device_intr_enter, 1834 .start = ohci_device_intr_start, 1835}; 1836 1837/*------------------------------------------------------------------------* 1838 * ohci isochronous support 1839 *------------------------------------------------------------------------*/ 1840static void 1841ohci_device_isoc_open(struct usb_xfer *xfer) 1842{ 1843 return; 1844} 1845 1846static void 1847ohci_device_isoc_close(struct usb_xfer *xfer) 1848{ 1849 /**/ 1850 ohci_device_done(xfer, USB_ERR_CANCELLED); 1851} 1852 1853static void 1854ohci_device_isoc_enter(struct usb_xfer *xfer) 1855{ 1856 struct usb_page_search buf_res; 1857 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1858 struct ohci_hcca *hcca; 1859 uint32_t buf_offset; 1860 uint32_t nframes; 1861 uint32_t ed_flags; 1862 uint32_t *plen; 1863 uint16_t itd_offset[OHCI_ITD_NOFFSET]; 1864 uint16_t length; 1865 uint8_t ncur; 1866 ohci_itd_t *td; 1867 ohci_itd_t *td_last = NULL; 1868 ohci_ed_t *ed; 1869 1870 hcca = ohci_get_hcca(sc); 1871 1872 nframes = le32toh(hcca->hcca_frame_number); 1873 1874 DPRINTFN(6, "xfer=%p isoc_next=%u nframes=%u hcca_fn=%u\n", 1875 xfer, xfer->endpoint->isoc_next, xfer->nframes, nframes); 1876 1877 if ((xfer->endpoint->is_synced == 0) || 1878 (((nframes - xfer->endpoint->isoc_next) & 0xFFFF) < xfer->nframes) || 1879 (((xfer->endpoint->isoc_next - nframes) & 0xFFFF) >= 128)) { 1880 /* 1881 * If there is data underflow or the pipe queue is empty we 1882 * schedule the transfer a few frames ahead of the current 1883 * frame position. Else two isochronous transfers might 1884 * overlap. 1885 */ 1886 xfer->endpoint->isoc_next = (nframes + 3) & 0xFFFF; 1887 xfer->endpoint->is_synced = 1; 1888 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1889 } 1890 /* 1891 * compute how many milliseconds the insertion is ahead of the 1892 * current frame position: 1893 */ 1894 buf_offset = ((xfer->endpoint->isoc_next - nframes) & 0xFFFF); 1895 1896 /* 1897 * pre-compute when the isochronous transfer will be finished: 1898 */ 1899 xfer->isoc_time_complete = 1900 (usb2_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 1901 xfer->nframes); 1902 1903 /* get the real number of frames */ 1904 1905 nframes = xfer->nframes; 1906 1907 buf_offset = 0; 1908 1909 plen = xfer->frlengths; 1910 1911 /* toggle the DMA set we are using */ 1912 xfer->flags_int.curr_dma_set ^= 1; 1913 1914 /* get next DMA set */ 1915 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1916 1917 xfer->td_transfer_first = td; 1918 1919 ncur = 0; 1920 length = 0; 1921 1922 while (nframes--) { 1923 if (td == NULL) { 1924 panic("%s:%d: out of TD's\n", 1925 __FUNCTION__, __LINE__); 1926 } 1927 itd_offset[ncur] = length; 1928 buf_offset += *plen; 1929 length += *plen; 1930 plen++; 1931 ncur++; 1932 1933 if ( /* check if the ITD is full */ 1934 (ncur == OHCI_ITD_NOFFSET) || 1935 /* check if we have put more than 4K into the ITD */ 1936 (length & 0xF000) || 1937 /* check if it is the last frame */ 1938 (nframes == 0)) { 1939 1940 /* fill current ITD */ 1941 td->itd_flags = htole32( 1942 OHCI_ITD_NOCC | 1943 OHCI_ITD_SET_SF(xfer->endpoint->isoc_next) | 1944 OHCI_ITD_NOINTR | 1945 OHCI_ITD_SET_FC(ncur)); 1946 1947 td->frames = ncur; 1948 xfer->endpoint->isoc_next += ncur; 1949 1950 if (length == 0) { 1951 /* all zero */ 1952 td->itd_bp0 = 0; 1953 td->itd_be = ~0; 1954 1955 while (ncur--) { 1956 td->itd_offset[ncur] = 1957 htole16(OHCI_ITD_MK_OFFS(0)); 1958 } 1959 } else { 1960 usb2_get_page(xfer->frbuffers, buf_offset - length, &buf_res); 1961 length = OHCI_PAGE_MASK(buf_res.physaddr); 1962 buf_res.physaddr = 1963 OHCI_PAGE(buf_res.physaddr); 1964 td->itd_bp0 = htole32(buf_res.physaddr); 1965 usb2_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 1966 td->itd_be = htole32(buf_res.physaddr); 1967 1968 while (ncur--) { 1969 itd_offset[ncur] += length; 1970 itd_offset[ncur] = 1971 OHCI_ITD_MK_OFFS(itd_offset[ncur]); 1972 td->itd_offset[ncur] = 1973 htole16(itd_offset[ncur]); 1974 } 1975 } 1976 ncur = 0; 1977 length = 0; 1978 td_last = td; 1979 td = td->obj_next; 1980 1981 if (td) { 1982 /* link the last TD with the next one */ 1983 td_last->itd_next = td->itd_self; 1984 } 1985 usb2_pc_cpu_flush(td_last->page_cache); 1986 } 1987 } 1988 1989 /* update the last TD */ 1990 td_last->itd_flags &= ~htole32(OHCI_ITD_NOINTR); 1991 td_last->itd_flags |= htole32(OHCI_ITD_SET_DI(0)); 1992 td_last->itd_next = 0; 1993 1994 usb2_pc_cpu_flush(td_last->page_cache); 1995 1996 xfer->td_transfer_last = td_last; 1997 1998#if USB_DEBUG 1999 if (ohcidebug > 8) { 2000 DPRINTF("data before transfer:\n"); 2001 ohci_dump_itds(xfer->td_transfer_first); 2002 } 2003#endif 2004 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2005 2006 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 2007 ed_flags = (OHCI_ED_DIR_IN | OHCI_ED_FORMAT_ISO); 2008 else 2009 ed_flags = (OHCI_ED_DIR_OUT | OHCI_ED_FORMAT_ISO); 2010 2011 ed_flags |= (OHCI_ED_SET_FA(xfer->address) | 2012 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpointno)) | 2013 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 2014 2015 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 2016 ed_flags |= OHCI_ED_SPEED; 2017 } 2018 ed->ed_flags = htole32(ed_flags); 2019 2020 td = xfer->td_transfer_first; 2021 2022 ed->ed_headp = td->itd_self; 2023 2024 /* isochronous transfers are not affected by suspend / resume */ 2025 /* the append function will flush the endpoint descriptor */ 2026 2027 OHCI_APPEND_QH(ed, sc->sc_isoc_p_last); 2028} 2029 2030static void 2031ohci_device_isoc_start(struct usb_xfer *xfer) 2032{ 2033 /* put transfer on interrupt queue */ 2034 ohci_transfer_intr_enqueue(xfer); 2035} 2036 2037struct usb_pipe_methods ohci_device_isoc_methods = 2038{ 2039 .open = ohci_device_isoc_open, 2040 .close = ohci_device_isoc_close, 2041 .enter = ohci_device_isoc_enter, 2042 .start = ohci_device_isoc_start, 2043}; 2044 2045/*------------------------------------------------------------------------* 2046 * ohci root control support 2047 *------------------------------------------------------------------------* 2048 * Simulate a hardware hub by handling all the necessary requests. 2049 *------------------------------------------------------------------------*/ 2050 2051static const 2052struct usb_device_descriptor ohci_devd = 2053{ 2054 sizeof(struct usb_device_descriptor), 2055 UDESC_DEVICE, /* type */ 2056 {0x00, 0x01}, /* USB version */ 2057 UDCLASS_HUB, /* class */ 2058 UDSUBCLASS_HUB, /* subclass */ 2059 UDPROTO_FSHUB, /* protocol */ 2060 64, /* max packet */ 2061 {0}, {0}, {0x00, 0x01}, /* device id */ 2062 1, 2, 0, /* string indicies */ 2063 1 /* # of configurations */ 2064}; 2065 2066static const 2067struct ohci_config_desc ohci_confd = 2068{ 2069 .confd = { 2070 .bLength = sizeof(struct usb_config_descriptor), 2071 .bDescriptorType = UDESC_CONFIG, 2072 .wTotalLength[0] = sizeof(ohci_confd), 2073 .bNumInterface = 1, 2074 .bConfigurationValue = 1, 2075 .iConfiguration = 0, 2076 .bmAttributes = UC_SELF_POWERED, 2077 .bMaxPower = 0, /* max power */ 2078 }, 2079 .ifcd = { 2080 .bLength = sizeof(struct usb_interface_descriptor), 2081 .bDescriptorType = UDESC_INTERFACE, 2082 .bNumEndpoints = 1, 2083 .bInterfaceClass = UICLASS_HUB, 2084 .bInterfaceSubClass = UISUBCLASS_HUB, 2085 .bInterfaceProtocol = UIPROTO_FSHUB, 2086 }, 2087 .endpd = { 2088 .bLength = sizeof(struct usb_endpoint_descriptor), 2089 .bDescriptorType = UDESC_ENDPOINT, 2090 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2091 .bmAttributes = UE_INTERRUPT, 2092 .wMaxPacketSize[0] = 32,/* max packet (255 ports) */ 2093 .bInterval = 255, 2094 }, 2095}; 2096 2097static const 2098struct usb_hub_descriptor ohci_hubd = 2099{ 2100 0, /* dynamic length */ 2101 UDESC_HUB, 2102 0, 2103 {0, 0}, 2104 0, 2105 0, 2106 {0}, 2107}; 2108 2109static usb_error_t 2110ohci_roothub_exec(struct usb_device *udev, 2111 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2112{ 2113 ohci_softc_t *sc = OHCI_BUS2SC(udev->bus); 2114 const void *ptr; 2115 const char *str_ptr; 2116 uint32_t port; 2117 uint32_t v; 2118 uint16_t len; 2119 uint16_t value; 2120 uint16_t index; 2121 uint8_t l; 2122 usb_error_t err; 2123 2124 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2125 2126 /* buffer reset */ 2127 ptr = (const void *)&sc->sc_hub_desc.temp; 2128 len = 0; 2129 err = 0; 2130 2131 value = UGETW(req->wValue); 2132 index = UGETW(req->wIndex); 2133 2134 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2135 "wValue=0x%04x wIndex=0x%04x\n", 2136 req->bmRequestType, req->bRequest, 2137 UGETW(req->wLength), value, index); 2138 2139#define C(x,y) ((x) | ((y) << 8)) 2140 switch (C(req->bRequest, req->bmRequestType)) { 2141 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2142 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2143 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2144 /* 2145 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2146 * for the integrated root hub. 2147 */ 2148 break; 2149 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2150 len = 1; 2151 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2152 break; 2153 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2154 switch (value >> 8) { 2155 case UDESC_DEVICE: 2156 if ((value & 0xff) != 0) { 2157 err = USB_ERR_IOERROR; 2158 goto done; 2159 } 2160 len = sizeof(ohci_devd); 2161 ptr = (const void *)&ohci_devd; 2162 break; 2163 2164 case UDESC_CONFIG: 2165 if ((value & 0xff) != 0) { 2166 err = USB_ERR_IOERROR; 2167 goto done; 2168 } 2169 len = sizeof(ohci_confd); 2170 ptr = (const void *)&ohci_confd; 2171 break; 2172 2173 case UDESC_STRING: 2174 switch (value & 0xff) { 2175 case 0: /* Language table */ 2176 str_ptr = "\001"; 2177 break; 2178 2179 case 1: /* Vendor */ 2180 str_ptr = sc->sc_vendor; 2181 break; 2182 2183 case 2: /* Product */ 2184 str_ptr = "OHCI root HUB"; 2185 break; 2186 2187 default: 2188 str_ptr = ""; 2189 break; 2190 } 2191 2192 len = usb2_make_str_desc( 2193 sc->sc_hub_desc.temp, 2194 sizeof(sc->sc_hub_desc.temp), 2195 str_ptr); 2196 break; 2197 2198 default: 2199 err = USB_ERR_IOERROR; 2200 goto done; 2201 } 2202 break; 2203 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2204 len = 1; 2205 sc->sc_hub_desc.temp[0] = 0; 2206 break; 2207 case C(UR_GET_STATUS, UT_READ_DEVICE): 2208 len = 2; 2209 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2210 break; 2211 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2212 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2213 len = 2; 2214 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2215 break; 2216 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2217 if (value >= OHCI_MAX_DEVICES) { 2218 err = USB_ERR_IOERROR; 2219 goto done; 2220 } 2221 sc->sc_addr = value; 2222 break; 2223 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2224 if ((value != 0) && (value != 1)) { 2225 err = USB_ERR_IOERROR; 2226 goto done; 2227 } 2228 sc->sc_conf = value; 2229 break; 2230 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2231 break; 2232 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2233 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2234 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2235 err = USB_ERR_IOERROR; 2236 goto done; 2237 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2238 break; 2239 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2240 break; 2241 /* Hub requests */ 2242 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2243 break; 2244 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2245 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE " 2246 "port=%d feature=%d\n", 2247 index, value); 2248 if ((index < 1) || 2249 (index > sc->sc_noport)) { 2250 err = USB_ERR_IOERROR; 2251 goto done; 2252 } 2253 port = OHCI_RH_PORT_STATUS(index); 2254 switch (value) { 2255 case UHF_PORT_ENABLE: 2256 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2257 break; 2258 case UHF_PORT_SUSPEND: 2259 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2260 break; 2261 case UHF_PORT_POWER: 2262 /* Yes, writing to the LOW_SPEED bit clears power. */ 2263 OWRITE4(sc, port, UPS_LOW_SPEED); 2264 break; 2265 case UHF_C_PORT_CONNECTION: 2266 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2267 break; 2268 case UHF_C_PORT_ENABLE: 2269 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2270 break; 2271 case UHF_C_PORT_SUSPEND: 2272 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2273 break; 2274 case UHF_C_PORT_OVER_CURRENT: 2275 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2276 break; 2277 case UHF_C_PORT_RESET: 2278 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2279 break; 2280 default: 2281 err = USB_ERR_IOERROR; 2282 goto done; 2283 } 2284 switch (value) { 2285 case UHF_C_PORT_CONNECTION: 2286 case UHF_C_PORT_ENABLE: 2287 case UHF_C_PORT_SUSPEND: 2288 case UHF_C_PORT_OVER_CURRENT: 2289 case UHF_C_PORT_RESET: 2290 /* enable RHSC interrupt if condition is cleared. */ 2291 if ((OREAD4(sc, port) >> 16) == 0) 2292 ohci_rhsc_enable(sc); 2293 break; 2294 default: 2295 break; 2296 } 2297 break; 2298 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2299 if ((value & 0xff) != 0) { 2300 err = USB_ERR_IOERROR; 2301 goto done; 2302 } 2303 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2304 2305 sc->sc_hub_desc.hubd = ohci_hubd; 2306 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 2307 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, 2308 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2309 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2310 /* XXX overcurrent */ 2311 ); 2312 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2313 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2314 2315 for (l = 0; l < sc->sc_noport; l++) { 2316 if (v & 1) { 2317 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] |= (1 << (l % 8)); 2318 } 2319 v >>= 1; 2320 } 2321 sc->sc_hub_desc.hubd.bDescLength = 2322 8 + ((sc->sc_noport + 7) / 8); 2323 len = sc->sc_hub_desc.hubd.bDescLength; 2324 break; 2325 2326 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2327 len = 16; 2328 bzero(sc->sc_hub_desc.temp, 16); 2329 break; 2330 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2331 DPRINTFN(9, "get port status i=%d\n", 2332 index); 2333 if ((index < 1) || 2334 (index > sc->sc_noport)) { 2335 err = USB_ERR_IOERROR; 2336 goto done; 2337 } 2338 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2339 DPRINTFN(9, "port status=0x%04x\n", v); 2340 USETW(sc->sc_hub_desc.ps.wPortStatus, v); 2341 USETW(sc->sc_hub_desc.ps.wPortChange, v >> 16); 2342 len = sizeof(sc->sc_hub_desc.ps); 2343 break; 2344 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2345 err = USB_ERR_IOERROR; 2346 goto done; 2347 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2348 break; 2349 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2350 if ((index < 1) || 2351 (index > sc->sc_noport)) { 2352 err = USB_ERR_IOERROR; 2353 goto done; 2354 } 2355 port = OHCI_RH_PORT_STATUS(index); 2356 switch (value) { 2357 case UHF_PORT_ENABLE: 2358 OWRITE4(sc, port, UPS_PORT_ENABLED); 2359 break; 2360 case UHF_PORT_SUSPEND: 2361 OWRITE4(sc, port, UPS_SUSPEND); 2362 break; 2363 case UHF_PORT_RESET: 2364 DPRINTFN(6, "reset port %d\n", index); 2365 OWRITE4(sc, port, UPS_RESET); 2366 for (v = 0;; v++) { 2367 if (v < 12) { 2368 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 2369 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY)); 2370 2371 if ((OREAD4(sc, port) & UPS_RESET) == 0) { 2372 break; 2373 } 2374 } else { 2375 err = USB_ERR_TIMEOUT; 2376 goto done; 2377 } 2378 } 2379 DPRINTFN(9, "ohci port %d reset, status = 0x%04x\n", 2380 index, OREAD4(sc, port)); 2381 break; 2382 case UHF_PORT_POWER: 2383 DPRINTFN(3, "set port power %d\n", index); 2384 OWRITE4(sc, port, UPS_PORT_POWER); 2385 break; 2386 default: 2387 err = USB_ERR_IOERROR; 2388 goto done; 2389 } 2390 break; 2391 default: 2392 err = USB_ERR_IOERROR; 2393 goto done; 2394 } 2395done: 2396 *plength = len; 2397 *pptr = ptr; 2398 return (err); 2399} 2400 2401static void 2402ohci_xfer_setup(struct usb_setup_params *parm) 2403{ 2404 struct usb_page_search page_info; 2405 struct usb_page_cache *pc; 2406 ohci_softc_t *sc; 2407 struct usb_xfer *xfer; 2408 void *last_obj; 2409 uint32_t ntd; 2410 uint32_t nitd; 2411 uint32_t nqh; 2412 uint32_t n; 2413 2414 sc = OHCI_BUS2SC(parm->udev->bus); 2415 xfer = parm->curr_xfer; 2416 2417 parm->hc_max_packet_size = 0x500; 2418 parm->hc_max_packet_count = 1; 2419 parm->hc_max_frame_size = OHCI_PAGE_SIZE; 2420 2421 /* 2422 * calculate ntd and nqh 2423 */ 2424 if (parm->methods == &ohci_device_ctrl_methods) { 2425 xfer->flags_int.bdma_enable = 1; 2426 2427 usb2_transfer_setup_sub(parm); 2428 2429 nitd = 0; 2430 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2431 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2432 nqh = 1; 2433 2434 } else if (parm->methods == &ohci_device_bulk_methods) { 2435 xfer->flags_int.bdma_enable = 1; 2436 2437 usb2_transfer_setup_sub(parm); 2438 2439 nitd = 0; 2440 ntd = ((2 * xfer->nframes) 2441 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2442 nqh = 1; 2443 2444 } else if (parm->methods == &ohci_device_intr_methods) { 2445 xfer->flags_int.bdma_enable = 1; 2446 2447 usb2_transfer_setup_sub(parm); 2448 2449 nitd = 0; 2450 ntd = ((2 * xfer->nframes) 2451 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2452 nqh = 1; 2453 2454 } else if (parm->methods == &ohci_device_isoc_methods) { 2455 xfer->flags_int.bdma_enable = 1; 2456 2457 usb2_transfer_setup_sub(parm); 2458 2459 nitd = ((xfer->max_data_length / OHCI_PAGE_SIZE) + 2460 ((xfer->nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET) + 2461 1 /* EXTRA */ ); 2462 ntd = 0; 2463 nqh = 1; 2464 2465 } else { 2466 2467 usb2_transfer_setup_sub(parm); 2468 2469 nitd = 0; 2470 ntd = 0; 2471 nqh = 0; 2472 } 2473 2474alloc_dma_set: 2475 2476 if (parm->err) { 2477 return; 2478 } 2479 last_obj = NULL; 2480 2481 if (usb2_transfer_setup_sub_malloc( 2482 parm, &pc, sizeof(ohci_td_t), 2483 OHCI_TD_ALIGN, ntd)) { 2484 parm->err = USB_ERR_NOMEM; 2485 return; 2486 } 2487 if (parm->buf) { 2488 for (n = 0; n != ntd; n++) { 2489 ohci_td_t *td; 2490 2491 usb2_get_page(pc + n, 0, &page_info); 2492 2493 td = page_info.buffer; 2494 2495 /* init TD */ 2496 td->td_self = htole32(page_info.physaddr); 2497 td->obj_next = last_obj; 2498 td->page_cache = pc + n; 2499 2500 last_obj = td; 2501 2502 usb2_pc_cpu_flush(pc + n); 2503 } 2504 } 2505 if (usb2_transfer_setup_sub_malloc( 2506 parm, &pc, sizeof(ohci_itd_t), 2507 OHCI_ITD_ALIGN, nitd)) { 2508 parm->err = USB_ERR_NOMEM; 2509 return; 2510 } 2511 if (parm->buf) { 2512 for (n = 0; n != nitd; n++) { 2513 ohci_itd_t *itd; 2514 2515 usb2_get_page(pc + n, 0, &page_info); 2516 2517 itd = page_info.buffer; 2518 2519 /* init TD */ 2520 itd->itd_self = htole32(page_info.physaddr); 2521 itd->obj_next = last_obj; 2522 itd->page_cache = pc + n; 2523 2524 last_obj = itd; 2525 2526 usb2_pc_cpu_flush(pc + n); 2527 } 2528 } 2529 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2530 2531 last_obj = NULL; 2532 2533 if (usb2_transfer_setup_sub_malloc( 2534 parm, &pc, sizeof(ohci_ed_t), 2535 OHCI_ED_ALIGN, nqh)) { 2536 parm->err = USB_ERR_NOMEM; 2537 return; 2538 } 2539 if (parm->buf) { 2540 for (n = 0; n != nqh; n++) { 2541 ohci_ed_t *ed; 2542 2543 usb2_get_page(pc + n, 0, &page_info); 2544 2545 ed = page_info.buffer; 2546 2547 /* init QH */ 2548 ed->ed_self = htole32(page_info.physaddr); 2549 ed->obj_next = last_obj; 2550 ed->page_cache = pc + n; 2551 2552 last_obj = ed; 2553 2554 usb2_pc_cpu_flush(pc + n); 2555 } 2556 } 2557 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 2558 2559 if (!xfer->flags_int.curr_dma_set) { 2560 xfer->flags_int.curr_dma_set = 1; 2561 goto alloc_dma_set; 2562 } 2563} 2564 2565static void 2566ohci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2567 struct usb_endpoint *ep) 2568{ 2569 ohci_softc_t *sc = OHCI_BUS2SC(udev->bus); 2570 2571 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2572 ep, udev->address, 2573 edesc->bEndpointAddress, udev->flags.usb_mode, 2574 sc->sc_addr); 2575 2576 if (udev->flags.usb_mode != USB_MODE_HOST) { 2577 /* not supported */ 2578 return; 2579 } 2580 if (udev->device_index != sc->sc_addr) { 2581 switch (edesc->bmAttributes & UE_XFERTYPE) { 2582 case UE_CONTROL: 2583 ep->methods = &ohci_device_ctrl_methods; 2584 break; 2585 case UE_INTERRUPT: 2586 ep->methods = &ohci_device_intr_methods; 2587 break; 2588 case UE_ISOCHRONOUS: 2589 if (udev->speed == USB_SPEED_FULL) { 2590 ep->methods = &ohci_device_isoc_methods; 2591 } 2592 break; 2593 case UE_BULK: 2594 if (udev->speed != USB_SPEED_LOW) { 2595 ep->methods = &ohci_device_bulk_methods; 2596 } 2597 break; 2598 default: 2599 /* do nothing */ 2600 break; 2601 } 2602 } 2603} 2604 2605static void 2606ohci_xfer_unsetup(struct usb_xfer *xfer) 2607{ 2608 return; 2609} 2610 2611static void 2612ohci_get_dma_delay(struct usb_bus *bus, uint32_t *pus) 2613{ 2614 /* 2615 * Wait until hardware has finished any possible use of the 2616 * transfer descriptor(s) and QH 2617 */ 2618 *pus = (1125); /* microseconds */ 2619} 2620 2621static void 2622ohci_device_resume(struct usb_device *udev) 2623{ 2624 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2625 struct usb_xfer *xfer; 2626 struct usb_pipe_methods *methods; 2627 ohci_ed_t *ed; 2628 2629 DPRINTF("\n"); 2630 2631 USB_BUS_LOCK(udev->bus); 2632 2633 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2634 2635 if (xfer->xroot->udev == udev) { 2636 2637 methods = xfer->endpoint->methods; 2638 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2639 2640 if (methods == &ohci_device_bulk_methods) { 2641 OHCI_APPEND_QH(ed, sc->sc_bulk_p_last); 2642 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2643 } 2644 if (methods == &ohci_device_ctrl_methods) { 2645 OHCI_APPEND_QH(ed, sc->sc_ctrl_p_last); 2646 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2647 } 2648 if (methods == &ohci_device_intr_methods) { 2649 OHCI_APPEND_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2650 } 2651 } 2652 } 2653 2654 USB_BUS_UNLOCK(udev->bus); 2655 2656 return; 2657} 2658 2659static void 2660ohci_device_suspend(struct usb_device *udev) 2661{ 2662 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2663 struct usb_xfer *xfer; 2664 struct usb_pipe_methods *methods; 2665 ohci_ed_t *ed; 2666 2667 DPRINTF("\n"); 2668 2669 USB_BUS_LOCK(udev->bus); 2670 2671 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2672 2673 if (xfer->xroot->udev == udev) { 2674 2675 methods = xfer->endpoint->methods; 2676 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2677 2678 if (methods == &ohci_device_bulk_methods) { 2679 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 2680 } 2681 if (methods == &ohci_device_ctrl_methods) { 2682 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 2683 } 2684 if (methods == &ohci_device_intr_methods) { 2685 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2686 } 2687 } 2688 } 2689 2690 USB_BUS_UNLOCK(udev->bus); 2691 2692 return; 2693} 2694 2695static void 2696ohci_set_hw_power(struct usb_bus *bus) 2697{ 2698 struct ohci_softc *sc = OHCI_BUS2SC(bus); 2699 uint32_t temp; 2700 uint32_t flags; 2701 2702 DPRINTF("\n"); 2703 2704 USB_BUS_LOCK(bus); 2705 2706 flags = bus->hw_power_state; 2707 2708 temp = OREAD4(sc, OHCI_CONTROL); 2709 temp &= ~(OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE); 2710 2711 if (flags & USB_HW_POWER_CONTROL) 2712 temp |= OHCI_CLE; 2713 2714 if (flags & USB_HW_POWER_BULK) 2715 temp |= OHCI_BLE; 2716 2717 if (flags & USB_HW_POWER_INTERRUPT) 2718 temp |= OHCI_PLE; 2719 2720 if (flags & USB_HW_POWER_ISOC) 2721 temp |= OHCI_IE | OHCI_PLE; 2722 2723 OWRITE4(sc, OHCI_CONTROL, temp); 2724 2725 USB_BUS_UNLOCK(bus); 2726 2727 return; 2728} 2729 2730struct usb_bus_methods ohci_bus_methods = 2731{ 2732 .endpoint_init = ohci_ep_init, 2733 .xfer_setup = ohci_xfer_setup, 2734 .xfer_unsetup = ohci_xfer_unsetup, 2735 .get_dma_delay = ohci_get_dma_delay, 2736 .device_resume = ohci_device_resume, 2737 .device_suspend = ohci_device_suspend, 2738 .set_hw_power = ohci_set_hw_power, 2739 .roothub_exec = ohci_roothub_exec, 2740}; 2741