ehcireg.h revision 213871 
1/* $FreeBSD: head/sys/dev/usb/controller/ehcireg.h 213871 2010-10-14 21:41:08Z hselasky $ */
2/*-
3 * Copyright (c) 2001 The NetBSD Foundation, Inc.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Lennart Augustsson (lennart@augustsson.net).
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef _EHCIREG_H_
32#define	_EHCIREG_H_
33
34/* PCI config registers  */
35#define	PCI_CBMEM		0x10	/* configuration base MEM */
36#define	PCI_INTERFACE_EHCI	0x20
37#define	PCI_USBREV		0x60	/* RO USB protocol revision */
38#define	PCI_USB_REV_MASK	0xff
39#define	PCI_USB_REV_PRE_1_0	0x00
40#define	PCI_USB_REV_1_0		0x10
41#define	PCI_USB_REV_1_1		0x11
42#define	PCI_USB_REV_2_0		0x20
43#define	PCI_EHCI_FLADJ		0x61	/* RW Frame len adj, SOF=59488+6*fladj */
44#define	PCI_EHCI_PORTWAKECAP	0x62	/* RW Port wake caps (opt)  */
45
46/* EHCI Extended Capabilities */
47#define	EHCI_EC_LEGSUP		0x01
48#define	EHCI_EECP_NEXT(x)	(((x) >> 8) & 0xff)
49#define	EHCI_EECP_ID(x)		((x) & 0xff)
50
51/* Legacy support extended capability */
52#define	EHCI_LEGSUP_BIOS_SEM		0x02
53#define	EHCI_LEGSUP_OS_SEM		0x03
54#define	EHCI_LEGSUP_USBLEGCTLSTS	0x04
55
56/* EHCI capability registers */
57#define	EHCI_CAPLENGTH		0x00	/* RO Capability register length field */
58#define	EHCI_RESERVED		0x01	/* Reserved register */
59#define	EHCI_HCIVERSION		0x02	/* RO Interface version number */
60#define	EHCI_HCSPARAMS		0x04	/* RO Structural parameters */
61#define	EHCI_HCS_DEBUGPORT(x)	(((x) >> 20) & 0xf)
62#define	EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000)
63#define	EHCI_HCS_N_CC(x)	(((x) >> 12) & 0xf)	/* # of companion ctlrs */
64#define	EHCI_HCS_N_PCC(x)	(((x) >> 8) & 0xf)	/* # of ports per comp. */
65#define	EHCI_HCS_PPC(x)		((x) & 0x10)	/* port power control */
66#define	EHCI_HCS_N_PORTS(x)	((x) & 0xf)	/* # of ports */
67#define	EHCI_HCCPARAMS		0x08	/* RO Capability parameters */
68#define	EHCI_HCC_EECP(x)	(((x) >> 8) & 0xff)	/* extended ports caps */
69#define	EHCI_HCC_IST(x)		(((x) >> 4) & 0xf)	/* isoc sched threshold */
70#define	EHCI_HCC_ASPC(x)	((x) & 0x4)	/* async sched park cap */
71#define	EHCI_HCC_PFLF(x)	((x) & 0x2)	/* prog frame list flag */
72#define	EHCI_HCC_64BIT(x)	((x) & 0x1)	/* 64 bit address cap */
73#define	EHCI_HCSP_PORTROUTE	0x0c	/* RO Companion port route description */
74
75/* EHCI operational registers.  Offset given by EHCI_CAPLENGTH register */
76#define	EHCI_USBCMD		0x00	/* RO, RW, WO Command register */
77#define	EHCI_CMD_ITC_M		0x00ff0000	/* RW interrupt threshold ctrl */
78#define	EHCI_CMD_ITC_1		0x00010000
79#define	EHCI_CMD_ITC_2		0x00020000
80#define	EHCI_CMD_ITC_4		0x00040000
81#define	EHCI_CMD_ITC_8		0x00080000
82#define	EHCI_CMD_ITC_16		0x00100000
83#define	EHCI_CMD_ITC_32		0x00200000
84#define	EHCI_CMD_ITC_64		0x00400000
85#define	EHCI_CMD_ASPME		0x00000800	/* RW/RO async park enable */
86#define	EHCI_CMD_ASPMC		0x00000300	/* RW/RO async park count */
87#define	EHCI_CMD_LHCR		0x00000080	/* RW light host ctrl reset */
88#define	EHCI_CMD_IAAD		0x00000040	/* RW intr on async adv door
89						 * bell */
90#define	EHCI_CMD_ASE		0x00000020	/* RW async sched enable */
91#define	EHCI_CMD_PSE		0x00000010	/* RW periodic sched enable */
92#define	EHCI_CMD_FLS_M		0x0000000c	/* RW/RO frame list size */
93#define	EHCI_CMD_FLS(x)		(((x) >> 2) & 3)	/* RW/RO frame list size */
94#define	EHCI_CMD_HCRESET	0x00000002	/* RW reset */
95#define	EHCI_CMD_RS		0x00000001	/* RW run/stop */
96#define	EHCI_USBSTS		0x04	/* RO, RW, RWC Status register */
97#define	EHCI_STS_ASS		0x00008000	/* RO async sched status */
98#define	EHCI_STS_PSS		0x00004000	/* RO periodic sched status */
99#define	EHCI_STS_REC		0x00002000	/* RO reclamation */
100#define	EHCI_STS_HCH		0x00001000	/* RO host controller halted */
101#define	EHCI_STS_IAA		0x00000020	/* RWC interrupt on async adv */
102#define	EHCI_STS_HSE		0x00000010	/* RWC host system error */
103#define	EHCI_STS_FLR		0x00000008	/* RWC frame list rollover */
104#define	EHCI_STS_PCD		0x00000004	/* RWC port change detect */
105#define	EHCI_STS_ERRINT		0x00000002	/* RWC error interrupt */
106#define	EHCI_STS_INT		0x00000001	/* RWC interrupt */
107#define	EHCI_STS_INTRS(x)	((x) & 0x3f)
108
109/*
110 * NOTE: the doorbell interrupt is enabled, but the doorbell is never
111 * used! SiS chipsets require this.
112 */
113#define	EHCI_NORMAL_INTRS	(EHCI_STS_IAA | EHCI_STS_HSE |	\
114				EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT)
115
116#define	EHCI_USBINTR		0x08	/* RW Interrupt register */
117#define	EHCI_INTR_IAAE		0x00000020	/* interrupt on async advance
118						 * ena */
119#define	EHCI_INTR_HSEE		0x00000010	/* host system error ena */
120#define	EHCI_INTR_FLRE		0x00000008	/* frame list rollover ena */
121#define	EHCI_INTR_PCIE		0x00000004	/* port change ena */
122#define	EHCI_INTR_UEIE		0x00000002	/* USB error intr ena */
123#define	EHCI_INTR_UIE		0x00000001	/* USB intr ena */
124
125#define	EHCI_FRINDEX		0x0c	/* RW Frame Index register */
126
127#define	EHCI_CTRLDSSEGMENT	0x10	/* RW Control Data Structure Segment */
128
129#define	EHCI_PERIODICLISTBASE	0x14	/* RW Periodic List Base */
130#define	EHCI_ASYNCLISTADDR	0x18	/* RW Async List Base */
131
132#define	EHCI_CONFIGFLAG		0x40	/* RW Configure Flag register */
133#define	EHCI_CONF_CF		0x00000001	/* RW configure flag */
134
135#define	EHCI_PORTSC(n)		(0x40+(4*(n)))	/* RO, RW, RWC Port Status reg */
136#define	EHCI_PS_WKOC_E		0x00400000	/* RW wake on over current ena */
137#define	EHCI_PS_WKDSCNNT_E	0x00200000	/* RW wake on disconnect ena */
138#define	EHCI_PS_WKCNNT_E	0x00100000	/* RW wake on connect ena */
139#define	EHCI_PS_PTC		0x000f0000	/* RW port test control */
140#define	EHCI_PS_PIC		0x0000c000	/* RW port indicator control */
141#define	EHCI_PS_PO		0x00002000	/* RW port owner */
142#define	EHCI_PS_PP		0x00001000	/* RW,RO port power */
143#define	EHCI_PS_LS		0x00000c00	/* RO line status */
144#define	EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == 0x00000400)
145#define	EHCI_PS_PR		0x00000100	/* RW port reset */
146#define	EHCI_PS_SUSP		0x00000080	/* RW suspend */
147#define	EHCI_PS_FPR		0x00000040	/* RW force port resume */
148#define	EHCI_PS_OCC		0x00000020	/* RWC over current change */
149#define	EHCI_PS_OCA		0x00000010	/* RO over current active */
150#define	EHCI_PS_PEC		0x00000008	/* RWC port enable change */
151#define	EHCI_PS_PE		0x00000004	/* RW port enable */
152#define	EHCI_PS_CSC		0x00000002	/* RWC connect status change */
153#define	EHCI_PS_CS		0x00000001	/* RO connect status */
154#define	EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
155
156#define	EHCI_USBMODE		0x68	/* RW USB Device mode register */
157#define	EHCI_UM_CM		0x00000003	/* R/WO Controller Mode */
158#define	EHCI_UM_CM_IDLE		0x0	/* Idle */
159#define	EHCI_UM_CM_HOST		0x3	/* Host Controller */
160#define	EHCI_UM_ES		0x00000004	/* R/WO Endian Select */
161#define	EHCI_UM_ES_LE		0x0	/* Little-endian byte alignment */
162#define	EHCI_UM_ES_BE		0x4	/* Big-endian byte alignment */
163#define	EHCI_UM_SDIS		0x00000010	/* R/WO Stream Disable Mode */
164
165#define	EHCI_PORT_RESET_COMPLETE	2	/* ms */
166
167#endif	/* _EHCIREG_H_ */
168