1187160Sthompsa/* $FreeBSD: releng/11.0/sys/dev/usb/controller/atmegadci.h 228483 2011-12-14 00:28:54Z hselasky $ */ 2187160Sthompsa/*- 3187160Sthompsa * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 4187160Sthompsa * 5187160Sthompsa * Redistribution and use in source and binary forms, with or without 6187160Sthompsa * modification, are permitted provided that the following conditions 7187160Sthompsa * are met: 8187160Sthompsa * 1. Redistributions of source code must retain the above copyright 9187160Sthompsa * notice, this list of conditions and the following disclaimer. 10187160Sthompsa * 2. Redistributions in binary form must reproduce the above copyright 11187160Sthompsa * notice, this list of conditions and the following disclaimer in the 12187160Sthompsa * documentation and/or other materials provided with the distribution. 13187160Sthompsa * 14187160Sthompsa * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15187160Sthompsa * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16187160Sthompsa * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17187160Sthompsa * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18187160Sthompsa * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19187160Sthompsa * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20187160Sthompsa * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21187160Sthompsa * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22187160Sthompsa * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23187160Sthompsa * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24187160Sthompsa * SUCH DAMAGE. 25187160Sthompsa */ 26187160Sthompsa 27187160Sthompsa/* 28190754Sthompsa * USB Device Port register definitions, copied from ATMEGA documentation 29190754Sthompsa * provided by ATMEL. 30187160Sthompsa */ 31187160Sthompsa 32187160Sthompsa#ifndef _ATMEGADCI_H_ 33187160Sthompsa#define _ATMEGADCI_H_ 34187160Sthompsa 35187160Sthompsa#define ATMEGA_MAX_DEVICES (USB_MIN_DEVICES + 1) 36187160Sthompsa 37192446Sthompsa#define ATMEGA_OTGTCON 0xF9 38192446Sthompsa#define ATMEGA_OTGTCON_VALUE(x) ((x) << 0) 39192446Sthompsa#define ATMEGA_OTGTCON_PAGE(x) ((x) << 5) 40192446Sthompsa 41187160Sthompsa#define ATMEGA_UEINT 0xF4 42187160Sthompsa#define ATMEGA_UEINT_MASK(n) (1 << (n)) /* endpoint interrupt mask */ 43187160Sthompsa 44187160Sthompsa#define ATMEGA_UEBCHX 0xF3 /* FIFO byte count high */ 45187160Sthompsa#define ATMEGA_UEBCLX 0xF2 /* FIFO byte count low */ 46187160Sthompsa#define ATMEGA_UEDATX 0xF1 /* FIFO data */ 47187160Sthompsa 48187160Sthompsa#define ATMEGA_UEIENX 0xF0 /* interrupt enable register */ 49187160Sthompsa#define ATMEGA_UEIENX_TXINE (1 << 0) 50187160Sthompsa#define ATMEGA_UEIENX_STALLEDE (1 << 1) 51187160Sthompsa#define ATMEGA_UEIENX_RXOUTE (1 << 2) 52187160Sthompsa#define ATMEGA_UEIENX_RXSTPE (1 << 3) /* received SETUP packet */ 53187160Sthompsa#define ATMEGA_UEIENX_NAKOUTE (1 << 4) 54187160Sthompsa#define ATMEGA_UEIENX_NAKINE (1 << 6) 55187160Sthompsa#define ATMEGA_UEIENX_FLERRE (1 << 7) 56187160Sthompsa 57187160Sthompsa#define ATMEGA_UESTA1X 0xEF 58187160Sthompsa#define ATMEGA_UESTA1X_CURRBK (3 << 0) /* current bank */ 59187160Sthompsa#define ATMEGA_UESTA1X_CTRLDIR (1 << 2) /* control endpoint direction */ 60187160Sthompsa 61187160Sthompsa#define ATMEGA_UESTA0X 0xEE 62187160Sthompsa#define ATMEGA_UESTA0X_NBUSYBK (3 << 0) 63187160Sthompsa#define ATMEGA_UESTA0X_DTSEQ (3 << 2) 64187160Sthompsa#define ATMEGA_UESTA0X_UNDERFI (1 << 5) /* underflow */ 65187160Sthompsa#define ATMEGA_UESTA0X_OVERFI (1 << 6) /* overflow */ 66187160Sthompsa#define ATMEGA_UESTA0X_CFGOK (1 << 7) 67187160Sthompsa 68187160Sthompsa#define ATMEGA_UECFG1X 0xED /* endpoint config register */ 69187160Sthompsa#define ATMEGA_UECFG1X_ALLOC (1 << 1) 70187160Sthompsa#define ATMEGA_UECFG1X_EPBK0 (0 << 2) 71187160Sthompsa#define ATMEGA_UECFG1X_EPBK1 (1 << 2) 72187160Sthompsa#define ATMEGA_UECFG1X_EPBK2 (2 << 2) 73187160Sthompsa#define ATMEGA_UECFG1X_EPBK3 (3 << 2) 74187160Sthompsa#define ATMEGA_UECFG1X_EPSIZE(n) ((n) << 4) 75187160Sthompsa 76187160Sthompsa#define ATMEGA_UECFG0X 0xEC 77187160Sthompsa#define ATMEGA_UECFG0X_EPDIR (1 << 0) /* endpoint direction */ 78187160Sthompsa#define ATMEGA_UECFG0X_EPTYPE0 (0 << 6) 79187160Sthompsa#define ATMEGA_UECFG0X_EPTYPE1 (1 << 6) 80187160Sthompsa#define ATMEGA_UECFG0X_EPTYPE2 (2 << 6) 81187160Sthompsa#define ATMEGA_UECFG0X_EPTYPE3 (3 << 6) 82187160Sthompsa 83187160Sthompsa#define ATMEGA_UECONX 0xEB 84187160Sthompsa#define ATMEGA_UECONX_EPEN (1 << 0) 85187160Sthompsa#define ATMEGA_UECONX_RSTDT (1 << 3) 86187160Sthompsa#define ATMEGA_UECONX_STALLRQC (1 << 4) /* stall request clear */ 87187160Sthompsa#define ATMEGA_UECONX_STALLRQ (1 << 5) /* stall request set */ 88187160Sthompsa 89187160Sthompsa#define ATMEGA_UERST 0xEA /* endpoint reset register */ 90187160Sthompsa#define ATMEGA_UERST_MASK(n) (1 << (n)) 91187160Sthompsa 92187160Sthompsa#define ATMEGA_UENUM 0xE9 /* endpoint number */ 93187160Sthompsa 94187160Sthompsa#define ATMEGA_UEINTX 0xE8 /* interrupt register */ 95187160Sthompsa#define ATMEGA_UEINTX_TXINI (1 << 0) 96187160Sthompsa#define ATMEGA_UEINTX_STALLEDI (1 << 1) 97187160Sthompsa#define ATMEGA_UEINTX_RXOUTI (1 << 2) 98187160Sthompsa#define ATMEGA_UEINTX_RXSTPI (1 << 3) /* received setup packet */ 99187160Sthompsa#define ATMEGA_UEINTX_NAKOUTI (1 << 4) 100187160Sthompsa#define ATMEGA_UEINTX_RWAL (1 << 5) 101187160Sthompsa#define ATMEGA_UEINTX_NAKINI (1 << 6) 102187160Sthompsa#define ATMEGA_UEINTX_FIFOCON (1 << 7) 103187160Sthompsa 104187160Sthompsa#define ATMEGA_UDMFN 0xE6 105187160Sthompsa#define ATMEGA_UDMFN_FNCERR (1 << 4) 106187160Sthompsa 107187160Sthompsa#define ATMEGA_UDFNUMH 0xE5 /* frame number high */ 108187160Sthompsa#define ATMEGA_UDFNUMH_MASK 7 109187160Sthompsa 110187160Sthompsa#define ATMEGA_UDFNUML 0xE4 /* frame number low */ 111187160Sthompsa#define ATMEGA_UDFNUML_MASK 0xFF 112187160Sthompsa 113187160Sthompsa#define ATMEGA_FRAME_MASK 0x7FF 114187160Sthompsa 115187160Sthompsa#define ATMEGA_UDADDR 0xE3 /* USB address */ 116187160Sthompsa#define ATMEGA_UDADDR_MASK 0x7F 117187160Sthompsa#define ATMEGA_UDADDR_ADDEN (1 << 7) 118187160Sthompsa 119187160Sthompsa#define ATMEGA_UDIEN 0xE2 /* USB device interrupt enable */ 120187160Sthompsa#define ATMEGA_UDINT_SUSPE (1 << 0) 121187160Sthompsa#define ATMEGA_UDINT_MSOFE (1 << 1) 122187160Sthompsa#define ATMEGA_UDINT_SOFE (1 << 2) 123187160Sthompsa#define ATMEGA_UDINT_EORSTE (1 << 3) 124187160Sthompsa#define ATMEGA_UDINT_WAKEUPE (1 << 4) 125187160Sthompsa#define ATMEGA_UDINT_EORSME (1 << 5) 126187160Sthompsa#define ATMEGA_UDINT_UPRSME (1 << 6) 127187160Sthompsa 128187160Sthompsa#define ATMEGA_UDINT 0xE1 /* USB device interrupt status */ 129187160Sthompsa#define ATMEGA_UDINT_SUSPI (1 << 0) 130187160Sthompsa#define ATMEGA_UDINT_MSOFI (1 << 1) 131187160Sthompsa#define ATMEGA_UDINT_SOFI (1 << 2) 132187160Sthompsa#define ATMEGA_UDINT_EORSTI (1 << 3) 133187160Sthompsa#define ATMEGA_UDINT_WAKEUPI (1 << 4) 134187160Sthompsa#define ATMEGA_UDINT_EORSMI (1 << 5) 135187160Sthompsa#define ATMEGA_UDINT_UPRSMI (1 << 6) 136187160Sthompsa 137187160Sthompsa#define ATMEGA_UDCON 0xE0 /* USB device connection register */ 138187160Sthompsa#define ATMEGA_UDCON_DETACH (1 << 0) 139187160Sthompsa#define ATMEGA_UDCON_RMWKUP (1 << 1) 140187160Sthompsa#define ATMEGA_UDCON_LSM (1 << 2) 141187160Sthompsa#define ATMEGA_UDCON_RSTCPU (1 << 3) 142187160Sthompsa 143192446Sthompsa#define ATMEGA_OTGINT 0xDF 144192446Sthompsa 145192446Sthompsa#define ATMEGA_OTGCON 0xDD 146192446Sthompsa#define ATMEGA_OTGCON_VBUSRQC (1 << 0) 147192446Sthompsa#define ATMEGA_OTGCON_VBUSREQ (1 << 1) 148192446Sthompsa#define ATMEGA_OTGCON_VBUSHWC (1 << 2) 149192446Sthompsa#define ATMEGA_OTGCON_SRPSEL (1 << 3) 150192446Sthompsa#define ATMEGA_OTGCON_SRPREQ (1 << 4) 151192446Sthompsa#define ATMEGA_OTGCON_HNPREQ (1 << 5) 152192446Sthompsa 153187160Sthompsa#define ATMEGA_USBINT 0xDA 154187160Sthompsa#define ATMEGA_USBINT_VBUSTI (1 << 0) /* USB VBUS interrupt */ 155192446Sthompsa#define ATMEGA_USBINT_IDI (1 << 1) /* USB ID interrupt */ 156187160Sthompsa 157187160Sthompsa#define ATMEGA_USBSTA 0xD9 158187160Sthompsa#define ATMEGA_USBSTA_VBUS (1 << 0) 159187160Sthompsa#define ATMEGA_USBSTA_ID (1 << 1) 160187160Sthompsa 161187160Sthompsa#define ATMEGA_USBCON 0xD8 162187160Sthompsa#define ATMEGA_USBCON_VBUSTE (1 << 0) 163192446Sthompsa#define ATMEGA_USBCON_IDE (1 << 1) 164187160Sthompsa#define ATMEGA_USBCON_OTGPADE (1 << 4) 165187160Sthompsa#define ATMEGA_USBCON_FRZCLK (1 << 5) 166187160Sthompsa#define ATMEGA_USBCON_USBE (1 << 7) 167187160Sthompsa 168187160Sthompsa#define ATMEGA_UHWCON 0xD7 169187160Sthompsa#define ATMEGA_UHWCON_UVREGE (1 << 0) 170189677Sthompsa#define ATMEGA_UHWCON_UVCONE (1 << 4) 171189677Sthompsa#define ATMEGA_UHWCON_UIDE (1 << 6) 172189677Sthompsa#define ATMEGA_UHWCON_UIMOD (1 << 7) 173187160Sthompsa 174187160Sthompsa#define ATMEGA_READ_1(sc, reg) \ 175187160Sthompsa bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) 176187160Sthompsa 177187160Sthompsa#define ATMEGA_WRITE_1(sc, reg, data) \ 178187160Sthompsa bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) 179187160Sthompsa 180187160Sthompsa#define ATMEGA_WRITE_MULTI_1(sc, reg, ptr, len) \ 181187160Sthompsa bus_space_write_multi_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len) 182187160Sthompsa 183187160Sthompsa#define ATMEGA_READ_MULTI_1(sc, reg, ptr, len) \ 184187160Sthompsa bus_space_read_multi_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len) 185187160Sthompsa 186187160Sthompsa/* 187187160Sthompsa * Maximum number of endpoints supported: 188187160Sthompsa */ 189187160Sthompsa#define ATMEGA_EP_MAX 7 190187160Sthompsa 191187160Sthompsastruct atmegadci_td; 192187160Sthompsa 193187160Sthompsatypedef uint8_t (atmegadci_cmd_t)(struct atmegadci_td *td); 194192984Sthompsatypedef void (atmegadci_clocks_t)(struct usb_bus *); 195187160Sthompsa 196187160Sthompsastruct atmegadci_td { 197187160Sthompsa struct atmegadci_td *obj_next; 198187160Sthompsa atmegadci_cmd_t *func; 199192984Sthompsa struct usb_page_cache *pc; 200187160Sthompsa uint32_t offset; 201187160Sthompsa uint32_t remainder; 202187160Sthompsa uint16_t max_packet_size; 203187160Sthompsa uint8_t error:1; 204187160Sthompsa uint8_t alt_next:1; 205187160Sthompsa uint8_t short_pkt:1; 206187160Sthompsa uint8_t support_multi_buffer:1; 207187160Sthompsa uint8_t did_stall:1; 208187160Sthompsa uint8_t ep_no:3; 209187160Sthompsa}; 210187160Sthompsa 211187160Sthompsastruct atmegadci_std_temp { 212187160Sthompsa atmegadci_cmd_t *func; 213192984Sthompsa struct usb_page_cache *pc; 214187160Sthompsa struct atmegadci_td *td; 215187160Sthompsa struct atmegadci_td *td_next; 216187160Sthompsa uint32_t len; 217187160Sthompsa uint32_t offset; 218187160Sthompsa uint16_t max_frame_size; 219187160Sthompsa uint8_t short_pkt; 220187160Sthompsa /* 221187160Sthompsa * short_pkt = 0: transfer should be short terminated 222187160Sthompsa * short_pkt = 1: transfer should not be short terminated 223187160Sthompsa */ 224187160Sthompsa uint8_t setup_alt_next; 225192552Sthompsa uint8_t did_stall; 226187160Sthompsa}; 227187160Sthompsa 228187160Sthompsastruct atmegadci_config_desc { 229192984Sthompsa struct usb_config_descriptor confd; 230192984Sthompsa struct usb_interface_descriptor ifcd; 231192984Sthompsa struct usb_endpoint_descriptor endpd; 232187160Sthompsa} __packed; 233187160Sthompsa 234187160Sthompsaunion atmegadci_hub_temp { 235187160Sthompsa uWord wValue; 236192984Sthompsa struct usb_port_status ps; 237187160Sthompsa}; 238187160Sthompsa 239187160Sthompsastruct atmegadci_flags { 240187160Sthompsa uint8_t change_connect:1; 241187160Sthompsa uint8_t change_suspend:1; 242187160Sthompsa uint8_t status_suspend:1; /* set if suspended */ 243187160Sthompsa uint8_t status_vbus:1; /* set if present */ 244187160Sthompsa uint8_t status_bus_reset:1; /* set if reset complete */ 245187160Sthompsa uint8_t remote_wakeup:1; 246187160Sthompsa uint8_t self_powered:1; 247187160Sthompsa uint8_t clocks_off:1; 248187160Sthompsa uint8_t port_powered:1; 249187160Sthompsa uint8_t port_enabled:1; 250187160Sthompsa uint8_t d_pulled_up:1; 251187160Sthompsa}; 252187160Sthompsa 253187160Sthompsastruct atmegadci_softc { 254192984Sthompsa struct usb_bus sc_bus; 255187160Sthompsa union atmegadci_hub_temp sc_hub_temp; 256187160Sthompsa 257187160Sthompsa /* must be set by by the bus interface layer */ 258187160Sthompsa atmegadci_clocks_t *sc_clocks_on; 259187160Sthompsa atmegadci_clocks_t *sc_clocks_off; 260187160Sthompsa 261192984Sthompsa struct usb_device *sc_devices[ATMEGA_MAX_DEVICES]; 262187160Sthompsa struct resource *sc_irq_res; 263187160Sthompsa void *sc_intr_hdl; 264187160Sthompsa struct resource *sc_io_res; 265187160Sthompsa bus_space_tag_t sc_io_tag; 266187160Sthompsa bus_space_handle_t sc_io_hdl; 267190735Sthompsa 268187160Sthompsa uint8_t sc_rt_addr; /* root hub address */ 269187160Sthompsa uint8_t sc_dv_addr; /* device address */ 270187160Sthompsa uint8_t sc_conf; /* root hub config */ 271187160Sthompsa 272187160Sthompsa uint8_t sc_hub_idata[1]; 273187160Sthompsa 274187160Sthompsa struct atmegadci_flags sc_flags; 275187160Sthompsa}; 276187160Sthompsa 277187160Sthompsa/* prototypes */ 278187160Sthompsa 279193045Sthompsausb_error_t atmegadci_init(struct atmegadci_softc *sc); 280187160Sthompsavoid atmegadci_uninit(struct atmegadci_softc *sc); 281187160Sthompsavoid atmegadci_interrupt(struct atmegadci_softc *sc); 282187160Sthompsa 283187160Sthompsa#endif /* _ATMEGADCI_H_ */ 284