if_urtwnreg.h revision 293180
1/*- 2 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 * 16 * $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $ 17 * $FreeBSD: head/sys/dev/usb/wlan/if_urtwnreg.h 293180 2016-01-04 21:16:49Z avos $ 18 */ 19 20#define URTWN_CONFIG_INDEX 0 21#define URTWN_IFACE_INDEX 0 22 23#define URTWN_NOISE_FLOOR -95 24 25#define R92C_MAX_CHAINS 2 26 27/* Maximum number of output pipes is 3. */ 28#define R92C_MAX_EPOUT 3 29 30#define R92C_MAX_TX_PWR 0x3f 31 32#define R92C_PUBQ_NPAGES 231 33#define R92C_TXPKTBUF_COUNT 256 34#define R92C_TX_PAGE_COUNT 248 35#define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 36#define R88E_TXPKTBUF_COUNT 177 37#define R88E_TX_PAGE_COUNT 169 38#define R88E_TX_PAGE_BOUNDARY (R88E_TX_PAGE_COUNT + 1) 39 40#define R92C_H2C_NBOX 4 41 42/* USB Requests. */ 43#define R92C_REQ_REGS 0x05 44 45/* 46 * MAC registers. 47 */ 48/* System Configuration. */ 49#define R92C_SYS_ISO_CTRL 0x000 50#define R92C_SYS_FUNC_EN 0x002 51#define R92C_APS_FSMCO 0x004 52#define R92C_SYS_CLKR 0x008 53#define R92C_AFE_MISC 0x010 54#define R92C_SPS0_CTRL 0x011 55#define R92C_SPS_OCP_CFG 0x018 56#define R92C_RSV_CTRL 0x01c 57#define R92C_RF_CTRL 0x01f 58#define R92C_LDOA15_CTRL 0x020 59#define R92C_LDOV12D_CTRL 0x021 60#define R92C_LDOHCI12_CTRL 0x022 61#define R92C_LPLDO_CTRL 0x023 62#define R92C_AFE_XTAL_CTRL 0x024 63#define R92C_AFE_PLL_CTRL 0x028 64#define R92C_EFUSE_CTRL 0x030 65#define R92C_EFUSE_TEST 0x034 66#define R92C_PWR_DATA 0x038 67#define R92C_CAL_TIMER 0x03c 68#define R92C_ACLK_MON 0x03e 69#define R92C_GPIO_MUXCFG 0x040 70#define R92C_GPIO_IO_SEL 0x042 71#define R92C_MAC_PINMUX_CFG 0x043 72#define R92C_GPIO_PIN_CTRL 0x044 73#define R92C_GPIO_INTM 0x048 74#define R92C_LEDCFG0 0x04c 75#define R92C_LEDCFG1 0x04d 76#define R92C_LEDCFG2 0x04e 77#define R92C_LEDCFG3 0x04f 78#define R92C_FSIMR 0x050 79#define R92C_FSISR 0x054 80#define R92C_HSIMR 0x058 81#define R92C_HSISR 0x05c 82#define R92C_MCUFWDL 0x080 83#define R92C_HMEBOX_EXT(idx) (0x088 + (idx) * 2) 84#define R88E_HIMR 0x0b0 85#define R88E_HISR 0x0b4 86#define R88E_HIMRE 0x0b8 87#define R88E_HISRE 0x0bc 88#define R92C_EFUSE_ACCESS 0x0cf 89#define R92C_BIST_SCAN 0x0d0 90#define R92C_BIST_RPT 0x0d4 91#define R92C_BIST_ROM_RPT 0x0d8 92#define R92C_USB_SIE_INTF 0x0e0 93#define R92C_PCIE_MIO_INTF 0x0e4 94#define R92C_PCIE_MIO_INTD 0x0e8 95#define R92C_HPON_FSM 0x0ec 96#define R92C_SYS_CFG 0x0f0 97/* MAC General Configuration. */ 98#define R92C_CR 0x100 99#define R92C_MSR 0x102 100#define R92C_PBP 0x104 101#define R92C_TRXDMA_CTRL 0x10c 102#define R92C_TRXFF_BNDY 0x114 103#define R92C_TRXFF_STATUS 0x118 104#define R92C_RXFF_PTR 0x11c 105#define R92C_HIMR 0x120 106#define R92C_HISR 0x124 107#define R92C_HIMRE 0x128 108#define R92C_HISRE 0x12c 109#define R92C_CPWM 0x12f 110#define R92C_FWIMR 0x130 111#define R92C_FWISR 0x134 112#define R92C_PKTBUF_DBG_CTRL 0x140 113#define R92C_PKTBUF_DBG_DATA_L 0x144 114#define R92C_PKTBUF_DBG_DATA_H 0x148 115#define R92C_TC0_CTRL(i) (0x150 + (i) * 4) 116#define R92C_TCUNIT_BASE 0x164 117#define R92C_MBIST_START 0x174 118#define R92C_MBIST_DONE 0x178 119#define R92C_MBIST_FAIL 0x17c 120#define R92C_C2HEVT_MSG_NORMAL 0x1a0 121#define R92C_C2HEVT_MSG_TEST 0x1b8 122#define R92C_C2HEVT_CLEAR 0x1bf 123#define R92C_MCUTST_1 0x1c0 124#define R92C_FMETHR 0x1c8 125#define R92C_HMETFR 0x1cc 126#define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4) 127#define R92C_LLT_INIT 0x1e0 128#define R92C_BB_ACCESS_CTRL 0x1e8 129#define R92C_BB_ACCESS_DATA 0x1ec 130#define R88E_HMEBOX_EXT(idx) (0x1f0 + (idx) * 4) 131/* Tx DMA Configuration. */ 132#define R92C_RQPN 0x200 133#define R92C_FIFOPAGE 0x204 134#define R92C_TDECTRL 0x208 135#define R92C_TXDMA_OFFSET_CHK 0x20c 136#define R92C_TXDMA_STATUS 0x210 137#define R92C_RQPN_NPQ 0x214 138/* Rx DMA Configuration. */ 139#define R92C_RXDMA_AGG_PG_TH 0x280 140#define R92C_RXPKT_NUM 0x284 141#define R92C_RXDMA_STATUS 0x288 142/* Protocol Configuration. */ 143#define R92C_FWHW_TXQ_CTRL 0x420 144#define R92C_HWSEQ_CTRL 0x423 145#define R92C_TXPKTBUF_BCNQ_BDNY 0x424 146#define R92C_TXPKTBUF_MGQ_BDNY 0x425 147#define R92C_SPEC_SIFS 0x428 148#define R92C_RL 0x42a 149#define R92C_DARFRC 0x430 150#define R92C_RARFRC 0x438 151#define R92C_RRSR 0x440 152#define R92C_ARFR(i) (0x444 + (i) * 4) 153#define R92C_AGGLEN_LMT 0x458 154#define R92C_AMPDU_MIN_SPACE 0x45c 155#define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d 156#define R92C_FAST_EDCA_CTRL 0x460 157#define R92C_RD_RESP_PKT_TH 0x463 158#define R92C_INIRTS_RATE_SEL 0x480 159#define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid)) 160#define R92C_MAX_AGGR_NUM 0x4ca 161#define R88E_TX_RPT_CTRL 0x4ec 162#define R88E_TX_RPT_MACID_MAX 0x4ed 163#define R88E_TX_RPT_TIME 0x4f0 164/* EDCA Configuration. */ 165#define R92C_EDCA_VO_PARAM 0x500 166#define R92C_EDCA_VI_PARAM 0x504 167#define R92C_EDCA_BE_PARAM 0x508 168#define R92C_EDCA_BK_PARAM 0x50c 169#define R92C_BCNTCFG 0x510 170#define R92C_PIFS 0x512 171#define R92C_RDG_PIFS 0x513 172#define R92C_SIFS_CCK 0x514 173#define R92C_SIFS_OFDM 0x516 174#define R92C_AGGR_BREAK_TIME 0x51a 175#define R92C_SLOT 0x51b 176#define R92C_TX_PTCL_CTRL 0x520 177#define R92C_TXPAUSE 0x522 178#define R92C_DIS_TXREQ_CLR 0x523 179#define R92C_RD_CTRL 0x524 180#define R92C_TBTT_PROHIBIT 0x540 181#define R92C_RD_NAV_NXT 0x544 182#define R92C_NAV_PROT_LEN 0x546 183#define R92C_BCN_CTRL 0x550 184#define R92C_MBID_NUM 0x552 185#define R92C_DUAL_TSF_RST 0x553 186#define R92C_BCN_INTERVAL 0x554 187#define R92C_DRVERLYINT 0x558 188#define R92C_BCNDMATIM 0x559 189#define R92C_ATIMWND 0x55a 190#define R92C_USTIME_TSF 0x55c 191#define R92C_BCN_MAX_ERR 0x55d 192#define R92C_RXTSF_OFFSET_CCK 0x55e 193#define R92C_RXTSF_OFFSET_OFDM 0x55f 194#define R92C_TSFTR 0x560 195#define R92C_INIT_TSFTR 0x564 196#define R92C_PSTIMER 0x580 197#define R92C_TIMER0 0x584 198#define R92C_TIMER1 0x588 199#define R92C_ACMHWCTRL 0x5c0 200#define R92C_ACMRSTCTRL 0x5c1 201#define R92C_ACMAVG 0x5c2 202#define R92C_VO_ADMTIME 0x5c4 203#define R92C_VI_ADMTIME 0x5c6 204#define R92C_BE_ADMTIME 0x5c8 205#define R92C_EDCA_RANDOM_GEN 0x5cc 206#define R92C_SCH_TXCMD 0x5d0 207/* WMAC Configuration. */ 208#define R92C_APSD_CTRL 0x600 209#define R92C_BWOPMODE 0x603 210#define R92C_RCR 0x608 211#define R92C_RX_DRVINFO_SZ 0x60f 212#define R92C_MACID 0x610 213#define R92C_BSSID 0x618 214#define R92C_MAR 0x620 215#define R92C_MAC_SPEC_SIFS 0x63a 216#define R92C_R2T_SIFS 0x63c 217#define R92C_T2T_SIFS 0x63e 218#define R92C_ACKTO 0x640 219#define R92C_CAMCMD 0x670 220#define R92C_CAMWRITE 0x674 221#define R92C_CAMREAD 0x678 222#define R92C_CAMDBG 0x67c 223#define R92C_SECCFG 0x680 224#define R92C_RXFLTMAP0 0x6a0 225#define R92C_RXFLTMAP1 0x6a2 226#define R92C_RXFLTMAP2 0x6a4 227 228/* Bits for R92C_SYS_ISO_CTRL. */ 229#define R92C_SYS_ISO_CTRL_MD2PP 0x0001 230#define R92C_SYS_ISO_CTRL_UA2USB 0x0002 231#define R92C_SYS_ISO_CTRL_UD2CORE 0x0004 232#define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008 233#define R92C_SYS_ISO_CTRL_PD2CORE 0x0010 234#define R92C_SYS_ISO_CTRL_IP2MAC 0x0020 235#define R92C_SYS_ISO_CTRL_DIOP 0x0040 236#define R92C_SYS_ISO_CTRL_DIOE 0x0080 237#define R92C_SYS_ISO_CTRL_EB2CORE 0x0100 238#define R92C_SYS_ISO_CTRL_DIOR 0x0200 239#define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000 240#define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000 241 242/* Bits for R92C_SYS_FUNC_EN. */ 243#define R92C_SYS_FUNC_EN_BBRSTB 0x0001 244#define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002 245#define R92C_SYS_FUNC_EN_USBA 0x0004 246#define R92C_SYS_FUNC_EN_UPLL 0x0008 247#define R92C_SYS_FUNC_EN_USBD 0x0010 248#define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020 249#define R92C_SYS_FUNC_EN_PCIEA 0x0040 250#define R92C_SYS_FUNC_EN_PPLL 0x0080 251#define R92C_SYS_FUNC_EN_PCIED 0x0100 252#define R92C_SYS_FUNC_EN_DIOE 0x0200 253#define R92C_SYS_FUNC_EN_CPUEN 0x0400 254#define R92C_SYS_FUNC_EN_DCORE 0x0800 255#define R92C_SYS_FUNC_EN_ELDR 0x1000 256#define R92C_SYS_FUNC_EN_DIO_RF 0x2000 257#define R92C_SYS_FUNC_EN_HWPDN 0x4000 258#define R92C_SYS_FUNC_EN_MREGEN 0x8000 259 260/* Bits for R92C_APS_FSMCO. */ 261#define R92C_APS_FSMCO_PFM_LDALL 0x00000001 262#define R92C_APS_FSMCO_PFM_ALDN 0x00000002 263#define R92C_APS_FSMCO_PFM_LDKP 0x00000004 264#define R92C_APS_FSMCO_PFM_WOWL 0x00000008 265#define R92C_APS_FSMCO_PDN_EN 0x00000010 266#define R92C_APS_FSMCO_PDN_PL 0x00000020 267#define R92C_APS_FSMCO_APFM_ONMAC 0x00000100 268#define R92C_APS_FSMCO_APFM_OFF 0x00000200 269#define R92C_APS_FSMCO_APFM_RSM 0x00000400 270#define R92C_APS_FSMCO_AFSM_HSUS 0x00000800 271#define R92C_APS_FSMCO_AFSM_PCIE 0x00001000 272#define R92C_APS_FSMCO_APDM_MAC 0x00002000 273#define R92C_APS_FSMCO_APDM_HOST 0x00004000 274#define R92C_APS_FSMCO_APDM_HPDN 0x00008000 275#define R92C_APS_FSMCO_RDY_MACON 0x00010000 276#define R92C_APS_FSMCO_SUS_HOST 0x00020000 277#define R92C_APS_FSMCO_ROP_ALD 0x00100000 278#define R92C_APS_FSMCO_ROP_PWR 0x00200000 279#define R92C_APS_FSMCO_ROP_SPS 0x00400000 280#define R92C_APS_FSMCO_SOP_MRST 0x02000000 281#define R92C_APS_FSMCO_SOP_FUSE 0x04000000 282#define R92C_APS_FSMCO_SOP_ABG 0x08000000 283#define R92C_APS_FSMCO_SOP_AMB 0x10000000 284#define R92C_APS_FSMCO_SOP_RCK 0x20000000 285#define R92C_APS_FSMCO_SOP_A8M 0x40000000 286#define R92C_APS_FSMCO_XOP_BTCK 0x80000000 287 288/* Bits for R92C_SYS_CLKR. */ 289#define R92C_SYS_CLKR_ANAD16V_EN 0x00000001 290#define R92C_SYS_CLKR_ANA8M 0x00000002 291#define R92C_SYS_CLKR_MACSLP 0x00000010 292#define R92C_SYS_CLKR_LOADER_EN 0x00000020 293#define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080 294#define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100 295#define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200 296#define R92C_SYS_CLKR_SEC_EN 0x00000400 297#define R92C_SYS_CLKR_MAC_EN 0x00000800 298#define R92C_SYS_CLKR_SYS_EN 0x00001000 299#define R92C_SYS_CLKR_RING_EN 0x00002000 300 301/* Bits for R92C_RF_CTRL. */ 302#define R92C_RF_CTRL_EN 0x01 303#define R92C_RF_CTRL_RSTB 0x02 304#define R92C_RF_CTRL_SDMRSTB 0x04 305 306/* Bits for R92C_LDOV12D_CTRL. */ 307#define R92C_LDOV12D_CTRL_LDV12_EN 0x01 308 309/* Bits for R92C_AFE_XTAL_CTRL. */ 310#define R92C_AFE_XTAL_CTRL_ADDR_M 0x007ff800 311#define R92C_AFE_XTAL_CTRL_ADDR_S 11 312 313/* Bits for R92C_EFUSE_CTRL. */ 314#define R92C_EFUSE_CTRL_DATA_M 0x000000ff 315#define R92C_EFUSE_CTRL_DATA_S 0 316#define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00 317#define R92C_EFUSE_CTRL_ADDR_S 8 318#define R92C_EFUSE_CTRL_VALID 0x80000000 319 320/* Bits for R92C_GPIO_MUXCFG. */ 321#define R92C_GPIO_MUXCFG_ENBT 0x0020 322 323/* Bits for R92C_LEDCFG0. */ 324#define R92C_LEDCFG0_DIS 0x08 325 326/* Bits for R92C_MCUFWDL. */ 327#define R92C_MCUFWDL_EN 0x00000001 328#define R92C_MCUFWDL_RDY 0x00000002 329#define R92C_MCUFWDL_CHKSUM_RPT 0x00000004 330#define R92C_MCUFWDL_MACINI_RDY 0x00000008 331#define R92C_MCUFWDL_BBINI_RDY 0x00000010 332#define R92C_MCUFWDL_RFINI_RDY 0x00000020 333#define R92C_MCUFWDL_WINTINI_RDY 0x00000040 334#define R92C_MCUFWDL_RAM_DL_SEL 0x00000080 335#define R92C_MCUFWDL_PAGE_M 0x00070000 336#define R92C_MCUFWDL_PAGE_S 16 337#define R92C_MCUFWDL_CPRST 0x00800000 338 339/* Bits for R88E_HIMR. */ 340#define R88E_HIMR_CPWM 0x00000100 341#define R88E_HIMR_CPWM2 0x00000200 342#define R88E_HIMR_TBDER 0x04000000 343#define R88E_HIMR_PSTIMEOUT 0x20000000 344 345/* Bits for R88E_HIMRE.*/ 346#define R88E_HIMRE_RXFOVW 0x00000100 347#define R88E_HIMRE_TXFOVW 0x00000200 348#define R88E_HIMRE_RXERR 0x00000400 349#define R88E_HIMRE_TXERR 0x00000800 350 351/* Bits for R92C_EFUSE_ACCESS. */ 352#define R92C_EFUSE_ACCESS_OFF 0x00 353#define R92C_EFUSE_ACCESS_ON 0x69 354 355/* Bits for R92C_HPON_FSM. */ 356#define R92C_HPON_FSM_CHIP_BONDING_ID_S 22 357#define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000 358#define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1 359 360/* Bits for R92C_SYS_CFG. */ 361#define R92C_SYS_CFG_XCLK_VLD 0x00000001 362#define R92C_SYS_CFG_ACLK_VLD 0x00000002 363#define R92C_SYS_CFG_UCLK_VLD 0x00000004 364#define R92C_SYS_CFG_PCLK_VLD 0x00000008 365#define R92C_SYS_CFG_PCIRSTB 0x00000010 366#define R92C_SYS_CFG_V15_VLD 0x00000020 367#define R92C_SYS_CFG_TRP_B15V_EN 0x00000080 368#define R92C_SYS_CFG_SIC_IDLE 0x00000100 369#define R92C_SYS_CFG_BD_MAC2 0x00000200 370#define R92C_SYS_CFG_BD_MAC1 0x00000400 371#define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800 372#define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000 373#define R92C_SYS_CFG_CHIP_VER_RTL_S 12 374#define R92C_SYS_CFG_BT_FUNC 0x00010000 375#define R92C_SYS_CFG_VENDOR_UMC 0x00080000 376#define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000 377#define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000 378#define R92C_SYS_CFG_TRP_BT_EN 0x01000000 379#define R92C_SYS_CFG_BD_PKG_SEL 0x02000000 380#define R92C_SYS_CFG_BD_HCI_SEL 0x04000000 381#define R92C_SYS_CFG_TYPE_92C 0x08000000 382 383/* Bits for R92C_CR. */ 384#define R92C_CR_HCI_TXDMA_EN 0x0001 385#define R92C_CR_HCI_RXDMA_EN 0x0002 386#define R92C_CR_TXDMA_EN 0x0004 387#define R92C_CR_RXDMA_EN 0x0008 388#define R92C_CR_PROTOCOL_EN 0x0010 389#define R92C_CR_SCHEDULE_EN 0x0020 390#define R92C_CR_MACTXEN 0x0040 391#define R92C_CR_MACRXEN 0x0080 392#define R92C_CR_ENSEC 0x0200 393#define R92C_CR_CALTMR_EN 0x0400 394 395/* Bits for R92C_MSR. */ 396#define R92C_MSR_NOLINK 0x00 397#define R92C_MSR_ADHOC 0x01 398#define R92C_MSR_INFRA 0x02 399#define R92C_MSR_AP 0x03 400#define R92C_MSR_MASK (R92C_MSR_AP) 401 402/* Bits for R92C_PBP. */ 403#define R92C_PBP_PSRX_M 0x0f 404#define R92C_PBP_PSRX_S 0 405#define R92C_PBP_PSTX_M 0xf0 406#define R92C_PBP_PSTX_S 4 407#define R92C_PBP_64 0 408#define R92C_PBP_128 1 409#define R92C_PBP_256 2 410#define R92C_PBP_512 3 411#define R92C_PBP_1024 4 412 413/* Bits for R92C_TRXDMA_CTRL. */ 414#define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004 415#define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030 416#define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4 417#define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0 418#define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6 419#define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300 420#define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8 421#define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00 422#define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10 423#define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000 424#define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12 425#define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000 426#define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14 427#define R92C_TRXDMA_CTRL_QUEUE_LOW 1 428#define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2 429#define R92C_TRXDMA_CTRL_QUEUE_HIGH 3 430#define R92C_TRXDMA_CTRL_QMAP_M 0xfff0 431/* Shortcuts. */ 432#define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0 433#define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0 434#define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0 435#define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550 436#define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0 437#define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0 438 439/* Bits for R92C_LLT_INIT. */ 440#define R92C_LLT_INIT_DATA_M 0x000000ff 441#define R92C_LLT_INIT_DATA_S 0 442#define R92C_LLT_INIT_ADDR_M 0x0000ff00 443#define R92C_LLT_INIT_ADDR_S 8 444#define R92C_LLT_INIT_OP_M 0xc0000000 445#define R92C_LLT_INIT_OP_S 30 446#define R92C_LLT_INIT_OP_NO_ACTIVE 0 447#define R92C_LLT_INIT_OP_WRITE 1 448 449/* Bits for R92C_RQPN. */ 450#define R92C_RQPN_HPQ_M 0x000000ff 451#define R92C_RQPN_HPQ_S 0 452#define R92C_RQPN_LPQ_M 0x0000ff00 453#define R92C_RQPN_LPQ_S 8 454#define R92C_RQPN_PUBQ_M 0x00ff0000 455#define R92C_RQPN_PUBQ_S 16 456#define R92C_RQPN_LD 0x80000000 457 458/* Bits for R92C_TDECTRL. */ 459#define R92C_TDECTRL_BLK_DESC_NUM_M 0x000000f0 460#define R92C_TDECTRL_BLK_DESC_NUM_S 4 461 462/* Bits for R92C_FWHW_TXQ_CTRL. */ 463#define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80 464 465/* Bits for R92C_SPEC_SIFS. */ 466#define R92C_SPEC_SIFS_CCK_M 0x00ff 467#define R92C_SPEC_SIFS_CCK_S 0 468#define R92C_SPEC_SIFS_OFDM_M 0xff00 469#define R92C_SPEC_SIFS_OFDM_S 8 470 471/* Bits for R92C_RL. */ 472#define R92C_RL_LRL_M 0x003f 473#define R92C_RL_LRL_S 0 474#define R92C_RL_SRL_M 0x3f00 475#define R92C_RL_SRL_S 8 476 477/* Bits for R92C_RRSR. */ 478#define R92C_RRSR_RATE_BITMAP_M 0x000fffff 479#define R92C_RRSR_RATE_BITMAP_S 0 480#define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1 481#define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000 482#define R92C_RRSR_RSC_UPSUBCHNL 0x00400000 483#define R92C_RRSR_SHORT 0x00800000 484 485/* Bits for R88E_TX_RPT_CTRL. */ 486#define R88E_TX_RPT1_ENA 0x01 487#define R88E_TX_RPT2_ENA 0x02 488 489/* Bits for R92C_EDCA_XX_PARAM. */ 490#define R92C_EDCA_PARAM_AIFS_M 0x000000ff 491#define R92C_EDCA_PARAM_AIFS_S 0 492#define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00 493#define R92C_EDCA_PARAM_ECWMIN_S 8 494#define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000 495#define R92C_EDCA_PARAM_ECWMAX_S 12 496#define R92C_EDCA_PARAM_TXOP_M 0xffff0000 497#define R92C_EDCA_PARAM_TXOP_S 16 498 499/* Bits for R92C_HWSEQ_CTRL / R92C_TXPAUSE. */ 500#define R92C_TX_QUEUE_VO 0x01 501#define R92C_TX_QUEUE_VI 0x02 502#define R92C_TX_QUEUE_BE 0x04 503#define R92C_TX_QUEUE_BK 0x08 504#define R92C_TX_QUEUE_MGT 0x10 505#define R92C_TX_QUEUE_HIGH 0x20 506#define R92C_TX_QUEUE_BCN 0x40 507 508/* Shortcuts. */ 509#define R92C_TX_QUEUE_AC \ 510 (R92C_TX_QUEUE_VO | R92C_TX_QUEUE_VI | \ 511 R92C_TX_QUEUE_BE | R92C_TX_QUEUE_BK) 512 513#define R92C_TX_QUEUE_ALL \ 514 (R92C_TX_QUEUE_AC | R92C_TX_QUEUE_MGT | \ 515 R92C_TX_QUEUE_HIGH | R92C_TX_QUEUE_BCN | 0x80) /* XXX */ 516 517/* Bits for R92C_BCN_CTRL. */ 518#define R92C_BCN_CTRL_EN_MBSSID 0x02 519#define R92C_BCN_CTRL_TXBCN_RPT 0x04 520#define R92C_BCN_CTRL_EN_BCN 0x08 521#define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10 522 523/* Bits for R92C_MBID_NUM. */ 524#define R92C_MBID_TXBCN_RPT0 0x08 525#define R92C_MBID_TXBCN_RPT1 0x10 526 527/* Bits for R92C_DUAL_TSF_RST. */ 528#define R92C_DUAL_TSF_RST0 0x01 529#define R92C_DUAL_TSF_RST1 0x02 530 531/* Bits for R92C_ACMHWCTRL. */ 532#define R92C_ACMHWCTRL_EN 0x01 533#define R92C_ACMHWCTRL_BE 0x02 534#define R92C_ACMHWCTRL_VI 0x04 535#define R92C_ACMHWCTRL_VO 0x08 536#define R92C_ACMHWCTRL_ACM_MASK 0x0f 537 538/* Bits for R92C_APSD_CTRL. */ 539#define R92C_APSD_CTRL_OFF 0x40 540#define R92C_APSD_CTRL_OFF_STATUS 0x80 541 542/* Bits for R92C_BWOPMODE. */ 543#define R92C_BWOPMODE_11J 0x01 544#define R92C_BWOPMODE_5G 0x02 545#define R92C_BWOPMODE_20MHZ 0x04 546 547/* Bits for R92C_RCR. */ 548#define R92C_RCR_AAP 0x00000001 549#define R92C_RCR_APM 0x00000002 550#define R92C_RCR_AM 0x00000004 551#define R92C_RCR_AB 0x00000008 552#define R92C_RCR_ADD3 0x00000010 553#define R92C_RCR_APWRMGT 0x00000020 554#define R92C_RCR_CBSSID_DATA 0x00000040 555#define R92C_RCR_CBSSID_BCN 0x00000080 556#define R92C_RCR_ACRC32 0x00000100 557#define R92C_RCR_AICV 0x00000200 558#define R92C_RCR_ADF 0x00000800 559#define R92C_RCR_ACF 0x00001000 560#define R92C_RCR_AMF 0x00002000 561#define R92C_RCR_HTC_LOC_CTRL 0x00004000 562#define R92C_RCR_MFBEN 0x00400000 563#define R92C_RCR_LSIGEN 0x00800000 564#define R92C_RCR_ENMBID 0x01000000 565#define R92C_RCR_APP_BA_SSN 0x08000000 566#define R92C_RCR_APP_PHYSTS 0x10000000 567#define R92C_RCR_APP_ICV 0x20000000 568#define R92C_RCR_APP_MIC 0x40000000 569#define R92C_RCR_APPFCS 0x80000000 570 571/* Bits for R92C_CAMCMD. */ 572#define R92C_CAMCMD_ADDR_M 0x0000ffff 573#define R92C_CAMCMD_ADDR_S 0 574#define R92C_CAMCMD_WRITE 0x00010000 575#define R92C_CAMCMD_CLR 0x40000000 576#define R92C_CAMCMD_POLLING 0x80000000 577 578/* Bits for R92C_SECCFG. */ 579#define R92C_SECCFG_TXUCKEY_DEF 0x0001 580#define R92C_SECCFG_RXUCKEY_DEF 0x0002 581#define R92C_SECCFG_TXENC_ENA 0x0004 582#define R92C_SECCFG_RXDEC_ENA 0x0008 583#define R92C_SECCFG_CMP_A2 0x0010 584#define R92C_SECCFG_TXBCKEY_DEF 0x0040 585#define R92C_SECCFG_RXBCKEY_DEF 0x0080 586#define R88E_SECCFG_CHK_KEYID 0x0100 587 588/* Bits for R92C_RXFLTMAP*. */ 589#define R92C_RXFLTMAP_SUBTYPE(subtype) \ 590 (1 << ((subtype) >> IEEE80211_FC0_SUBTYPE_SHIFT)) 591 592 593/* 594 * Baseband registers. 595 */ 596#define R92C_FPGA0_RFMOD 0x800 597#define R92C_FPGA0_TXINFO 0x804 598#define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8) 599#define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8) 600#define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830) 601#define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834) 602#define R92C_TXAGC_A_CCK1_MCS32 0xe08 603#define R92C_TXAGC_B_CCK1_55_MCS32 0x838 604#define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c 605#define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c) 606#define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848) 607#define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c) 608#define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868) 609#define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4) 610#define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4) 611#define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4) 612#define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4) 613#define R92C_FPGA0_ANAPARAM2 0x884 614#define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4) 615#define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4) 616#define R92C_FPGA1_RFMOD 0x900 617#define R92C_FPGA1_TXINFO 0x90c 618#define R92C_CCK0_SYSTEM 0xa00 619#define R92C_CCK0_AFESETTING 0xa04 620#define R92C_OFDM0_TRXPATHENA 0xc04 621#define R92C_OFDM0_TRMUXPAR 0xc08 622#define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8) 623#define R92C_OFDM0_AGCPARAM1 0xc70 624#define R92C_OFDM0_AGCRSSITABLE 0xc78 625#define R92C_OFDM1_LSTF 0xd00 626 627/* Bits for R92C_FPGA[01]_RFMOD. */ 628#define R92C_RFMOD_40MHZ 0x00000001 629#define R92C_RFMOD_JAPAN 0x00000002 630#define R92C_RFMOD_CCK_TXSC 0x00000030 631#define R92C_RFMOD_CCK_EN 0x01000000 632#define R92C_RFMOD_OFDM_EN 0x02000000 633 634/* Bits for R92C_HSSI_PARAM1(i). */ 635#define R92C_HSSI_PARAM1_PI 0x00000100 636 637/* Bits for R92C_HSSI_PARAM2(i). */ 638#define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200 639#define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400 640#define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800 641#define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000 642#define R92C_HSSI_PARAM2_READ_ADDR_S 23 643#define R92C_HSSI_PARAM2_READ_EDGE 0x80000000 644 645/* Bits for R92C_TXAGC_A_CCK1_MCS32. */ 646#define R92C_TXAGC_A_CCK1_M 0x0000ff00 647#define R92C_TXAGC_A_CCK1_S 8 648 649/* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */ 650#define R92C_TXAGC_B_CCK11_M 0x000000ff 651#define R92C_TXAGC_B_CCK11_S 0 652#define R92C_TXAGC_A_CCK2_M 0x0000ff00 653#define R92C_TXAGC_A_CCK2_S 8 654#define R92C_TXAGC_A_CCK55_M 0x00ff0000 655#define R92C_TXAGC_A_CCK55_S 16 656#define R92C_TXAGC_A_CCK11_M 0xff000000 657#define R92C_TXAGC_A_CCK11_S 24 658 659/* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */ 660#define R92C_TXAGC_B_CCK1_M 0x0000ff00 661#define R92C_TXAGC_B_CCK1_S 8 662#define R92C_TXAGC_B_CCK2_M 0x00ff0000 663#define R92C_TXAGC_B_CCK2_S 16 664#define R92C_TXAGC_B_CCK55_M 0xff000000 665#define R92C_TXAGC_B_CCK55_S 24 666 667/* Bits for R92C_TXAGC_RATE18_06(x). */ 668#define R92C_TXAGC_RATE06_M 0x000000ff 669#define R92C_TXAGC_RATE06_S 0 670#define R92C_TXAGC_RATE09_M 0x0000ff00 671#define R92C_TXAGC_RATE09_S 8 672#define R92C_TXAGC_RATE12_M 0x00ff0000 673#define R92C_TXAGC_RATE12_S 16 674#define R92C_TXAGC_RATE18_M 0xff000000 675#define R92C_TXAGC_RATE18_S 24 676 677/* Bits for R92C_TXAGC_RATE54_24(x). */ 678#define R92C_TXAGC_RATE24_M 0x000000ff 679#define R92C_TXAGC_RATE24_S 0 680#define R92C_TXAGC_RATE36_M 0x0000ff00 681#define R92C_TXAGC_RATE36_S 8 682#define R92C_TXAGC_RATE48_M 0x00ff0000 683#define R92C_TXAGC_RATE48_S 16 684#define R92C_TXAGC_RATE54_M 0xff000000 685#define R92C_TXAGC_RATE54_S 24 686 687/* Bits for R92C_TXAGC_MCS03_MCS00(x). */ 688#define R92C_TXAGC_MCS00_M 0x000000ff 689#define R92C_TXAGC_MCS00_S 0 690#define R92C_TXAGC_MCS01_M 0x0000ff00 691#define R92C_TXAGC_MCS01_S 8 692#define R92C_TXAGC_MCS02_M 0x00ff0000 693#define R92C_TXAGC_MCS02_S 16 694#define R92C_TXAGC_MCS03_M 0xff000000 695#define R92C_TXAGC_MCS03_S 24 696 697/* Bits for R92C_TXAGC_MCS07_MCS04(x). */ 698#define R92C_TXAGC_MCS04_M 0x000000ff 699#define R92C_TXAGC_MCS04_S 0 700#define R92C_TXAGC_MCS05_M 0x0000ff00 701#define R92C_TXAGC_MCS05_S 8 702#define R92C_TXAGC_MCS06_M 0x00ff0000 703#define R92C_TXAGC_MCS06_S 16 704#define R92C_TXAGC_MCS07_M 0xff000000 705#define R92C_TXAGC_MCS07_S 24 706 707/* Bits for R92C_TXAGC_MCS11_MCS08(x). */ 708#define R92C_TXAGC_MCS08_M 0x000000ff 709#define R92C_TXAGC_MCS08_S 0 710#define R92C_TXAGC_MCS09_M 0x0000ff00 711#define R92C_TXAGC_MCS09_S 8 712#define R92C_TXAGC_MCS10_M 0x00ff0000 713#define R92C_TXAGC_MCS10_S 16 714#define R92C_TXAGC_MCS11_M 0xff000000 715#define R92C_TXAGC_MCS11_S 24 716 717/* Bits for R92C_TXAGC_MCS15_MCS12(x). */ 718#define R92C_TXAGC_MCS12_M 0x000000ff 719#define R92C_TXAGC_MCS12_S 0 720#define R92C_TXAGC_MCS13_M 0x0000ff00 721#define R92C_TXAGC_MCS13_S 8 722#define R92C_TXAGC_MCS14_M 0x00ff0000 723#define R92C_TXAGC_MCS14_S 16 724#define R92C_TXAGC_MCS15_M 0xff000000 725#define R92C_TXAGC_MCS15_S 24 726 727/* Bits for R92C_LSSI_PARAM(i). */ 728#define R92C_LSSI_PARAM_DATA_M 0x000fffff 729#define R92C_LSSI_PARAM_DATA_S 0 730#define R92C_LSSI_PARAM_ADDR_M 0x03f00000 731#define R92C_LSSI_PARAM_ADDR_S 20 732#define R88E_LSSI_PARAM_ADDR_M 0x0ff00000 733#define R88E_LSSI_PARAM_ADDR_S 20 734 735/* Bits for R92C_FPGA0_ANAPARAM2. */ 736#define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400 737 738/* Bits for R92C_LSSI_READBACK(i). */ 739#define R92C_LSSI_READBACK_DATA_M 0x000fffff 740#define R92C_LSSI_READBACK_DATA_S 0 741 742/* Bits for R92C_OFDM0_AGCCORE1(i). */ 743#define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f 744#define R92C_OFDM0_AGCCORE1_GAIN_S 0 745 746 747/* 748 * USB registers. 749 */ 750#define R92C_USB_INFO 0xfe17 751#define R92C_USB_SPECIAL_OPTION 0xfe55 752#define R92C_USB_HCPWM 0xfe57 753#define R92C_USB_HRPWM 0xfe58 754#define R92C_USB_DMA_AGG_TO 0xfe5b 755#define R92C_USB_AGG_TO 0xfe5c 756#define R92C_USB_AGG_TH 0xfe5d 757#define R92C_USB_VID 0xfe60 758#define R92C_USB_PID 0xfe62 759#define R92C_USB_OPTIONAL 0xfe64 760#define R92C_USB_EP 0xfe65 761#define R92C_USB_PHY 0xfe68 762#define R92C_USB_MAC_ADDR 0xfe70 763#define R92C_USB_STRING 0xfe80 764 765/* Bits for R92C_USB_SPECIAL_OPTION. */ 766#define R92C_USB_SPECIAL_OPTION_AGG_EN 0x08 767#define R92C_USB_SPECIAL_OPTION_INT_BULK_SEL 0x10 768 769/* Bits for R92C_USB_EP. */ 770#define R92C_USB_EP_HQ_M 0x000f 771#define R92C_USB_EP_HQ_S 0 772#define R92C_USB_EP_NQ_M 0x00f0 773#define R92C_USB_EP_NQ_S 4 774#define R92C_USB_EP_LQ_M 0x0f00 775#define R92C_USB_EP_LQ_S 8 776 777 778/* 779 * Firmware base address. 780 */ 781#define R92C_FW_START_ADDR 0x1000 782#define R92C_FW_PAGE_SIZE 4096 783 784 785/* 786 * RF (6052) registers. 787 */ 788#define R92C_RF_AC 0x00 789#define R92C_RF_IQADJ_G(i) (0x01 + (i)) 790#define R92C_RF_POW_TRSW 0x05 791#define R92C_RF_GAIN_RX 0x06 792#define R92C_RF_GAIN_TX 0x07 793#define R92C_RF_TXM_IDAC 0x08 794#define R92C_RF_BS_IQGEN 0x0f 795#define R92C_RF_MODE1 0x10 796#define R92C_RF_MODE2 0x11 797#define R92C_RF_RX_AGC_HP 0x12 798#define R92C_RF_TX_AGC 0x13 799#define R92C_RF_BIAS 0x14 800#define R92C_RF_IPA 0x15 801#define R92C_RF_POW_ABILITY 0x17 802#define R92C_RF_CHNLBW 0x18 803#define R92C_RF_RX_G1 0x1a 804#define R92C_RF_RX_G2 0x1b 805#define R92C_RF_RX_BB2 0x1c 806#define R92C_RF_RX_BB1 0x1d 807#define R92C_RF_RCK1 0x1e 808#define R92C_RF_RCK2 0x1f 809#define R92C_RF_TX_G(i) (0x20 + (i)) 810#define R92C_RF_TX_BB1 0x23 811#define R92C_RF_T_METER 0x24 812#define R92C_RF_SYN_G(i) (0x25 + (i)) 813#define R92C_RF_RCK_OS 0x30 814#define R92C_RF_TXPA_G(i) (0x31 + (i)) 815 816/* Bits for R92C_RF_AC. */ 817#define R92C_RF_AC_MODE_M 0x70000 818#define R92C_RF_AC_MODE_S 16 819#define R92C_RF_AC_MODE_STANDBY 1 820 821/* Bits for R92C_RF_CHNLBW. */ 822#define R92C_RF_CHNLBW_CHNL_M 0x003ff 823#define R92C_RF_CHNLBW_CHNL_S 0 824#define R92C_RF_CHNLBW_BW20 0x00400 825#define R88E_RF_CHNLBW_BW20 0x00c00 826#define R92C_RF_CHNLBW_LCSTART 0x08000 827 828 829/* 830 * CAM entries. 831 */ 832#define R92C_CAM_ENTRY_COUNT 32 833 834#define R92C_CAM_CTL0(entry) ((entry) * 8 + 0) 835#define R92C_CAM_CTL1(entry) ((entry) * 8 + 1) 836#define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) 837 838/* Bits for R92C_CAM_CTL0(i). */ 839#define R92C_CAM_KEYID_M 0x00000003 840#define R92C_CAM_KEYID_S 0 841#define R92C_CAM_ALGO_M 0x0000001c 842#define R92C_CAM_ALGO_S 2 843#define R92C_CAM_ALGO_NONE 0 844#define R92C_CAM_ALGO_WEP40 1 845#define R92C_CAM_ALGO_TKIP 2 846#define R92C_CAM_ALGO_AES 4 847#define R92C_CAM_ALGO_WEP104 5 848#define R92C_CAM_VALID 0x00008000 849#define R92C_CAM_MACLO_M 0xffff0000 850#define R92C_CAM_MACLO_S 16 851 852/* Rate adaptation modes. */ 853#define R92C_RAID_11GN 1 854#define R92C_RAID_11N 3 855#define R92C_RAID_11BG 4 856#define R92C_RAID_11G 5 /* "pure" 11g */ 857#define R92C_RAID_11B 6 858 859 860/* 861 * Macros to access subfields in registers. 862 */ 863/* Mask and Shift (getter). */ 864#define MS(val, field) \ 865 (((val) & field##_M) >> field##_S) 866 867/* Shift and Mask (setter). */ 868#define SM(field, val) \ 869 (((val) << field##_S) & field##_M) 870 871/* Rewrite. */ 872#define RW(var, field, val) \ 873 (((var) & ~field##_M) | SM(field, val)) 874 875/* 876 * Firmware image header. 877 */ 878struct r92c_fw_hdr { 879 /* QWORD0 */ 880 uint16_t signature; 881 uint8_t category; 882 uint8_t function; 883 uint16_t version; 884 uint16_t subversion; 885 /* QWORD1 */ 886 uint8_t month; 887 uint8_t date; 888 uint8_t hour; 889 uint8_t minute; 890 uint16_t ramcodesize; 891 uint16_t reserved2; 892 /* QWORD2 */ 893 uint32_t svnidx; 894 uint32_t reserved3; 895 /* QWORD3 */ 896 uint32_t reserved4; 897 uint32_t reserved5; 898} __packed; 899 900/* 901 * Host to firmware commands. 902 */ 903struct r92c_fw_cmd { 904 uint8_t id; 905#define R92C_CMD_AP_OFFLOAD 0 906#define R92C_CMD_SET_PWRMODE 1 907#define R92C_CMD_JOINBSS_RPT 2 908#define R92C_CMD_RSVD_PAGE 3 909#define R92C_CMD_RSSI 4 910#define R92C_CMD_RSSI_SETTING 5 911#define R92C_CMD_MACID_CONFIG 6 912#define R92C_CMD_MACID_PS_MODE 7 913#define R92C_CMD_P2P_PS_OFFLOAD 8 914#define R92C_CMD_SELECTIVE_SUSPEND 9 915#define R92C_CMD_FLAG_EXT 0x80 916 917 uint8_t msg[5]; 918} __packed; 919 920/* Structure for R92C_CMD_RSSI_SETTING. */ 921struct r92c_fw_cmd_rssi { 922 uint8_t macid; 923 uint8_t reserved; 924 uint8_t pwdb; 925} __packed; 926 927/* Structure for R92C_CMD_MACID_CONFIG. */ 928struct r92c_fw_cmd_macid_cfg { 929 uint32_t mask; 930 uint8_t macid; 931#define URTWN_MACID_BSS 0 932#define URTWN_MACID_BC 4 /* Broadcast. */ 933#define R92C_MACID_MAX 31 934#define R88E_MACID_MAX 63 935#define URTWN_MACID_MAX(sc) (((sc)->chip & URTWN_CHIP_88E) ? \ 936 R88E_MACID_MAX : R92C_MACID_MAX) 937#define URTWN_MACID_UNDEFINED (uint8_t)-1 938#define URTWN_MACID_VALID 0x80 939} __packed; 940 941/* 942 * RTL8192CU ROM image. 943 */ 944struct r92c_rom { 945 uint16_t id; /* 0x8192 */ 946 uint8_t reserved1[5]; 947 uint8_t dbg_sel; 948 uint16_t reserved2; 949 uint16_t vid; 950 uint16_t pid; 951 uint8_t usb_opt; 952 uint8_t ep_setting; 953 uint16_t reserved3; 954 uint8_t usb_phy; 955 uint8_t reserved4[3]; 956 uint8_t macaddr[6]; 957 uint8_t string[61]; /* "Realtek" */ 958 uint8_t subcustomer_id; 959 uint8_t cck_tx_pwr[R92C_MAX_CHAINS][3]; 960 uint8_t ht40_1s_tx_pwr[R92C_MAX_CHAINS][3]; 961 uint8_t ht40_2s_tx_pwr_diff[3]; 962 uint8_t ht20_tx_pwr_diff[3]; 963 uint8_t ofdm_tx_pwr_diff[3]; 964 uint8_t ht40_max_pwr[3]; 965 uint8_t ht20_max_pwr[3]; 966 uint8_t xtal_calib; 967 uint8_t tssi[R92C_MAX_CHAINS]; 968 uint8_t thermal_meter; 969 uint8_t rf_opt1; 970#define R92C_ROM_RF1_REGULATORY_M 0x07 971#define R92C_ROM_RF1_REGULATORY_S 0 972#define R92C_ROM_RF1_BOARD_TYPE_M 0xe0 973#define R92C_ROM_RF1_BOARD_TYPE_S 5 974#define R92C_BOARD_TYPE_DONGLE 0 975#define R92C_BOARD_TYPE_HIGHPA 1 976#define R92C_BOARD_TYPE_MINICARD 2 977#define R92C_BOARD_TYPE_SOLO 3 978#define R92C_BOARD_TYPE_COMBO 4 979 980 uint8_t rf_opt2; 981 uint8_t rf_opt3; 982 uint8_t rf_opt4; 983 uint8_t channel_plan; 984 uint8_t version; 985 uint8_t curstomer_id; 986} __packed; 987 988#define URTWN_EFUSE_MAX_LEN 512 989 990/* Rx MAC descriptor. */ 991struct r92c_rx_stat { 992 uint32_t rxdw0; 993#define R92C_RXDW0_PKTLEN_M 0x00003fff 994#define R92C_RXDW0_PKTLEN_S 0 995#define R92C_RXDW0_CRCERR 0x00004000 996#define R92C_RXDW0_ICVERR 0x00008000 997#define R92C_RXDW0_INFOSZ_M 0x000f0000 998#define R92C_RXDW0_INFOSZ_S 16 999#define R92C_RXDW0_CIPHER_M 0x00700000 1000#define R92C_RXDW0_CIPHER_S 20 1001#define R92C_RXDW0_QOS 0x00800000 1002#define R92C_RXDW0_SHIFT_M 0x03000000 1003#define R92C_RXDW0_SHIFT_S 24 1004#define R92C_RXDW0_PHYST 0x04000000 1005#define R92C_RXDW0_DECRYPTED 0x08000000 1006 1007 uint32_t rxdw1; 1008 uint32_t rxdw2; 1009#define R92C_RXDW2_PKTCNT_M 0x00ff0000 1010#define R92C_RXDW2_PKTCNT_S 16 1011 1012 uint32_t rxdw3; 1013#define R92C_RXDW3_RATE_M 0x0000003f 1014#define R92C_RXDW3_RATE_S 0 1015#define R92C_RXDW3_HT 0x00000040 1016#define R92C_RXDW3_HTC 0x00000400 1017#define R88E_RXDW3_RPT_M 0x0000c000 1018#define R88E_RXDW3_RPT_S 14 1019#define R88E_RXDW3_RPT_RX 0 1020#define R88E_RXDW3_RPT_TX1 1 1021#define R88E_RXDW3_RPT_TX2 2 1022 1023 uint32_t rxdw4; 1024 uint32_t rxdw5; 1025} __packed __attribute__((aligned(4))); 1026 1027/* Rx PHY descriptor. */ 1028struct r92c_rx_phystat { 1029 uint32_t phydw0; 1030 uint32_t phydw1; 1031 uint32_t phydw2; 1032 uint32_t phydw3; 1033 uint32_t phydw4; 1034 uint32_t phydw5; 1035 uint32_t phydw6; 1036 uint32_t phydw7; 1037} __packed __attribute__((aligned(4))); 1038 1039/* Rx PHY CCK descriptor. */ 1040struct r92c_rx_cck { 1041 uint8_t adc_pwdb[4]; 1042 uint8_t sq_rpt; 1043 uint8_t agc_rpt; 1044} __packed; 1045 1046struct r88e_rx_cck { 1047 uint8_t path_agc[2]; 1048 uint8_t chan; 1049 uint8_t reserved1; 1050 uint8_t sig_qual; 1051 uint8_t agc_rpt; 1052 uint8_t rpt_b; 1053 uint8_t reserved2; 1054 uint8_t noise_power; 1055 uint8_t path_cfotail[2]; 1056 uint8_t pcts_mask[2]; 1057 uint8_t stream_rxevm[2]; 1058 uint8_t path_rxsnr[2]; 1059 uint8_t noise_power_db_lsb; 1060 uint8_t reserved3[3]; 1061 uint8_t stream_csi[2]; 1062 uint8_t stream_target_csi[2]; 1063 uint8_t sig_evm; 1064} __packed; 1065 1066/* Tx MAC descriptor. */ 1067struct r92c_tx_desc { 1068 uint32_t txdw0; 1069#define R92C_TXDW0_PKTLEN_M 0x0000ffff 1070#define R92C_TXDW0_PKTLEN_S 0 1071#define R92C_TXDW0_OFFSET_M 0x00ff0000 1072#define R92C_TXDW0_OFFSET_S 16 1073#define R92C_TXDW0_BMCAST 0x01000000 1074#define R92C_TXDW0_LSG 0x04000000 1075#define R92C_TXDW0_FSG 0x08000000 1076#define R92C_TXDW0_OWN 0x80000000 1077 1078 uint32_t txdw1; 1079#define R92C_TXDW1_MACID_M 0x0000001f 1080#define R92C_TXDW1_MACID_S 0 1081#define R88E_TXDW1_MACID_M 0x0000003f 1082#define R88E_TXDW1_MACID_S 0 1083#define R92C_TXDW1_AGGEN 0x00000020 1084#define R92C_TXDW1_AGGBK 0x00000040 1085#define R92C_TXDW1_QSEL_M 0x00001f00 1086#define R92C_TXDW1_QSEL_S 8 1087 1088#define R92C_TXDW1_QSEL_BE 0x00 /* or 0x03 */ 1089#define R92C_TXDW1_QSEL_BK 0x01 /* or 0x02 */ 1090#define R92C_TXDW1_QSEL_VI 0x04 /* or 0x05 */ 1091#define R92C_TXDW1_QSEL_VO 0x06 /* or 0x07 */ 1092#define URTWN_MAX_TID 8 1093 1094#define R92C_TXDW1_QSEL_BEACON 0x10 1095#define R92C_TXDW1_QSEL_MGNT 0x12 1096 1097#define R92C_TXDW1_RAID_M 0x000f0000 1098#define R92C_TXDW1_RAID_S 16 1099#define R92C_TXDW1_CIPHER_M 0x00c00000 1100#define R92C_TXDW1_CIPHER_S 22 1101#define R92C_TXDW1_CIPHER_NONE 0 1102#define R92C_TXDW1_CIPHER_RC4 1 1103#define R92C_TXDW1_CIPHER_AES 3 1104#define R92C_TXDW1_PKTOFF_M 0x7c000000 1105#define R92C_TXDW1_PKTOFF_S 26 1106 1107 uint32_t txdw2; 1108#define R88E_TXDW2_AGGBK 0x00010000 1109#define R88E_TXDW2_CCX_RPT 0x00080000 1110 1111 uint16_t txdw3; 1112 uint16_t txdseq; 1113#define R88E_TXDSEQ_HWSEQ_EN 0x8000 1114 1115 uint32_t txdw4; 1116#define R92C_TXDW4_RTSRATE_M 0x0000003f 1117#define R92C_TXDW4_RTSRATE_S 0 1118#define R92C_TXDW4_HWSEQ_QOS 0x00000040 1119#define R92C_TXDW4_HWSEQ_EN 0x00000080 1120#define R92C_TXDW4_DRVRATE 0x00000100 1121#define R92C_TXDW4_CTS2SELF 0x00000800 1122#define R92C_TXDW4_RTSEN 0x00001000 1123#define R92C_TXDW4_HWRTSEN 0x00002000 1124#define R92C_TXDW4_SCO_M 0x003f0000 1125#define R92C_TXDW4_SCO_S 20 1126#define R92C_TXDW4_SCO_SCA 1 1127#define R92C_TXDW4_SCO_SCB 2 1128#define R92C_TXDW4_40MHZ 0x02000000 1129 1130 uint32_t txdw5; 1131#define R92C_TXDW5_DATARATE_M 0x0000003f 1132#define R92C_TXDW5_DATARATE_S 0 1133#define R92C_TXDW5_SGI 0x00000040 1134#define R92C_TXDW5_AGGNUM_M 0xff000000 1135#define R92C_TXDW5_AGGNUM_S 24 1136 1137 uint32_t txdw6; 1138 uint16_t txdsum; 1139 uint16_t pad; 1140} __packed __attribute__((aligned(4))); 1141 1142struct r88e_tx_rpt_ccx { 1143 uint8_t rptb0; 1144 uint8_t rptb1; 1145#define R88E_RPTB1_MACID_M 0x3f 1146#define R88E_RPTB1_MACID_S 0 1147#define R88E_RPTB1_PKT_OK 0x40 1148#define R88E_RPTB1_BMC 0x80 1149 1150 uint8_t rptb2; 1151#define R88E_RPTB2_RETRY_CNT_M 0x3f 1152#define R88E_RPTB2_RETRY_CNT_S 0 1153#define R88E_RPTB2_LIFE_EXPIRE 0x40 1154#define R88E_RPTB2_RETRY_OVER 0x80 1155 1156 uint8_t rptb3; 1157 uint8_t rptb4; 1158 uint8_t rptb5; 1159 uint8_t rptb6; 1160#define R88E_RPTB6_QSEL_M 0xf0 1161#define R88E_RPTB6_QSEL_S 4 1162 1163 uint8_t rptb7; 1164} __packed; 1165 1166 1167static const uint8_t ridx2rate[] = 1168 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 1169 1170/* HW rate indices. */ 1171#define URTWN_RIDX_CCK1 0 1172#define URTWN_RIDX_CCK11 3 1173#define URTWN_RIDX_OFDM6 4 1174#define URTWN_RIDX_OFDM24 8 1175#define URTWN_RIDX_OFDM54 11 1176 1177#define URTWN_RIDX_COUNT 28 1178 1179 1180/* 1181 * MAC initialization values. 1182 */ 1183static const struct { 1184 uint16_t reg; 1185 uint8_t val; 1186} rtl8188eu_mac[] = { 1187 { 0x026, 0x41 }, { 0x027, 0x35 }, { 0x040, 0x00 }, { 0x428, 0x0a }, 1188 { 0x429, 0x10 }, { 0x430, 0x00 }, { 0x431, 0x01 }, { 0x432, 0x02 }, 1189 { 0x433, 0x04 }, { 0x434, 0x05 }, { 0x435, 0x06 }, { 0x436, 0x07 }, 1190 { 0x437, 0x08 }, { 0x438, 0x00 }, { 0x439, 0x00 }, { 0x43a, 0x01 }, 1191 { 0x43b, 0x02 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, { 0x43e, 0x06 }, 1192 { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, { 0x442, 0x00 }, 1193 { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, { 0x447, 0x00 }, 1194 { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, { 0x45b, 0xb9 }, 1195 { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x480, 0x08 }, { 0x4c8, 0xff }, 1196 { 0x4c9, 0x08 }, { 0x4cc, 0xff }, { 0x4cd, 0xff }, { 0x4ce, 0x01 }, 1197 { 0x4d3, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, { 0x502, 0x2f }, 1198 { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, { 0x506, 0x5e }, 1199 { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, { 0x50a, 0x5e }, 1200 { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, { 0x50e, 0x00 }, 1201 { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, { 0x516, 0x0a }, 1202 { 0x525, 0x4f }, { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 }, 1203 { 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a }, 1204 { 0x620, 0xff }, { 0x621, 0xff }, { 0x622, 0xff }, { 0x623, 0xff }, 1205 { 0x624, 0xff }, { 0x625, 0xff }, { 0x626, 0xff }, { 0x627, 0xff }, 1206 { 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0a }, { 0x63e, 0x0e }, 1207 { 0x63f, 0x0e }, { 0x640, 0x40 }, { 0x66e, 0x05 }, { 0x700, 0x21 }, 1208 { 0x701, 0x43 }, { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 }, 1209 { 0x709, 0x43 }, { 0x70a, 0x65 }, { 0x70b, 0x87 } 1210}, rtl8192cu_mac[] = { 1211 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 }, 1212 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 }, 1213 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 }, 1214 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, 1215 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, 1216 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, 1217 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, 1218 { 0x45b, 0xb9 }, { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x462, 0x08 }, 1219 { 0x463, 0x03 }, { 0x4c8, 0xff }, { 0x4c9, 0x08 }, { 0x4cc, 0xff }, 1220 { 0x4cd, 0xff }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, 1221 { 0x502, 0x2f }, { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, 1222 { 0x506, 0x5e }, { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, 1223 { 0x50a, 0x5e }, { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, 1224 { 0x50e, 0x00 }, { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, 1225 { 0x515, 0x10 }, { 0x516, 0x0a }, { 0x517, 0x10 }, { 0x51a, 0x16 }, 1226 { 0x524, 0x0f }, { 0x525, 0x4f }, { 0x546, 0x40 }, { 0x547, 0x00 }, 1227 { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 }, { 0x55a, 0x02 }, 1228 { 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a }, 1229 { 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0e }, { 0x63e, 0x0a }, 1230 { 0x63f, 0x0e }, { 0x66e, 0x05 }, { 0x700, 0x21 }, { 0x701, 0x43 }, 1231 { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 }, { 0x709, 0x43 }, 1232 { 0x70a, 0x65 }, { 0x70b, 0x87 } 1233}; 1234 1235/* 1236 * Baseband initialization values. 1237 */ 1238struct urtwn_bb_prog { 1239 int count; 1240 const uint16_t *regs; 1241 const uint32_t *vals; 1242 int agccount; 1243 const uint32_t *agcvals; 1244}; 1245 1246/* 1247 * RTL8192CU and RTL8192CE-VAU. 1248 */ 1249static const uint16_t rtl8192ce_bb_regs[] = { 1250 0x024, 0x028, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 1251 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 1252 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860, 1253 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884, 1254 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 0x908, 1255 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 1256 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 0xc08, 1257 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 0xc2c, 1258 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 1259 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 1260 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 1261 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 1262 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 0xce0, 1263 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 0xd14, 1264 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 0xd48, 1265 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 0xd6c, 1266 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 1267 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 1268 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 1269 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, 1270 0xed8, 0xedc, 0xee0, 0xeec, 0xf14, 0xf4c, 0xf00 1271}; 1272 1273static const uint32_t rtl8192ce_bb_vals[] = { 1274 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1275 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1276 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1277 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1278 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1279 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1280 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1281 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1282 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1283 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1284 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1285 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1286 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1287 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1288 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1289 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1290 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1291 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1292 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1293 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1294 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1295 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1296 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1297 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1298 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1299 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1300 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1301 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1302 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1303 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1304 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1305 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1306 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1307 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1308 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1309 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1310 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1311 0x00000000, 0x00000300 1312}; 1313 1314static const uint32_t rtl8192ce_agc_vals[] = { 1315 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1316 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1317 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1318 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1319 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1320 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1321 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1322 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1323 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1324 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1325 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1326 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1327 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1328 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1329 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1330 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1331 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1332 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1333 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1334 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1335 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1336 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1337 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1338 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1339 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1340 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1341 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1342 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1343 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1344 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1345 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1346 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1347}; 1348 1349static const struct urtwn_bb_prog rtl8192ce_bb_prog = { 1350 nitems(rtl8192ce_bb_regs), 1351 rtl8192ce_bb_regs, 1352 rtl8192ce_bb_vals, 1353 nitems(rtl8192ce_agc_vals), 1354 rtl8192ce_agc_vals 1355}; 1356 1357/* 1358 * RTL8188CU. 1359 */ 1360static const uint32_t rtl8192cu_bb_vals[] = { 1361 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1362 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1363 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1364 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1365 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1366 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1367 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1368 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1369 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1370 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1371 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1372 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1373 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1374 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1375 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1376 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1377 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1378 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x0186115b, 1379 0x0000001f, 0x00b99612, 0x40000100, 0x20f60000, 0x40000100, 1380 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1381 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1382 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1383 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1384 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1385 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1386 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1387 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1388 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1389 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1390 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1391 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1392 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1393 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1394 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1395 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1396 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1397 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1398 0x00000000, 0x00000300 1399}; 1400 1401static const struct urtwn_bb_prog rtl8192cu_bb_prog = { 1402 nitems(rtl8192ce_bb_regs), 1403 rtl8192ce_bb_regs, 1404 rtl8192cu_bb_vals, 1405 nitems(rtl8192ce_agc_vals), 1406 rtl8192ce_agc_vals 1407}; 1408 1409/* 1410 * RTL8188CE-VAU. 1411 */ 1412static const uint32_t rtl8188ce_bb_vals[] = { 1413 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1414 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1415 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1416 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1417 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1418 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1419 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1420 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1421 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1422 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1423 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1424 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1425 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1426 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1427 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1428 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1429 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1430 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1431 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1432 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1433 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1434 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1435 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1436 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1437 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1438 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1439 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1440 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1441 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1442 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1443 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1444 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1445 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1446 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1447 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1448 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1449 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1450 0x00000000, 0x00000300 1451}; 1452 1453static const uint32_t rtl8188ce_agc_vals[] = { 1454 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1455 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1456 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1457 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1458 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1459 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1460 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1461 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1462 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1463 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1464 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1465 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1466 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1467 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1468 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1469 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1470 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1471 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1472 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1473 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1474 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1475 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1476 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1477 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1478 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1479 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1480 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1481 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1482 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1483 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1484 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1485 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1486}; 1487 1488static const struct urtwn_bb_prog rtl8188ce_bb_prog = { 1489 nitems(rtl8192ce_bb_regs), 1490 rtl8192ce_bb_regs, 1491 rtl8188ce_bb_vals, 1492 nitems(rtl8188ce_agc_vals), 1493 rtl8188ce_agc_vals 1494}; 1495 1496static const uint32_t rtl8188cu_bb_vals[] = { 1497 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1498 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1499 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1500 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1501 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1502 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1503 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1504 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1505 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1506 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1507 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1508 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1509 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1510 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1511 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1512 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1513 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1514 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1515 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1516 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1517 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1518 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1519 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1520 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1521 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1522 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1523 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1524 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1525 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1526 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1527 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1528 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1529 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1530 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1531 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1532 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1533 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1534 0x00000000, 0x00000300 1535}; 1536 1537static const struct urtwn_bb_prog rtl8188cu_bb_prog = { 1538 nitems(rtl8192ce_bb_regs), 1539 rtl8192ce_bb_regs, 1540 rtl8188cu_bb_vals, 1541 nitems(rtl8188ce_agc_vals), 1542 rtl8188ce_agc_vals 1543}; 1544 1545/* 1546 * RTL8188EU. 1547 */ 1548static const uint16_t rtl8188eu_bb_regs[] = { 1549 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 0x81c, 1550 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 1551 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 1552 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 1553 0x880, 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 1554 0x900, 0x904, 0x908, 0x90c, 0x910, 0x914, 0xa00, 0xa04, 1555 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 0xa20, 0xa24, 1556 0xa28, 0xa2c, 0xa70, 0xa74, 0xa78, 0xa7c, 0xa80, 0xb2c, 1557 0xc00, 0xc04, 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 1558 0xc20, 0xc24, 0xc28, 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 1559 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 0xc54, 0xc58, 0xc5c, 1560 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 0xc78, 0xc7c, 1561 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 0xc9c, 1562 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 1563 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 1564 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 1565 0xd10, 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 1566 0xd40, 0xd44, 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 1567 0xd60, 0xd64, 0xd68, 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 1568 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 0xe1c, 0xe28, 0xe30, 1569 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 0xe4c, 0xe50, 1570 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 0xe74, 1571 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, 1572 0xed8, 0xedc, 0xee0, 0xee8, 0xeec, 0xf14, 0xf4c, 0xf00 1573}; 1574 1575static const uint32_t rtl8188eu_bb_vals[] = { 1576 0x80040000, 0x00000003, 0x0000fc00, 0x0000000a, 0x10001331, 1577 0x020c3d10, 0x02200385, 0x00000000, 0x01000100, 0x00390204, 1578 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1579 0x00000000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, 1580 0x00000000, 0x00000000, 0x569a11a9, 0x01000014, 0x66f60110, 1581 0x061f0649, 0x00000000, 0x27272700, 0x07000760, 0x25004000, 1582 0x00000808, 0x00000000, 0xb0000c1c, 0x00000001, 0x00000000, 1583 0xccc000c0, 0x00000800, 0xfffffffe, 0x40302010, 0x00706050, 1584 0x00000000, 0x00000023, 0x00000000, 0x81121111, 0x00000002, 1585 0x00000201, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e7f120f, 1586 0x9500bb78, 0x1114d028, 0x00881117, 0x89140f00, 0x1a1b0000, 1587 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1588 0x00000900, 0x225b0606, 0x218075b1, 0x80000000, 0x48071d40, 1589 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 0x40000100, 1590 0x08800000, 0x40000100, 0x00000000, 0x00000000, 0x00000000, 1591 0x00000000, 0x69e9ac47, 0x469652af, 0x49795994, 0x0a97971c, 1592 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 0x69553420, 1593 0x43bc0094, 0x00013169, 0x00250492, 0x00000000, 0x7112848b, 1594 0x47c00bff, 0x00000036, 0x2c7f000d, 0x020610db, 0x0000001f, 1595 0x00b91612, 0x390000e4, 0x20f60000, 0x40000100, 0x20200000, 1596 0x00091521, 0x00000000, 0x00121820, 0x00007f7f, 0x00000000, 1597 0x000300a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1598 0x00000000, 0x28000000, 0x00000000, 0x00000000, 0x00000000, 1599 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 0x00766932, 1600 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 0x00000740, 1601 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 0x3333bc43, 1602 0x7a8f5b6f, 0xcc979975, 0x00000000, 0x80608000, 0x00000000, 1603 0x00127353, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1604 0x6437140a, 0x00000000, 0x00000282, 0x30032064, 0x4653de68, 1605 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 0x322c2220, 1606 0x000e3c24, 0x2d2d2d2d, 0x2d2d2d2d, 0x0390272d, 0x2d2d2d2d, 1607 0x2d2d2d2d, 0x2d2d2d2d, 0x2d2d2d2d, 0x00000000, 0x1000dc1f, 1608 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 0x01004800, 1609 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 0x02140102, 1610 0x28160d05, 0x00000008, 0x001b25a4, 0x00c00014, 0x00c00014, 1611 0x01000014, 0x01000014, 0x01000014, 0x01000014, 0x00c00014, 1612 0x01000014, 0x00c00014, 0x00c00014, 0x00c00014, 0x00c00014, 1613 0x00000014, 0x00000014, 0x21555448, 0x01c00014, 0x00000003, 1614 0x00000000, 0x00000300 1615}; 1616 1617static const uint32_t rtl8188eu_agc_vals[] = { 1618 0xfb000001, 0xfb010001, 0xfb020001, 0xfb030001, 0xfb040001, 1619 0xfb050001, 0xfa060001, 0xf9070001, 0xf8080001, 0xf7090001, 1620 0xf60a0001, 0xf50b0001, 0xf40c0001, 0xf30d0001, 0xf20e0001, 1621 0xf10f0001, 0xf0100001, 0xef110001, 0xee120001, 0xed130001, 1622 0xec140001, 0xeb150001, 0xea160001, 0xe9170001, 0xe8180001, 1623 0xe7190001, 0xe61a0001, 0xe51b0001, 0xe41c0001, 0xe31d0001, 1624 0xe21e0001, 0xe11f0001, 0x8a200001, 0x89210001, 0x88220001, 1625 0x87230001, 0x86240001, 0x85250001, 0x84260001, 0x83270001, 1626 0x82280001, 0x6b290001, 0x6a2a0001, 0x692b0001, 0x682c0001, 1627 0x672d0001, 0x662e0001, 0x652f0001, 0x64300001, 0x63310001, 1628 0x62320001, 0x61330001, 0x46340001, 0x45350001, 0x44360001, 1629 0x43370001, 0x42380001, 0x41390001, 0x403a0001, 0x403b0001, 1630 0x403c0001, 0x403d0001, 0x403e0001, 0x403f0001, 0xfb400001, 1631 0xfb410001, 0xfb420001, 0xfb430001, 0xfb440001, 0xfb450001, 1632 0xfb460001, 0xfb470001, 0xfb480001, 0xfa490001, 0xf94a0001, 1633 0xf84B0001, 0xf74c0001, 0xf64d0001, 0xf54e0001, 0xf44f0001, 1634 0xf3500001, 0xf2510001, 0xf1520001, 0xf0530001, 0xef540001, 1635 0xee550001, 0xed560001, 0xec570001, 0xeb580001, 0xea590001, 1636 0xe95a0001, 0xe85b0001, 0xe75c0001, 0xe65d0001, 0xe55e0001, 1637 0xe45f0001, 0xe3600001, 0xe2610001, 0xc3620001, 0xc2630001, 1638 0xc1640001, 0x8b650001, 0x8a660001, 0x89670001, 0x88680001, 1639 0x87690001, 0x866a0001, 0x856b0001, 0x846c0001, 0x676d0001, 1640 0x666e0001, 0x656f0001, 0x64700001, 0x63710001, 0x62720001, 1641 0x61730001, 0x60740001, 0x46750001, 0x45760001, 0x44770001, 1642 0x43780001, 0x42790001, 0x417a0001, 0x407b0001, 0x407c0001, 1643 0x407d0001, 0x407e0001, 0x407f0001 1644}; 1645 1646static const struct urtwn_bb_prog rtl8188eu_bb_prog = { 1647 nitems(rtl8188eu_bb_regs), 1648 rtl8188eu_bb_regs, 1649 rtl8188eu_bb_vals, 1650 nitems(rtl8188eu_agc_vals), 1651 rtl8188eu_agc_vals 1652}; 1653 1654/* 1655 * RTL8188RU. 1656 */ 1657static const uint16_t rtl8188ru_bb_regs[] = { 1658 0x024, 0x028, 0x040, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 1659 0x818, 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 1660 0x83c, 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 1661 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 1662 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 1663 0x908, 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 1664 0xa1c, 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 1665 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 1666 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 1667 0xc50, 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 1668 0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 1669 0xc98, 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 1670 0xcbc, 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 1671 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 1672 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 1673 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 1674 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 1675 0xe18, 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 1676 0xe48, 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 1677 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 1678 0xed4, 0xed8, 0xedc, 0xee0, 0xeec, 0xee8, 0xf14, 0xf4c, 0xf00 1679}; 1680 1681static const uint32_t rtl8188ru_bb_vals[] = { 1682 0x0011800d, 0x00ffdb83, 0x000c0004, 0x80040000, 0x00000001, 1683 0x0000fc00, 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 1684 0x00000000, 0x01000100, 0x00390204, 0x00000000, 0x00000000, 1685 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010000, 1686 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1687 0x569a569a, 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 1688 0x32323200, 0x03000300, 0x22004000, 0x00000808, 0x00ffc3f1, 1689 0xc0083070, 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 1690 0xfffffffe, 0x40302010, 0x00706050, 0x00000000, 0x00000023, 1691 0x00000000, 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 1692 0x2e68120f, 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 1693 0x15160000, 0x070b0f12, 0x00000104, 0x00d30000, 0x101fbf00, 1694 0x00000007, 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 1695 0x08800000, 0x40000100, 0x08800000, 0x40000100, 0x00000000, 1696 0x00000000, 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 1697 0x49795994, 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 1698 0x007f037f, 0x6954342e, 0x43bc0094, 0x6954342f, 0x433c0094, 1699 0x00000000, 0x5116848b, 0x47c00bff, 0x00000036, 0x2c56000d, 1700 0x018610db, 0x0000001f, 0x00b91612, 0x24000090, 0x20f60000, 1701 0x24000090, 0x20200000, 0x00121820, 0x00000000, 0x00121820, 1702 0x00007f7f, 0x00000000, 0x00000080, 0x00000000, 0x00000000, 1703 0x00000000, 0x00000000, 0x00000000, 0x28000000, 0x00000000, 1704 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1705 0x64b22427, 0x00766932, 0x00222222, 0x00000000, 0x37644302, 1706 0x2f97d40c, 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 1707 0xa0633333, 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 1708 0x80608000, 0x00000000, 0x00027293, 0x00000000, 0x00000000, 1709 0x00000000, 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 1710 0x30032064, 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 1711 0x1812362e, 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 1712 0x03902a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 1713 0x00000000, 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 1714 0x01007c00, 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 1715 0x10008c1f, 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 1716 0x631b25a0, 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1717 0x081b25a0, 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 1718 0x631b25a0, 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 1719 0x31555448, 0x00000003, 0x00000000, 0x00000300 1720}; 1721 1722static const uint32_t rtl8188ru_agc_vals[] = { 1723 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1724 0x7b050001, 0x7b060001, 0x7b070001, 0x7b080001, 0x7a090001, 1725 0x790a0001, 0x780b0001, 0x770c0001, 0x760d0001, 0x750e0001, 1726 0x740f0001, 0x73100001, 0x72110001, 0x71120001, 0x70130001, 1727 0x6f140001, 0x6e150001, 0x6d160001, 0x6c170001, 0x6b180001, 1728 0x6a190001, 0x691a0001, 0x681b0001, 0x671c0001, 0x661d0001, 1729 0x651e0001, 0x641f0001, 0x63200001, 0x62210001, 0x61220001, 1730 0x60230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1731 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1732 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1733 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1734 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1735 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1736 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1737 0x7b460001, 0x7b470001, 0x7b480001, 0x7a490001, 0x794a0001, 1738 0x784b0001, 0x774c0001, 0x764d0001, 0x754e0001, 0x744f0001, 1739 0x73500001, 0x72510001, 0x71520001, 0x70530001, 0x6f540001, 1740 0x6e550001, 0x6d560001, 0x6c570001, 0x6b580001, 0x6a590001, 1741 0x695a0001, 0x685b0001, 0x675c0001, 0x665d0001, 0x655e0001, 1742 0x645f0001, 0x63600001, 0x62610001, 0x61620001, 0x60630001, 1743 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1744 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1745 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1746 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1747 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1748 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1749 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1750 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1751 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1752 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1753 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1754 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1755}; 1756 1757static const struct urtwn_bb_prog rtl8188ru_bb_prog = { 1758 nitems(rtl8188ru_bb_regs), 1759 rtl8188ru_bb_regs, 1760 rtl8188ru_bb_vals, 1761 nitems(rtl8188ru_agc_vals), 1762 rtl8188ru_agc_vals 1763}; 1764 1765/* 1766 * RF initialization values. 1767 */ 1768struct urtwn_rf_prog { 1769 int count; 1770 const uint8_t *regs; 1771 const uint32_t *vals; 1772}; 1773 1774/* 1775 * RTL8192CU and RTL8192CE-VAU. 1776 */ 1777static const uint8_t rtl8192ce_rf1_regs[] = { 1778 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 1779 0x0f, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 1780 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2a, 0x2b, 1781 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 1782 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 1783 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 1784 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 1785 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 1786 0x2c, 0x2a, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 1787 0x11, 0x10, 0x11, 0x10, 0x11, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 1788 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 1789 0x14, 0x14, 0x15, 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16, 0x00, 1790 0x18, 0xfe, 0xfe, 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 1791}; 1792 1793static const uint32_t rtl8192ce_rf1_vals[] = { 1794 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1795 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1796 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1797 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 1798 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1799 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1800 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1801 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1802 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1803 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1804 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1805 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1806 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1807 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1808 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1809 0x71000, 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 1810 0x18493, 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 1811 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 1812 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1813 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1814 0x30159 1815}; 1816 1817static const uint8_t rtl8192ce_rf2_regs[] = { 1818 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 1819 0x0f, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 1820 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 0x14, 0x14, 0x15, 0x15, 1821 0x15, 0x15, 0x16, 0x16, 0x16, 0x16 1822}; 1823 1824static const uint32_t rtl8192ce_rf2_vals[] = { 1825 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1826 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x32000, 0x71000, 1827 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 0x18493, 1828 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 0x1944c, 1829 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 0xcf424, 1830 0xe0330, 0xa0330, 0x60330, 0x20330 1831}; 1832 1833static const struct urtwn_rf_prog rtl8192ce_rf_prog[] = { 1834 { 1835 nitems(rtl8192ce_rf1_regs), 1836 rtl8192ce_rf1_regs, 1837 rtl8192ce_rf1_vals 1838 }, 1839 { 1840 nitems(rtl8192ce_rf2_regs), 1841 rtl8192ce_rf2_regs, 1842 rtl8192ce_rf2_vals 1843 } 1844}; 1845 1846/* 1847 * RTL8188CE-VAU. 1848 */ 1849static const uint32_t rtl8188ce_rf_vals[] = { 1850 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1851 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1852 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1853 0x00000, 0x01558, 0x00060, 0x00483, 0x4f200, 0xec7d9, 0x577c0, 1854 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1855 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1856 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1857 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1858 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1859 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1860 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1861 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1862 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1863 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1864 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1865 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 1866 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 1867 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 1868 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1869 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1870 0x30159 1871}; 1872 1873static const struct urtwn_rf_prog rtl8188ce_rf_prog[] = { 1874 { 1875 nitems(rtl8192ce_rf1_regs), 1876 rtl8192ce_rf1_regs, 1877 rtl8188ce_rf_vals 1878 } 1879}; 1880 1881 1882/* 1883 * RTL8188CU. 1884 */ 1885static const uint32_t rtl8188cu_rf_vals[] = { 1886 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1887 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1888 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1889 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 1890 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1891 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1892 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1893 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1894 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1895 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1896 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1897 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1898 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1899 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1900 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1901 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 1902 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 1903 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 1904 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1905 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1906 0x30159 1907}; 1908 1909static const struct urtwn_rf_prog rtl8188cu_rf_prog[] = { 1910 { 1911 nitems(rtl8192ce_rf1_regs), 1912 rtl8192ce_rf1_regs, 1913 rtl8188cu_rf_vals 1914 } 1915}; 1916 1917/* 1918 * RTL8188EU. 1919 */ 1920static const uint8_t rtl8188eu_rf_regs[] = { 1921 0x00, 0x08, 0x18, 0x19, 0x1e, 0x1f, 0x2f, 0x3f, 0x42, 0x57, 1922 0x58, 0x67, 0x83, 0xb0, 0xb1, 0xb2, 0xb4, 0xb6, 0xb7, 0xb8, 1923 0xb9, 0xba, 0xbb, 0xbf, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 1924 0xc8, 0xc9, 0xca, 0xdf, 0xef, 0x51, 0x52, 0x53, 0x56, 1925 0x35, 0x35, 0x35, 0x36, 0x36, 0x36, 0x36, 0xb6, 0x18, 0x5a, 1926 0x19, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 1927 0x34, 0x34, 0x00, 0x84, 0x86, 0x87, 0x8e, 0x8f, 0xef, 0x3b, 1928 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 1929 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0xef, 0x00, 0x18, 0xfe, 0xfe, 1930 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 1931}; 1932 1933static const uint32_t rtl8188eu_rf_vals[] = { 1934 0x30000, 0x84000, 0x00407, 0x00012, 0x80009, 0x00880, 0x1a060, 1935 0x00000, 0x060c0, 0xd0000, 0xbe180, 0x01552, 0x00000, 0xff8fc, 1936 0x54400, 0xccc19, 0x43003, 0x4953e, 0x1c718, 0x060ff, 0x80001, 1937 0x40000, 0x00400, 0xc0000, 0x02400, 0x00009, 0x40c91, 0x99999, 1938 0x000a3, 0x88820, 0x76c06, 0x00000, 0x80000, 0x00180, 0x001a0, 1939 0x6b27d, 0x7e49d, 0x00073, 0x51ff3, 0x00086, 0x00186, 1940 0x00286, 0x01c25, 0x09c25, 0x11c25, 0x19c25, 0x48538, 0x00c07, 1941 0x4bd00, 0x739d0, 0x0adf3, 0x09df0, 0x08ded, 0x07dea, 0x06de7, 1942 0x054ee, 0x044eb, 0x034e8, 0x0246b, 0x01468, 0x0006d, 0x30159, 1943 0x68200, 0x000ce, 0x48a00, 0x65540, 0x88000, 0x020a0, 0xf02b0, 1944 0xef7b0, 0xd4fb0, 0xcf060, 0xb0090, 0xa0080, 0x90080, 0x8f780, 1945 0x722b0, 0x6f7b0, 0x54fb0, 0x4f060, 0x30090, 0x20080, 0x10080, 1946 0x0f780, 0x000a0, 0x10159, 0x0f407, 0x00000, 0x00000, 0x80003, 1947 0x00000, 0x00000, 0x00001, 0x80000, 0x33e60 1948}; 1949 1950static const struct urtwn_rf_prog rtl8188eu_rf_prog[] = { 1951 { 1952 nitems(rtl8188eu_rf_regs), 1953 rtl8188eu_rf_regs, 1954 rtl8188eu_rf_vals 1955 } 1956}; 1957 1958/* 1959 * RTL8188RU. 1960 */ 1961static const uint32_t rtl8188ru_rf_vals[] = { 1962 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb0, 1963 0x54867, 0x8992e, 0x0e529, 0x39ce7, 0x00451, 0x00000, 0x00255, 1964 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1965 0x0083c, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x977c0, 1966 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1967 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1968 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1969 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1970 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1971 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1972 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1973 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1974 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1975 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1976 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0xd8000, 1977 0x90000, 0x51000, 0x12000, 0x28fb4, 0x24fa8, 0x207a4, 0x1c798, 1978 0x183a4, 0x14398, 0x101a4, 0x0c198, 0x080a4, 0x04098, 0x00014, 1979 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 1980 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1981 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1982 0x30159 1983}; 1984 1985static const struct urtwn_rf_prog rtl8188ru_rf_prog[] = { 1986 { 1987 nitems(rtl8192ce_rf1_regs), 1988 rtl8192ce_rf1_regs, 1989 rtl8188ru_rf_vals 1990 } 1991}; 1992 1993struct urtwn_txpwr { 1994 uint8_t pwr[3][28]; 1995}; 1996 1997struct urtwn_r88e_txpwr { 1998 uint8_t pwr[6][28]; 1999}; 2000 2001/* 2002 * Per RF chain/group/rate Tx gain values. 2003 */ 2004static const struct urtwn_txpwr rtl8192cu_txagc[] = { 2005 { { /* Chain 0. */ 2006 { /* Group 0. */ 2007 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2008 0x0c, 0x0c, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* OFDM6~54. */ 2009 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* MCS0~7. */ 2010 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02 /* MCS8~15. */ 2011 }, 2012 { /* Group 1. */ 2013 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2014 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2015 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2016 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2017 }, 2018 { /* Group 2. */ 2019 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2020 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ 2021 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2022 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2023 } 2024 } }, 2025 { { /* Chain 1. */ 2026 { /* Group 0. */ 2027 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2028 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2029 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2030 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2031 }, 2032 { /* Group 1. */ 2033 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2034 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2035 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2036 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2037 }, 2038 { /* Group 2. */ 2039 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2040 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ 2041 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2042 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2043 } 2044 } } 2045}; 2046 2047static const struct urtwn_txpwr rtl8188ru_txagc[] = { 2048 { { /* Chain 0. */ 2049 { /* Group 0. */ 2050 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2051 0x08, 0x08, 0x08, 0x06, 0x06, 0x04, 0x04, 0x00, /* OFDM6~54. */ 2052 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00, /* MCS0~7. */ 2053 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00 /* MCS8~15. */ 2054 }, 2055 { /* Group 1. */ 2056 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2057 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2058 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2059 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2060 }, 2061 { /* Group 2. */ 2062 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2063 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2064 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2065 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2066 } 2067 } } 2068}; 2069 2070static const struct urtwn_r88e_txpwr rtl8188eu_txagc[] = { 2071 { { /* Chain 0. */ 2072 { /* Group 0. */ 2073 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2074 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2075 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2076 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2077 }, 2078 { /* Group 1. */ 2079 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2080 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2081 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2082 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2083 }, 2084 { /* Group 2. */ 2085 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2086 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2087 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2088 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2089 }, 2090 { /* Group 3. */ 2091 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2092 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2093 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2094 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2095 }, 2096 { /* Group 4. */ 2097 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2098 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2099 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2100 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2101 }, 2102 { /* Group 5. */ 2103 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2104 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2105 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2106 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2107 } 2108 } } 2109}; 2110