if_urtwnreg.h revision 290632
1/*- 2 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 * 16 * $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $ 17 * $FreeBSD: head/sys/dev/usb/wlan/if_urtwnreg.h 290632 2015-11-10 00:42:32Z avos $ 18 */ 19 20#define URTWN_CONFIG_INDEX 0 21#define URTWN_IFACE_INDEX 0 22 23#define URTWN_NOISE_FLOOR -95 24 25#define R92C_MAX_CHAINS 2 26 27/* Maximum number of output pipes is 3. */ 28#define R92C_MAX_EPOUT 3 29 30#define R92C_MAX_TX_PWR 0x3f 31 32#define R92C_PUBQ_NPAGES 231 33#define R92C_TXPKTBUF_COUNT 256 34#define R92C_TX_PAGE_COUNT 248 35#define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 36#define R88E_TXPKTBUF_COUNT 177 37#define R88E_TX_PAGE_COUNT 169 38#define R88E_TX_PAGE_BOUNDARY (R88E_TX_PAGE_COUNT + 1) 39 40#define R92C_H2C_NBOX 4 41 42/* USB Requests. */ 43#define R92C_REQ_REGS 0x05 44 45/* 46 * MAC registers. 47 */ 48/* System Configuration. */ 49#define R92C_SYS_ISO_CTRL 0x000 50#define R92C_SYS_FUNC_EN 0x002 51#define R92C_APS_FSMCO 0x004 52#define R92C_SYS_CLKR 0x008 53#define R92C_AFE_MISC 0x010 54#define R92C_SPS0_CTRL 0x011 55#define R92C_SPS_OCP_CFG 0x018 56#define R92C_RSV_CTRL 0x01c 57#define R92C_RF_CTRL 0x01f 58#define R92C_LDOA15_CTRL 0x020 59#define R92C_LDOV12D_CTRL 0x021 60#define R92C_LDOHCI12_CTRL 0x022 61#define R92C_LPLDO_CTRL 0x023 62#define R92C_AFE_XTAL_CTRL 0x024 63#define R92C_AFE_PLL_CTRL 0x028 64#define R92C_EFUSE_CTRL 0x030 65#define R92C_EFUSE_TEST 0x034 66#define R92C_PWR_DATA 0x038 67#define R92C_CAL_TIMER 0x03c 68#define R92C_ACLK_MON 0x03e 69#define R92C_GPIO_MUXCFG 0x040 70#define R92C_GPIO_IO_SEL 0x042 71#define R92C_MAC_PINMUX_CFG 0x043 72#define R92C_GPIO_PIN_CTRL 0x044 73#define R92C_GPIO_INTM 0x048 74#define R92C_LEDCFG0 0x04c 75#define R92C_LEDCFG1 0x04d 76#define R92C_LEDCFG2 0x04e 77#define R92C_LEDCFG3 0x04f 78#define R92C_FSIMR 0x050 79#define R92C_FSISR 0x054 80#define R92C_HSIMR 0x058 81#define R92C_HSISR 0x05c 82#define R92C_MCUFWDL 0x080 83#define R92C_HMEBOX_EXT(idx) (0x088 + (idx) * 2) 84#define R88E_HIMR 0x0b0 85#define R88E_HISR 0x0b4 86#define R88E_HIMRE 0x0b8 87#define R88E_HISRE 0x0bc 88#define R92C_EFUSE_ACCESS 0x0cf 89#define R92C_BIST_SCAN 0x0d0 90#define R92C_BIST_RPT 0x0d4 91#define R92C_BIST_ROM_RPT 0x0d8 92#define R92C_USB_SIE_INTF 0x0e0 93#define R92C_PCIE_MIO_INTF 0x0e4 94#define R92C_PCIE_MIO_INTD 0x0e8 95#define R92C_HPON_FSM 0x0ec 96#define R92C_SYS_CFG 0x0f0 97/* MAC General Configuration. */ 98#define R92C_CR 0x100 99#define R92C_MSR 0x102 100#define R92C_PBP 0x104 101#define R92C_TRXDMA_CTRL 0x10c 102#define R92C_TRXFF_BNDY 0x114 103#define R92C_TRXFF_STATUS 0x118 104#define R92C_RXFF_PTR 0x11c 105#define R92C_HIMR 0x120 106#define R92C_HISR 0x124 107#define R92C_HIMRE 0x128 108#define R92C_HISRE 0x12c 109#define R92C_CPWM 0x12f 110#define R92C_FWIMR 0x130 111#define R92C_FWISR 0x134 112#define R92C_PKTBUF_DBG_CTRL 0x140 113#define R92C_PKTBUF_DBG_DATA_L 0x144 114#define R92C_PKTBUF_DBG_DATA_H 0x148 115#define R92C_TC0_CTRL(i) (0x150 + (i) * 4) 116#define R92C_TCUNIT_BASE 0x164 117#define R92C_MBIST_START 0x174 118#define R92C_MBIST_DONE 0x178 119#define R92C_MBIST_FAIL 0x17c 120#define R92C_C2HEVT_MSG_NORMAL 0x1a0 121#define R92C_C2HEVT_MSG_TEST 0x1b8 122#define R92C_C2HEVT_CLEAR 0x1bf 123#define R92C_MCUTST_1 0x1c0 124#define R92C_FMETHR 0x1c8 125#define R92C_HMETFR 0x1cc 126#define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4) 127#define R92C_LLT_INIT 0x1e0 128#define R92C_BB_ACCESS_CTRL 0x1e8 129#define R92C_BB_ACCESS_DATA 0x1ec 130#define R88E_HMEBOX_EXT(idx) (0x1f0 + (idx) * 4) 131/* Tx DMA Configuration. */ 132#define R92C_RQPN 0x200 133#define R92C_FIFOPAGE 0x204 134#define R92C_TDECTRL 0x208 135#define R92C_TXDMA_OFFSET_CHK 0x20c 136#define R92C_TXDMA_STATUS 0x210 137#define R92C_RQPN_NPQ 0x214 138/* Rx DMA Configuration. */ 139#define R92C_RXDMA_AGG_PG_TH 0x280 140#define R92C_RXPKT_NUM 0x284 141#define R92C_RXDMA_STATUS 0x288 142/* Protocol Configuration. */ 143#define R92C_FWHW_TXQ_CTRL 0x420 144#define R92C_HWSEQ_CTRL 0x423 145#define R92C_TXPKTBUF_BCNQ_BDNY 0x424 146#define R92C_TXPKTBUF_MGQ_BDNY 0x425 147#define R92C_SPEC_SIFS 0x428 148#define R92C_RL 0x42a 149#define R92C_DARFRC 0x430 150#define R92C_RARFRC 0x438 151#define R92C_RRSR 0x440 152#define R92C_ARFR(i) (0x444 + (i) * 4) 153#define R92C_AGGLEN_LMT 0x458 154#define R92C_AMPDU_MIN_SPACE 0x45c 155#define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d 156#define R92C_FAST_EDCA_CTRL 0x460 157#define R92C_RD_RESP_PKT_TH 0x463 158#define R92C_INIRTS_RATE_SEL 0x480 159#define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid)) 160#define R92C_MAX_AGGR_NUM 0x4ca 161/* EDCA Configuration. */ 162#define R92C_EDCA_VO_PARAM 0x500 163#define R92C_EDCA_VI_PARAM 0x504 164#define R92C_EDCA_BE_PARAM 0x508 165#define R92C_EDCA_BK_PARAM 0x50c 166#define R92C_BCNTCFG 0x510 167#define R92C_PIFS 0x512 168#define R92C_RDG_PIFS 0x513 169#define R92C_SIFS_CCK 0x514 170#define R92C_SIFS_OFDM 0x516 171#define R92C_AGGR_BREAK_TIME 0x51a 172#define R92C_SLOT 0x51b 173#define R92C_TX_PTCL_CTRL 0x520 174#define R92C_TXPAUSE 0x522 175#define R92C_DIS_TXREQ_CLR 0x523 176#define R92C_RD_CTRL 0x524 177#define R92C_TBTT_PROHIBIT 0x540 178#define R92C_RD_NAV_NXT 0x544 179#define R92C_NAV_PROT_LEN 0x546 180#define R92C_BCN_CTRL 0x550 181#define R92C_MBID_NUM 0x552 182#define R92C_DUAL_TSF_RST 0x553 183#define R92C_BCN_INTERVAL 0x554 184#define R92C_DRVERLYINT 0x558 185#define R92C_BCNDMATIM 0x559 186#define R92C_ATIMWND 0x55a 187#define R92C_USTIME_TSF 0x55c 188#define R92C_BCN_MAX_ERR 0x55d 189#define R92C_RXTSF_OFFSET_CCK 0x55e 190#define R92C_RXTSF_OFFSET_OFDM 0x55f 191#define R92C_TSFTR 0x560 192#define R92C_INIT_TSFTR 0x564 193#define R92C_PSTIMER 0x580 194#define R92C_TIMER0 0x584 195#define R92C_TIMER1 0x588 196#define R92C_ACMHWCTRL 0x5c0 197#define R92C_ACMRSTCTRL 0x5c1 198#define R92C_ACMAVG 0x5c2 199#define R92C_VO_ADMTIME 0x5c4 200#define R92C_VI_ADMTIME 0x5c6 201#define R92C_BE_ADMTIME 0x5c8 202#define R92C_EDCA_RANDOM_GEN 0x5cc 203#define R92C_SCH_TXCMD 0x5d0 204/* WMAC Configuration. */ 205#define R92C_APSD_CTRL 0x600 206#define R92C_BWOPMODE 0x603 207#define R92C_RCR 0x608 208#define R92C_RX_DRVINFO_SZ 0x60f 209#define R92C_MACID 0x610 210#define R92C_BSSID 0x618 211#define R92C_MAR 0x620 212#define R92C_MAC_SPEC_SIFS 0x63a 213#define R92C_R2T_SIFS 0x63c 214#define R92C_T2T_SIFS 0x63e 215#define R92C_ACKTO 0x640 216#define R92C_CAMCMD 0x670 217#define R92C_CAMWRITE 0x674 218#define R92C_CAMREAD 0x678 219#define R92C_CAMDBG 0x67c 220#define R92C_SECCFG 0x680 221#define R92C_RXFLTMAP0 0x6a0 222#define R92C_RXFLTMAP1 0x6a2 223#define R92C_RXFLTMAP2 0x6a4 224 225/* Bits for R92C_SYS_ISO_CTRL. */ 226#define R92C_SYS_ISO_CTRL_MD2PP 0x0001 227#define R92C_SYS_ISO_CTRL_UA2USB 0x0002 228#define R92C_SYS_ISO_CTRL_UD2CORE 0x0004 229#define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008 230#define R92C_SYS_ISO_CTRL_PD2CORE 0x0010 231#define R92C_SYS_ISO_CTRL_IP2MAC 0x0020 232#define R92C_SYS_ISO_CTRL_DIOP 0x0040 233#define R92C_SYS_ISO_CTRL_DIOE 0x0080 234#define R92C_SYS_ISO_CTRL_EB2CORE 0x0100 235#define R92C_SYS_ISO_CTRL_DIOR 0x0200 236#define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000 237#define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000 238 239/* Bits for R92C_SYS_FUNC_EN. */ 240#define R92C_SYS_FUNC_EN_BBRSTB 0x0001 241#define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002 242#define R92C_SYS_FUNC_EN_USBA 0x0004 243#define R92C_SYS_FUNC_EN_UPLL 0x0008 244#define R92C_SYS_FUNC_EN_USBD 0x0010 245#define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020 246#define R92C_SYS_FUNC_EN_PCIEA 0x0040 247#define R92C_SYS_FUNC_EN_PPLL 0x0080 248#define R92C_SYS_FUNC_EN_PCIED 0x0100 249#define R92C_SYS_FUNC_EN_DIOE 0x0200 250#define R92C_SYS_FUNC_EN_CPUEN 0x0400 251#define R92C_SYS_FUNC_EN_DCORE 0x0800 252#define R92C_SYS_FUNC_EN_ELDR 0x1000 253#define R92C_SYS_FUNC_EN_DIO_RF 0x2000 254#define R92C_SYS_FUNC_EN_HWPDN 0x4000 255#define R92C_SYS_FUNC_EN_MREGEN 0x8000 256 257/* Bits for R92C_APS_FSMCO. */ 258#define R92C_APS_FSMCO_PFM_LDALL 0x00000001 259#define R92C_APS_FSMCO_PFM_ALDN 0x00000002 260#define R92C_APS_FSMCO_PFM_LDKP 0x00000004 261#define R92C_APS_FSMCO_PFM_WOWL 0x00000008 262#define R92C_APS_FSMCO_PDN_EN 0x00000010 263#define R92C_APS_FSMCO_PDN_PL 0x00000020 264#define R92C_APS_FSMCO_APFM_ONMAC 0x00000100 265#define R92C_APS_FSMCO_APFM_OFF 0x00000200 266#define R92C_APS_FSMCO_APFM_RSM 0x00000400 267#define R92C_APS_FSMCO_AFSM_HSUS 0x00000800 268#define R92C_APS_FSMCO_AFSM_PCIE 0x00001000 269#define R92C_APS_FSMCO_APDM_MAC 0x00002000 270#define R92C_APS_FSMCO_APDM_HOST 0x00004000 271#define R92C_APS_FSMCO_APDM_HPDN 0x00008000 272#define R92C_APS_FSMCO_RDY_MACON 0x00010000 273#define R92C_APS_FSMCO_SUS_HOST 0x00020000 274#define R92C_APS_FSMCO_ROP_ALD 0x00100000 275#define R92C_APS_FSMCO_ROP_PWR 0x00200000 276#define R92C_APS_FSMCO_ROP_SPS 0x00400000 277#define R92C_APS_FSMCO_SOP_MRST 0x02000000 278#define R92C_APS_FSMCO_SOP_FUSE 0x04000000 279#define R92C_APS_FSMCO_SOP_ABG 0x08000000 280#define R92C_APS_FSMCO_SOP_AMB 0x10000000 281#define R92C_APS_FSMCO_SOP_RCK 0x20000000 282#define R92C_APS_FSMCO_SOP_A8M 0x40000000 283#define R92C_APS_FSMCO_XOP_BTCK 0x80000000 284 285/* Bits for R92C_SYS_CLKR. */ 286#define R92C_SYS_CLKR_ANAD16V_EN 0x00000001 287#define R92C_SYS_CLKR_ANA8M 0x00000002 288#define R92C_SYS_CLKR_MACSLP 0x00000010 289#define R92C_SYS_CLKR_LOADER_EN 0x00000020 290#define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080 291#define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100 292#define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200 293#define R92C_SYS_CLKR_SEC_EN 0x00000400 294#define R92C_SYS_CLKR_MAC_EN 0x00000800 295#define R92C_SYS_CLKR_SYS_EN 0x00001000 296#define R92C_SYS_CLKR_RING_EN 0x00002000 297 298/* Bits for R92C_RF_CTRL. */ 299#define R92C_RF_CTRL_EN 0x01 300#define R92C_RF_CTRL_RSTB 0x02 301#define R92C_RF_CTRL_SDMRSTB 0x04 302 303/* Bits for R92C_LDOV12D_CTRL. */ 304#define R92C_LDOV12D_CTRL_LDV12_EN 0x01 305 306/* Bits for R92C_AFE_XTAL_CTRL. */ 307#define R92C_AFE_XTAL_CTRL_ADDR_M 0x007ff800 308#define R92C_AFE_XTAL_CTRL_ADDR_S 11 309 310/* Bits for R92C_EFUSE_CTRL. */ 311#define R92C_EFUSE_CTRL_DATA_M 0x000000ff 312#define R92C_EFUSE_CTRL_DATA_S 0 313#define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00 314#define R92C_EFUSE_CTRL_ADDR_S 8 315#define R92C_EFUSE_CTRL_VALID 0x80000000 316 317/* Bits for R92C_GPIO_MUXCFG. */ 318#define R92C_GPIO_MUXCFG_ENBT 0x0020 319 320/* Bits for R92C_LEDCFG0. */ 321#define R92C_LEDCFG0_DIS 0x08 322 323/* Bits for R92C_MCUFWDL. */ 324#define R92C_MCUFWDL_EN 0x00000001 325#define R92C_MCUFWDL_RDY 0x00000002 326#define R92C_MCUFWDL_CHKSUM_RPT 0x00000004 327#define R92C_MCUFWDL_MACINI_RDY 0x00000008 328#define R92C_MCUFWDL_BBINI_RDY 0x00000010 329#define R92C_MCUFWDL_RFINI_RDY 0x00000020 330#define R92C_MCUFWDL_WINTINI_RDY 0x00000040 331#define R92C_MCUFWDL_RAM_DL_SEL 0x00000080 332#define R92C_MCUFWDL_PAGE_M 0x00070000 333#define R92C_MCUFWDL_PAGE_S 16 334#define R92C_MCUFWDL_CPRST 0x00800000 335 336/* Bits for R88E_HIMR. */ 337#define R88E_HIMR_CPWM 0x00000100 338#define R88E_HIMR_CPWM2 0x00000200 339#define R88E_HIMR_TBDER 0x04000000 340#define R88E_HIMR_PSTIMEOUT 0x20000000 341 342/* Bits for R88E_HIMRE.*/ 343#define R88E_HIMRE_RXFOVW 0x00000100 344#define R88E_HIMRE_TXFOVW 0x00000200 345#define R88E_HIMRE_RXERR 0x00000400 346#define R88E_HIMRE_TXERR 0x00000800 347 348/* Bits for R92C_EFUSE_ACCESS. */ 349#define R92C_EFUSE_ACCESS_OFF 0x00 350#define R92C_EFUSE_ACCESS_ON 0x69 351 352/* Bits for R92C_HPON_FSM. */ 353#define R92C_HPON_FSM_CHIP_BONDING_ID_S 22 354#define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000 355#define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1 356 357/* Bits for R92C_SYS_CFG. */ 358#define R92C_SYS_CFG_XCLK_VLD 0x00000001 359#define R92C_SYS_CFG_ACLK_VLD 0x00000002 360#define R92C_SYS_CFG_UCLK_VLD 0x00000004 361#define R92C_SYS_CFG_PCLK_VLD 0x00000008 362#define R92C_SYS_CFG_PCIRSTB 0x00000010 363#define R92C_SYS_CFG_V15_VLD 0x00000020 364#define R92C_SYS_CFG_TRP_B15V_EN 0x00000080 365#define R92C_SYS_CFG_SIC_IDLE 0x00000100 366#define R92C_SYS_CFG_BD_MAC2 0x00000200 367#define R92C_SYS_CFG_BD_MAC1 0x00000400 368#define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800 369#define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000 370#define R92C_SYS_CFG_CHIP_VER_RTL_S 12 371#define R92C_SYS_CFG_BT_FUNC 0x00010000 372#define R92C_SYS_CFG_VENDOR_UMC 0x00080000 373#define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000 374#define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000 375#define R92C_SYS_CFG_TRP_BT_EN 0x01000000 376#define R92C_SYS_CFG_BD_PKG_SEL 0x02000000 377#define R92C_SYS_CFG_BD_HCI_SEL 0x04000000 378#define R92C_SYS_CFG_TYPE_92C 0x08000000 379 380/* Bits for R92C_CR. */ 381#define R92C_CR_HCI_TXDMA_EN 0x0001 382#define R92C_CR_HCI_RXDMA_EN 0x0002 383#define R92C_CR_TXDMA_EN 0x0004 384#define R92C_CR_RXDMA_EN 0x0008 385#define R92C_CR_PROTOCOL_EN 0x0010 386#define R92C_CR_SCHEDULE_EN 0x0020 387#define R92C_CR_MACTXEN 0x0040 388#define R92C_CR_MACRXEN 0x0080 389#define R92C_CR_ENSEC 0x0200 390#define R92C_CR_CALTMR_EN 0x0400 391 392/* Bits for R92C_MSR. */ 393#define R92C_MSR_NOLINK 0x00 394#define R92C_MSR_ADHOC 0x01 395#define R92C_MSR_INFRA 0x02 396#define R92C_MSR_AP 0x03 397#define R92C_MSR_MASK (R92C_MSR_AP) 398 399/* Bits for R92C_PBP. */ 400#define R92C_PBP_PSRX_M 0x0f 401#define R92C_PBP_PSRX_S 0 402#define R92C_PBP_PSTX_M 0xf0 403#define R92C_PBP_PSTX_S 4 404#define R92C_PBP_64 0 405#define R92C_PBP_128 1 406#define R92C_PBP_256 2 407#define R92C_PBP_512 3 408#define R92C_PBP_1024 4 409 410/* Bits for R92C_TRXDMA_CTRL. */ 411#define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004 412#define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030 413#define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4 414#define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0 415#define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6 416#define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300 417#define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8 418#define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00 419#define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10 420#define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000 421#define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12 422#define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000 423#define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14 424#define R92C_TRXDMA_CTRL_QUEUE_LOW 1 425#define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2 426#define R92C_TRXDMA_CTRL_QUEUE_HIGH 3 427#define R92C_TRXDMA_CTRL_QMAP_M 0xfff0 428/* Shortcuts. */ 429#define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0 430#define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0 431#define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0 432#define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550 433#define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0 434#define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0 435 436/* Bits for R92C_LLT_INIT. */ 437#define R92C_LLT_INIT_DATA_M 0x000000ff 438#define R92C_LLT_INIT_DATA_S 0 439#define R92C_LLT_INIT_ADDR_M 0x0000ff00 440#define R92C_LLT_INIT_ADDR_S 8 441#define R92C_LLT_INIT_OP_M 0xc0000000 442#define R92C_LLT_INIT_OP_S 30 443#define R92C_LLT_INIT_OP_NO_ACTIVE 0 444#define R92C_LLT_INIT_OP_WRITE 1 445 446/* Bits for R92C_RQPN. */ 447#define R92C_RQPN_HPQ_M 0x000000ff 448#define R92C_RQPN_HPQ_S 0 449#define R92C_RQPN_LPQ_M 0x0000ff00 450#define R92C_RQPN_LPQ_S 8 451#define R92C_RQPN_PUBQ_M 0x00ff0000 452#define R92C_RQPN_PUBQ_S 16 453#define R92C_RQPN_LD 0x80000000 454 455/* Bits for R92C_TDECTRL. */ 456#define R92C_TDECTRL_BLK_DESC_NUM_M 0x000000f0 457#define R92C_TDECTRL_BLK_DESC_NUM_S 4 458 459/* Bits for R92C_FWHW_TXQ_CTRL. */ 460#define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80 461 462/* Bits for R92C_SPEC_SIFS. */ 463#define R92C_SPEC_SIFS_CCK_M 0x00ff 464#define R92C_SPEC_SIFS_CCK_S 0 465#define R92C_SPEC_SIFS_OFDM_M 0xff00 466#define R92C_SPEC_SIFS_OFDM_S 8 467 468/* Bits for R92C_RL. */ 469#define R92C_RL_LRL_M 0x003f 470#define R92C_RL_LRL_S 0 471#define R92C_RL_SRL_M 0x3f00 472#define R92C_RL_SRL_S 8 473 474/* Bits for R92C_RRSR. */ 475#define R92C_RRSR_RATE_BITMAP_M 0x000fffff 476#define R92C_RRSR_RATE_BITMAP_S 0 477#define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1 478#define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000 479#define R92C_RRSR_RSC_UPSUBCHNL 0x00400000 480#define R92C_RRSR_SHORT 0x00800000 481 482/* Bits for R92C_EDCA_XX_PARAM. */ 483#define R92C_EDCA_PARAM_AIFS_M 0x000000ff 484#define R92C_EDCA_PARAM_AIFS_S 0 485#define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00 486#define R92C_EDCA_PARAM_ECWMIN_S 8 487#define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000 488#define R92C_EDCA_PARAM_ECWMAX_S 12 489#define R92C_EDCA_PARAM_TXOP_M 0xffff0000 490#define R92C_EDCA_PARAM_TXOP_S 16 491 492/* Bits for R92C_BCN_CTRL. */ 493#define R92C_BCN_CTRL_EN_MBSSID 0x02 494#define R92C_BCN_CTRL_TXBCN_RPT 0x04 495#define R92C_BCN_CTRL_EN_BCN 0x08 496#define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10 497 498/* Bits for R92C_MBID_NUM. */ 499#define R92C_MBID_TXBCN_RPT0 0x08 500#define R92C_MBID_TXBCN_RPT1 0x10 501 502/* Bits for R92C_DUAL_TSF_RST. */ 503#define R92C_DUAL_TSF_RST0 0x01 504#define R92C_DUAL_TSF_RST1 0x02 505 506/* Bits for R92C_APSD_CTRL. */ 507#define R92C_APSD_CTRL_OFF 0x40 508#define R92C_APSD_CTRL_OFF_STATUS 0x80 509 510/* Bits for R92C_BWOPMODE. */ 511#define R92C_BWOPMODE_11J 0x01 512#define R92C_BWOPMODE_5G 0x02 513#define R92C_BWOPMODE_20MHZ 0x04 514 515/* Bits for R92C_RCR. */ 516#define R92C_RCR_AAP 0x00000001 517#define R92C_RCR_APM 0x00000002 518#define R92C_RCR_AM 0x00000004 519#define R92C_RCR_AB 0x00000008 520#define R92C_RCR_ADD3 0x00000010 521#define R92C_RCR_APWRMGT 0x00000020 522#define R92C_RCR_CBSSID_DATA 0x00000040 523#define R92C_RCR_CBSSID_BCN 0x00000080 524#define R92C_RCR_ACRC32 0x00000100 525#define R92C_RCR_AICV 0x00000200 526#define R92C_RCR_ADF 0x00000800 527#define R92C_RCR_ACF 0x00001000 528#define R92C_RCR_AMF 0x00002000 529#define R92C_RCR_HTC_LOC_CTRL 0x00004000 530#define R92C_RCR_MFBEN 0x00400000 531#define R92C_RCR_LSIGEN 0x00800000 532#define R92C_RCR_ENMBID 0x01000000 533#define R92C_RCR_APP_BA_SSN 0x08000000 534#define R92C_RCR_APP_PHYSTS 0x10000000 535#define R92C_RCR_APP_ICV 0x20000000 536#define R92C_RCR_APP_MIC 0x40000000 537#define R92C_RCR_APPFCS 0x80000000 538 539/* Bits for R92C_CAMCMD. */ 540#define R92C_CAMCMD_ADDR_M 0x0000ffff 541#define R92C_CAMCMD_ADDR_S 0 542#define R92C_CAMCMD_WRITE 0x00010000 543#define R92C_CAMCMD_CLR 0x40000000 544#define R92C_CAMCMD_POLLING 0x80000000 545 546/* Bits for R92C_RXFLTMAP*. */ 547#define R92C_RXFLTMAP_SUBTYPE(subtype) \ 548 (1 << ((subtype) >> IEEE80211_FC0_SUBTYPE_SHIFT)) 549 550 551/* 552 * Baseband registers. 553 */ 554#define R92C_FPGA0_RFMOD 0x800 555#define R92C_FPGA0_TXINFO 0x804 556#define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8) 557#define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8) 558#define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830) 559#define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834) 560#define R92C_TXAGC_A_CCK1_MCS32 0xe08 561#define R92C_TXAGC_B_CCK1_55_MCS32 0x838 562#define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c 563#define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c) 564#define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848) 565#define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c) 566#define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868) 567#define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4) 568#define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4) 569#define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4) 570#define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4) 571#define R92C_FPGA0_ANAPARAM2 0x884 572#define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4) 573#define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4) 574#define R92C_FPGA1_RFMOD 0x900 575#define R92C_FPGA1_TXINFO 0x90c 576#define R92C_CCK0_SYSTEM 0xa00 577#define R92C_CCK0_AFESETTING 0xa04 578#define R92C_OFDM0_TRXPATHENA 0xc04 579#define R92C_OFDM0_TRMUXPAR 0xc08 580#define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8) 581#define R92C_OFDM0_AGCPARAM1 0xc70 582#define R92C_OFDM0_AGCRSSITABLE 0xc78 583#define R92C_OFDM1_LSTF 0xd00 584 585/* Bits for R92C_FPGA[01]_RFMOD. */ 586#define R92C_RFMOD_40MHZ 0x00000001 587#define R92C_RFMOD_JAPAN 0x00000002 588#define R92C_RFMOD_CCK_TXSC 0x00000030 589#define R92C_RFMOD_CCK_EN 0x01000000 590#define R92C_RFMOD_OFDM_EN 0x02000000 591 592/* Bits for R92C_HSSI_PARAM1(i). */ 593#define R92C_HSSI_PARAM1_PI 0x00000100 594 595/* Bits for R92C_HSSI_PARAM2(i). */ 596#define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200 597#define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400 598#define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800 599#define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000 600#define R92C_HSSI_PARAM2_READ_ADDR_S 23 601#define R92C_HSSI_PARAM2_READ_EDGE 0x80000000 602 603/* Bits for R92C_TXAGC_A_CCK1_MCS32. */ 604#define R92C_TXAGC_A_CCK1_M 0x0000ff00 605#define R92C_TXAGC_A_CCK1_S 8 606 607/* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */ 608#define R92C_TXAGC_B_CCK11_M 0x000000ff 609#define R92C_TXAGC_B_CCK11_S 0 610#define R92C_TXAGC_A_CCK2_M 0x0000ff00 611#define R92C_TXAGC_A_CCK2_S 8 612#define R92C_TXAGC_A_CCK55_M 0x00ff0000 613#define R92C_TXAGC_A_CCK55_S 16 614#define R92C_TXAGC_A_CCK11_M 0xff000000 615#define R92C_TXAGC_A_CCK11_S 24 616 617/* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */ 618#define R92C_TXAGC_B_CCK1_M 0x0000ff00 619#define R92C_TXAGC_B_CCK1_S 8 620#define R92C_TXAGC_B_CCK2_M 0x00ff0000 621#define R92C_TXAGC_B_CCK2_S 16 622#define R92C_TXAGC_B_CCK55_M 0xff000000 623#define R92C_TXAGC_B_CCK55_S 24 624 625/* Bits for R92C_TXAGC_RATE18_06(x). */ 626#define R92C_TXAGC_RATE06_M 0x000000ff 627#define R92C_TXAGC_RATE06_S 0 628#define R92C_TXAGC_RATE09_M 0x0000ff00 629#define R92C_TXAGC_RATE09_S 8 630#define R92C_TXAGC_RATE12_M 0x00ff0000 631#define R92C_TXAGC_RATE12_S 16 632#define R92C_TXAGC_RATE18_M 0xff000000 633#define R92C_TXAGC_RATE18_S 24 634 635/* Bits for R92C_TXAGC_RATE54_24(x). */ 636#define R92C_TXAGC_RATE24_M 0x000000ff 637#define R92C_TXAGC_RATE24_S 0 638#define R92C_TXAGC_RATE36_M 0x0000ff00 639#define R92C_TXAGC_RATE36_S 8 640#define R92C_TXAGC_RATE48_M 0x00ff0000 641#define R92C_TXAGC_RATE48_S 16 642#define R92C_TXAGC_RATE54_M 0xff000000 643#define R92C_TXAGC_RATE54_S 24 644 645/* Bits for R92C_TXAGC_MCS03_MCS00(x). */ 646#define R92C_TXAGC_MCS00_M 0x000000ff 647#define R92C_TXAGC_MCS00_S 0 648#define R92C_TXAGC_MCS01_M 0x0000ff00 649#define R92C_TXAGC_MCS01_S 8 650#define R92C_TXAGC_MCS02_M 0x00ff0000 651#define R92C_TXAGC_MCS02_S 16 652#define R92C_TXAGC_MCS03_M 0xff000000 653#define R92C_TXAGC_MCS03_S 24 654 655/* Bits for R92C_TXAGC_MCS07_MCS04(x). */ 656#define R92C_TXAGC_MCS04_M 0x000000ff 657#define R92C_TXAGC_MCS04_S 0 658#define R92C_TXAGC_MCS05_M 0x0000ff00 659#define R92C_TXAGC_MCS05_S 8 660#define R92C_TXAGC_MCS06_M 0x00ff0000 661#define R92C_TXAGC_MCS06_S 16 662#define R92C_TXAGC_MCS07_M 0xff000000 663#define R92C_TXAGC_MCS07_S 24 664 665/* Bits for R92C_TXAGC_MCS11_MCS08(x). */ 666#define R92C_TXAGC_MCS08_M 0x000000ff 667#define R92C_TXAGC_MCS08_S 0 668#define R92C_TXAGC_MCS09_M 0x0000ff00 669#define R92C_TXAGC_MCS09_S 8 670#define R92C_TXAGC_MCS10_M 0x00ff0000 671#define R92C_TXAGC_MCS10_S 16 672#define R92C_TXAGC_MCS11_M 0xff000000 673#define R92C_TXAGC_MCS11_S 24 674 675/* Bits for R92C_TXAGC_MCS15_MCS12(x). */ 676#define R92C_TXAGC_MCS12_M 0x000000ff 677#define R92C_TXAGC_MCS12_S 0 678#define R92C_TXAGC_MCS13_M 0x0000ff00 679#define R92C_TXAGC_MCS13_S 8 680#define R92C_TXAGC_MCS14_M 0x00ff0000 681#define R92C_TXAGC_MCS14_S 16 682#define R92C_TXAGC_MCS15_M 0xff000000 683#define R92C_TXAGC_MCS15_S 24 684 685/* Bits for R92C_LSSI_PARAM(i). */ 686#define R92C_LSSI_PARAM_DATA_M 0x000fffff 687#define R92C_LSSI_PARAM_DATA_S 0 688#define R92C_LSSI_PARAM_ADDR_M 0x03f00000 689#define R92C_LSSI_PARAM_ADDR_S 20 690#define R88E_LSSI_PARAM_ADDR_M 0x0ff00000 691#define R88E_LSSI_PARAM_ADDR_S 20 692 693/* Bits for R92C_FPGA0_ANAPARAM2. */ 694#define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400 695 696/* Bits for R92C_LSSI_READBACK(i). */ 697#define R92C_LSSI_READBACK_DATA_M 0x000fffff 698#define R92C_LSSI_READBACK_DATA_S 0 699 700/* Bits for R92C_OFDM0_AGCCORE1(i). */ 701#define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f 702#define R92C_OFDM0_AGCCORE1_GAIN_S 0 703 704 705/* 706 * USB registers. 707 */ 708#define R92C_USB_INFO 0xfe17 709#define R92C_USB_SPECIAL_OPTION 0xfe55 710#define R92C_USB_HCPWM 0xfe57 711#define R92C_USB_HRPWM 0xfe58 712#define R92C_USB_DMA_AGG_TO 0xfe5b 713#define R92C_USB_AGG_TO 0xfe5c 714#define R92C_USB_AGG_TH 0xfe5d 715#define R92C_USB_VID 0xfe60 716#define R92C_USB_PID 0xfe62 717#define R92C_USB_OPTIONAL 0xfe64 718#define R92C_USB_EP 0xfe65 719#define R92C_USB_PHY 0xfe68 720#define R92C_USB_MAC_ADDR 0xfe70 721#define R92C_USB_STRING 0xfe80 722 723/* Bits for R92C_USB_SPECIAL_OPTION. */ 724#define R92C_USB_SPECIAL_OPTION_AGG_EN 0x08 725#define R92C_USB_SPECIAL_OPTION_INT_BULK_SEL 0x10 726 727/* Bits for R92C_USB_EP. */ 728#define R92C_USB_EP_HQ_M 0x000f 729#define R92C_USB_EP_HQ_S 0 730#define R92C_USB_EP_NQ_M 0x00f0 731#define R92C_USB_EP_NQ_S 4 732#define R92C_USB_EP_LQ_M 0x0f00 733#define R92C_USB_EP_LQ_S 8 734 735 736/* 737 * Firmware base address. 738 */ 739#define R92C_FW_START_ADDR 0x1000 740#define R92C_FW_PAGE_SIZE 4096 741 742 743/* 744 * RF (6052) registers. 745 */ 746#define R92C_RF_AC 0x00 747#define R92C_RF_IQADJ_G(i) (0x01 + (i)) 748#define R92C_RF_POW_TRSW 0x05 749#define R92C_RF_GAIN_RX 0x06 750#define R92C_RF_GAIN_TX 0x07 751#define R92C_RF_TXM_IDAC 0x08 752#define R92C_RF_BS_IQGEN 0x0f 753#define R92C_RF_MODE1 0x10 754#define R92C_RF_MODE2 0x11 755#define R92C_RF_RX_AGC_HP 0x12 756#define R92C_RF_TX_AGC 0x13 757#define R92C_RF_BIAS 0x14 758#define R92C_RF_IPA 0x15 759#define R92C_RF_POW_ABILITY 0x17 760#define R92C_RF_CHNLBW 0x18 761#define R92C_RF_RX_G1 0x1a 762#define R92C_RF_RX_G2 0x1b 763#define R92C_RF_RX_BB2 0x1c 764#define R92C_RF_RX_BB1 0x1d 765#define R92C_RF_RCK1 0x1e 766#define R92C_RF_RCK2 0x1f 767#define R92C_RF_TX_G(i) (0x20 + (i)) 768#define R92C_RF_TX_BB1 0x23 769#define R92C_RF_T_METER 0x24 770#define R92C_RF_SYN_G(i) (0x25 + (i)) 771#define R92C_RF_RCK_OS 0x30 772#define R92C_RF_TXPA_G(i) (0x31 + (i)) 773 774/* Bits for R92C_RF_AC. */ 775#define R92C_RF_AC_MODE_M 0x70000 776#define R92C_RF_AC_MODE_S 16 777#define R92C_RF_AC_MODE_STANDBY 1 778 779/* Bits for R92C_RF_CHNLBW. */ 780#define R92C_RF_CHNLBW_CHNL_M 0x003ff 781#define R92C_RF_CHNLBW_CHNL_S 0 782#define R92C_RF_CHNLBW_BW20 0x00400 783#define R88E_RF_CHNLBW_BW20 0x00c00 784#define R92C_RF_CHNLBW_LCSTART 0x08000 785 786 787/* 788 * CAM entries. 789 */ 790#define R92C_CAM_ENTRY_COUNT 32 791 792#define R92C_CAM_CTL0(entry) ((entry) * 8 + 0) 793#define R92C_CAM_CTL1(entry) ((entry) * 8 + 1) 794#define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) 795 796/* Bits for R92C_CAM_CTL0(i). */ 797#define R92C_CAM_KEYID_M 0x00000003 798#define R92C_CAM_KEYID_S 0 799#define R92C_CAM_ALGO_M 0x0000001c 800#define R92C_CAM_ALGO_S 2 801#define R92C_CAM_ALGO_NONE 0 802#define R92C_CAM_ALGO_WEP40 1 803#define R92C_CAM_ALGO_TKIP 2 804#define R92C_CAM_ALGO_AES 4 805#define R92C_CAM_ALGO_WEP104 5 806#define R92C_CAM_VALID 0x00008000 807#define R92C_CAM_MACLO_M 0xffff0000 808#define R92C_CAM_MACLO_S 16 809 810/* Rate adaptation modes. */ 811#define R92C_RAID_11GN 1 812#define R92C_RAID_11N 3 813#define R92C_RAID_11BG 4 814#define R92C_RAID_11G 5 /* "pure" 11g */ 815#define R92C_RAID_11B 6 816 817 818/* 819 * Macros to access subfields in registers. 820 */ 821/* Mask and Shift (getter). */ 822#define MS(val, field) \ 823 (((val) & field##_M) >> field##_S) 824 825/* Shift and Mask (setter). */ 826#define SM(field, val) \ 827 (((val) << field##_S) & field##_M) 828 829/* Rewrite. */ 830#define RW(var, field, val) \ 831 (((var) & ~field##_M) | SM(field, val)) 832 833/* 834 * Firmware image header. 835 */ 836struct r92c_fw_hdr { 837 /* QWORD0 */ 838 uint16_t signature; 839 uint8_t category; 840 uint8_t function; 841 uint16_t version; 842 uint16_t subversion; 843 /* QWORD1 */ 844 uint8_t month; 845 uint8_t date; 846 uint8_t hour; 847 uint8_t minute; 848 uint16_t ramcodesize; 849 uint16_t reserved2; 850 /* QWORD2 */ 851 uint32_t svnidx; 852 uint32_t reserved3; 853 /* QWORD3 */ 854 uint32_t reserved4; 855 uint32_t reserved5; 856} __packed; 857 858/* 859 * Host to firmware commands. 860 */ 861struct r92c_fw_cmd { 862 uint8_t id; 863#define R92C_CMD_AP_OFFLOAD 0 864#define R92C_CMD_SET_PWRMODE 1 865#define R92C_CMD_JOINBSS_RPT 2 866#define R92C_CMD_RSVD_PAGE 3 867#define R92C_CMD_RSSI 4 868#define R92C_CMD_RSSI_SETTING 5 869#define R92C_CMD_MACID_CONFIG 6 870#define R92C_CMD_MACID_PS_MODE 7 871#define R92C_CMD_P2P_PS_OFFLOAD 8 872#define R92C_CMD_SELECTIVE_SUSPEND 9 873#define R92C_CMD_FLAG_EXT 0x80 874 875 uint8_t msg[5]; 876} __packed; 877 878/* Structure for R92C_CMD_RSSI_SETTING. */ 879struct r92c_fw_cmd_rssi { 880 uint8_t macid; 881 uint8_t reserved; 882 uint8_t pwdb; 883} __packed; 884 885/* Structure for R92C_CMD_MACID_CONFIG. */ 886struct r92c_fw_cmd_macid_cfg { 887 uint32_t mask; 888 uint8_t macid; 889#define URTWN_MACID_BSS 0 890#define URTWN_MACID_BC 4 /* Broadcast. */ 891#define URTWN_MACID_VALID 0x80 892} __packed; 893 894/* 895 * RTL8192CU ROM image. 896 */ 897struct r92c_rom { 898 uint16_t id; /* 0x8192 */ 899 uint8_t reserved1[5]; 900 uint8_t dbg_sel; 901 uint16_t reserved2; 902 uint16_t vid; 903 uint16_t pid; 904 uint8_t usb_opt; 905 uint8_t ep_setting; 906 uint16_t reserved3; 907 uint8_t usb_phy; 908 uint8_t reserved4[3]; 909 uint8_t macaddr[6]; 910 uint8_t string[61]; /* "Realtek" */ 911 uint8_t subcustomer_id; 912 uint8_t cck_tx_pwr[R92C_MAX_CHAINS][3]; 913 uint8_t ht40_1s_tx_pwr[R92C_MAX_CHAINS][3]; 914 uint8_t ht40_2s_tx_pwr_diff[3]; 915 uint8_t ht20_tx_pwr_diff[3]; 916 uint8_t ofdm_tx_pwr_diff[3]; 917 uint8_t ht40_max_pwr[3]; 918 uint8_t ht20_max_pwr[3]; 919 uint8_t xtal_calib; 920 uint8_t tssi[R92C_MAX_CHAINS]; 921 uint8_t thermal_meter; 922 uint8_t rf_opt1; 923#define R92C_ROM_RF1_REGULATORY_M 0x07 924#define R92C_ROM_RF1_REGULATORY_S 0 925#define R92C_ROM_RF1_BOARD_TYPE_M 0xe0 926#define R92C_ROM_RF1_BOARD_TYPE_S 5 927#define R92C_BOARD_TYPE_DONGLE 0 928#define R92C_BOARD_TYPE_HIGHPA 1 929#define R92C_BOARD_TYPE_MINICARD 2 930#define R92C_BOARD_TYPE_SOLO 3 931#define R92C_BOARD_TYPE_COMBO 4 932 933 uint8_t rf_opt2; 934 uint8_t rf_opt3; 935 uint8_t rf_opt4; 936 uint8_t channel_plan; 937 uint8_t version; 938 uint8_t curstomer_id; 939} __packed; 940 941/* Rx MAC descriptor. */ 942struct r92c_rx_stat { 943 uint32_t rxdw0; 944#define R92C_RXDW0_PKTLEN_M 0x00003fff 945#define R92C_RXDW0_PKTLEN_S 0 946#define R92C_RXDW0_CRCERR 0x00004000 947#define R92C_RXDW0_ICVERR 0x00008000 948#define R92C_RXDW0_INFOSZ_M 0x000f0000 949#define R92C_RXDW0_INFOSZ_S 16 950#define R92C_RXDW0_QOS 0x00800000 951#define R92C_RXDW0_SHIFT_M 0x03000000 952#define R92C_RXDW0_SHIFT_S 24 953#define R92C_RXDW0_PHYST 0x04000000 954#define R92C_RXDW0_DECRYPTED 0x08000000 955 956 uint32_t rxdw1; 957 uint32_t rxdw2; 958#define R92C_RXDW2_PKTCNT_M 0x00ff0000 959#define R92C_RXDW2_PKTCNT_S 16 960 961 uint32_t rxdw3; 962#define R92C_RXDW3_RATE_M 0x0000003f 963#define R92C_RXDW3_RATE_S 0 964#define R92C_RXDW3_HT 0x00000040 965#define R92C_RXDW3_HTC 0x00000400 966 967 uint32_t rxdw4; 968 uint32_t rxdw5; 969} __packed __attribute__((aligned(4))); 970 971/* Rx PHY descriptor. */ 972struct r92c_rx_phystat { 973 uint32_t phydw0; 974 uint32_t phydw1; 975 uint32_t phydw2; 976 uint32_t phydw3; 977 uint32_t phydw4; 978 uint32_t phydw5; 979 uint32_t phydw6; 980 uint32_t phydw7; 981} __packed __attribute__((aligned(4))); 982 983/* Rx PHY CCK descriptor. */ 984struct r92c_rx_cck { 985 uint8_t adc_pwdb[4]; 986 uint8_t sq_rpt; 987 uint8_t agc_rpt; 988} __packed; 989 990struct r88e_rx_cck { 991 uint8_t path_agc[2]; 992 uint8_t chan; 993 uint8_t reserved1; 994 uint8_t sig_qual; 995 uint8_t agc_rpt; 996 uint8_t rpt_b; 997 uint8_t reserved2; 998 uint8_t noise_power; 999 uint8_t path_cfotail[2]; 1000 uint8_t pcts_mask[2]; 1001 uint8_t stream_rxevm[2]; 1002 uint8_t path_rxsnr[2]; 1003 uint8_t noise_power_db_lsb; 1004 uint8_t reserved3[3]; 1005 uint8_t stream_csi[2]; 1006 uint8_t stream_target_csi[2]; 1007 uint8_t sig_evm; 1008} __packed; 1009 1010/* Tx MAC descriptor. */ 1011struct r92c_tx_desc { 1012 uint32_t txdw0; 1013#define R92C_TXDW0_PKTLEN_M 0x0000ffff 1014#define R92C_TXDW0_PKTLEN_S 0 1015#define R92C_TXDW0_OFFSET_M 0x00ff0000 1016#define R92C_TXDW0_OFFSET_S 16 1017#define R92C_TXDW0_BMCAST 0x01000000 1018#define R92C_TXDW0_LSG 0x04000000 1019#define R92C_TXDW0_FSG 0x08000000 1020#define R92C_TXDW0_OWN 0x80000000 1021 1022 uint32_t txdw1; 1023#define R92C_TXDW1_MACID_M 0x0000001f 1024#define R92C_TXDW1_MACID_S 0 1025#define R88E_TXDW1_MACID_M 0x0000003f 1026#define R88E_TXDW1_MACID_S 0 1027#define R92C_TXDW1_AGGEN 0x00000020 1028#define R92C_TXDW1_AGGBK 0x00000040 1029#define R92C_TXDW1_QSEL_M 0x00001f00 1030#define R92C_TXDW1_QSEL_S 8 1031 1032#define R92C_TXDW1_QSEL_BE 0x00 /* or 0x03 */ 1033#define R92C_TXDW1_QSEL_BK 0x01 /* or 0x02 */ 1034#define R92C_TXDW1_QSEL_VI 0x04 /* or 0x05 */ 1035#define R92C_TXDW1_QSEL_VO 0x06 /* or 0x07 */ 1036#define URTWN_MAX_TID 8 1037 1038#define R92C_TXDW1_QSEL_BEACON 0x10 1039#define R92C_TXDW1_QSEL_MGNT 0x12 1040 1041#define R92C_TXDW1_RAID_M 0x000f0000 1042#define R92C_TXDW1_RAID_S 16 1043#define R92C_TXDW1_CIPHER_M 0x00c00000 1044#define R92C_TXDW1_CIPHER_S 22 1045#define R92C_TXDW1_CIPHER_NONE 0 1046#define R92C_TXDW1_CIPHER_RC4 1 1047#define R92C_TXDW1_CIPHER_AES 3 1048#define R92C_TXDW1_PKTOFF_M 0x7c000000 1049#define R92C_TXDW1_PKTOFF_S 26 1050 1051 uint32_t txdw2; 1052#define R88E_TXDW2_AGGBK 0x00010000 1053 1054 uint16_t txdw3; 1055 uint16_t txdseq; 1056#define R92C_TXDSEQ_HWSEQ_EN 0x8000 1057 1058 uint32_t txdw4; 1059#define R92C_TXDW4_RTSRATE_M 0x0000003f 1060#define R92C_TXDW4_RTSRATE_S 0 1061#define R92C_TXDW4_HWSEQ_QOS 0x00000040 1062#define R92C_TXDW4_DRVRATE 0x00000100 1063#define R92C_TXDW4_CTS2SELF 0x00000800 1064#define R92C_TXDW4_RTSEN 0x00001000 1065#define R92C_TXDW4_HWRTSEN 0x00002000 1066#define R92C_TXDW4_SCO_M 0x003f0000 1067#define R92C_TXDW4_SCO_S 20 1068#define R92C_TXDW4_SCO_SCA 1 1069#define R92C_TXDW4_SCO_SCB 2 1070#define R92C_TXDW4_40MHZ 0x02000000 1071 1072 uint32_t txdw5; 1073#define R92C_TXDW5_DATARATE_M 0x0000003f 1074#define R92C_TXDW5_DATARATE_S 0 1075#define R92C_TXDW5_SGI 0x00000040 1076#define R92C_TXDW5_AGGNUM_M 0xff000000 1077#define R92C_TXDW5_AGGNUM_S 24 1078 1079 uint32_t txdw6; 1080 uint16_t txdsum; 1081 uint16_t pad; 1082} __packed __attribute__((aligned(4))); 1083 1084 1085static const uint8_t ridx2rate[] = 1086 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 1087 1088/* HW rate indices. */ 1089#define URTWN_RIDX_CCK1 0 1090#define URTWN_RIDX_CCK11 3 1091#define URTWN_RIDX_OFDM6 4 1092#define URTWN_RIDX_OFDM24 8 1093#define URTWN_RIDX_OFDM54 11 1094 1095#define URTWN_RIDX_COUNT 28 1096 1097 1098/* 1099 * MAC initialization values. 1100 */ 1101static const struct { 1102 uint16_t reg; 1103 uint8_t val; 1104} rtl8188eu_mac[] = { 1105 { 0x026, 0x41 }, { 0x027, 0x35 }, { 0x040, 0x00 }, { 0x428, 0x0a }, 1106 { 0x429, 0x10 }, { 0x430, 0x00 }, { 0x431, 0x01 }, { 0x432, 0x02 }, 1107 { 0x433, 0x04 }, { 0x434, 0x05 }, { 0x435, 0x06 }, { 0x436, 0x07 }, 1108 { 0x437, 0x08 }, { 0x438, 0x00 }, { 0x439, 0x00 }, { 0x43a, 0x01 }, 1109 { 0x43b, 0x02 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, { 0x43e, 0x06 }, 1110 { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, { 0x442, 0x00 }, 1111 { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, { 0x447, 0x00 }, 1112 { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, { 0x45b, 0xb9 }, 1113 { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x480, 0x08 }, { 0x4c8, 0xff }, 1114 { 0x4c9, 0x08 }, { 0x4cc, 0xff }, { 0x4cd, 0xff }, { 0x4ce, 0x01 }, 1115 { 0x4d3, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, { 0x502, 0x2f }, 1116 { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, { 0x506, 0x5e }, 1117 { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, { 0x50a, 0x5e }, 1118 { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, { 0x50e, 0x00 }, 1119 { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, { 0x516, 0x0a }, 1120 { 0x525, 0x4f }, { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 }, 1121 { 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a }, 1122 { 0x620, 0xff }, { 0x621, 0xff }, { 0x622, 0xff }, { 0x623, 0xff }, 1123 { 0x624, 0xff }, { 0x625, 0xff }, { 0x626, 0xff }, { 0x627, 0xff }, 1124 { 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0a }, { 0x63e, 0x0e }, 1125 { 0x63f, 0x0e }, { 0x640, 0x40 }, { 0x66e, 0x05 }, { 0x700, 0x21 }, 1126 { 0x701, 0x43 }, { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 }, 1127 { 0x709, 0x43 }, { 0x70a, 0x65 }, { 0x70b, 0x87 } 1128}, rtl8192cu_mac[] = { 1129 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 }, 1130 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 }, 1131 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 }, 1132 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, 1133 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, 1134 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, 1135 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, 1136 { 0x45b, 0xb9 }, { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x462, 0x08 }, 1137 { 0x463, 0x03 }, { 0x4c8, 0xff }, { 0x4c9, 0x08 }, { 0x4cc, 0xff }, 1138 { 0x4cd, 0xff }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, 1139 { 0x502, 0x2f }, { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, 1140 { 0x506, 0x5e }, { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, 1141 { 0x50a, 0x5e }, { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, 1142 { 0x50e, 0x00 }, { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, 1143 { 0x515, 0x10 }, { 0x516, 0x0a }, { 0x517, 0x10 }, { 0x51a, 0x16 }, 1144 { 0x524, 0x0f }, { 0x525, 0x4f }, { 0x546, 0x40 }, { 0x547, 0x00 }, 1145 { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 }, { 0x55a, 0x02 }, 1146 { 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a }, 1147 { 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0e }, { 0x63e, 0x0a }, 1148 { 0x63f, 0x0e }, { 0x66e, 0x05 }, { 0x700, 0x21 }, { 0x701, 0x43 }, 1149 { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 }, { 0x709, 0x43 }, 1150 { 0x70a, 0x65 }, { 0x70b, 0x87 } 1151}; 1152 1153/* 1154 * Baseband initialization values. 1155 */ 1156struct urtwn_bb_prog { 1157 int count; 1158 const uint16_t *regs; 1159 const uint32_t *vals; 1160 int agccount; 1161 const uint32_t *agcvals; 1162}; 1163 1164/* 1165 * RTL8192CU and RTL8192CE-VAU. 1166 */ 1167static const uint16_t rtl8192ce_bb_regs[] = { 1168 0x024, 0x028, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 1169 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 1170 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860, 1171 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884, 1172 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 0x908, 1173 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 1174 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 0xc08, 1175 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 0xc2c, 1176 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 1177 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 1178 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 1179 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 1180 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 0xce0, 1181 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 0xd14, 1182 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 0xd48, 1183 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 0xd6c, 1184 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 1185 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 1186 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 1187 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, 1188 0xed8, 0xedc, 0xee0, 0xeec, 0xf14, 0xf4c, 0xf00 1189}; 1190 1191static const uint32_t rtl8192ce_bb_vals[] = { 1192 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1193 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1194 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1195 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1196 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1197 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1198 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1199 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1200 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1201 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1202 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1203 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1204 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1205 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1206 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1207 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1208 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1209 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1210 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1211 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1212 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1213 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1214 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1215 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1216 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1217 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1218 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1219 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1220 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1221 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1222 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1223 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1224 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1225 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1226 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1227 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1228 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1229 0x00000000, 0x00000300 1230}; 1231 1232static const uint32_t rtl8192ce_agc_vals[] = { 1233 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1234 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1235 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1236 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1237 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1238 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1239 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1240 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1241 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1242 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1243 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1244 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1245 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1246 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1247 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1248 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1249 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1250 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1251 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1252 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1253 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1254 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1255 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1256 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1257 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1258 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1259 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1260 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1261 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1262 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1263 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1264 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1265}; 1266 1267static const struct urtwn_bb_prog rtl8192ce_bb_prog = { 1268 nitems(rtl8192ce_bb_regs), 1269 rtl8192ce_bb_regs, 1270 rtl8192ce_bb_vals, 1271 nitems(rtl8192ce_agc_vals), 1272 rtl8192ce_agc_vals 1273}; 1274 1275/* 1276 * RTL8188CU. 1277 */ 1278static const uint32_t rtl8192cu_bb_vals[] = { 1279 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1280 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1281 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1282 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1283 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1284 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1285 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1286 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1287 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1288 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1289 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1290 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1291 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1292 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1293 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1294 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1295 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1296 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x0186115b, 1297 0x0000001f, 0x00b99612, 0x40000100, 0x20f60000, 0x40000100, 1298 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1299 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1300 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1301 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1302 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1303 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1304 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1305 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1306 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1307 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1308 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1309 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1310 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1311 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1312 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1313 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1314 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1315 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1316 0x00000000, 0x00000300 1317}; 1318 1319static const struct urtwn_bb_prog rtl8192cu_bb_prog = { 1320 nitems(rtl8192ce_bb_regs), 1321 rtl8192ce_bb_regs, 1322 rtl8192cu_bb_vals, 1323 nitems(rtl8192ce_agc_vals), 1324 rtl8192ce_agc_vals 1325}; 1326 1327/* 1328 * RTL8188CE-VAU. 1329 */ 1330static const uint32_t rtl8188ce_bb_vals[] = { 1331 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1332 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1333 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1334 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1335 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1336 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1337 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1338 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1339 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1340 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1341 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1342 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1343 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1344 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1345 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1346 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1347 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1348 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1349 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1350 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1351 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1352 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1353 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1354 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1355 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1356 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1357 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1358 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1359 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1360 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1361 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1362 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1363 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1364 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1365 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1366 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1367 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1368 0x00000000, 0x00000300 1369}; 1370 1371static const uint32_t rtl8188ce_agc_vals[] = { 1372 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1373 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1374 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1375 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1376 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1377 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1378 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1379 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1380 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1381 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1382 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1383 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1384 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1385 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1386 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1387 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1388 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1389 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1390 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1391 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1392 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1393 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1394 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1395 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1396 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1397 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1398 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1399 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1400 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1401 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1402 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1403 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1404}; 1405 1406static const struct urtwn_bb_prog rtl8188ce_bb_prog = { 1407 nitems(rtl8192ce_bb_regs), 1408 rtl8192ce_bb_regs, 1409 rtl8188ce_bb_vals, 1410 nitems(rtl8188ce_agc_vals), 1411 rtl8188ce_agc_vals 1412}; 1413 1414static const uint32_t rtl8188cu_bb_vals[] = { 1415 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1416 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1417 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1418 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1419 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1420 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1421 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1422 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1423 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1424 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1425 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1426 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1427 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1428 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1429 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1430 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1431 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1432 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1433 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1434 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1435 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1436 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1437 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1438 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1439 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1440 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1441 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1442 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1443 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1444 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1445 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1446 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1447 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1448 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1449 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1450 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1451 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1452 0x00000000, 0x00000300 1453}; 1454 1455static const struct urtwn_bb_prog rtl8188cu_bb_prog = { 1456 nitems(rtl8192ce_bb_regs), 1457 rtl8192ce_bb_regs, 1458 rtl8188cu_bb_vals, 1459 nitems(rtl8188ce_agc_vals), 1460 rtl8188ce_agc_vals 1461}; 1462 1463/* 1464 * RTL8188EU. 1465 */ 1466static const uint16_t rtl8188eu_bb_regs[] = { 1467 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 0x81c, 1468 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 1469 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 1470 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 1471 0x880, 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 1472 0x900, 0x904, 0x908, 0x90c, 0x910, 0x914, 0xa00, 0xa04, 1473 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 0xa20, 0xa24, 1474 0xa28, 0xa2c, 0xa70, 0xa74, 0xa78, 0xa7c, 0xa80, 0xb2c, 1475 0xc00, 0xc04, 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 1476 0xc20, 0xc24, 0xc28, 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 1477 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 0xc54, 0xc58, 0xc5c, 1478 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 0xc78, 0xc7c, 1479 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 0xc9c, 1480 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 1481 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 1482 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 1483 0xd10, 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 1484 0xd40, 0xd44, 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 1485 0xd60, 0xd64, 0xd68, 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 1486 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 0xe1c, 0xe28, 0xe30, 1487 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 0xe4c, 0xe50, 1488 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 0xe74, 1489 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, 1490 0xed8, 0xedc, 0xee0, 0xee8, 0xeec, 0xf14, 0xf4c, 0xf00 1491}; 1492 1493static const uint32_t rtl8188eu_bb_vals[] = { 1494 0x80040000, 0x00000003, 0x0000fc00, 0x0000000a, 0x10001331, 1495 0x020c3d10, 0x02200385, 0x00000000, 0x01000100, 0x00390204, 1496 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1497 0x00000000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, 1498 0x00000000, 0x00000000, 0x569a11a9, 0x01000014, 0x66f60110, 1499 0x061f0649, 0x00000000, 0x27272700, 0x07000760, 0x25004000, 1500 0x00000808, 0x00000000, 0xb0000c1c, 0x00000001, 0x00000000, 1501 0xccc000c0, 0x00000800, 0xfffffffe, 0x40302010, 0x00706050, 1502 0x00000000, 0x00000023, 0x00000000, 0x81121111, 0x00000002, 1503 0x00000201, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e7f120f, 1504 0x9500bb78, 0x1114d028, 0x00881117, 0x89140f00, 0x1a1b0000, 1505 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1506 0x00000900, 0x225b0606, 0x218075b1, 0x80000000, 0x48071d40, 1507 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 0x40000100, 1508 0x08800000, 0x40000100, 0x00000000, 0x00000000, 0x00000000, 1509 0x00000000, 0x69e9ac47, 0x469652af, 0x49795994, 0x0a97971c, 1510 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 0x69553420, 1511 0x43bc0094, 0x00013169, 0x00250492, 0x00000000, 0x7112848b, 1512 0x47c00bff, 0x00000036, 0x2c7f000d, 0x020610db, 0x0000001f, 1513 0x00b91612, 0x390000e4, 0x20f60000, 0x40000100, 0x20200000, 1514 0x00091521, 0x00000000, 0x00121820, 0x00007f7f, 0x00000000, 1515 0x000300a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1516 0x00000000, 0x28000000, 0x00000000, 0x00000000, 0x00000000, 1517 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 0x00766932, 1518 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 0x00000740, 1519 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 0x3333bc43, 1520 0x7a8f5b6f, 0xcc979975, 0x00000000, 0x80608000, 0x00000000, 1521 0x00127353, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1522 0x6437140a, 0x00000000, 0x00000282, 0x30032064, 0x4653de68, 1523 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 0x322c2220, 1524 0x000e3c24, 0x2d2d2d2d, 0x2d2d2d2d, 0x0390272d, 0x2d2d2d2d, 1525 0x2d2d2d2d, 0x2d2d2d2d, 0x2d2d2d2d, 0x00000000, 0x1000dc1f, 1526 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 0x01004800, 1527 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 0x02140102, 1528 0x28160d05, 0x00000008, 0x001b25a4, 0x00c00014, 0x00c00014, 1529 0x01000014, 0x01000014, 0x01000014, 0x01000014, 0x00c00014, 1530 0x01000014, 0x00c00014, 0x00c00014, 0x00c00014, 0x00c00014, 1531 0x00000014, 0x00000014, 0x21555448, 0x01c00014, 0x00000003, 1532 0x00000000, 0x00000300 1533}; 1534 1535static const uint32_t rtl8188eu_agc_vals[] = { 1536 0xfb000001, 0xfb010001, 0xfb020001, 0xfb030001, 0xfb040001, 1537 0xfb050001, 0xfa060001, 0xf9070001, 0xf8080001, 0xf7090001, 1538 0xf60a0001, 0xf50b0001, 0xf40c0001, 0xf30d0001, 0xf20e0001, 1539 0xf10f0001, 0xf0100001, 0xef110001, 0xee120001, 0xed130001, 1540 0xec140001, 0xeb150001, 0xea160001, 0xe9170001, 0xe8180001, 1541 0xe7190001, 0xe61a0001, 0xe51b0001, 0xe41c0001, 0xe31d0001, 1542 0xe21e0001, 0xe11f0001, 0x8a200001, 0x89210001, 0x88220001, 1543 0x87230001, 0x86240001, 0x85250001, 0x84260001, 0x83270001, 1544 0x82280001, 0x6b290001, 0x6a2a0001, 0x692b0001, 0x682c0001, 1545 0x672d0001, 0x662e0001, 0x652f0001, 0x64300001, 0x63310001, 1546 0x62320001, 0x61330001, 0x46340001, 0x45350001, 0x44360001, 1547 0x43370001, 0x42380001, 0x41390001, 0x403a0001, 0x403b0001, 1548 0x403c0001, 0x403d0001, 0x403e0001, 0x403f0001, 0xfb400001, 1549 0xfb410001, 0xfb420001, 0xfb430001, 0xfb440001, 0xfb450001, 1550 0xfb460001, 0xfb470001, 0xfb480001, 0xfa490001, 0xf94a0001, 1551 0xf84B0001, 0xf74c0001, 0xf64d0001, 0xf54e0001, 0xf44f0001, 1552 0xf3500001, 0xf2510001, 0xf1520001, 0xf0530001, 0xef540001, 1553 0xee550001, 0xed560001, 0xec570001, 0xeb580001, 0xea590001, 1554 0xe95a0001, 0xe85b0001, 0xe75c0001, 0xe65d0001, 0xe55e0001, 1555 0xe45f0001, 0xe3600001, 0xe2610001, 0xc3620001, 0xc2630001, 1556 0xc1640001, 0x8b650001, 0x8a660001, 0x89670001, 0x88680001, 1557 0x87690001, 0x866a0001, 0x856b0001, 0x846c0001, 0x676d0001, 1558 0x666e0001, 0x656f0001, 0x64700001, 0x63710001, 0x62720001, 1559 0x61730001, 0x60740001, 0x46750001, 0x45760001, 0x44770001, 1560 0x43780001, 0x42790001, 0x417a0001, 0x407b0001, 0x407c0001, 1561 0x407d0001, 0x407e0001, 0x407f0001 1562}; 1563 1564static const struct urtwn_bb_prog rtl8188eu_bb_prog = { 1565 nitems(rtl8188eu_bb_regs), 1566 rtl8188eu_bb_regs, 1567 rtl8188eu_bb_vals, 1568 nitems(rtl8188eu_agc_vals), 1569 rtl8188eu_agc_vals 1570}; 1571 1572/* 1573 * RTL8188RU. 1574 */ 1575static const uint16_t rtl8188ru_bb_regs[] = { 1576 0x024, 0x028, 0x040, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 1577 0x818, 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 1578 0x83c, 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 1579 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 1580 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 1581 0x908, 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 1582 0xa1c, 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 1583 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 1584 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 1585 0xc50, 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 1586 0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 1587 0xc98, 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 1588 0xcbc, 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 1589 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 1590 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 1591 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 1592 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 1593 0xe18, 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 1594 0xe48, 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 1595 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 1596 0xed4, 0xed8, 0xedc, 0xee0, 0xeec, 0xee8, 0xf14, 0xf4c, 0xf00 1597}; 1598 1599static const uint32_t rtl8188ru_bb_vals[] = { 1600 0x0011800d, 0x00ffdb83, 0x000c0004, 0x80040000, 0x00000001, 1601 0x0000fc00, 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 1602 0x00000000, 0x01000100, 0x00390204, 0x00000000, 0x00000000, 1603 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010000, 1604 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1605 0x569a569a, 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 1606 0x32323200, 0x03000300, 0x22004000, 0x00000808, 0x00ffc3f1, 1607 0xc0083070, 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 1608 0xfffffffe, 0x40302010, 0x00706050, 0x00000000, 0x00000023, 1609 0x00000000, 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 1610 0x2e68120f, 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 1611 0x15160000, 0x070b0f12, 0x00000104, 0x00d30000, 0x101fbf00, 1612 0x00000007, 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 1613 0x08800000, 0x40000100, 0x08800000, 0x40000100, 0x00000000, 1614 0x00000000, 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 1615 0x49795994, 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 1616 0x007f037f, 0x6954342e, 0x43bc0094, 0x6954342f, 0x433c0094, 1617 0x00000000, 0x5116848b, 0x47c00bff, 0x00000036, 0x2c56000d, 1618 0x018610db, 0x0000001f, 0x00b91612, 0x24000090, 0x20f60000, 1619 0x24000090, 0x20200000, 0x00121820, 0x00000000, 0x00121820, 1620 0x00007f7f, 0x00000000, 0x00000080, 0x00000000, 0x00000000, 1621 0x00000000, 0x00000000, 0x00000000, 0x28000000, 0x00000000, 1622 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1623 0x64b22427, 0x00766932, 0x00222222, 0x00000000, 0x37644302, 1624 0x2f97d40c, 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 1625 0xa0633333, 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 1626 0x80608000, 0x00000000, 0x00027293, 0x00000000, 0x00000000, 1627 0x00000000, 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 1628 0x30032064, 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 1629 0x1812362e, 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 1630 0x03902a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 1631 0x00000000, 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 1632 0x01007c00, 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 1633 0x10008c1f, 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 1634 0x631b25a0, 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1635 0x081b25a0, 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 1636 0x631b25a0, 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 1637 0x31555448, 0x00000003, 0x00000000, 0x00000300 1638}; 1639 1640static const uint32_t rtl8188ru_agc_vals[] = { 1641 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1642 0x7b050001, 0x7b060001, 0x7b070001, 0x7b080001, 0x7a090001, 1643 0x790a0001, 0x780b0001, 0x770c0001, 0x760d0001, 0x750e0001, 1644 0x740f0001, 0x73100001, 0x72110001, 0x71120001, 0x70130001, 1645 0x6f140001, 0x6e150001, 0x6d160001, 0x6c170001, 0x6b180001, 1646 0x6a190001, 0x691a0001, 0x681b0001, 0x671c0001, 0x661d0001, 1647 0x651e0001, 0x641f0001, 0x63200001, 0x62210001, 0x61220001, 1648 0x60230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1649 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1650 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1651 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1652 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1653 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1654 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1655 0x7b460001, 0x7b470001, 0x7b480001, 0x7a490001, 0x794a0001, 1656 0x784b0001, 0x774c0001, 0x764d0001, 0x754e0001, 0x744f0001, 1657 0x73500001, 0x72510001, 0x71520001, 0x70530001, 0x6f540001, 1658 0x6e550001, 0x6d560001, 0x6c570001, 0x6b580001, 0x6a590001, 1659 0x695a0001, 0x685b0001, 0x675c0001, 0x665d0001, 0x655e0001, 1660 0x645f0001, 0x63600001, 0x62610001, 0x61620001, 0x60630001, 1661 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1662 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1663 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1664 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1665 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1666 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1667 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1668 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1669 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1670 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1671 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1672 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1673}; 1674 1675static const struct urtwn_bb_prog rtl8188ru_bb_prog = { 1676 nitems(rtl8188ru_bb_regs), 1677 rtl8188ru_bb_regs, 1678 rtl8188ru_bb_vals, 1679 nitems(rtl8188ru_agc_vals), 1680 rtl8188ru_agc_vals 1681}; 1682 1683/* 1684 * RF initialization values. 1685 */ 1686struct urtwn_rf_prog { 1687 int count; 1688 const uint8_t *regs; 1689 const uint32_t *vals; 1690}; 1691 1692/* 1693 * RTL8192CU and RTL8192CE-VAU. 1694 */ 1695static const uint8_t rtl8192ce_rf1_regs[] = { 1696 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 1697 0x0f, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 1698 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2a, 0x2b, 1699 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 1700 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 1701 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 1702 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 1703 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 1704 0x2c, 0x2a, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 1705 0x11, 0x10, 0x11, 0x10, 0x11, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 1706 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 1707 0x14, 0x14, 0x15, 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16, 0x00, 1708 0x18, 0xfe, 0xfe, 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 1709}; 1710 1711static const uint32_t rtl8192ce_rf1_vals[] = { 1712 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1713 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1714 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1715 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 1716 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1717 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1718 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1719 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1720 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1721 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1722 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1723 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1724 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1725 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1726 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1727 0x71000, 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 1728 0x18493, 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 1729 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 1730 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1731 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1732 0x30159 1733}; 1734 1735static const uint8_t rtl8192ce_rf2_regs[] = { 1736 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 1737 0x0f, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 1738 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 0x14, 0x14, 0x15, 0x15, 1739 0x15, 0x15, 0x16, 0x16, 0x16, 0x16 1740}; 1741 1742static const uint32_t rtl8192ce_rf2_vals[] = { 1743 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1744 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x32000, 0x71000, 1745 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 0x18493, 1746 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 0x1944c, 1747 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 0xcf424, 1748 0xe0330, 0xa0330, 0x60330, 0x20330 1749}; 1750 1751static const struct urtwn_rf_prog rtl8192ce_rf_prog[] = { 1752 { 1753 nitems(rtl8192ce_rf1_regs), 1754 rtl8192ce_rf1_regs, 1755 rtl8192ce_rf1_vals 1756 }, 1757 { 1758 nitems(rtl8192ce_rf2_regs), 1759 rtl8192ce_rf2_regs, 1760 rtl8192ce_rf2_vals 1761 } 1762}; 1763 1764/* 1765 * RTL8188CE-VAU. 1766 */ 1767static const uint32_t rtl8188ce_rf_vals[] = { 1768 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1769 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1770 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1771 0x00000, 0x01558, 0x00060, 0x00483, 0x4f200, 0xec7d9, 0x577c0, 1772 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1773 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1774 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1775 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1776 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1777 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1778 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1779 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1780 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1781 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1782 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1783 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 1784 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 1785 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 1786 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1787 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1788 0x30159 1789}; 1790 1791static const struct urtwn_rf_prog rtl8188ce_rf_prog[] = { 1792 { 1793 nitems(rtl8192ce_rf1_regs), 1794 rtl8192ce_rf1_regs, 1795 rtl8188ce_rf_vals 1796 } 1797}; 1798 1799 1800/* 1801 * RTL8188CU. 1802 */ 1803static const uint32_t rtl8188cu_rf_vals[] = { 1804 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1805 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1806 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1807 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 1808 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1809 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1810 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1811 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1812 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1813 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1814 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1815 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1816 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1817 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1818 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1819 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 1820 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 1821 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 1822 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1823 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1824 0x30159 1825}; 1826 1827static const struct urtwn_rf_prog rtl8188cu_rf_prog[] = { 1828 { 1829 nitems(rtl8192ce_rf1_regs), 1830 rtl8192ce_rf1_regs, 1831 rtl8188cu_rf_vals 1832 } 1833}; 1834 1835/* 1836 * RTL8188EU. 1837 */ 1838static const uint8_t rtl8188eu_rf_regs[] = { 1839 0x00, 0x08, 0x18, 0x19, 0x1e, 0x1f, 0x2f, 0x3f, 0x42, 0x57, 1840 0x58, 0x67, 0x83, 0xb0, 0xb1, 0xb2, 0xb4, 0xb6, 0xb7, 0xb8, 1841 0xb9, 0xba, 0xbb, 0xbf, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 1842 0xc8, 0xc9, 0xca, 0xdf, 0xef, 0x51, 0x52, 0x53, 0x56, 1843 0x35, 0x35, 0x35, 0x36, 0x36, 0x36, 0x36, 0xb6, 0x18, 0x5a, 1844 0x19, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 1845 0x34, 0x34, 0x00, 0x84, 0x86, 0x87, 0x8e, 0x8f, 0xef, 0x3b, 1846 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 1847 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0xef, 0x00, 0x18, 0xfe, 0xfe, 1848 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 1849}; 1850 1851static const uint32_t rtl8188eu_rf_vals[] = { 1852 0x30000, 0x84000, 0x00407, 0x00012, 0x80009, 0x00880, 0x1a060, 1853 0x00000, 0x060c0, 0xd0000, 0xbe180, 0x01552, 0x00000, 0xff8fc, 1854 0x54400, 0xccc19, 0x43003, 0x4953e, 0x1c718, 0x060ff, 0x80001, 1855 0x40000, 0x00400, 0xc0000, 0x02400, 0x00009, 0x40c91, 0x99999, 1856 0x000a3, 0x88820, 0x76c06, 0x00000, 0x80000, 0x00180, 0x001a0, 1857 0x6b27d, 0x7e49d, 0x00073, 0x51ff3, 0x00086, 0x00186, 1858 0x00286, 0x01c25, 0x09c25, 0x11c25, 0x19c25, 0x48538, 0x00c07, 1859 0x4bd00, 0x739d0, 0x0adf3, 0x09df0, 0x08ded, 0x07dea, 0x06de7, 1860 0x054ee, 0x044eb, 0x034e8, 0x0246b, 0x01468, 0x0006d, 0x30159, 1861 0x68200, 0x000ce, 0x48a00, 0x65540, 0x88000, 0x020a0, 0xf02b0, 1862 0xef7b0, 0xd4fb0, 0xcf060, 0xb0090, 0xa0080, 0x90080, 0x8f780, 1863 0x722b0, 0x6f7b0, 0x54fb0, 0x4f060, 0x30090, 0x20080, 0x10080, 1864 0x0f780, 0x000a0, 0x10159, 0x0f407, 0x00000, 0x00000, 0x80003, 1865 0x00000, 0x00000, 0x00001, 0x80000, 0x33e60 1866}; 1867 1868static const struct urtwn_rf_prog rtl8188eu_rf_prog[] = { 1869 { 1870 nitems(rtl8188eu_rf_regs), 1871 rtl8188eu_rf_regs, 1872 rtl8188eu_rf_vals 1873 } 1874}; 1875 1876/* 1877 * RTL8188RU. 1878 */ 1879static const uint32_t rtl8188ru_rf_vals[] = { 1880 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb0, 1881 0x54867, 0x8992e, 0x0e529, 0x39ce7, 0x00451, 0x00000, 0x00255, 1882 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1883 0x0083c, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x977c0, 1884 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1885 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1886 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1887 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1888 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1889 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1890 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1891 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1892 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1893 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1894 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0xd8000, 1895 0x90000, 0x51000, 0x12000, 0x28fb4, 0x24fa8, 0x207a4, 0x1c798, 1896 0x183a4, 0x14398, 0x101a4, 0x0c198, 0x080a4, 0x04098, 0x00014, 1897 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 1898 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1899 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1900 0x30159 1901}; 1902 1903static const struct urtwn_rf_prog rtl8188ru_rf_prog[] = { 1904 { 1905 nitems(rtl8192ce_rf1_regs), 1906 rtl8192ce_rf1_regs, 1907 rtl8188ru_rf_vals 1908 } 1909}; 1910 1911struct urtwn_txpwr { 1912 uint8_t pwr[3][28]; 1913}; 1914 1915struct urtwn_r88e_txpwr { 1916 uint8_t pwr[6][28]; 1917}; 1918 1919/* 1920 * Per RF chain/group/rate Tx gain values. 1921 */ 1922static const struct urtwn_txpwr rtl8192cu_txagc[] = { 1923 { { /* Chain 0. */ 1924 { /* Group 0. */ 1925 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 1926 0x0c, 0x0c, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* OFDM6~54. */ 1927 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* MCS0~7. */ 1928 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02 /* MCS8~15. */ 1929 }, 1930 { /* Group 1. */ 1931 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 1932 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 1933 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 1934 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 1935 }, 1936 { /* Group 2. */ 1937 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 1938 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ 1939 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 1940 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 1941 } 1942 } }, 1943 { { /* Chain 1. */ 1944 { /* Group 0. */ 1945 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 1946 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 1947 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 1948 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 1949 }, 1950 { /* Group 1. */ 1951 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 1952 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 1953 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 1954 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 1955 }, 1956 { /* Group 2. */ 1957 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 1958 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ 1959 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 1960 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 1961 } 1962 } } 1963}; 1964 1965static const struct urtwn_txpwr rtl8188ru_txagc[] = { 1966 { { /* Chain 0. */ 1967 { /* Group 0. */ 1968 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 1969 0x08, 0x08, 0x08, 0x06, 0x06, 0x04, 0x04, 0x00, /* OFDM6~54. */ 1970 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00, /* MCS0~7. */ 1971 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00 /* MCS8~15. */ 1972 }, 1973 { /* Group 1. */ 1974 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 1975 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 1976 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 1977 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 1978 }, 1979 { /* Group 2. */ 1980 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 1981 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 1982 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 1983 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 1984 } 1985 } } 1986}; 1987 1988static const struct urtwn_r88e_txpwr rtl8188eu_txagc[] = { 1989 { { /* Chain 0. */ 1990 { /* Group 0. */ 1991 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 1992 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 1993 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 1994 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 1995 }, 1996 { /* Group 1. */ 1997 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 1998 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 1999 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2000 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2001 }, 2002 { /* Group 2. */ 2003 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2004 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2005 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2006 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2007 }, 2008 { /* Group 3. */ 2009 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2010 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2011 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2012 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2013 }, 2014 { /* Group 4. */ 2015 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2016 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2017 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2018 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2019 }, 2020 { /* Group 5. */ 2021 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2022 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2023 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2024 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2025 } 2026 } } 2027}; 2028