ubsecreg.h revision 104478
1/* $FreeBSD: head/sys/dev/ubsec/ubsecreg.h 104478 2002-10-04 20:33:20Z sam $ */ 2/* $OpenBSD: ubsecreg.h,v 1.23 2002/05/08 23:05:28 jason Exp $ */ 3 4/* 5 * Copyright (c) 2000 Theo de Raadt 6 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Effort sponsored in part by the Defense Advanced Research Projects 32 * Agency (DARPA) and Air Force Research Laboratory, Air Force 33 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 34 * 35 */ 36 37/* 38 * Register definitions for 5601 BlueSteel Networks Ubiquitous Broadband 39 * Security "uBSec" chip. Definitions from revision 2.8 of the product 40 * datasheet. 41 */ 42 43#define BS_BAR 0x10 /* DMA base address register */ 44#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */ 45#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */ 46 47#define PCI_VENDOR_BROADCOM 0x14e4 /* Broadcom */ 48#define PCI_VENDOR_BLUESTEEL 0x15ab /* Bluesteel Networks */ 49 50/* Bluesteel Networks */ 51#define PCI_PRODUCT_BLUESTEEL_5501 0x0000 /* 5501 */ 52#define PCI_PRODUCT_BLUESTEEL_5601 0x5601 /* 5601 */ 53 54/* Broadcom */ 55#define PCI_PRODUCT_BROADCOM_BCM5700 0x1644 /* BCM5700 */ 56#define PCI_PRODUCT_BROADCOM_BCM5701 0x1645 /* BCM5701 */ 57#define PCI_PRODUCT_BROADCOM_5805 0x5805 /* 5805 */ 58#define PCI_PRODUCT_BROADCOM_5820 0x5820 /* 5820 */ 59#define PCI_PRODUCT_BROADCOM_5821 0x5821 /* 5821 */ 60#define PCI_PRODUCT_BROADCOM_5822 0x5822 /* 5822 */ 61 62#define UBS_PCI_RTY_SHIFT 8 63#define UBS_PCI_RTY_MASK 0xff 64#define UBS_PCI_RTY(misc) \ 65 (((misc) >> UBS_PCI_RTY_SHIFT) & UBS_PCI_RTY_MASK) 66 67#define UBS_PCI_TOUT_SHIFT 0 68#define UBS_PCI_TOUT_MASK 0xff 69#define UBS_PCI_TOUT(misc) \ 70 (((misc) >> PCI_TOUT_SHIFT) & PCI_TOUT_MASK) 71 72/* 73 * DMA Control & Status Registers (offset from BS_BAR) 74 */ 75#define BS_MCR1 0x00 /* DMA Master Command Record 1 */ 76#define BS_CTRL 0x04 /* DMA Control */ 77#define BS_STAT 0x08 /* DMA Status */ 78#define BS_ERR 0x0c /* DMA Error Address */ 79#define BS_MCR2 0x10 /* DMA Master Command Record 2 */ 80 81/* BS_CTRL - DMA Control */ 82#define BS_CTRL_RESET 0x80000000 /* hardware reset, 5805/5820 */ 83#define BS_CTRL_MCR2INT 0x40000000 /* enable intr MCR for MCR2 */ 84#define BS_CTRL_MCR1INT 0x20000000 /* enable intr MCR for MCR1 */ 85#define BS_CTRL_OFM 0x10000000 /* Output fragment mode */ 86#define BS_CTRL_BE32 0x08000000 /* big-endian, 32bit bytes */ 87#define BS_CTRL_BE64 0x04000000 /* big-endian, 64bit bytes */ 88#define BS_CTRL_DMAERR 0x02000000 /* enable intr DMA error */ 89#define BS_CTRL_RNG_M 0x01800000 /* RND mode */ 90#define BS_CTRL_RNG_1 0x00000000 /* 1bit rn/one slow clock */ 91#define BS_CTRL_RNG_4 0x00800000 /* 1bit rn/four slow clocks */ 92#define BS_CTRL_RNG_8 0x01000000 /* 1bit rn/eight slow clocks */ 93#define BS_CTRL_RNG_16 0x01800000 /* 1bit rn/16 slow clocks */ 94#define BS_CTRL_FRAG_M 0x0000ffff /* output fragment size mask */ 95 96/* BS_STAT - DMA Status */ 97#define BS_STAT_MCR1_BUSY 0x80000000 /* MCR1 is busy */ 98#define BS_STAT_MCR1_FULL 0x40000000 /* MCR1 is full */ 99#define BS_STAT_MCR1_DONE 0x20000000 /* MCR1 is done */ 100#define BS_STAT_DMAERR 0x10000000 /* DMA error */ 101#define BS_STAT_MCR2_FULL 0x08000000 /* MCR2 is full */ 102#define BS_STAT_MCR2_DONE 0x04000000 /* MCR2 is done */ 103#define BS_STAT_MCR1_ALLEMPTY 0x02000000 /* MCR1 is completely empty */ 104#define BS_STAT_MCR2_ALLEMPTY 0x01000000 /* MCR2 is completely empty */ 105 106/* BS_ERR - DMA Error Address */ 107#define BS_ERR_ADDR 0xfffffffc /* error address mask */ 108#define BS_ERR_READ 0x00000002 /* fault was on read */ 109 110struct ubsec_pktctx { 111 u_int32_t pc_deskey[6]; /* 3DES key */ 112 u_int32_t pc_hminner[5]; /* hmac inner state */ 113 u_int32_t pc_hmouter[5]; /* hmac outer state */ 114 u_int32_t pc_iv[2]; /* [3]DES iv */ 115 u_int16_t pc_flags; /* flags, below */ 116 u_int16_t pc_offset; /* crypto offset */ 117}; 118#define UBS_PKTCTX_ENC_3DES 0x8000 /* use 3des */ 119#define UBS_PKTCTX_ENC_NONE 0x0000 /* no encryption */ 120#define UBS_PKTCTX_INBOUND 0x4000 /* inbound packet */ 121#define UBS_PKTCTX_AUTH 0x3000 /* authentication mask */ 122#define UBS_PKTCTX_AUTH_NONE 0x0000 /* no authentication */ 123#define UBS_PKTCTX_AUTH_MD5 0x1000 /* use hmac-md5 */ 124#define UBS_PKTCTX_AUTH_SHA1 0x2000 /* use hmac-sha1 */ 125 126struct ubsec_pktctx_long { 127 volatile u_int16_t pc_len; /* length of ctx struct */ 128 volatile u_int16_t pc_type; /* context type, 0 */ 129 volatile u_int16_t pc_flags; /* flags, same as above */ 130 volatile u_int16_t pc_offset; /* crypto/auth offset */ 131 volatile u_int32_t pc_deskey[6]; /* 3DES key */ 132 volatile u_int32_t pc_iv[2]; /* [3]DES iv */ 133 volatile u_int32_t pc_hminner[5]; /* hmac inner state */ 134 volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ 135}; 136#define UBS_PKTCTX_TYPE_IPSEC 0x0000 137 138struct ubsec_pktbuf { 139 volatile u_int32_t pb_addr; /* address of buffer start */ 140 volatile u_int32_t pb_next; /* pointer to next pktbuf */ 141 volatile u_int32_t pb_len; /* packet length */ 142}; 143#define UBS_PKTBUF_LEN 0x0000ffff /* length mask */ 144 145struct ubsec_mcr { 146 volatile u_int16_t mcr_pkts; /* #pkts in this mcr */ 147 volatile u_int16_t mcr_flags; /* mcr flags (below) */ 148 volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */ 149 struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */ 150 volatile u_int16_t mcr_reserved; 151 volatile u_int16_t mcr_pktlen; 152 struct ubsec_pktbuf mcr_opktbuf; /* output chain header */ 153}; 154 155struct ubsec_mcr_add { 156 volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */ 157 struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */ 158 volatile u_int16_t mcr_reserved; 159 volatile u_int16_t mcr_pktlen; 160 struct ubsec_pktbuf mcr_opktbuf; /* output chain header */ 161}; 162 163#define UBS_MCR_DONE 0x0001 /* mcr has been processed */ 164#define UBS_MCR_ERROR 0x0002 /* error in processing */ 165#define UBS_MCR_ERRORCODE 0xff00 /* error type */ 166 167struct ubsec_ctx_keyop { 168 volatile u_int16_t ctx_len; /* command length */ 169 volatile u_int16_t ctx_op; /* operation code */ 170 volatile u_int8_t ctx_pad[60]; /* padding */ 171}; 172#define UBS_CTXOP_DHPKGEN 0x01 /* dh public key generation */ 173#define UBS_CTXOP_DHSSGEN 0x02 /* dh shared secret gen. */ 174#define UBS_CTXOP_RSAPUB 0x03 /* rsa public key op */ 175#define UBS_CTXOP_RSAPRIV 0x04 /* rsa private key op */ 176#define UBS_CTXOP_DSASIGN 0x05 /* dsa signing op */ 177#define UBS_CTXOP_DSAVRFY 0x06 /* dsa verification */ 178#define UBS_CTXOP_RNGBYPASS 0x41 /* rng direct test mode */ 179#define UBS_CTXOP_RNGSHA1 0x42 /* rng sha1 test mode */ 180#define UBS_CTXOP_MODADD 0x43 /* modular addition */ 181#define UBS_CTXOP_MODSUB 0x44 /* modular subtraction */ 182#define UBS_CTXOP_MODMUL 0x45 /* modular multiplication */ 183#define UBS_CTXOP_MODRED 0x46 /* modular reduction */ 184#define UBS_CTXOP_MODEXP 0x47 /* modular exponentiation */ 185#define UBS_CTXOP_MODINV 0x48 /* modular inverse */ 186 187struct ubsec_ctx_rngbypass { 188 volatile u_int16_t rbp_len; /* command length, 64 */ 189 volatile u_int16_t rbp_op; /* rng bypass, 0x41 */ 190 volatile u_int8_t rbp_pad[60]; /* padding */ 191}; 192 193/* modexp: C = (M ^ E) mod N */ 194struct ubsec_ctx_modexp { 195 volatile u_int16_t me_len; /* command length */ 196 volatile u_int16_t me_op; /* modexp, 0x47 */ 197 volatile u_int16_t me_E_len; /* E (bits) */ 198 volatile u_int16_t me_N_len; /* N (bits) */ 199 u_int8_t me_N[1024/8]; /* N */ 200}; 201 202struct ubsec_ctx_rsapriv { 203 volatile u_int16_t rpr_len; /* command length */ 204 volatile u_int16_t rpr_op; /* rsaprivate, 0x04 */ 205 volatile u_int16_t rpr_q_len; /* q (bits) */ 206 volatile u_int16_t rpr_p_len; /* p (bits) */ 207 u_int8_t rpr_buf[5 * 1024 / 8]; /* parameters: */ 208 /* p, q, dp, dq, pinv */ 209}; 210