uart_dev_quicc.c revision 248965
1/*- 2 * Copyright (c) 2006 Juniper Networks 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_quicc.c 248965 2013-04-01 00:44:20Z ian $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/conf.h> 34#include <sys/endian.h> 35#include <machine/bus.h> 36 37#include <dev/ic/quicc.h> 38 39#include <dev/uart/uart.h> 40#include <dev/uart/uart_cpu.h> 41#include <dev/uart/uart_bus.h> 42 43#include "uart_if.h" 44 45#define DEFAULT_RCLK ((266000000 * 2) / 16) 46 47#define quicc_read2(bas, reg) \ 48 bus_space_read_2((bas)->bst, (bas)->bsh, reg) 49#define quicc_read4(bas, reg) \ 50 bus_space_read_4((bas)->bst, (bas)->bsh, reg) 51 52#define quicc_write2(bas, reg, val) \ 53 bus_space_write_2((bas)->bst, (bas)->bsh, reg, val) 54#define quicc_write4(bas, reg, val) \ 55 bus_space_write_4((bas)->bst, (bas)->bsh, reg, val) 56 57static int 58quicc_divisor(int rclk, int baudrate) 59{ 60 int act_baud, divisor, error; 61 62 if (baudrate == 0) 63 return (-1); 64 65 divisor = rclk / baudrate / 16; 66 if (divisor > 4096) 67 divisor = ((divisor >> 3) - 2) | 1; 68 else if (divisor >= 0) 69 divisor = (divisor - 1) << 1; 70 if (divisor < 0 || divisor >= 8192) 71 return (-1); 72 act_baud = rclk / (((divisor >> 1) + 1) << ((divisor & 1) ? 8 : 4)); 73 74 /* 10 times error in percent: */ 75 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1; 76 77 /* 3.0% maximum error tolerance: */ 78 if (error < -30 || error > 30) 79 return (-1); 80 81 return (divisor); 82} 83 84static int 85quicc_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 86 int parity) 87{ 88 int divisor; 89 uint16_t psmr; 90 91 if (baudrate > 0) { 92 divisor = quicc_divisor(bas->rclk, baudrate); 93 if (divisor == -1) 94 return (EINVAL); 95 quicc_write4(bas, QUICC_REG_BRG(bas->chan - 1), 96 divisor | 0x10000); 97 } 98 99 psmr = 0; 100 switch (databits) { 101 case 5: psmr |= 0x0000; break; 102 case 6: psmr |= 0x1000; break; 103 case 7: psmr |= 0x2000; break; 104 case 8: psmr |= 0x3000; break; 105 default: return (EINVAL); 106 } 107 switch (stopbits) { 108 case 1: psmr |= 0x0000; break; 109 case 2: psmr |= 0x4000; break; 110 default: return (EINVAL); 111 } 112 switch (parity) { 113 case UART_PARITY_EVEN: psmr |= 0x1a; break; 114 case UART_PARITY_MARK: psmr |= 0x1f; break; 115 case UART_PARITY_NONE: psmr |= 0x00; break; 116 case UART_PARITY_ODD: psmr |= 0x10; break; 117 case UART_PARITY_SPACE: psmr |= 0x15; break; 118 default: return (EINVAL); 119 } 120 quicc_write2(bas, QUICC_REG_SCC_PSMR(bas->chan - 1), psmr); 121 return (0); 122} 123 124static void 125quicc_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits, 126 int parity) 127{ 128 129 if (bas->rclk == 0) 130 bas->rclk = DEFAULT_RCLK; 131 132 /* 133 * GSMR_L = 0x00028034 134 * GSMR_H = 0x00000020 135 */ 136 quicc_param(bas, baudrate, databits, stopbits, parity); 137 138 quicc_write2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1), ~0); 139 quicc_write2(bas, QUICC_REG_SCC_SCCM(bas->chan - 1), 0x0027); 140} 141 142/* 143 * Low-level UART interface. 144 */ 145static int quicc_probe(struct uart_bas *bas); 146static void quicc_init(struct uart_bas *bas, int, int, int, int); 147static void quicc_term(struct uart_bas *bas); 148static void quicc_putc(struct uart_bas *bas, int); 149static int quicc_rxready(struct uart_bas *bas); 150static int quicc_getc(struct uart_bas *bas, struct mtx *); 151 152static struct uart_ops uart_quicc_ops = { 153 .probe = quicc_probe, 154 .init = quicc_init, 155 .term = quicc_term, 156 .putc = quicc_putc, 157 .rxready = quicc_rxready, 158 .getc = quicc_getc, 159}; 160 161static int 162quicc_probe(struct uart_bas *bas) 163{ 164 165 return (0); 166} 167 168static void 169quicc_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 170 int parity) 171{ 172 173 quicc_setup(bas, baudrate, databits, stopbits, parity); 174} 175 176static void 177quicc_term(struct uart_bas *bas) 178{ 179} 180 181static void 182quicc_putc(struct uart_bas *bas, int c) 183{ 184 int unit; 185 uint16_t toseq; 186 187 unit = bas->chan - 1; 188 while (quicc_read2(bas, QUICC_PRAM_SCC_UART_TOSEQ(unit)) & 0x2000) 189 DELAY(10); 190 191 toseq = 0x2000 | (c & 0xff); 192 quicc_write2(bas, QUICC_PRAM_SCC_UART_TOSEQ(unit), toseq); 193} 194 195static int 196quicc_rxready(struct uart_bas *bas) 197{ 198 uint16_t rb; 199 200 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1)); 201 return ((quicc_read2(bas, rb) & 0x8000) ? 0 : 1); 202} 203 204static int 205quicc_getc(struct uart_bas *bas, struct mtx *hwmtx) 206{ 207 volatile char *buf; 208 int c; 209 uint16_t rb, sc; 210 211 uart_lock(hwmtx); 212 213 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1)); 214 215 while ((sc = quicc_read2(bas, rb)) & 0x8000) { 216 uart_unlock(hwmtx); 217 DELAY(4); 218 uart_lock(hwmtx); 219 } 220 221 buf = (void *)(uintptr_t)quicc_read4(bas, rb + 4); 222 c = *buf; 223 quicc_write2(bas, rb, sc | 0x8000); 224 225 uart_unlock(hwmtx); 226 227 return (c); 228} 229 230/* 231 * High-level UART interface. 232 */ 233struct quicc_softc { 234 struct uart_softc base; 235}; 236 237static int quicc_bus_attach(struct uart_softc *); 238static int quicc_bus_detach(struct uart_softc *); 239static int quicc_bus_flush(struct uart_softc *, int); 240static int quicc_bus_getsig(struct uart_softc *); 241static int quicc_bus_ioctl(struct uart_softc *, int, intptr_t); 242static int quicc_bus_ipend(struct uart_softc *); 243static int quicc_bus_param(struct uart_softc *, int, int, int, int); 244static int quicc_bus_probe(struct uart_softc *); 245static int quicc_bus_receive(struct uart_softc *); 246static int quicc_bus_setsig(struct uart_softc *, int); 247static int quicc_bus_transmit(struct uart_softc *); 248 249static kobj_method_t quicc_methods[] = { 250 KOBJMETHOD(uart_attach, quicc_bus_attach), 251 KOBJMETHOD(uart_detach, quicc_bus_detach), 252 KOBJMETHOD(uart_flush, quicc_bus_flush), 253 KOBJMETHOD(uart_getsig, quicc_bus_getsig), 254 KOBJMETHOD(uart_ioctl, quicc_bus_ioctl), 255 KOBJMETHOD(uart_ipend, quicc_bus_ipend), 256 KOBJMETHOD(uart_param, quicc_bus_param), 257 KOBJMETHOD(uart_probe, quicc_bus_probe), 258 KOBJMETHOD(uart_receive, quicc_bus_receive), 259 KOBJMETHOD(uart_setsig, quicc_bus_setsig), 260 KOBJMETHOD(uart_transmit, quicc_bus_transmit), 261 { 0, 0 } 262}; 263 264struct uart_class uart_quicc_class = { 265 "quicc", 266 quicc_methods, 267 sizeof(struct quicc_softc), 268 .uc_ops = &uart_quicc_ops, 269 .uc_range = 2, 270 .uc_rclk = DEFAULT_RCLK 271}; 272 273#define SIGCHG(c, i, s, d) \ 274 if (c) { \ 275 i |= (i & s) ? s : s | d; \ 276 } else { \ 277 i = (i & s) ? (i & ~s) | d : i; \ 278 } 279 280static int 281quicc_bus_attach(struct uart_softc *sc) 282{ 283 struct uart_bas *bas; 284 struct uart_devinfo *di; 285 uint16_t st, rb; 286 287 bas = &sc->sc_bas; 288 if (sc->sc_sysdev != NULL) { 289 di = sc->sc_sysdev; 290 quicc_param(bas, di->baudrate, di->databits, di->stopbits, 291 di->parity); 292 } else { 293 quicc_setup(bas, 9600, 8, 1, UART_PARITY_NONE); 294 } 295 296 /* Enable interrupts on the receive buffer. */ 297 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1)); 298 st = quicc_read2(bas, rb); 299 quicc_write2(bas, rb, st | 0x9000); 300 301 (void)quicc_bus_getsig(sc); 302 303 return (0); 304} 305 306static int 307quicc_bus_detach(struct uart_softc *sc) 308{ 309 310 return (0); 311} 312 313static int 314quicc_bus_flush(struct uart_softc *sc, int what) 315{ 316 317 return (0); 318} 319 320static int 321quicc_bus_getsig(struct uart_softc *sc) 322{ 323 uint32_t new, old, sig; 324 uint32_t dummy; 325 326 do { 327 old = sc->sc_hwsig; 328 sig = old; 329 uart_lock(sc->sc_hwmtx); 330 /* XXX SIGNALS */ 331 dummy = 0; 332 uart_unlock(sc->sc_hwmtx); 333 SIGCHG(dummy, sig, SER_CTS, SER_DCTS); 334 SIGCHG(dummy, sig, SER_DCD, SER_DDCD); 335 SIGCHG(dummy, sig, SER_DSR, SER_DDSR); 336 new = sig & ~SER_MASK_DELTA; 337 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 338 return (sig); 339} 340 341static int 342quicc_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 343{ 344 struct uart_bas *bas; 345 uint32_t brg; 346 int baudrate, error; 347 348 bas = &sc->sc_bas; 349 error = 0; 350 uart_lock(sc->sc_hwmtx); 351 switch (request) { 352 case UART_IOCTL_BREAK: 353 break; 354 case UART_IOCTL_BAUD: 355 brg = quicc_read4(bas, QUICC_REG_BRG(bas->chan - 1)) & 0x1fff; 356 brg = (brg & 1) ? (brg + 1) << 3 : (brg + 2) >> 1; 357 baudrate = bas->rclk / (brg * 16); 358 *(int*)data = baudrate; 359 break; 360 default: 361 error = EINVAL; 362 break; 363 } 364 uart_unlock(sc->sc_hwmtx); 365 return (error); 366} 367 368static int 369quicc_bus_ipend(struct uart_softc *sc) 370{ 371 struct uart_bas *bas; 372 int ipend; 373 uint16_t scce; 374 375 bas = &sc->sc_bas; 376 ipend = 0; 377 378 uart_lock(sc->sc_hwmtx); 379 scce = quicc_read2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1)); 380 quicc_write2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1), ~0); 381 uart_unlock(sc->sc_hwmtx); 382 if (scce & 0x0001) 383 ipend |= SER_INT_RXREADY; 384 if (scce & 0x0002) 385 ipend |= SER_INT_TXIDLE; 386 if (scce & 0x0004) 387 ipend |= SER_INT_OVERRUN; 388 if (scce & 0x0020) 389 ipend |= SER_INT_BREAK; 390 /* XXX SIGNALS */ 391 return (ipend); 392} 393 394static int 395quicc_bus_param(struct uart_softc *sc, int baudrate, int databits, 396 int stopbits, int parity) 397{ 398 int error; 399 400 uart_lock(sc->sc_hwmtx); 401 error = quicc_param(&sc->sc_bas, baudrate, databits, stopbits, 402 parity); 403 uart_unlock(sc->sc_hwmtx); 404 return (error); 405} 406 407static int 408quicc_bus_probe(struct uart_softc *sc) 409{ 410 char buf[80]; 411 int error; 412 413 error = quicc_probe(&sc->sc_bas); 414 if (error) 415 return (error); 416 417 sc->sc_rxfifosz = 1; 418 sc->sc_txfifosz = 1; 419 420 snprintf(buf, sizeof(buf), "quicc, channel %d", sc->sc_bas.chan); 421 device_set_desc_copy(sc->sc_dev, buf); 422 return (0); 423} 424 425static int 426quicc_bus_receive(struct uart_softc *sc) 427{ 428 struct uart_bas *bas; 429 volatile char *buf; 430 uint16_t st, rb; 431 432 bas = &sc->sc_bas; 433 uart_lock(sc->sc_hwmtx); 434 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1)); 435 st = quicc_read2(bas, rb); 436 buf = (void *)(uintptr_t)quicc_read4(bas, rb + 4); 437 uart_rx_put(sc, *buf); 438 quicc_write2(bas, rb, st | 0x9000); 439 uart_unlock(sc->sc_hwmtx); 440 return (0); 441} 442 443static int 444quicc_bus_setsig(struct uart_softc *sc, int sig) 445{ 446 struct uart_bas *bas; 447 uint32_t new, old; 448 449 bas = &sc->sc_bas; 450 do { 451 old = sc->sc_hwsig; 452 new = old; 453 if (sig & SER_DDTR) { 454 SIGCHG(sig & SER_DTR, new, SER_DTR, 455 SER_DDTR); 456 } 457 if (sig & SER_DRTS) { 458 SIGCHG(sig & SER_RTS, new, SER_RTS, 459 SER_DRTS); 460 } 461 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 462 463 uart_lock(sc->sc_hwmtx); 464 /* XXX SIGNALS */ 465 uart_unlock(sc->sc_hwmtx); 466 return (0); 467} 468 469static int 470quicc_bus_transmit(struct uart_softc *sc) 471{ 472 volatile char *buf; 473 struct uart_bas *bas; 474 uint16_t st, tb; 475 476 bas = &sc->sc_bas; 477 uart_lock(sc->sc_hwmtx); 478 tb = quicc_read2(bas, QUICC_PRAM_SCC_TBASE(bas->chan - 1)); 479 st = quicc_read2(bas, tb); 480 buf = (void *)(uintptr_t)quicc_read4(bas, tb + 4); 481 *buf = sc->sc_txbuf[0]; 482 quicc_write2(bas, tb + 2, 1); 483 quicc_write2(bas, tb, st | 0x9000); 484 sc->sc_txbusy = 1; 485 uart_unlock(sc->sc_hwmtx); 486 return (0); 487} 488