if_txvar.h revision 78677
1/* $OpenBSD: if_txvar.h,v 1.7 1999/11/17 05:21:19 jason Exp $ */ 2/* $FreeBSD: head/sys/dev/tx/if_txvar.h 78677 2001-06-23 19:30:26Z semenu $ */ 3 4/*- 5 * Copyright (c) 1997 Semen Ustimenko 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/* 31 * Configuration 32 */ 33/*#define EPIC_DEBUG 1*/ 34/*#define EPIC_USEIOSPACE 1*/ 35#define EARLY_RX 1 36 37#ifndef ETHER_MAX_LEN 38#define ETHER_MAX_LEN 1518 39#endif 40#ifndef ETHER_MIN_LEN 41#define ETHER_MIN_LEN 64 42#endif 43#ifndef ETHER_CRC_LEN 44#define ETHER_CRC_LEN 4 45#endif 46#define TX_RING_SIZE 16 /* Leave this a power of 2 */ 47#define RX_RING_SIZE 16 /* And this too, to do not */ 48 /* confuse RX(TX)_RING_MASK */ 49#define TX_RING_MASK (TX_RING_SIZE - 1) 50#define RX_RING_MASK (RX_RING_SIZE - 1) 51#define ETHER_MAX_FRAME_LEN (ETHER_MAX_LEN + ETHER_CRC_LEN) 52 53/* PCI aux configuration registers */ 54#if defined(__FreeBSD__) 55#define PCIR_BASEIO (PCIR_MAPS + 0x0) /* Base IO Address */ 56#define PCIR_BASEMEM (PCIR_MAPS + 0x4) /* Base Memory Address */ 57#else /* __OpenBSD__ */ 58#define PCI_BASEIO (PCI_MAPS + 0x0) /* Base IO Address */ 59#define PCI_BASEMEM (PCI_MAPS + 0x4) /* Base Memory Address */ 60#endif /* __FreeBSD__ */ 61 62/* PCI identification */ 63#define SMC_VENDORID 0x10B8 64#define SMC_DEVICEID_83C170 0x0005 65 66/* EPIC's registers */ 67#define COMMAND 0x0000 68#define INTSTAT 0x0004 /* Interrupt status. See below */ 69#define INTMASK 0x0008 /* Interrupt mask. See below */ 70#define GENCTL 0x000C 71#define NVCTL 0x0010 72#define EECTL 0x0014 /* EEPROM control **/ 73#define TEST1 0x001C /* XXXXX */ 74#define CRCCNT 0x0020 /* CRC error counter */ 75#define ALICNT 0x0024 /* FrameTooLang error counter */ 76#define MPCNT 0x0028 /* MissedFrames error counters */ 77#define MIICTL 0x0030 78#define MIIDATA 0x0034 79#define MIICFG 0x0038 80#define IPG 0x003C 81#define LAN0 0x0040 /* MAC address */ 82#define LAN1 0x0044 /* MAC address */ 83#define LAN2 0x0048 /* MAC address */ 84#define ID_CHK 0x004C 85#define MC0 0x0050 /* Multicast filter table */ 86#define MC1 0x0054 /* Multicast filter table */ 87#define MC2 0x0058 /* Multicast filter table */ 88#define MC3 0x005C /* Multicast filter table */ 89#define RXCON 0x0060 /* Rx control register */ 90#define TXCON 0x0070 /* Tx control register */ 91#define TXSTAT 0x0074 92#define PRCDAR 0x0084 /* RxRing bus address */ 93#define PRSTAT 0x00A4 94#define PRCPTHR 0x00B0 95#define PTCDAR 0x00C4 /* TxRing bus address */ 96#define ETXTHR 0x00DC 97 98#define COMMAND_STOP_RX 0x01 99#define COMMAND_START_RX 0x02 100#define COMMAND_TXQUEUED 0x04 101#define COMMAND_RXQUEUED 0x08 102#define COMMAND_NEXTFRAME 0x10 103#define COMMAND_STOP_TDMA 0x20 104#define COMMAND_STOP_RDMA 0x40 105#define COMMAND_TXUGO 0x80 106 107/* Interrupt register bits */ 108#define INTSTAT_RCC 0x00000001 109#define INTSTAT_HCC 0x00000002 110#define INTSTAT_RQE 0x00000004 111#define INTSTAT_OVW 0x00000008 112#define INTSTAT_RXE 0x00000010 113#define INTSTAT_TXC 0x00000020 114#define INTSTAT_TCC 0x00000040 115#define INTSTAT_TQE 0x00000080 116#define INTSTAT_TXU 0x00000100 117#define INTSTAT_CNT 0x00000200 118#define INTSTAT_PREI 0x00000400 119#define INTSTAT_RCT 0x00000800 120#define INTSTAT_FATAL 0x00001000 /* One of DPE,APE,PMA,PTA happend */ 121#define INTSTAT_UNUSED1 0x00002000 122#define INTSTAT_UNUSED2 0x00004000 123#define INTSTAT_GP2 0x00008000 /* PHY Event */ 124#define INTSTAT_INT_ACTV 0x00010000 125#define INTSTAT_RXIDLE 0x00020000 126#define INTSTAT_TXIDLE 0x00040000 127#define INTSTAT_RCIP 0x00080000 128#define INTSTAT_TCIP 0x00100000 129#define INTSTAT_RBE 0x00200000 130#define INTSTAT_RCTS 0x00400000 131#define INTSTAT_RSV 0x00800000 132#define INTSTAT_DPE 0x01000000 /* PCI Fatal error */ 133#define INTSTAT_APE 0x02000000 /* PCI Fatal error */ 134#define INTSTAT_PMA 0x04000000 /* PCI Fatal error */ 135#define INTSTAT_PTA 0x08000000 /* PCI Fatal error */ 136 137#define GENCTL_SOFT_RESET 0x00000001 138#define GENCTL_ENABLE_INTERRUPT 0x00000002 139#define GENCTL_SOFTWARE_INTERRUPT 0x00000004 140#define GENCTL_POWER_DOWN 0x00000008 141#define GENCTL_ONECOPY 0x00000010 142#define GENCTL_BIG_ENDIAN 0x00000020 143#define GENCTL_RECEIVE_DMA_PRIORITY 0x00000040 144#define GENCTL_TRANSMIT_DMA_PRIORITY 0x00000080 145#define GENCTL_RECEIVE_FIFO_THRESHOLD128 0x00000300 146#define GENCTL_RECEIVE_FIFO_THRESHOLD96 0x00000200 147#define GENCTL_RECEIVE_FIFO_THRESHOLD64 0x00000100 148#define GENCTL_RECEIVE_FIFO_THRESHOLD32 0x00000000 149#define GENCTL_MEMORY_READ_LINE 0x00000400 150#define GENCTL_MEMORY_READ_MULTIPLE 0x00000800 151#define GENCTL_SOFTWARE1 0x00001000 152#define GENCTL_SOFTWARE2 0x00002000 153#define GENCTL_RESET_PHY 0x00004000 154 155#define NVCTL_ENABLE_MEMORY_MAP 0x00000001 156#define NVCTL_CLOCK_RUN_SUPPORTED 0x00000002 157#define NVCTL_GP1_OUTPUT_ENABLE 0x00000004 158#define NVCTL_GP2_OUTPUT_ENABLE 0x00000008 159#define NVCTL_GP1 0x00000010 160#define NVCTL_GP2 0x00000020 161#define NVCTL_CARDBUS_MODE 0x00000040 162#define NVCTL_IPG_DELAY_MASK(x) ((x&0xF)<<7) 163 164#define RXCON_SAVE_ERRORED_PACKETS 0x00000001 165#define RXCON_RECEIVE_RUNT_FRAMES 0x00000002 166#define RXCON_RECEIVE_BROADCAST_FRAMES 0x00000004 167#define RXCON_RECEIVE_MULTICAST_FRAMES 0x00000008 168#define RXCON_RECEIVE_INVERSE_INDIVIDUAL_ADDRESS_FRAMES 0x00000010 169#define RXCON_PROMISCUOUS_MODE 0x00000020 170#define RXCON_MONITOR_MODE 0x00000040 171#define RXCON_EARLY_RECEIVE_ENABLE 0x00000080 172#define RXCON_EXTERNAL_BUFFER_DISABLE 0x00000000 173#define RXCON_EXTERNAL_BUFFER_16K 0x00000100 174#define RXCON_EXTERNAL_BUFFER_32K 0x00000200 175#define RXCON_EXTERNAL_BUFFER_128K 0x00000300 176 177#define TXCON_EARLY_TRANSMIT_ENABLE 0x00000001 178#define TXCON_LOOPBACK_DISABLE 0x00000000 179#define TXCON_LOOPBACK_MODE_INT 0x00000002 180#define TXCON_LOOPBACK_MODE_PHY 0x00000004 181#define TXCON_LOOPBACK_MODE 0x00000006 182#define TXCON_FULL_DUPLEX 0x00000006 183#define TXCON_SLOT_TIME 0x00000078 184 185#define MIICFG_SERIAL_ENABLE 0x00000001 186#define MIICFG_694_ENABLE 0x00000002 187#define MIICFG_694_STATUS 0x00000004 188#define MIICFG_PHY_PRESENT 0x00000008 189#define MIICFG_SMI_ENABLE 0x00000010 190 191#define TEST1_CLOCK_TEST 0x00000008 192 193/* 194 * Some default values 195 */ 196#define TXCON_DEFAULT (TXCON_SLOT_TIME | TXCON_EARLY_TRANSMIT_ENABLE) 197#define TRANSMIT_THRESHOLD 0x300 198 199#if defined(EARLY_RX) 200#define RXCON_EARLY (RXCON_EARLY_RECEIVE_ENABLE | \ 201 RXCON_SAVE_ERRORED_PACKETS) 202#else 203#define RXCON_EARLY (0) 204#endif 205 206#define RXCON_DEFAULT (RXCON_EARLY | \ 207 RXCON_RECEIVE_MULTICAST_FRAMES | \ 208 RXCON_RECEIVE_BROADCAST_FRAMES) 209/* 210 * EEPROM structure 211 * SMC9432* eeprom is organized by words and only first 8 words 212 * have distinctive meaning (according to datasheet) 213 */ 214#define EEPROM_MAC0 0x0000 /* Byte 0 / Byte 1 */ 215#define EEPROM_MAC1 0x0001 /* Byte 2 / Byte 3 */ 216#define EEPROM_MAC2 0x0002 /* Byte 4 / Byte 5 */ 217#define EEPROM_BID_CSUM 0x0003 /* Board Id / Check Sum */ 218#define EEPROM_NVCTL 0x0004 /* NVCTL (bits 0-5) / nothing */ 219#define EEPROM_PCI_MGD_MLD 0x0005 /* PCI MinGrant / MaxLatency. Desired */ 220#define EEPROM_SSVENDID 0x0006 /* Subsystem Vendor Id */ 221#define EEPROM_SSID 0x0006 /* Subsystem Id */ 222 223/* 224 * Structures definition and Functions prototypes 225 */ 226 227/* EPIC's hardware descriptors, must be aligned on dword in memory */ 228/* NB: to make driver happy, this two structures MUST have thier sizes */ 229/* be divisor of PAGE_SIZE */ 230struct epic_tx_desc { 231 volatile u_int16_t status; 232 volatile u_int16_t txlength; 233 volatile u_int32_t bufaddr; 234 volatile u_int16_t buflength; 235 volatile u_int16_t control; 236 volatile u_int32_t next; 237}; 238struct epic_rx_desc { 239 volatile u_int16_t status; 240 volatile u_int16_t rxlength; 241 volatile u_int32_t bufaddr; 242 volatile u_int32_t buflength; 243 volatile u_int32_t next; 244}; 245 246/* This structure defines EPIC's fragment list, maximum number of frags */ 247/* is 63. Let use maximum, becouse size of struct MUST be divisor of */ 248/* PAGE_SIZE, and sometimes come mbufs with more then 30 frags */ 249#define EPIC_MAX_FRAGS 63 250struct epic_frag_list { 251 volatile u_int32_t numfrags; 252 struct { 253 volatile u_int32_t fragaddr; 254 volatile u_int32_t fraglen; 255 } frag[EPIC_MAX_FRAGS]; 256 volatile u_int32_t pad; /* align on 256 bytes */ 257}; 258 259/* This is driver's structure to define EPIC descriptors */ 260struct epic_rx_buffer { 261 struct mbuf * mbuf; /* mbuf receiving packet */ 262}; 263 264struct epic_tx_buffer { 265 struct mbuf * mbuf; /* mbuf contained packet */ 266}; 267 268/* 269 * NB: ALIGN OF ABOVE STRUCTURES 270 * epic_rx_desc, epic_tx_desc, epic_frag_list - must be aligned on dword 271 */ 272 273/* PHY, known by tx driver */ 274#define EPIC_UNKN_PHY 0x0000 275#define EPIC_QS6612_PHY 0x0001 276#define EPIC_AC101_PHY 0x0002 277#define EPIC_LXT970_PHY 0x0003 278#define EPIC_SERIAL 0x0004 279 280#define SMC9432DMT 0xA010 281#define SMC9432TX 0xA011 282#define SMC9032TXM 0xA012 283#define SMC9032TX 0xA013 284#define SMC9432TXPWR 0xA014 285#define SMC9432BTX 0xA015 286#define SMC9432FTX 0xA016 287#define SMC9432FTX_SC 0xA017 288#define SMC9432TX_XG_ADHOC 0xA020 289#define SMC9434TX_XG_ADHOC 0xA021 290#define SMC9432FTX_ADHOC 0xA022 291#define SMC9432BTX1 0xA024 292 293/* Driver status structure */ 294typedef struct { 295 struct arpcom arpcom; 296#if defined(__OpenBSD__) 297 mii_data_t sc_mii; 298 struct device dev; 299#else /* __FreeBSD__ */ 300 struct resource *res; 301 struct resource *irq; 302 303 device_t miibus; 304 device_t dev; 305 struct callout_handle stat_ch; 306 307 u_int32_t unit; 308#endif 309 void *sc_ih; 310 bus_space_tag_t sc_st; 311 bus_space_handle_t sc_sh; 312 313 struct epic_rx_buffer rx_buffer[RX_RING_SIZE]; 314 struct epic_tx_buffer tx_buffer[TX_RING_SIZE]; 315 316 /* Each element of array MUST be aligned on dword */ 317 /* and bounded on PAGE_SIZE */ 318 struct epic_rx_desc *rx_desc; 319 struct epic_tx_desc *tx_desc; 320 struct epic_frag_list *tx_flist; 321 u_int32_t flags; 322 u_int32_t tx_threshold; 323 u_int32_t txcon; 324 u_int32_t miicfg; 325 u_int32_t cur_tx; 326 u_int32_t cur_rx; 327 u_int32_t dirty_tx; 328 u_int32_t pending_txs; 329 u_int16_t cardvend; 330 u_int16_t cardid; 331 struct mii_softc *physc; 332 u_int32_t phyid; 333 int serinst; 334 void *pool; 335} epic_softc_t; 336 337struct epic_type { 338 u_int16_t ven_id; 339 u_int16_t dev_id; 340 char *name; 341}; 342 343#if defined(EPIC_DEBUG) 344#define dprintf(a) printf a 345#else 346#define dprintf(a) 347#endif 348 349#if defined(__FreeBSD__) 350#define EPIC_FORMAT "tx%d" 351#define EPIC_ARGS(sc) (sc->unit) 352#define EPIC_BPFTAP_ARG(ifp) ifp 353#else /* __OpenBSD__ */ 354#define EPIC_FORMAT "%s" 355#define EPIC_ARGS(sc) (sc->sc_dev.dv_xname) 356#define EPIC_BPFTAP_ARG(ifp) (ifp)->if_bpf 357#endif 358 359#define sc_if arpcom.ac_if 360#define sc_macaddr arpcom.ac_enaddr 361 362#define CSR_WRITE_4(sc,reg,val) \ 363 bus_space_write_4( (sc)->sc_st, (sc)->sc_sh, (reg), (val) ) 364#define CSR_WRITE_2(sc,reg,val) \ 365 bus_space_write_2( (sc)->sc_st, (sc)->sc_sh, (reg), (val) ) 366#define CSR_WRITE_1(sc,reg,val) \ 367 bus_space_write_1( (sc)->sc_st, (sc)->sc_sh, (reg), (val) ) 368#define CSR_READ_4(sc,reg) \ 369 bus_space_read_4( (sc)->sc_st, (sc)->sc_sh, (reg) ) 370#define CSR_READ_2(sc,reg) \ 371 bus_space_read_2( (sc)->sc_st, (sc)->sc_sh, (reg) ) 372#define CSR_READ_1(sc,reg) \ 373 bus_space_read_1( (sc)->sc_st, (sc)->sc_sh, (reg) ) 374 375#define PHY_READ_2(sc,phy,reg) \ 376 epic_read_phy_reg((sc),(phy),(reg)) 377#define PHY_WRITE_2(sc,phy,reg,val) \ 378 epic_write_phy_reg((sc),(phy),(reg),(val)) 379 380/* Macro to get either mbuf cluster or nothing */ 381#define EPIC_MGETCLUSTER(m) \ 382 { MGETHDR((m),M_DONTWAIT,MT_DATA); \ 383 if (m) { \ 384 MCLGET((m),M_DONTWAIT); \ 385 if( 0 == ((m)->m_flags & M_EXT) ) { \ 386 m_freem(m); \ 387 (m) = NULL; \ 388 } \ 389 } \ 390 } 391 392