if_txvar.h revision 105666
1218885Sdim/*- 2218885Sdim * Copyright (c) 1997 Semen Ustimenko 3218885Sdim * All rights reserved. 4218885Sdim * 5218885Sdim * Redistribution and use in source and binary forms, with or without 6218885Sdim * modification, are permitted provided that the following conditions 7218885Sdim * are met: 8218885Sdim * 1. Redistributions of source code must retain the above copyright 9218885Sdim * notice, this list of conditions and the following disclaimer. 10218885Sdim * 2. Redistributions in binary form must reproduce the above copyright 11218885Sdim * notice, this list of conditions and the following disclaimer in the 12218885Sdim * documentation and/or other materials provided with the distribution. 13218885Sdim * 14249423Sdim * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15249423Sdim * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16249423Sdim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17218885Sdim * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18218885Sdim * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19218885Sdim * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20218885Sdim * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21218885Sdim * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22218885Sdim * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23218885Sdim * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24218885Sdim * SUCH DAMAGE. 25218885Sdim * 26218885Sdim * $FreeBSD: head/sys/dev/tx/if_txvar.h 105666 2002-10-22 00:57:51Z semenu $ 27218885Sdim */ 28218885Sdim 29218885Sdim/* 30218885Sdim * Configuration 31218885Sdim */ 32218885Sdim/*#define EPIC_DIAG 1*/ 33218885Sdim/*#define EPIC_USEIOSPACE 1*/ 34218885Sdim/*#define EPIC_EARLY_RX 1*/ 35218885Sdim 36218885Sdim#ifndef ETHER_MAX_LEN 37218885Sdim#define ETHER_MAX_LEN 1518 38221345Sdim#endif 39218885Sdim#ifndef ETHER_MIN_LEN 40218885Sdim#define ETHER_MIN_LEN 64 41218885Sdim#endif 42218885Sdim#ifndef ETHER_CRC_LEN 43218885Sdim#define ETHER_CRC_LEN 4 44221345Sdim#endif 45218885Sdim#define TX_RING_SIZE 16 /* Leave this a power of 2 */ 46218885Sdim#define RX_RING_SIZE 16 /* And this too, to do not */ 47218885Sdim /* confuse RX(TX)_RING_MASK */ 48218885Sdim#define TX_RING_MASK (TX_RING_SIZE - 1) 49218885Sdim#define RX_RING_MASK (RX_RING_SIZE - 1) 50218885Sdim#define ETHER_MAX_FRAME_LEN (ETHER_MAX_LEN + ETHER_CRC_LEN) 51218885Sdim 52218885Sdim/* This is driver's structure to define EPIC descriptors */ 53218885Sdimstruct epic_rx_buffer { 54218885Sdim struct mbuf * mbuf; /* mbuf receiving packet */ 55218885Sdim}; 56218885Sdim 57218885Sdimstruct epic_tx_buffer { 58218885Sdim struct mbuf * mbuf; /* mbuf contained packet */ 59218885Sdim}; 60218885Sdim 61218885Sdim/* PHY, known by tx driver */ 62218885Sdim#define EPIC_UNKN_PHY 0x0000 63218885Sdim#define EPIC_QS6612_PHY 0x0001 64218885Sdim#define EPIC_AC101_PHY 0x0002 65218885Sdim#define EPIC_LXT970_PHY 0x0003 66218885Sdim#define EPIC_SERIAL 0x0004 67218885Sdim 68218885Sdim/* Driver status structure */ 69218885Sdimtypedef struct { 70218885Sdim struct arpcom arpcom; 71218885Sdim struct resource *res; 72218885Sdim struct resource *irq; 73218885Sdim 74218885Sdim device_t miibus; 75218885Sdim device_t dev; 76218885Sdim struct callout_handle stat_ch; 77218885Sdim 78218885Sdim u_int32_t unit; 79218885Sdim void *sc_ih; 80218885Sdim bus_space_tag_t sc_st; 81218885Sdim bus_space_handle_t sc_sh; 82218885Sdim 83218885Sdim struct epic_rx_buffer rx_buffer[RX_RING_SIZE]; 84218885Sdim struct epic_tx_buffer tx_buffer[TX_RING_SIZE]; 85249423Sdim 86249423Sdim /* Each element of array MUST be aligned on dword */ 87249423Sdim /* and bounded on PAGE_SIZE */ 88218885Sdim struct epic_rx_desc *rx_desc; 89218885Sdim struct epic_tx_desc *tx_desc; 90218885Sdim struct epic_frag_list *tx_flist; 91218885Sdim u_int32_t flags; 92218885Sdim u_int32_t tx_threshold; 93218885Sdim u_int32_t txcon; 94218885Sdim u_int32_t miicfg; 95218885Sdim u_int32_t cur_tx; 96218885Sdim u_int32_t cur_rx; 97218885Sdim u_int32_t dirty_tx; 98218885Sdim u_int32_t pending_txs; 99218885Sdim u_int16_t cardvend; 100218885Sdim u_int16_t cardid; 101218885Sdim struct mii_softc *physc; 102218885Sdim u_int32_t phyid; 103218885Sdim int serinst; 104218885Sdim void *pool; 105218885Sdim} epic_softc_t; 106218885Sdim 107218885Sdimstruct epic_type { 108218885Sdim u_int16_t ven_id; 109218885Sdim u_int16_t dev_id; 110218885Sdim char *name; 111218885Sdim}; 112218885Sdim 113218885Sdim#define sc_if arpcom.ac_if 114218885Sdim#define sc_macaddr arpcom.ac_enaddr 115218885Sdim 116218885Sdim#define CSR_WRITE_4(sc, reg, val) \ 117218885Sdim bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 118218885Sdim#define CSR_WRITE_2(sc, reg, val) \ 119218885Sdim bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 120218885Sdim#define CSR_WRITE_1(sc, reg, val) \ 121218885Sdim bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 122218885Sdim#define CSR_READ_4(sc, reg) \ 123218885Sdim bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 124218885Sdim#define CSR_READ_2(sc, reg) \ 125218885Sdim bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 126218885Sdim#define CSR_READ_1(sc, reg) \ 127218885Sdim bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 128218885Sdim 129218885Sdim#define PHY_READ_2(sc, phy, reg) \ 130218885Sdim epic_read_phy_reg((sc), (phy), (reg)) 131218885Sdim#define PHY_WRITE_2(sc, phy, reg, val) \ 132218885Sdim epic_write_phy_reg((sc), (phy), (reg), (val)) 133218885Sdim 134218885Sdim/* Macro to get either mbuf cluster or nothing */ 135218885Sdim#define EPIC_MGETCLUSTER(m) \ 136218885Sdim { MGETHDR((m),M_DONTWAIT,MT_DATA); \ 137218885Sdim if (m) { \ 138218885Sdim MCLGET((m),M_DONTWAIT); \ 139218885Sdim if( 0 == ((m)->m_flags & M_EXT) ) { \ 140218885Sdim m_freem(m); \ 141218885Sdim (m) = NULL; \ 142218885Sdim } \ 143218885Sdim } \ 144218885Sdim } 145218885Sdim 146218885Sdim