if_txreg.h revision 95075
1/* $OpenBSD: if_txvar.h,v 1.7 1999/11/17 05:21:19 jason Exp $ */ 2/* $FreeBSD: head/sys/dev/tx/if_txreg.h 95075 2002-04-19 22:43:57Z semenu $ */ 3 4/*- 5 * Copyright (c) 1997 Semen Ustimenko 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#define EPIC_MAX_MTU 1600 /* This is experiment-derived value */ 31 32/* PCI aux configuration registers */ 33#if defined(__FreeBSD__) 34#define PCIR_BASEIO (PCIR_MAPS + 0x0) /* Base IO Address */ 35#define PCIR_BASEMEM (PCIR_MAPS + 0x4) /* Base Memory Address */ 36#else /* __OpenBSD__ */ 37#define PCI_BASEIO (PCI_MAPS + 0x0) /* Base IO Address */ 38#define PCI_BASEMEM (PCI_MAPS + 0x4) /* Base Memory Address */ 39#endif /* __FreeBSD__ */ 40 41/* PCI identification */ 42#define SMC_VENDORID 0x10B8 43#define SMC_DEVICEID_83C170 0x0005 44 45/* EPIC's registers */ 46#define COMMAND 0x0000 47#define INTSTAT 0x0004 /* Interrupt status. See below */ 48#define INTMASK 0x0008 /* Interrupt mask. See below */ 49#define GENCTL 0x000C 50#define NVCTL 0x0010 51#define EECTL 0x0014 /* EEPROM control **/ 52#define TEST1 0x001C /* XXXXX */ 53#define CRCCNT 0x0020 /* CRC error counter */ 54#define ALICNT 0x0024 /* FrameTooLang error counter */ 55#define MPCNT 0x0028 /* MissedFrames error counters */ 56#define MIICTL 0x0030 57#define MIIDATA 0x0034 58#define MIICFG 0x0038 59#define IPG 0x003C 60#define LAN0 0x0040 /* MAC address */ 61#define LAN1 0x0044 /* MAC address */ 62#define LAN2 0x0048 /* MAC address */ 63#define ID_CHK 0x004C 64#define MC0 0x0050 /* Multicast filter table */ 65#define MC1 0x0054 /* Multicast filter table */ 66#define MC2 0x0058 /* Multicast filter table */ 67#define MC3 0x005C /* Multicast filter table */ 68#define RXCON 0x0060 /* Rx control register */ 69#define TXCON 0x0070 /* Tx control register */ 70#define TXSTAT 0x0074 71#define PRCDAR 0x0084 /* RxRing bus address */ 72#define PRSTAT 0x00A4 73#define PRCPTHR 0x00B0 74#define PTCDAR 0x00C4 /* TxRing bus address */ 75#define ETXTHR 0x00DC 76 77#define COMMAND_STOP_RX 0x01 78#define COMMAND_START_RX 0x02 79#define COMMAND_TXQUEUED 0x04 80#define COMMAND_RXQUEUED 0x08 81#define COMMAND_NEXTFRAME 0x10 82#define COMMAND_STOP_TDMA 0x20 83#define COMMAND_STOP_RDMA 0x40 84#define COMMAND_TXUGO 0x80 85 86/* Interrupt register bits */ 87#define INTSTAT_RCC 0x00000001 88#define INTSTAT_HCC 0x00000002 89#define INTSTAT_RQE 0x00000004 90#define INTSTAT_OVW 0x00000008 91#define INTSTAT_RXE 0x00000010 92#define INTSTAT_TXC 0x00000020 93#define INTSTAT_TCC 0x00000040 94#define INTSTAT_TQE 0x00000080 95#define INTSTAT_TXU 0x00000100 96#define INTSTAT_CNT 0x00000200 97#define INTSTAT_PREI 0x00000400 98#define INTSTAT_RCT 0x00000800 99#define INTSTAT_FATAL 0x00001000 /* One of DPE,APE,PMA,PTA happend */ 100#define INTSTAT_UNUSED1 0x00002000 101#define INTSTAT_UNUSED2 0x00004000 102#define INTSTAT_GP2 0x00008000 /* PHY Event */ 103#define INTSTAT_INT_ACTV 0x00010000 104#define INTSTAT_RXIDLE 0x00020000 105#define INTSTAT_TXIDLE 0x00040000 106#define INTSTAT_RCIP 0x00080000 107#define INTSTAT_TCIP 0x00100000 108#define INTSTAT_RBE 0x00200000 109#define INTSTAT_RCTS 0x00400000 110#define INTSTAT_RSV 0x00800000 111#define INTSTAT_DPE 0x01000000 /* PCI Fatal error */ 112#define INTSTAT_APE 0x02000000 /* PCI Fatal error */ 113#define INTSTAT_PMA 0x04000000 /* PCI Fatal error */ 114#define INTSTAT_PTA 0x08000000 /* PCI Fatal error */ 115 116#define GENCTL_SOFT_RESET 0x00000001 117#define GENCTL_ENABLE_INTERRUPT 0x00000002 118#define GENCTL_SOFTWARE_INTERRUPT 0x00000004 119#define GENCTL_POWER_DOWN 0x00000008 120#define GENCTL_ONECOPY 0x00000010 121#define GENCTL_BIG_ENDIAN 0x00000020 122#define GENCTL_RECEIVE_DMA_PRIORITY 0x00000040 123#define GENCTL_TRANSMIT_DMA_PRIORITY 0x00000080 124#define GENCTL_RECEIVE_FIFO_THRESHOLD128 0x00000300 125#define GENCTL_RECEIVE_FIFO_THRESHOLD96 0x00000200 126#define GENCTL_RECEIVE_FIFO_THRESHOLD64 0x00000100 127#define GENCTL_RECEIVE_FIFO_THRESHOLD32 0x00000000 128#define GENCTL_MEMORY_READ_LINE 0x00000400 129#define GENCTL_MEMORY_READ_MULTIPLE 0x00000800 130#define GENCTL_SOFTWARE1 0x00001000 131#define GENCTL_SOFTWARE2 0x00002000 132#define GENCTL_RESET_PHY 0x00004000 133 134#define NVCTL_ENABLE_MEMORY_MAP 0x00000001 135#define NVCTL_CLOCK_RUN_SUPPORTED 0x00000002 136#define NVCTL_GP1_OUTPUT_ENABLE 0x00000004 137#define NVCTL_GP2_OUTPUT_ENABLE 0x00000008 138#define NVCTL_GP1 0x00000010 139#define NVCTL_GP2 0x00000020 140#define NVCTL_CARDBUS_MODE 0x00000040 141#define NVCTL_IPG_DELAY_MASK(x) ((x&0xF)<<7) 142 143#define RXCON_SAVE_ERRORED_PACKETS 0x00000001 144#define RXCON_RECEIVE_RUNT_FRAMES 0x00000002 145#define RXCON_RECEIVE_BROADCAST_FRAMES 0x00000004 146#define RXCON_RECEIVE_MULTICAST_FRAMES 0x00000008 147#define RXCON_RECEIVE_INVERSE_INDIVIDUAL_ADDRESS_FRAMES 0x00000010 148#define RXCON_PROMISCUOUS_MODE 0x00000020 149#define RXCON_MONITOR_MODE 0x00000040 150#define RXCON_EARLY_RECEIVE_ENABLE 0x00000080 151#define RXCON_EXTERNAL_BUFFER_DISABLE 0x00000000 152#define RXCON_EXTERNAL_BUFFER_16K 0x00000100 153#define RXCON_EXTERNAL_BUFFER_32K 0x00000200 154#define RXCON_EXTERNAL_BUFFER_128K 0x00000300 155 156#define TXCON_EARLY_TRANSMIT_ENABLE 0x00000001 157#define TXCON_LOOPBACK_DISABLE 0x00000000 158#define TXCON_LOOPBACK_MODE_INT 0x00000002 159#define TXCON_LOOPBACK_MODE_PHY 0x00000004 160#define TXCON_LOOPBACK_MODE 0x00000006 161#define TXCON_FULL_DUPLEX 0x00000006 162#define TXCON_SLOT_TIME 0x00000078 163 164#define MIICFG_SERIAL_ENABLE 0x00000001 165#define MIICFG_694_ENABLE 0x00000002 166#define MIICFG_694_STATUS 0x00000004 167#define MIICFG_PHY_PRESENT 0x00000008 168#define MIICFG_SMI_ENABLE 0x00000010 169 170#define TEST1_CLOCK_TEST 0x00000008 171 172/* 173 * Some default values 174 */ 175#define TXCON_DEFAULT (TXCON_SLOT_TIME | TXCON_EARLY_TRANSMIT_ENABLE) 176#define TRANSMIT_THRESHOLD 0x300 177 178#define RXCON_DEFAULT (RXCON_RECEIVE_MULTICAST_FRAMES | \ 179 RXCON_RECEIVE_BROADCAST_FRAMES) 180 181#define RXCON_EARLY_RX (RXCON_EARLY_RECEIVE_ENABLE | \ 182 RXCON_SAVE_ERRORED_PACKETS) 183/* 184 * EEPROM structure 185 * SMC9432* eeprom is organized by words and only first 8 words 186 * have distinctive meaning (according to datasheet) 187 */ 188#define EEPROM_MAC0 0x0000 /* Byte 0 / Byte 1 */ 189#define EEPROM_MAC1 0x0001 /* Byte 2 / Byte 3 */ 190#define EEPROM_MAC2 0x0002 /* Byte 4 / Byte 5 */ 191#define EEPROM_BID_CSUM 0x0003 /* Board Id / Check Sum */ 192#define EEPROM_NVCTL 0x0004 /* NVCTL (bits 0-5) / nothing */ 193#define EEPROM_PCI_MGD_MLD 0x0005 /* PCI MinGrant / MaxLatency. Desired */ 194#define EEPROM_SSVENDID 0x0006 /* Subsystem Vendor Id */ 195#define EEPROM_SSID 0x0006 /* Subsystem Id */ 196 197/* 198 * Hardware structures 199 */ 200 201/* EPIC's hardware descriptors, must be aligned on dword in memory */ 202/* NB: to make driver happy, this two structures MUST have thier sizes */ 203/* be divisor of PAGE_SIZE */ 204struct epic_tx_desc { 205 volatile u_int16_t status; 206 volatile u_int16_t txlength; 207 volatile u_int32_t bufaddr; 208 volatile u_int16_t buflength; 209 volatile u_int16_t control; 210 volatile u_int32_t next; 211}; 212struct epic_rx_desc { 213 volatile u_int16_t status; 214 volatile u_int16_t rxlength; 215 volatile u_int32_t bufaddr; 216 volatile u_int32_t buflength; 217 volatile u_int32_t next; 218}; 219 220/* This structure defines EPIC's fragment list, maximum number of frags */ 221/* is 63. Let use maximum, becouse size of struct MUST be divisor of */ 222/* PAGE_SIZE, and sometimes come mbufs with more then 30 frags */ 223#define EPIC_MAX_FRAGS 63 224struct epic_frag_list { 225 volatile u_int32_t numfrags; 226 struct { 227 volatile u_int32_t fragaddr; 228 volatile u_int32_t fraglen; 229 } frag[EPIC_MAX_FRAGS]; 230 volatile u_int32_t pad; /* align on 256 bytes */ 231}; 232 233/* 234 * NB: ALIGN OF ABOVE STRUCTURES 235 * epic_rx_desc, epic_tx_desc, epic_frag_list - must be aligned on dword 236 */ 237 238#define SMC9432DMT 0xA010 239#define SMC9432TX 0xA011 240#define SMC9032TXM 0xA012 241#define SMC9032TX 0xA013 242#define SMC9432TXPWR 0xA014 243#define SMC9432BTX 0xA015 244#define SMC9432FTX 0xA016 245#define SMC9432FTX_SC 0xA017 246#define SMC9432TX_XG_ADHOC 0xA020 247#define SMC9434TX_XG_ADHOC 0xA021 248#define SMC9432FTX_ADHOC 0xA022 249#define SMC9432BTX1 0xA024 250 251