if_txreg.h revision 61906
1/* $OpenBSD: if_txvar.h,v 1.7 1999/11/17 05:21:19 jason Exp $ */ 2/* $FreeBSD: head/sys/dev/tx/if_txreg.h 61906 2000-06-21 19:19:49Z semenu $ */ 3 4/*- 5 * Copyright (c) 1997 Semen Ustimenko 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/* 31 * Configuration 32 */ 33/*#define EPIC_DEBUG 1*/ 34/*#define EPIC_USEIOSPACE 1*/ 35#define EARLY_RX 1 36 37#ifndef ETHER_MAX_LEN 38#define ETHER_MAX_LEN 1518 39#endif 40#ifndef ETHER_MIN_LEN 41#define ETHER_MIN_LEN 64 42#endif 43#ifndef ETHER_CRC_LEN 44#define ETHER_CRC_LEN 4 45#endif 46#define TX_RING_SIZE 16 /* Leave this a power of 2 */ 47#define RX_RING_SIZE 16 /* And this too, to do not */ 48 /* confuse RX(TX)_RING_MASK */ 49#define TX_RING_MASK (TX_RING_SIZE - 1) 50#define RX_RING_MASK (RX_RING_SIZE - 1) 51#define ETHER_MAX_FRAME_LEN (ETHER_MAX_LEN + ETHER_CRC_LEN) 52 53/* PCI aux configuration registers */ 54#if defined(__FreeBSD__) 55#define PCIR_BASEIO (PCIR_MAPS + 0x0) /* Base IO Address */ 56#define PCIR_BASEMEM (PCIR_MAPS + 0x4) /* Base Memory Address */ 57#else /* __OpenBSD__ */ 58#define PCI_BASEIO (PCI_MAPS + 0x0) /* Base IO Address */ 59#define PCI_BASEMEM (PCI_MAPS + 0x4) /* Base Memory Address */ 60#endif /* __FreeBSD__ */ 61 62/* PCI identification */ 63#define SMC_VENDORID 0x10B8 64#define SMC_DEVICEID_83C170 0x0005 65 66/* EPIC's registers */ 67#define COMMAND 0x0000 68#define INTSTAT 0x0004 /* Interrupt status. See below */ 69#define INTMASK 0x0008 /* Interrupt mask. See below */ 70#define GENCTL 0x000C 71#define NVCTL 0x0010 72#define EECTL 0x0014 /* EEPROM control **/ 73#define TEST1 0x001C /* XXXXX */ 74#define CRCCNT 0x0020 /* CRC error counter */ 75#define ALICNT 0x0024 /* FrameTooLang error counter */ 76#define MPCNT 0x0028 /* MissedFrames error counters */ 77#define MIICTL 0x0030 78#define MIIDATA 0x0034 79#define MIICFG 0x0038 80#define IPG 0x003C 81#define LAN0 0x0040 /* MAC address */ 82#define LAN1 0x0044 /* MAC address */ 83#define LAN2 0x0048 /* MAC address */ 84#define ID_CHK 0x004C 85#define MC0 0x0050 /* Multicast filter table */ 86#define MC1 0x0054 /* Multicast filter table */ 87#define MC2 0x0058 /* Multicast filter table */ 88#define MC3 0x005C /* Multicast filter table */ 89#define RXCON 0x0060 /* Rx control register */ 90#define TXCON 0x0070 /* Tx control register */ 91#define TXSTAT 0x0074 92#define PRCDAR 0x0084 /* RxRing bus address */ 93#define PRSTAT 0x00A4 94#define PRCPTHR 0x00B0 95#define PTCDAR 0x00C4 /* TxRing bus address */ 96#define ETXTHR 0x00DC 97 98#define COMMAND_STOP_RX 0x01 99#define COMMAND_START_RX 0x02 100#define COMMAND_TXQUEUED 0x04 101#define COMMAND_RXQUEUED 0x08 102#define COMMAND_NEXTFRAME 0x10 103#define COMMAND_STOP_TDMA 0x20 104#define COMMAND_STOP_RDMA 0x40 105#define COMMAND_TXUGO 0x80 106 107/* Interrupt register bits */ 108#define INTSTAT_RCC 0x00000001 109#define INTSTAT_HCC 0x00000002 110#define INTSTAT_RQE 0x00000004 111#define INTSTAT_OVW 0x00000008 112#define INTSTAT_RXE 0x00000010 113#define INTSTAT_TXC 0x00000020 114#define INTSTAT_TCC 0x00000040 115#define INTSTAT_TQE 0x00000080 116#define INTSTAT_TXU 0x00000100 117#define INTSTAT_CNT 0x00000200 118#define INTSTAT_PREI 0x00000400 119#define INTSTAT_RCT 0x00000800 120#define INTSTAT_FATAL 0x00001000 /* One of DPE,APE,PMA,PTA happend */ 121#define INTSTAT_UNUSED1 0x00002000 122#define INTSTAT_UNUSED2 0x00004000 123#define INTSTAT_GP2 0x00008000 /* PHY Event */ 124#define INTSTAT_INT_ACTV 0x00010000 125#define INTSTAT_RXIDLE 0x00020000 126#define INTSTAT_TXIDLE 0x00040000 127#define INTSTAT_RCIP 0x00080000 128#define INTSTAT_TCIP 0x00100000 129#define INTSTAT_RBE 0x00200000 130#define INTSTAT_RCTS 0x00400000 131#define INTSTAT_RSV 0x00800000 132#define INTSTAT_DPE 0x01000000 /* PCI Fatal error */ 133#define INTSTAT_APE 0x02000000 /* PCI Fatal error */ 134#define INTSTAT_PMA 0x04000000 /* PCI Fatal error */ 135#define INTSTAT_PTA 0x08000000 /* PCI Fatal error */ 136 137#define GENCTL_SOFT_RESET 0x00000001 138#define GENCTL_ENABLE_INTERRUPT 0x00000002 139#define GENCTL_SOFTWARE_INTERRUPT 0x00000004 140#define GENCTL_POWER_DOWN 0x00000008 141#define GENCTL_ONECOPY 0x00000010 142#define GENCTL_BIG_ENDIAN 0x00000020 143#define GENCTL_RECEIVE_DMA_PRIORITY 0x00000040 144#define GENCTL_TRANSMIT_DMA_PRIORITY 0x00000080 145#define GENCTL_RECEIVE_FIFO_THRESHOLD128 0x00000300 146#define GENCTL_RECEIVE_FIFO_THRESHOLD96 0x00000200 147#define GENCTL_RECEIVE_FIFO_THRESHOLD64 0x00000100 148#define GENCTL_RECEIVE_FIFO_THRESHOLD32 0x00000000 149#define GENCTL_MEMORY_READ_LINE 0x00000400 150#define GENCTL_MEMORY_READ_MULTIPLE 0x00000800 151#define GENCTL_SOFTWARE1 0x00001000 152#define GENCTL_SOFTWARE2 0x00002000 153#define GENCTL_RESET_PHY 0x00004000 154 155#define NVCTL_ENABLE_MEMORY_MAP 0x00000001 156#define NVCTL_CLOCK_RUN_SUPPORTED 0x00000002 157#define NVCTL_GP1_OUTPUT_ENABLE 0x00000004 158#define NVCTL_GP2_OUTPUT_ENABLE 0x00000008 159#define NVCTL_GP1 0x00000010 160#define NVCTL_GP2 0x00000020 161#define NVCTL_CARDBUS_MODE 0x00000040 162#define NVCTL_IPG_DELAY_MASK(x) ((x&0xF)<<7) 163 164#define RXCON_SAVE_ERRORED_PACKETS 0x00000001 165#define RXCON_RECEIVE_RUNT_FRAMES 0x00000002 166#define RXCON_RECEIVE_BROADCAST_FRAMES 0x00000004 167#define RXCON_RECEIVE_MULTICAST_FRAMES 0x00000008 168#define RXCON_RECEIVE_INVERSE_INDIVIDUAL_ADDRESS_FRAMES 0x00000010 169#define RXCON_PROMISCUOUS_MODE 0x00000020 170#define RXCON_MONITOR_MODE 0x00000040 171#define RXCON_EARLY_RECEIVE_ENABLE 0x00000080 172#define RXCON_EXTERNAL_BUFFER_DISABLE 0x00000000 173#define RXCON_EXTERNAL_BUFFER_16K 0x00000100 174#define RXCON_EXTERNAL_BUFFER_32K 0x00000200 175#define RXCON_EXTERNAL_BUFFER_128K 0x00000300 176 177#define TXCON_EARLY_TRANSMIT_ENABLE 0x00000001 178#define TXCON_LOOPBACK_DISABLE 0x00000000 179#define TXCON_LOOPBACK_MODE_INT 0x00000002 180#define TXCON_LOOPBACK_MODE_PHY 0x00000004 181#define TXCON_LOOPBACK_MODE 0x00000006 182#define TXCON_FULL_DUPLEX 0x00000006 183#define TXCON_SLOT_TIME 0x00000078 184 185#define MIICFG_SERIAL_ENABLE 0x00000001 186#define MIICFG_694_ENABLE 0x00000002 187#define MIICFG_694_STATUS 0x00000004 188#define MIICFG_PHY_PRESENT 0x00000008 189#define MIICFG_SMI_ENABLE 0x00000010 190 191#define TEST1_CLOCK_TEST 0x00000008 192 193/* 194 * Some default values 195 */ 196#define TXCON_DEFAULT (TXCON_SLOT_TIME | TXCON_EARLY_TRANSMIT_ENABLE) 197#define TRANSMIT_THRESHOLD 0x300 198 199#if defined(EARLY_RX) 200#define RXCON_EARLY (RXCON_EARLY_RECEIVE_ENABLE | \ 201 RXCON_SAVE_ERRORED_PACKETS) 202#else 203#define RXCON_EARLY (0) 204#endif 205 206#define RXCON_DEFAULT (RXCON_EARLY | \ 207 RXCON_RECEIVE_MULTICAST_FRAMES | \ 208 RXCON_RECEIVE_BROADCAST_FRAMES) 209 210/* 211 * Structures definition and Functions prototypes 212 */ 213 214/* EPIC's hardware descriptors, must be aligned on dword in memory */ 215/* NB: to make driver happy, this two structures MUST have thier sizes */ 216/* be divisor of PAGE_SIZE */ 217struct epic_tx_desc { 218 volatile u_int16_t status; 219 volatile u_int16_t txlength; 220 volatile u_int32_t bufaddr; 221 volatile u_int16_t buflength; 222 volatile u_int16_t control; 223 volatile u_int32_t next; 224}; 225struct epic_rx_desc { 226 volatile u_int16_t status; 227 volatile u_int16_t rxlength; 228 volatile u_int32_t bufaddr; 229 volatile u_int32_t buflength; 230 volatile u_int32_t next; 231}; 232 233/* This structure defines EPIC's fragment list, maximum number of frags */ 234/* is 63. Let use maximum, becouse size of struct MUST be divisor of */ 235/* PAGE_SIZE, and sometimes come mbufs with more then 30 frags */ 236#define EPIC_MAX_FRAGS 63 237struct epic_frag_list { 238 volatile u_int32_t numfrags; 239 struct { 240 volatile u_int32_t fragaddr; 241 volatile u_int32_t fraglen; 242 } frag[EPIC_MAX_FRAGS]; 243 volatile u_int32_t pad; /* align on 256 bytes */ 244}; 245 246/* This is driver's structure to define EPIC descriptors */ 247struct epic_rx_buffer { 248 struct mbuf * mbuf; /* mbuf receiving packet */ 249}; 250 251struct epic_tx_buffer { 252 struct mbuf * mbuf; /* mbuf contained packet */ 253}; 254 255/* 256 * NB: ALIGN OF ABOVE STRUCTURES 257 * epic_rx_desc, epic_tx_desc, epic_frag_list - must be aligned on dword 258 */ 259 260/* Driver status structure */ 261typedef struct { 262 struct arpcom arpcom; 263#if defined(__OpenBSD__) 264 mii_data_t sc_mii; 265 struct device dev; 266#else /* __FreeBSD__ */ 267 struct resource *res; 268 struct resource *irq; 269 270 device_t miibus; 271 device_t dev; 272 struct callout_handle stat_ch; 273 274 u_int32_t unit; 275#endif 276 void *sc_ih; 277 bus_space_tag_t sc_st; 278 bus_space_handle_t sc_sh; 279 280 struct epic_rx_buffer rx_buffer[RX_RING_SIZE]; 281 struct epic_tx_buffer tx_buffer[TX_RING_SIZE]; 282 283 /* Each element of array MUST be aligned on dword */ 284 /* and bounded on PAGE_SIZE */ 285 struct epic_rx_desc *rx_desc; 286 struct epic_tx_desc *tx_desc; 287 struct epic_frag_list *tx_flist; 288 u_int32_t flags; 289 u_int32_t tx_threshold; 290 u_int32_t txcon; 291 u_int32_t phyid; 292 u_int32_t cur_tx; 293 u_int32_t cur_rx; 294 u_int32_t dirty_tx; 295 u_int32_t pending_txs; 296 void *pool; 297} epic_softc_t; 298 299struct epic_type { 300 u_int16_t ven_id; 301 u_int16_t dev_id; 302 char *name; 303}; 304 305#if defined(EPIC_DEBUG) 306#define dprintf(a) printf a 307#else 308#define dprintf(a) 309#endif 310 311#if defined(__FreeBSD__) 312#define EPIC_FORMAT "tx%d" 313#define EPIC_ARGS(sc) (sc->unit) 314#define EPIC_BPFTAP_ARG(ifp) ifp 315#else /* __OpenBSD__ */ 316#define EPIC_FORMAT "%s" 317#define EPIC_ARGS(sc) (sc->sc_dev.dv_xname) 318#define EPIC_BPFTAP_ARG(ifp) (ifp)->if_bpf 319#endif 320 321#define sc_if arpcom.ac_if 322#define sc_macaddr arpcom.ac_enaddr 323 324#define CSR_WRITE_4(sc,reg,val) \ 325 bus_space_write_4( (sc)->sc_st, (sc)->sc_sh, (reg), (val) ) 326#define CSR_WRITE_2(sc,reg,val) \ 327 bus_space_write_2( (sc)->sc_st, (sc)->sc_sh, (reg), (val) ) 328#define CSR_WRITE_1(sc,reg,val) \ 329 bus_space_write_1( (sc)->sc_st, (sc)->sc_sh, (reg), (val) ) 330#define CSR_READ_4(sc,reg) \ 331 bus_space_read_4( (sc)->sc_st, (sc)->sc_sh, (reg) ) 332#define CSR_READ_2(sc,reg) \ 333 bus_space_read_2( (sc)->sc_st, (sc)->sc_sh, (reg) ) 334#define CSR_READ_1(sc,reg) \ 335 bus_space_read_1( (sc)->sc_st, (sc)->sc_sh, (reg) ) 336 337#define PHY_READ_2(sc,phy,reg) \ 338 epic_read_phy_reg((sc),(phy),(reg)) 339#define PHY_WRITE_2(sc,phy,reg,val) \ 340 epic_write_phy_reg((sc),(phy),(reg),(val)) 341 342/* Macro to get either mbuf cluster or nothing */ 343#define EPIC_MGETCLUSTER(m) \ 344 { MGETHDR((m),M_DONTWAIT,MT_DATA); \ 345 if (m) { \ 346 MCLGET((m),M_DONTWAIT); \ 347 if( 0 == ((m)->m_flags & M_EXT) ) { \ 348 m_freem(m); \ 349 (m) = NULL; \ 350 } \ 351 } \ 352 } 353 354