twereg.h revision 76340
1/*-
2 * Copyright (c) 2000 Michael Smith
3 * Copyright (c) 2000 BSDi
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *      $FreeBSD: head/sys/dev/twe/twereg.h 76340 2001-05-07 21:46:44Z msmith $
28 */
29
30/*
31 * Register names, bit definitions, structure names and members are
32 * identical with those in the Linux driver where possible and sane
33 * for simplicity's sake.  (The TW_ prefix has become TWE_)
34 * Some defines that are clearly irrelevant to FreeBSD have been
35 * removed.
36 */
37
38/* control register bit definitions */
39#define TWE_CONTROL_CLEAR_HOST_INTERRUPT	0x00080000
40#define TWE_CONTROL_CLEAR_ATTENTION_INTERRUPT	0x00040000
41#define TWE_CONTROL_MASK_COMMAND_INTERRUPT	0x00020000
42#define TWE_CONTROL_MASK_RESPONSE_INTERRUPT	0x00010000
43#define TWE_CONTROL_UNMASK_COMMAND_INTERRUPT	0x00008000
44#define TWE_CONTROL_UNMASK_RESPONSE_INTERRUPT	0x00004000
45#define TWE_CONTROL_CLEAR_ERROR_STATUS		0x00000200
46#define TWE_CONTROL_ISSUE_SOFT_RESET		0x00000100
47#define TWE_CONTROL_ENABLE_INTERRUPTS		0x00000080
48#define TWE_CONTROL_DISABLE_INTERRUPTS		0x00000040
49#define TWE_CONTROL_ISSUE_HOST_INTERRUPT	0x00000020
50
51#define TWE_SOFT_RESET(sc)	TWE_CONTROL(sc, TWE_CONTROL_ISSUE_SOFT_RESET |		\
52					   TWE_CONTROL_CLEAR_HOST_INTERRUPT |		\
53					   TWE_CONTROL_CLEAR_ATTENTION_INTERRUPT |	\
54					   TWE_CONTROL_MASK_COMMAND_INTERRUPT |		\
55					   TWE_CONTROL_MASK_RESPONSE_INTERRUPT |	\
56					   TWE_CONTROL_CLEAR_ERROR_STATUS |		\
57					   TWE_CONTROL_DISABLE_INTERRUPTS)
58
59/* status register bit definitions */
60#define TWE_STATUS_MAJOR_VERSION_MASK		0xF0000000
61#define TWE_STATUS_MINOR_VERSION_MASK		0x0F000000
62#define TWE_STATUS_PCI_PARITY_ERROR		0x00800000
63#define TWE_STATUS_QUEUE_ERROR			0x00400000
64#define TWE_STATUS_MICROCONTROLLER_ERROR	0x00200000
65#define TWE_STATUS_PCI_ABORT			0x00100000
66#define TWE_STATUS_HOST_INTERRUPT		0x00080000
67#define TWE_STATUS_ATTENTION_INTERRUPT		0x00040000
68#define TWE_STATUS_COMMAND_INTERRUPT		0x00020000
69#define TWE_STATUS_RESPONSE_INTERRUPT		0x00010000
70#define TWE_STATUS_COMMAND_QUEUE_FULL		0x00008000
71#define TWE_STATUS_RESPONSE_QUEUE_EMPTY		0x00004000
72#define TWE_STATUS_MICROCONTROLLER_READY	0x00002000
73#define TWE_STATUS_COMMAND_QUEUE_EMPTY		0x00001000
74#define TWE_STATUS_ALL_INTERRUPTS		0x000F0000
75#define TWE_STATUS_CLEARABLE_BITS		0x00D00000
76#define TWE_STATUS_EXPECTED_BITS		0x00002000
77#define TWE_STATUS_UNEXPECTED_BITS		0x00F80000
78
79/* XXX this is a little harsh, but necessary to chase down firmware problems */
80#define TWE_STATUS_PANIC_BITS			(TWE_STATUS_MICROCONTROLLER_ERROR)
81
82/* for use with the %b printf format */
83#define TWE_STATUS_BITS_DESCRIPTION \
84	"\20\15CQEMPTY\16UCREADY\17RQEMPTY\20CQFULL\21RINTR\22CINTR\23AINTR\24HINTR\25PCIABRT\26MCERR\27QERR\30PCIPERR\n"
85
86/* detect inconsistencies in the status register */
87#define TWE_STATUS_ERRORS(x)				\
88	(((x & TWE_STATUS_PCI_ABORT) 		||	\
89	  (x & TWE_STATUS_PCI_PARITY_ERROR) 	||	\
90	  (x & TWE_STATUS_QUEUE_ERROR)		||	\
91	  (x & TWE_STATUS_MICROCONTROLLER_ERROR)) &&	\
92	 (x & TWE_STATUS_MICROCONTROLLER_READY))
93
94/* Response queue bit definitions */
95#define TWE_RESPONSE_ID_MASK		0x00000FF0
96
97/* PCI related defines */
98#define TWE_IO_CONFIG_REG		0x10
99#define TWE_DEVICE_NAME			"3ware Storage Controller"
100#define TWE_VENDOR_ID			0x13C1
101#define TWE_DEVICE_ID			0x1000
102#define TWE_DEVICE_ID_ASIC		0x1001
103
104/* command packet opcodes */
105#define TWE_OP_NOP			0x00
106#define TWE_OP_INIT_CONNECTION		0x01
107#define TWE_OP_READ			0x02
108#define TWE_OP_WRITE			0x03
109#define TWE_OP_READVERIFY		0x04
110#define TWE_OP_VERIFY			0x05
111#define TWE_OP_ZEROUNIT			0x08
112#define TWE_OP_REPLACEUNIT		0x09
113#define TWE_OP_HOTSWAP			0x0a
114#define TWE_OP_SETATAFEATURE		0x0c
115#define TWE_OP_FLUSH			0x0e
116#define TWE_OP_ABORT			0x0f
117#define TWE_OP_CHECKSTATUS		0x10
118#define TWE_OP_GET_PARAM		0x12
119#define TWE_OP_SET_PARAM		0x13
120#define TWE_OP_CREATEUNIT		0x14
121#define TWE_OP_DELETEUNIT		0x15
122#define TWE_OP_REBUILDUNIT		0x17
123#define TWE_OP_SECTOR_INFO		0x1a
124#define TWE_OP_AEN_LISTEN		0x1c
125#define TWE_OP_CMD_PACKET		0x1d
126
127/* command status values */
128#define TWE_STATUS_RESET		0xff	/* controller requests reset */
129#define TWE_STATUS_FATAL		0xc0	/* fatal errors not requiring reset */
130#define TWE_STATUS_WARNING		0x80	/* warnings */
131#define TWE_STAUS_INFO			0x40	/* informative status */
132
133/* misc defines */
134#define TWE_ALIGNMENT			0x200
135#define TWE_MAX_UNITS			16
136#define TWE_COMMAND_ALIGNMENT_MASK	0x1ff
137#define TWE_INIT_MESSAGE_CREDITS	0xff	/* older firmware has issues with 256 commands */
138#define TWE_SHUTDOWN_MESSAGE_CREDITS	0x001
139#define TWE_INIT_COMMAND_PACKET_SIZE	0x3
140#define TWE_MAX_SGL_LENGTH		62
141#define TWE_Q_LENGTH			TWE_INIT_MESSAGE_CREDITS
142#define TWE_Q_START			0
143#define TWE_MAX_RESET_TRIES		3
144#define TWE_BLOCK_SIZE			0x200	/* 512-byte blocks */
145#define TWE_SECTOR_SIZE			0x200	/* generic I/O bufffer */
146#define TWE_IOCTL			0x80
147#define TWE_MAX_AEN_TRIES		100
148#define TWE_UNIT_ONLINE			1
149
150/* scatter/gather list entry */
151typedef struct
152{
153    u_int32_t	address;
154    u_int32_t	length;
155} TWE_SG_Entry __attribute__ ((packed));
156
157typedef struct {
158    u_int8_t	opcode:5;		/* TWE_OP_INITCONNECTION */
159    u_int8_t	res1:3;
160    u_int8_t	size;
161    u_int8_t	request_id;
162    u_int8_t	res2:4;
163    u_int8_t	host_id:4;
164    u_int8_t	status;
165    u_int8_t	flags;
166    u_int16_t	message_credits;
167    u_int32_t	response_queue_pointer;
168} TWE_Command_INITCONNECTION __attribute__ ((packed));
169
170typedef struct
171{
172    u_int8_t	opcode:5;		/* TWE_OP_READ/TWE_OP_WRITE */
173    u_int8_t	res1:3;
174    u_int8_t	size;
175    u_int8_t	request_id;
176    u_int8_t	unit:4;
177    u_int8_t	host_id:4;
178    u_int8_t	status;
179    u_int8_t	flags;
180    u_int16_t	block_count;
181    u_int32_t	lba;
182    TWE_SG_Entry sgl[TWE_MAX_SGL_LENGTH];
183} TWE_Command_IO __attribute__ ((packed));
184
185typedef struct
186{
187    u_int8_t	opcode:5;		/* TWE_OP_HOTSWAP */
188    u_int8_t	res1:3;
189    u_int8_t	size;
190    u_int8_t	request_id;
191    u_int8_t	unit:4;
192    u_int8_t	host_id:4;
193    u_int8_t	status;
194    u_int8_t	flags;
195    u_int8_t	action;
196#define TWE_OP_HOTSWAP_REMOVE		0x00	/* remove assumed-degraded unit */
197#define TWE_OP_HOTSWAP_ADD_CBOD		0x01	/* add CBOD to empty port */
198#define TWE_OP_HOTSWAP_ADD_SPARE	0x02	/* add spare to empty port */
199    u_int8_t	aport;
200} TWE_Command_HOTSWAP __attribute__ ((packed));
201
202typedef struct
203{
204    u_int8_t	opcode:5;		/* TWE_OP_SETATAFEATURE */
205    u_int8_t	res1:3;
206    u_int8_t	size;
207    u_int8_t	request_id;
208    u_int8_t	unit:4;
209    u_int8_t	host_id:4;
210    u_int8_t	status;
211    u_int8_t	flags;
212    u_int8_t	feature;
213#define TWE_OP_SETATAFEATURE_WCE	0x02
214#define TWE_OP_SETATAFEATURE_DIS_WCE	0x82
215    u_int8_t	feature_mode;
216    u_int16_t	all_units;
217    u_int16_t	persistence;
218} TWE_Command_SETATAFEATURE __attribute__ ((packed));
219
220typedef struct
221{
222    u_int8_t	opcode:5;		/* TWE_OP_CHECKSTATUS */
223    u_int8_t	res1:3;
224    u_int8_t	size;
225    u_int8_t	request_id;
226    u_int8_t	unit:4;
227    u_int8_t	res2:4;
228    u_int8_t	status;
229    u_int8_t	flags;
230    u_int16_t	target_status;		/* set low byte to target request's ID */
231} TWE_Command_CHECKSTATUS __attribute__ ((packed));
232
233typedef struct
234{
235    u_int8_t	opcode:5;		/* TWE_OP_GETPARAM, TWE_OP_SETPARAM */
236    u_int8_t	res1:3;
237    u_int8_t	size;
238    u_int8_t	request_id;
239    u_int8_t	unit:4;
240    u_int8_t	host_id:4;
241    u_int8_t	status;
242    u_int8_t	flags;
243    u_int16_t	param_count;
244    TWE_SG_Entry sgl[TWE_MAX_SGL_LENGTH];
245} TWE_Command_PARAM __attribute__ ((packed));
246
247typedef struct
248{
249    u_int8_t	opcode:5;		/* TWE_OP_REBUILDUNIT */
250    u_int8_t	res1:3;
251    u_int8_t	size;
252    u_int8_t	request_id;
253    u_int8_t	src_unit:4;
254    u_int8_t	host_id:4;
255    u_int8_t	status;
256    u_int8_t	flags;
257    u_int8_t	action:7;
258#define TWE_OP_REBUILDUNIT_NOP		0
259#define TWE_OP_REBUILDUNIT_STOP		2	/* stop all rebuilds */
260#define TWE_OP_REBUILDUNIT_START	4	/* start rebuild with lowest unit */
261#define TWE_OP_REBUILDUNIT_STARTUNIT	5	/* rebuild src_unit (not supported) */
262    u_int8_t	cs:1;				/* request state change on src_unit */
263    u_int8_t	logical_subunit;		/* for RAID10 rebuild of logical subunit */
264} TWE_Command_REBUILDUNIT __attribute__ ((packed));
265
266typedef struct
267{
268    u_int8_t	opcode:5;
269    u_int8_t	sgl_offset:3;
270    u_int8_t	size;
271    u_int8_t	request_id;
272    u_int8_t	unit:4;
273    u_int8_t	host_id:4;
274    u_int8_t	status;
275    u_int8_t	flags;
276#define TWE_FLAGS_SUCCESS	0x00
277#define TWE_FLAGS_INFORMATIONAL	0x01
278#define TWE_FLAGS_WARNING	0x02
279#define TWE_FLAGS_FATAL		0x03
280#define TWE_FLAGS_PERCENTAGE	(1<<8)	/* bits 0-6 indicate completion percentage */
281    u_int16_t	count;			/* block count, parameter count, message credits */
282} TWE_Command_Generic __attribute__ ((packed));
283
284/* command packet - must be TWE_ALIGNMENT aligned */
285typedef union
286{
287    TWE_Command_INITCONNECTION	initconnection;
288    TWE_Command_IO		io;
289    TWE_Command_PARAM		param;
290    TWE_Command_CHECKSTATUS	checkstatus;
291    TWE_Command_REBUILDUNIT	rebuildunit;
292    TWE_Command_SETATAFEATURE	setatafeature;
293    TWE_Command_Generic		generic;
294    u_int8_t			pad[512];
295} TWE_Command;
296
297/* response queue entry */
298typedef union
299{
300    struct
301    {
302	u_int32_t	undefined_1:4;
303	u_int32_t	response_id:8;
304	u_int32_t	undefined_2:20;
305    } u;
306    u_int32_t	value;
307} TWE_Response_Queue;
308
309/*
310 * From 3ware's documentation:
311 *   All parameters maintained by the controller are grouped into related tables.
312 *   Tables are are accessed indirectly via get and set parameter commands.
313 *   To access a specific parameter in a table, the table ID and parameter index
314 *   are used to uniquely identify a parameter.  Table 0xffff is the directory
315 *   table and provides a list of the table IDs and sizes of all other tables.
316 *   Index zero in each table specifies the entire table, and index one specifies
317 *   the size of the table.  An entire table can be read or set by using index zero.
318 */
319
320#define TWE_PARAM_PARAM_ALL	0
321#define TWE_PARAM_PARAM_SIZE	1
322
323#define TWE_PARAM_DIRECTORY	0xffff			/* size is 4 * number of tables */
324#define TWE_PARAM_DIRECTORY_TABLES		2	/* 16 bits * number of tables */
325#define TWE_PARAM_DIRECTORY_SIZES		3	/* 16 bits * number of tables */
326
327#define TWE_PARAM_DRIVESUMMARY	0x0002
328#define TWE_PARAM_DRIVESUMMARY_Num		2	/* number of physical drives [2] */
329#define TWE_PARAM_DRIVESUMMARY_Status		3	/* array giving drive status per aport */
330#define TWE_PARAM_DRIVESTATUS_Missing	0x00
331#define TWE_PARAM_DRIVESTATUS_NotSupp	0xfe
332#define TWE_PARAM_DRIVESTATUS_Present	0xff
333
334#define TWE_PARAM_UNITSUMMARY	0x0003
335#define TWE_PARAM_UNITSUMMARY_Num		2	/* number of logical units [2] */
336#define TWE_PARAM_UNITSUMMARY_Status		3	/* array giving unit status [16] */
337#define TWE_PARAM_UNITSTATUS_Online		(1<<0)
338#define TWE_PARAM_UNITSTATUS_Complete		(1<<1)
339#define TWE_PARAM_UNITSTATUS_MASK		0xfc
340#define TWE_PARAM_UNITSTATUS_Normal		0xfc
341#define TWE_PARAM_UNITSTATUS_Initialising	0xf4	/* cannot be incomplete */
342#define TWE_PARAM_UNITSTATUS_Degraded		0xec
343#define TWE_PARAM_UNITSTATUS_Rebuilding		0xdc	/* cannot be incomplete */
344#define TWE_PARAM_UNITSTATUS_Verifying		0xcc	/* cannot be incomplete */
345#define TWE_PARAM_UNITSTATUS_Corrupt		0xbc	/* cannot be complete */
346#define TWE_PARAM_UNITSTATUS_Missing		0x00	/* cannot be complete or online */
347
348#define TWE_PARAM_DRIVEINFO	0x0200			/* add drive number 0x00-0x0f XXX docco confused 0x0100 vs 0x0200 */
349#define TWE_PARAM_DRIVEINFO_Size		2	/* size in blocks [4] */
350#define TWE_PARAM_DRIVEINFO_Model		3	/* drive model string [40] */
351#define TWE_PARAM_DRIVEINFO_Serial		4	/* drive serial number [20] */
352#define TWE_PARAM_DRIVEINFO_PhysCylNum		5	/* physical geometry [2] */
353#define TWE_PARAM_DRIVEINFO_PhysHeadNum		6	/* [2] */
354#define TWE_PARAM_DRIVEINFO_PhysSectorNym	7	/* [2] */
355#define TWE_PARAM_DRIVEINFO_LogCylNum		8	/* logical geometry [2] */
356#define TWE_PARAM_DRIVEINFO_LogHeadNum		9	/* [2] */
357#define TWE_PARAM_DRIVEINFO_LogSectorNum	10	/* [2] */
358#define TWE_PARAM_DRIVEINFO_UnitNum		11	/* unit number this drive is associated with or 0xff [1] */
359#define TWE_PARAM_DRIVEINFO_DriveFlags		12	/* N/A [1] */
360
361#define TWE_PARAM_APORTTIMEOUT	0x02c0			/* add (aport_number * 3) to parameter index */
362#define TWE_PARAM_APORTTIMEOUT_READ		2	/* read timeouts last 24hrs [2] */
363#define TWE_PARAM_APORTTIMEOUT_WRITE		3	/* write timeouts last 24hrs [2] */
364#define TWE_PARAM_APORTTIMEOUT_DEGRADE		4	/* degrade threshold [2] */
365
366#define TWE_PARAM_UNITINFO	0x0300			/* add unit number 0x00-0x0f */
367#define TWE_PARAM_UNITINFO_Number		2	/* unit number [1] */
368#define TWE_PARAM_UNITINFO_Status		3	/* unit status [1] */
369#define TWE_PARAM_UNITINFO_Capacity		4	/* unit capacity in blocks [4] */
370#define TWE_PARAM_UNITINFO_DescriptorSize	5	/* unit descriptor size + 3 bytes [2] */
371#define TWE_PARAM_UNITINFO_Descriptor		6	/* unit descriptor, TWE_UnitDescriptor or TWE_Array_Descriptor */
372#define TWE_PARAM_UNITINFO_Flags		7	/* unit flags [1] */
373#define TWE_PARAM_UNITFLAGS_WCE			(1<<0)
374
375#define TWE_PARAM_AEN		0x0401
376#define TWE_PARAM_AEN_UnitCode			2	/* (unit number << 8) | AEN code [2] */
377#define TWE_AEN_QUEUE_EMPTY		0x00
378#define TWE_AEN_SOFT_RESET		0x01
379#define TWE_AEN_DEGRADED_MIRROR		0x02	/* reports unit */
380#define TWE_AEN_CONTROLLER_ERROR	0x03
381#define TWE_AEN_REBUILD_FAIL		0x04	/* reports unit */
382#define TWE_AEN_REBUILD_DONE		0x05	/* reports unit */
383#define TWE_AEN_INCOMP_UNIT		0x06	/* reports unit */
384#define TWE_AEN_INIT_DONE		0x07	/* reports unit */
385#define TWE_AEN_UNCLEAN_SHUTDOWN	0x08	/* reports unit */
386#define TWE_AEN_APORT_TIMEOUT		0x09	/* reports unit, rate limited to 1 per 2^16 errors */
387#define TWE_AEN_DRIVE_ERROR		0x0a	/* reports unit */
388#define TWE_AEN_REBUILD_STARTED		0x0b	/* reports unit */
389#define TWE_AEN_QUEUE_FULL		0xff
390#define TWE_AEN_TABLE_UNDEFINED		0x15
391#define TWE_AEN_CODE(x)			((x) & 0xff)
392#define TWE_AEN_UNIT(x)			((x) >> 8)
393
394#define TWE_PARAM_VERSION	0x0402
395#define TWE_PARAM_VERSION_Mon			2	/* monitor version [16] */
396#define TWE_PARAM_VERSION_FW			3	/* firmware version [16] */
397#define TWE_PARAM_VERSION_BIOS			4	/* BIOSs version [16] */
398#define TWE_PARAM_VERSION_PCB			5	/* PCB version [8] */
399#define TWE_PARAM_VERSION_ATA			6	/* A-chip version [8] */
400#define TWE_PARAM_VERSION_PCI			7	/* P-chip version [8] */
401#define TWE_PARAM_VERSION_CtrlModel		8	/* N/A */
402#define TWE_PARAM_VERSION_CtrlSerial		9	/* N/A */
403#define TWE_PARAM_VERSION_SBufSize		10	/* N/A */
404#define TWE_PARAM_VERSION_CompCode		11	/* compatibility code [4] */
405
406#define TWE_PARAM_CONTROLLER	0x0403
407#define TWE_PARAM_CONTROLLER_DCBSectors		2	/* # sectors reserved for DCB per drive [2] */
408#define TWE_PARAM_CONTROLLER_PortCount		3	/* number of drive ports [1] */
409
410#define TWE_PARAM_FEATURES	0x404
411#define TWE_PARAM_FEATURES_DriverShutdown	2	/* set to 1 if driver supports shutdown notification [1] */
412
413typedef struct
414{
415    u_int8_t		num_subunits;	/* must be zero */
416    u_int8_t		configuration;
417#define TWE_UD_CONFIG_CBOD	0x0c	/* JBOD with DCB, used for mirrors */
418#define TWE_UD_CONFIG_SPARE	0x0d	/* same as CBOD, but firmware will use as spare */
419#define TWE_UD_CONFIG_SUBUNIT	0x0e	/* drive is a subunit in an array */
420#define TWE_UD_CONFIG_JBOD	0x0f	/* plain drive */
421    u_int8_t		phys_drv_num;	/* may be 0xff if port can't be determined at runtime */
422    u_int8_t		log_drv_num;	/* must be zero for configuration == 0x0f */
423    u_int32_t		start_lba;
424    u_int32_t		block_count;	/* actual drive size if configuration == 0x0f, otherwise less DCB size */
425} TWE_Unit_Descriptor __attribute__ ((packed));
426
427typedef struct
428{
429    u_int8_t		flag;			/* must be 0xff */
430    u_int8_t		res1;
431    u_int8_t		mirunit_status[4];	/* bitmap of functional subunits in each mirror */
432    u_int8_t		res2[6];
433} TWE_Mirror_Descriptor __attribute__ ((packed));
434
435typedef struct
436{
437    u_int8_t		num_subunits;	/* number of subunits, or number of mirror units in RAID10 */
438    u_int8_t		configuration;
439#define TWE_UD_CONFIG_RAID0	0x00
440#define TWE_UD_CONFIG_RAID1	0x01
441#define TWE_UD_CONFIG_TwinStor	0x02
442#define TWE_UD_CONFIG_RAID5	0x05
443#define TWE_UD_CONFIG_RAID10	0x06
444    u_int8_t		stripe_size;
445#define TWE_UD_STRIPE_4k	0x03
446#define TWE_UD_STRIPE_8k	0x04
447#define TWE_UD_STRIPE_16k	0x05
448#define TWE_UD_STRIPE_32k	0x06
449#define TWE_UD_STRIPE_64k	0x07
450    u_int8_t		log_drv_status;	/* bitmap of functional subunits, or mirror units in RAID10 */
451    u_int32_t		start_lba;
452    u_int32_t		block_count;	/* actual drive size if configuration == 0x0f, otherwise less DCB size */
453    TWE_Unit_Descriptor	subunit[0];	/* subunit descriptors, in RAID10 mode is [mirunit][subunit] */
454} TWE_Array_Descriptor __attribute__ ((packed));
455
456typedef struct
457{
458    u_int16_t	table_id;
459    u_int8_t	parameter_id;
460    u_int8_t	parameter_size_bytes;
461    u_int8_t	data[0];
462} TWE_Param __attribute__ ((packed));
463