tw_cl_fwif.h revision 144966 
1/*
2 * Copyright (c) 2004-05 Applied Micro Circuits Corporation.
3 * Copyright (c) 2004-05 Vinod Kashyap
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *	$FreeBSD: head/sys/dev/twa/tw_cl_fwif.h 144966 2005-04-12 22:07:11Z vkashyap $
28 */
29
30/*
31 * AMCC'S 3ware driver for 9000 series storage controllers.
32 *
33 * Author: Vinod Kashyap
34 */
35
36
37
38#ifndef TW_CL_FWIF_H
39
40#define TW_CL_FWIF_H
41
42
43/*
44 * Macros and data structures for interfacing with the firmware.
45 */
46
47
48/* Register offsets from base address. */
49#define	TWA_CONTROL_REGISTER_OFFSET		0x0
50#define	TWA_STATUS_REGISTER_OFFSET		0x4
51#define	TWA_COMMAND_QUEUE_OFFSET		0x8
52#define	TWA_RESPONSE_QUEUE_OFFSET		0xC
53#define	TWA_COMMAND_QUEUE_OFFSET_LOW		0x20
54#define	TWA_COMMAND_QUEUE_OFFSET_HIGH		0x24
55
56
57/* Control register bit definitions. */
58#define TWA_CONTROL_CLEAR_SBUF_WRITE_ERROR	0x00000008
59#define TWA_CONTROL_ISSUE_HOST_INTERRUPT	0x00000020
60#define TWA_CONTROL_DISABLE_INTERRUPTS		0x00000040
61#define TWA_CONTROL_ENABLE_INTERRUPTS		0x00000080
62#define TWA_CONTROL_ISSUE_SOFT_RESET		0x00000100
63#define TWA_CONTROL_UNMASK_RESPONSE_INTERRUPT	0x00004000
64#define TWA_CONTROL_UNMASK_COMMAND_INTERRUPT	0x00008000
65#define TWA_CONTROL_MASK_RESPONSE_INTERRUPT	0x00010000
66#define TWA_CONTROL_MASK_COMMAND_INTERRUPT	0x00020000
67#define TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT	0x00040000
68#define TWA_CONTROL_CLEAR_HOST_INTERRUPT	0x00080000
69#define TWA_CONTROL_CLEAR_PCI_ABORT		0x00100000
70#define TWA_CONTROL_CLEAR_QUEUE_ERROR		0x00400000
71#define TWA_CONTROL_CLEAR_PARITY_ERROR		0x00800000
72
73
74/* Status register bit definitions. */
75#define TWA_STATUS_ROM_BIOS_IN_SBUF		0x00000002
76#define TWA_STATUS_SBUF_WRITE_ERROR		0x00000008
77#define TWA_STATUS_COMMAND_QUEUE_EMPTY		0x00001000
78#define TWA_STATUS_MICROCONTROLLER_READY	0x00002000
79#define TWA_STATUS_RESPONSE_QUEUE_EMPTY		0x00004000
80#define TWA_STATUS_COMMAND_QUEUE_FULL		0x00008000
81#define TWA_STATUS_RESPONSE_INTERRUPT		0x00010000
82#define TWA_STATUS_COMMAND_INTERRUPT		0x00020000
83#define TWA_STATUS_ATTENTION_INTERRUPT		0x00040000
84#define TWA_STATUS_HOST_INTERRUPT		0x00080000
85#define TWA_STATUS_PCI_ABORT_INTERRUPT		0x00100000
86#define TWA_STATUS_MICROCONTROLLER_ERROR	0x00200000
87#define TWA_STATUS_QUEUE_ERROR_INTERRUPT	0x00400000
88#define TWA_STATUS_PCI_PARITY_ERROR_INTERRUPT	0x00800000
89#define TWA_STATUS_MINOR_VERSION_MASK		0x0F000000
90#define TWA_STATUS_MAJOR_VERSION_MASK		0xF0000000
91
92#define TWA_STATUS_EXPECTED_BITS		0x00002000
93#define TWA_STATUS_UNEXPECTED_BITS		0x00F00000
94
95
96/* PCI related defines. */
97#define TWA_IO_CONFIG_REG			0x10
98
99#define TWA_PCI_CONFIG_CLEAR_PARITY_ERROR	0xc100
100#define TWA_PCI_CONFIG_CLEAR_PCI_ABORT		0x2000
101
102
103/* Command packet opcodes. */
104#define TWA_FW_CMD_NOP				0x00
105#define TWA_FW_CMD_INIT_CONNECTION		0x01
106#define TWA_FW_CMD_READ				0x02
107#define TWA_FW_CMD_WRITE			0x03
108#define TWA_FW_CMD_READVERIFY			0x04
109#define TWA_FW_CMD_VERIFY			0x05
110#define TWA_FW_CMD_ZEROUNIT			0x08
111#define TWA_FW_CMD_REPLACEUNIT			0x09
112#define TWA_FW_CMD_HOTSWAP			0x0A
113#define TWA_FW_CMD_SELFTESTS			0x0B
114#define TWA_FW_CMD_SYNC_PARAM			0x0C
115#define TWA_FW_CMD_REORDER_UNITS		0x0D
116
117#define TWA_FW_CMD_EXECUTE_SCSI			0x10
118#define TWA_FW_CMD_ATA_PASSTHROUGH		0x11
119#define TWA_FW_CMD_GET_PARAM			0x12
120#define TWA_FW_CMD_SET_PARAM			0x13
121#define TWA_FW_CMD_CREATEUNIT			0x14
122#define TWA_FW_CMD_DELETEUNIT			0x15
123#define TWA_FW_CMD_DOWNLOAD_FIRMWARE		0x16
124#define TWA_FW_CMD_REBUILDUNIT			0x17
125#define TWA_FW_CMD_POWER_MANAGEMENT		0x18
126
127#define TWA_FW_CMD_REMOTE_PRINT			0x1B
128#define TWA_FW_CMD_HARD_RESET_FIRMWARE		0x1C
129#define TWA_FW_CMD_DEBUG			0x1D
130
131#define TWA_FW_CMD_DIAGNOSTICS			0x1F
132
133
134/* Misc defines. */
135#define TWA_BUNDLED_FW_VERSION_STRING	"2.06.00.009"
136#define TWA_SHUTDOWN_MESSAGE_CREDITS	0x001
137#define TWA_64BIT_SG_ADDRESSES		0x00000001
138#define TWA_EXTENDED_INIT_CONNECT	0x00000002
139#define TWA_BASE_MODE			1
140#define TWA_BASE_FW_SRL			24
141#define TWA_BASE_FW_BRANCH		0
142#define TWA_BASE_FW_BUILD		1
143#define TWA_CURRENT_FW_SRL		28
144#define TWA_CURRENT_FW_BRANCH		4
145#define TWA_CURRENT_FW_BUILD		9
146#define TWA_MULTI_LUN_FW_SRL		28
147#define TWA_9000_ARCH_ID		0x5	/* 9000 series controllers */
148#define TWA_CTLR_FW_SAME_OR_NEWER	0x00000001
149#define TWA_CTLR_FW_COMPATIBLE		0x00000002
150#define TWA_BUNDLED_FW_SAFE_TO_FLASH	0x00000004
151#define TWA_CTLR_FW_RECOMMENDS_FLASH	0x00000008
152#define TWA_SENSE_DATA_LENGTH		18
153
154
155/*
156 * All SG addresses and DMA'able memory allocated by the OSL should be
157 * TWA_ALIGNMENT bytes aligned, and have a size that is a multiple of
158 * TWA_SG_ELEMENT_SIZE_FACTOR.
159 */
160#define TWA_ALIGNMENT			0x4
161#define TWA_SG_ELEMENT_SIZE_FACTOR	512
162
163
164/*
165 * Some errors of interest (in cmd_hdr->status_block.error) when a command
166 * is completed by the firmware with a bad status.
167 */
168#define TWA_ERROR_LOGICAL_UNIT_NOT_SUPPORTED	0x010a
169#define TWA_ERROR_UNIT_OFFLINE			0x0128
170#define TWA_ERROR_MORE_DATA			0x0231
171
172
173/* AEN codes of interest. */
174#define TWA_AEN_QUEUE_EMPTY		0x00
175#define TWA_AEN_SOFT_RESET		0x01
176#define TWA_AEN_SYNC_TIME_WITH_HOST	0x31
177
178
179/* Table #'s and id's of parameters of interest in firmware's param table. */
180#define TWA_PARAM_VERSION_TABLE		0x0402
181#define TWA_PARAM_VERSION_FW		3	/* firmware version [16] */
182#define TWA_PARAM_VERSION_BIOS		4	/* BIOSs version [16] */
183
184#define TWA_PARAM_CONTROLLER_TABLE	0x0403
185#define TWA_PARAM_CONTROLLER_PORT_COUNT	3	/* number of ports [1] */
186
187#define TWA_PARAM_TIME_TABLE		0x40A
188#define TWA_PARAM_TIME_SCHED_TIME	0x3
189
190#define TWA_9K_PARAM_DESCRIPTOR		0x8000
191
192
193#pragma pack(1)
194/* 7000 structures. */
195struct tw_cl_command_init_connect {
196	TW_UINT8	res1__opcode;	/* 3:5 */
197	TW_UINT8	size;
198	TW_UINT8	request_id;
199	TW_UINT8	res2;
200	TW_UINT8	status;
201	TW_UINT8	flags;
202	TW_UINT16	message_credits;
203	TW_UINT32	features;
204	TW_UINT16	fw_srl;
205	TW_UINT16	fw_arch_id;
206	TW_UINT16	fw_branch;
207	TW_UINT16	fw_build;
208	TW_UINT32	result;
209};
210
211
212/* Structure for downloading firmware onto the controller. */
213struct tw_cl_command_download_firmware {
214	TW_UINT8	sgl_off__opcode;/* 3:5 */
215	TW_UINT8	size;
216	TW_UINT8	request_id;
217	TW_UINT8	unit;
218	TW_UINT8	status;
219	TW_UINT8	flags;
220	TW_UINT16	param;
221	TW_UINT8	sgl[1];
222};
223
224
225/* Structure for hard resetting the controller. */
226struct tw_cl_command_reset_firmware {
227	TW_UINT8	res1__opcode;	/* 3:5 */
228	TW_UINT8	size;
229	TW_UINT8	request_id;
230	TW_UINT8	unit;
231	TW_UINT8	status;
232	TW_UINT8	flags;
233	TW_UINT8	res2;
234	TW_UINT8	param;
235};
236
237
238/* Structure for sending get/set param commands. */
239struct tw_cl_command_param {
240	TW_UINT8	sgl_off__opcode;/* 3:5 */
241	TW_UINT8	size;
242	TW_UINT8	request_id;
243	TW_UINT8	host_id__unit;	/* 4:4 */
244	TW_UINT8	status;
245	TW_UINT8	flags;
246	TW_UINT16	param_count;
247	TW_UINT8	sgl[1];
248};
249
250
251/* Generic command packet. */
252struct tw_cl_command_generic {
253	TW_UINT8	sgl_off__opcode;/* 3:5 */
254	TW_UINT8	size;
255	TW_UINT8	request_id;
256	TW_UINT8	host_id__unit;	/* 4:4 */
257	TW_UINT8	status;
258	TW_UINT8	flags;
259	TW_UINT16	count;	/* block cnt, parameter cnt, message credits */
260};
261
262
263/* Command packet header. */
264struct tw_cl_command_header {
265	TW_UINT8	sense_data[TWA_SENSE_DATA_LENGTH];
266	struct {
267		TW_INT8		reserved[4];
268		TW_UINT16	error;
269		TW_UINT8	padding;
270		TW_UINT8	res__severity;	/* 5:3 */
271	} status_block;
272	TW_UINT8	err_specific_desc[98];
273	struct {
274		TW_UINT8	size_header;
275		TW_UINT16	reserved;
276		TW_UINT8	size_sense;
277	} header_desc;
278};
279
280
281/* 7000 Command packet. */
282union tw_cl_command_7k {
283	struct tw_cl_command_init_connect	init_connect;
284	struct tw_cl_command_download_firmware	download_fw;
285	struct tw_cl_command_reset_firmware	reset_fw;
286	struct tw_cl_command_param		param;
287	struct tw_cl_command_generic		generic;
288	TW_UINT8	padding[1024 - sizeof(struct tw_cl_command_header)];
289};
290
291
292/* 9000 Command Packet. */
293struct tw_cl_command_9k {
294	TW_UINT8	res__opcode;	/* 3:5 */
295	TW_UINT8	unit;
296	TW_UINT16	lun_l4__req_id;	/* 4:12 */
297	TW_UINT8	status;
298	TW_UINT8	sgl_offset; /* offset (in bytes) to sg_list, from the
299					end of sgl_entries */
300	TW_UINT16	lun_h4__sgl_entries;
301	TW_UINT8	cdb[16];
302	TW_UINT8	sg_list[872];/* total struct size =
303					1024-sizeof(cmd_hdr) */
304};
305
306
307/* Full command packet. */
308struct tw_cl_command_packet {
309	struct tw_cl_command_header	cmd_hdr;
310	union {
311		union tw_cl_command_7k	cmd_pkt_7k;
312		struct tw_cl_command_9k cmd_pkt_9k;
313	} command;
314};
315
316
317/* Structure describing payload for get/set param commands. */
318struct tw_cl_param_9k {
319	TW_UINT16	table_id;
320	TW_UINT8	parameter_id;
321	TW_UINT8	reserved;
322	TW_UINT16	parameter_size_bytes;
323	TW_UINT16	parameter_actual_size_bytes;
324	TW_UINT8	data[1];
325};
326#pragma pack()
327
328
329/* Functions to read from, and write to registers */
330#define TW_CLI_WRITE_CONTROL_REGISTER(ctlr_handle, value)		\
331	tw_osl_write_reg(ctlr_handle, TWA_CONTROL_REGISTER_OFFSET, value, 4)
332
333
334#define TW_CLI_READ_STATUS_REGISTER(ctlr_handle)			\
335	tw_osl_read_reg(ctlr_handle, TWA_STATUS_REGISTER_OFFSET, 4)
336
337
338#define TW_CLI_WRITE_COMMAND_QUEUE(ctlr_handle, value)	do {		\
339	if (ctlr->flags & TW_CL_64BIT_ADDRESSES) {			\
340		/* First write the low 4 bytes, then the high 4. */	\
341		tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET_LOW, \
342			(TW_UINT32)(value), 4);				\
343		tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET_HIGH,\
344			(TW_UINT32)(((TW_UINT64)value)>>32), 4);	\
345	} else								\
346		tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET,	\
347					(TW_UINT32)(value), 4);		\
348} while (0)
349
350
351#define TW_CLI_READ_RESPONSE_QUEUE(ctlr_handle)				\
352	tw_osl_read_reg(ctlr_handle, TWA_RESPONSE_QUEUE_OFFSET, 4)
353
354
355#define TW_CLI_SOFT_RESET(ctlr)					\
356	TW_CLI_WRITE_CONTROL_REGISTER(ctlr,			\
357		TWA_CONTROL_ISSUE_SOFT_RESET |			\
358		TWA_CONTROL_CLEAR_HOST_INTERRUPT |		\
359		TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT |		\
360		TWA_CONTROL_MASK_COMMAND_INTERRUPT |		\
361		TWA_CONTROL_MASK_RESPONSE_INTERRUPT |		\
362		TWA_CONTROL_DISABLE_INTERRUPTS)
363
364/* Detect inconsistencies in the status register. */
365#define TW_CLI_STATUS_ERRORS(x)					\
366	((x & TWA_STATUS_UNEXPECTED_BITS) &&			\
367	 (x & TWA_STATUS_MICROCONTROLLER_READY))
368
369
370/*
371 * Functions for making transparent, the bit fields in firmware
372 * interface structures.
373 */
374#define BUILD_SGL_OFF__OPCODE(sgl_off, opcode)	\
375	((sgl_off << 5) & 0xE0) | (opcode & 0x1F)	/* 3:5 */
376
377#define BUILD_RES__OPCODE(res, opcode)		\
378	((res << 5) & 0xE0) | (opcode & 0x1F)		/* 3:5 */
379
380#define BUILD_HOST_ID__UNIT(host_id, unit)	\
381	((host_id << 4) & 0xF0) | (unit & 0xF)		/* 4:4 */
382
383#define BUILD_RES__SEVERITY(res, severity)	\
384	((res << 3) & 0xF8) | (severity & 0x7)		/* 5:3 */
385
386#define BUILD_LUN_L4__REQ_ID(lun, req_id)	\
387	(((lun << 12) & 0xF000) | (req_id & 0xFFF))	/* 4:12 */
388
389#define BUILD_LUN_H4__SGL_ENTRIES(lun, sgl_entries)	\
390	(((lun << 8) & 0xF000) | (sgl_entries & 0xFFF))	/* 4:12 */
391
392
393#define GET_OPCODE(sgl_off__opcode)	\
394	(sgl_off__opcode & 0x1F)		/* 3:5 */
395
396#define GET_SGL_OFF(sgl_off__opcode)	\
397	((sgl_off__opcode >> 5) & 0x7)		/* 3:5 */
398
399#define GET_UNIT(host_id__unit)		\
400	(host_id__unit & 0xF)			/* 4:4 */
401
402#define GET_HOST_ID(host_id__unit)	\
403	((host_id__unit >> 4) & 0xF)		/* 4:4 */
404
405#define GET_SEVERITY(res__severity)	\
406	(res__severity & 0x7)			/* 5:3 */
407
408#define GET_RESP_ID(undef2__resp_id__undef1)	\
409	((undef2__resp_id__undef1 >> 4) & 0xFF)	/* 20:8:4 */
410
411#define GET_REQ_ID(lun_l4__req_id)	\
412	(lun_l4__req_id & 0xFFF)		/* 4:12 */
413
414#define GET_LUN_L4(lun_l4__req_id)	\
415	((lun_l4__req_id >> 12) & 0xF)		/* 4:12 */
416
417#define GET_SGL_ENTRIES(lun_h4__sgl_entries)	\
418	(lun_h4__sgl_entries & 0xFFF)		/* 4:12 */
419
420#define GET_LUN_H4(lun_h4__sgl_entries)	\
421	((lun_h4__sgl_entries >> 12) & 0xF)	/* 4:12 */
422
423
424
425#endif /* TW_CL_FWIF_H */
426