es137x.c revision 62483
150724Scg/* 253413Sroger * Support the ENSONIQ AudioPCI board and Creative Labs SoundBlaster PCI 353413Sroger * boards based on the ES1370, ES1371 and ES1373 chips. 450724Scg * 553413Sroger * Copyright (c) 1999 Russell Cattelan <cattelan@thebarn.com> 650724Scg * Copyright (c) 1999 Cameron Grant <gandalf@vilnya.demon.co.uk> 750724Scg * Copyright (c) 1998 by Joachim Kuebart. All rights reserved. 850724Scg * 950724Scg * Redistribution and use in source and binary forms, with or without 1050724Scg * modification, are permitted provided that the following conditions 1150724Scg * are met: 1250724Scg * 1350724Scg * 1. Redistributions of source code must retain the above copyright 1450724Scg * notice, this list of conditions and the following disclaimer. 1550724Scg * 1650724Scg * 2. Redistributions in binary form must reproduce the above copyright 1750724Scg * notice, this list of conditions and the following disclaimer in 1850724Scg * the documentation and/or other materials provided with the 1950724Scg * distribution. 2050724Scg * 2150724Scg * 3. All advertising materials mentioning features or use of this 2250724Scg * software must display the following acknowledgement: 2350724Scg * This product includes software developed by Joachim Kuebart. 2450724Scg * 2550724Scg * 4. The name of the author may not be used to endorse or promote 2650724Scg * products derived from this software without specific prior 2750724Scg * written permission. 2850724Scg * 2950724Scg * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 3050724Scg * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 3150724Scg * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 3250724Scg * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 3350724Scg * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 3450724Scg * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 3550724Scg * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3650724Scg * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 3750724Scg * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3850724Scg * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 3950724Scg * OF THE POSSIBILITY OF SUCH DAMAGE. 4050724Scg * 4150733Speter * $FreeBSD: head/sys/dev/sound/pci/es137x.c 62483 2000-07-03 20:52:27Z cg $ 4250724Scg */ 4350724Scg 4453413Sroger/* 4553413Sroger * Part of this code was heavily inspired by the linux driver from 4653413Sroger * Thomas Sailer (sailer@ife.ee.ethz.ch) 4754831Scg * Just about everything has been touched and reworked in some way but 4854831Scg * the all the underlying sequences/timing/register values are from 4953413Sroger * Thomas' code. 5053413Sroger * 5153413Sroger*/ 5253413Sroger 5353465Scg#include <dev/sound/pcm/sound.h> 5453465Scg#include <dev/sound/pcm/ac97.h> 5553465Scg#include <dev/sound/pci/es137x.h> 5650724Scg 5750724Scg#include <pci/pcireg.h> 5850724Scg#include <pci/pcivar.h> 5950724Scg 6053413Sroger#include <sys/sysctl.h> 6153413Sroger 6253413Srogerstatic int debug = 0; 6353413SrogerSYSCTL_INT(_debug, OID_AUTO, es_debug, CTLFLAG_RW, &debug, 0, ""); 6453413Sroger 6550724Scg#define MEM_MAP_REG 0x14 6650724Scg 6750724Scg/* PCI IDs of supported chips */ 6850724Scg#define ES1370_PCI_ID 0x50001274 6953413Sroger#define ES1371_PCI_ID 0x13711274 7056154Speter#define ES1371_PCI_ID2 0x13713274 7162412Sroberto#define ES1371_PCI_ID3 0x58801274 7250724Scg 7359019Scg#define ES_BUFFSIZE 4096 7459019Scg 7550724Scg/* device private data */ 7650724Scgstruct es_info; 7750724Scg 7855209Scgstruct es_chinfo { 7950724Scg struct es_info *parent; 8050724Scg pcm_channel *channel; 8150724Scg snd_dbuf *buffer; 8254831Scg int dir, num; 8350724Scg u_int32_t fmt; 8455209Scg}; 8550724Scg 8655209Scgstruct es_info { 8750724Scg bus_space_tag_t st; 8850724Scg bus_space_handle_t sh; 8950724Scg bus_dma_tag_t parent_dmat; 9050724Scg 9159019Scg device_t dev; 9254831Scg int num; 9350724Scg /* Contents of board's registers */ 9450724Scg u_long ctrl; 9550724Scg u_long sctrl; 9650724Scg struct es_chinfo pch, rch; 9755209Scg}; 9850724Scg 9950724Scg/* -------------------------------------------------------------------- */ 10054831Scg 10153413Sroger/* prototypes */ 10254831Scgstatic void es_intr(void *); 10350724Scg 10454831Scgstatic void es1371_wrcodec(void *, int, u_int32_t); 10554831Scgstatic u_int32_t es1371_rdcodec(void *, int); 10655209Scgstatic u_int es1371_wait_src_ready(struct es_info *); 10755209Scgstatic void es1371_src_write(struct es_info *, u_short, unsigned short); 10855209Scgstatic u_int es1371_adc_rate(struct es_info *, u_int, int); 10955209Scgstatic u_int es1371_dac_rate(struct es_info *, u_int, int); 11055209Scgstatic int es1371_init(struct es_info *es, int); 11154831Scgstatic int es1370_init(struct es_info *); 11254831Scgstatic int es1370_wrcodec(struct es_info *, u_char, u_char); 11350724Scg 11450724Scg/* channel interface */ 11550724Scgstatic void *eschan_init(void *devinfo, snd_dbuf *b, pcm_channel *c, int dir); 11654831Scgstatic int eschan_setdir(void *data, int dir); 11754831Scgstatic int eschan_setformat(void *data, u_int32_t format); 11854831Scgstatic int eschan1370_setspeed(void *data, u_int32_t speed); 11955209Scgstatic int eschan1371_setspeed(void *data, u_int32_t speed); 12054831Scgstatic int eschan_setblocksize(void *data, u_int32_t blocksize); 12154831Scgstatic int eschan_trigger(void *data, int go); 12254831Scgstatic int eschan_getptr(void *data); 12350724Scgstatic pcmchan_caps *eschan_getcaps(void *data); 12450724Scg 12550724Scgstatic pcmchan_caps es_playcaps = { 12650724Scg 4000, 48000, 12750724Scg AFMT_STEREO | AFMT_U8 | AFMT_S16_LE, 12850724Scg AFMT_STEREO | AFMT_S16_LE 12950724Scg}; 13050724Scg 13150724Scgstatic pcmchan_caps es_reccaps = { 13250724Scg 4000, 48000, 13350724Scg AFMT_STEREO | AFMT_U8 | AFMT_S16_LE, 13450724Scg AFMT_STEREO | AFMT_S16_LE 13550724Scg}; 13650724Scg 13754831Scgstatic pcm_channel es1370_chantemplate = { 13850724Scg eschan_init, 13950724Scg eschan_setdir, 14050724Scg eschan_setformat, 14154831Scg eschan1370_setspeed, 14250724Scg eschan_setblocksize, 14350724Scg eschan_trigger, 14450724Scg eschan_getptr, 14550724Scg eschan_getcaps, 14650724Scg}; 14750724Scg 14854831Scgstatic pcm_channel es1371_chantemplate = { 14954831Scg eschan_init, 15054831Scg eschan_setdir, 15154831Scg eschan_setformat, 15254831Scg eschan1371_setspeed, 15354831Scg eschan_setblocksize, 15454831Scg eschan_trigger, 15554831Scg eschan_getptr, 15654831Scg eschan_getcaps, 15754831Scg}; 15854831Scg 15950724Scg/* -------------------------------------------------------------------- */ 16050724Scg 16154831Scg/* The es1370 mixer interface */ 16250724Scg 16354831Scgstatic int es1370_mixinit(snd_mixer *m); 16454831Scgstatic int es1370_mixset(snd_mixer *m, unsigned dev, unsigned left, unsigned right); 16554831Scgstatic int es1370_mixsetrecsrc(snd_mixer *m, u_int32_t src); 16650724Scg 16754831Scgstatic snd_mixer es1370_mixer = { 16854831Scg "AudioPCI 1370 mixer", 16954831Scg es1370_mixinit, 17054831Scg es1370_mixset, 17154831Scg es1370_mixsetrecsrc, 17250724Scg}; 17350724Scg 17450724Scgstatic const struct { 17550724Scg unsigned volidx:4; 17650724Scg unsigned left:4; 17750724Scg unsigned right:4; 17850724Scg unsigned stereo:1; 17950724Scg unsigned recmask:13; 18050724Scg unsigned avail:1; 18150724Scg} mixtable[SOUND_MIXER_NRDEVICES] = { 18250724Scg [SOUND_MIXER_VOLUME] = { 0, 0x0, 0x1, 1, 0x0000, 1 }, 18350724Scg [SOUND_MIXER_PCM] = { 1, 0x2, 0x3, 1, 0x0400, 1 }, 18450724Scg [SOUND_MIXER_SYNTH] = { 2, 0x4, 0x5, 1, 0x0060, 1 }, 18550724Scg [SOUND_MIXER_CD] = { 3, 0x6, 0x7, 1, 0x0006, 1 }, 18650724Scg [SOUND_MIXER_LINE] = { 4, 0x8, 0x9, 1, 0x0018, 1 }, 18750724Scg [SOUND_MIXER_LINE1] = { 5, 0xa, 0xb, 1, 0x1800, 1 }, 18850724Scg [SOUND_MIXER_LINE2] = { 6, 0xc, 0x0, 0, 0x0100, 1 }, 18950724Scg [SOUND_MIXER_LINE3] = { 7, 0xd, 0x0, 0, 0x0200, 1 }, 19050724Scg [SOUND_MIXER_MIC] = { 8, 0xe, 0x0, 0, 0x0001, 1 }, 19154831Scg [SOUND_MIXER_OGAIN] = { 9, 0xf, 0x0, 0, 0x0000, 1 } 19254831Scg}; 19350724Scg 19450724Scgstatic int 19554831Scges1370_mixinit(snd_mixer *m) 19650724Scg{ 19750724Scg int i; 19850724Scg u_int32_t v; 19950724Scg 20050724Scg v = 0; 20150724Scg for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) 20250724Scg if (mixtable[i].avail) v |= (1 << i); 20350724Scg mix_setdevs(m, v); 20450724Scg v = 0; 20550724Scg for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) 20650724Scg if (mixtable[i].recmask) v |= (1 << i); 20750724Scg mix_setrecdevs(m, v); 20850724Scg return 0; 20950724Scg} 21050724Scg 21150724Scgstatic int 21254831Scges1370_mixset(snd_mixer *m, unsigned dev, unsigned left, unsigned right) 21350724Scg{ 21450724Scg int l, r, rl, rr; 21550724Scg 21650724Scg if (!mixtable[dev].avail) return -1; 21750724Scg l = left; 21850724Scg r = mixtable[dev].stereo? right : l; 21950724Scg if (mixtable[dev].left == 0xf) { 22050724Scg rl = (l < 2)? 0x80 : 7 - (l - 2) / 14; 22150724Scg } else { 22250724Scg rl = (l < 10)? 0x80 : 15 - (l - 10) / 6; 22350724Scg } 22450724Scg if (mixtable[dev].stereo) { 22550724Scg rr = (r < 10)? 0x80 : 15 - (r - 10) / 6; 22654831Scg es1370_wrcodec(mix_getdevinfo(m), mixtable[dev].right, rr); 22750724Scg } 22854831Scg es1370_wrcodec(mix_getdevinfo(m), mixtable[dev].left, rl); 22950724Scg return l | (r << 8); 23050724Scg} 23150724Scg 23250724Scgstatic int 23354831Scges1370_mixsetrecsrc(snd_mixer *m, u_int32_t src) 23450724Scg{ 23550724Scg int i, j = 0; 23650724Scg 23750724Scg if (src == 0) src = 1 << SOUND_MIXER_MIC; 23850724Scg src &= mix_getrecdevs(m); 23950724Scg for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) 24050724Scg if ((src & (1 << i)) != 0) j |= mixtable[i].recmask; 24150724Scg 24254831Scg es1370_wrcodec(mix_getdevinfo(m), CODEC_LIMIX1, j & 0x55); 24354831Scg es1370_wrcodec(mix_getdevinfo(m), CODEC_RIMIX1, j & 0xaa); 24454831Scg es1370_wrcodec(mix_getdevinfo(m), CODEC_LIMIX2, (j >> 8) & 0x17); 24554831Scg es1370_wrcodec(mix_getdevinfo(m), CODEC_RIMIX2, (j >> 8) & 0x0f); 24654831Scg es1370_wrcodec(mix_getdevinfo(m), CODEC_OMIX1, 0x7f); 24754831Scg es1370_wrcodec(mix_getdevinfo(m), CODEC_OMIX2, 0x3f); 24850724Scg return src; 24950724Scg} 25050724Scg 25150724Scgstatic int 25254831Scges1370_wrcodec(struct es_info *es, u_char i, u_char data) 25350724Scg{ 25450724Scg int wait = 100; /* 100 msec timeout */ 25550724Scg 25650724Scg do { 25750724Scg if ((bus_space_read_4(es->st, es->sh, ES1370_REG_STATUS) & 25850724Scg STAT_CSTAT) == 0) { 25950724Scg bus_space_write_2(es->st, es->sh, ES1370_REG_CODEC, 26050724Scg ((u_short)i << CODEC_INDEX_SHIFT) | data); 26150724Scg return 0; 26250724Scg } 26350724Scg DELAY(1000); 26450724Scg } while (--wait); 26554831Scg printf("pcm: es1370_wrcodec timed out\n"); 26650724Scg return -1; 26750724Scg} 26850724Scg 26950724Scg/* -------------------------------------------------------------------- */ 27050724Scg 27150724Scg/* channel interface */ 27250724Scgstatic void * 27350724Scgeschan_init(void *devinfo, snd_dbuf *b, pcm_channel *c, int dir) 27450724Scg{ 27550724Scg struct es_info *es = devinfo; 27650724Scg struct es_chinfo *ch = (dir == PCMDIR_PLAY)? &es->pch : &es->rch; 27750724Scg 27850724Scg ch->parent = es; 27950724Scg ch->channel = c; 28050724Scg ch->buffer = b; 28150724Scg ch->buffer->bufsize = ES_BUFFSIZE; 28254831Scg ch->num = ch->parent->num++; 28350724Scg if (chn_allocbuf(ch->buffer, es->parent_dmat) == -1) return NULL; 28450724Scg return ch; 28550724Scg} 28650724Scg 28750724Scgstatic int 28850724Scgeschan_setdir(void *data, int dir) 28950724Scg{ 29050724Scg struct es_chinfo *ch = data; 29150724Scg struct es_info *es = ch->parent; 29250724Scg 29350724Scg if (dir == PCMDIR_PLAY) { 29450724Scg bus_space_write_1(es->st, es->sh, ES1370_REG_MEMPAGE, 29550724Scg ES1370_REG_DAC2_FRAMEADR >> 8); 29650724Scg bus_space_write_4(es->st, es->sh, ES1370_REG_DAC2_FRAMEADR & 0xff, 29750724Scg vtophys(ch->buffer->buf)); 29850724Scg bus_space_write_4(es->st, es->sh, ES1370_REG_DAC2_FRAMECNT & 0xff, 29950724Scg (ch->buffer->bufsize >> 2) - 1); 30050724Scg } else { 30150724Scg bus_space_write_1(es->st, es->sh, ES1370_REG_MEMPAGE, 30250724Scg ES1370_REG_ADC_FRAMEADR >> 8); 30350724Scg bus_space_write_4(es->st, es->sh, ES1370_REG_ADC_FRAMEADR & 0xff, 30450724Scg vtophys(ch->buffer->buf)); 30550724Scg bus_space_write_4(es->st, es->sh, ES1370_REG_ADC_FRAMECNT & 0xff, 30650724Scg (ch->buffer->bufsize >> 2) - 1); 30750724Scg } 30850724Scg ch->dir = dir; 30950724Scg return 0; 31050724Scg} 31150724Scg 31250724Scgstatic int 31350724Scgeschan_setformat(void *data, u_int32_t format) 31450724Scg{ 31550724Scg struct es_chinfo *ch = data; 31650724Scg struct es_info *es = ch->parent; 31750724Scg 31850724Scg if (ch->dir == PCMDIR_PLAY) { 31950724Scg es->sctrl &= ~SCTRL_P2FMT; 32050724Scg if (format & AFMT_S16_LE) es->sctrl |= SCTRL_P2SEB; 32150724Scg if (format & AFMT_STEREO) es->sctrl |= SCTRL_P2SMB; 32250724Scg } else { 32350724Scg es->sctrl &= ~SCTRL_R1FMT; 32450724Scg if (format & AFMT_S16_LE) es->sctrl |= SCTRL_R1SEB; 32550724Scg if (format & AFMT_STEREO) es->sctrl |= SCTRL_R1SMB; 32650724Scg } 32750724Scg bus_space_write_4(es->st, es->sh, ES1370_REG_SERIAL_CONTROL, es->sctrl); 32850724Scg ch->fmt = format; 32950724Scg return 0; 33050724Scg} 33150724Scg 33250724Scgstatic int 33354831Scgeschan1370_setspeed(void *data, u_int32_t speed) 33450724Scg{ 33550724Scg struct es_chinfo *ch = data; 33650724Scg struct es_info *es = ch->parent; 33750724Scg 33850724Scg es->ctrl &= ~CTRL_PCLKDIV; 33950724Scg es->ctrl |= DAC2_SRTODIV(speed) << CTRL_SH_PCLKDIV; 34050724Scg bus_space_write_4(es->st, es->sh, ES1370_REG_CONTROL, es->ctrl); 34150724Scg /* rec/play speeds locked together - should indicate in flags */ 34250724Scg return speed; /* XXX calc real speed */ 34350724Scg} 34450724Scg 34554831Scgint 34654831Scgeschan1371_setspeed(void *data, u_int32_t speed) 34754831Scg{ 34854831Scg struct es_chinfo *ch = data; 34954831Scg struct es_info *es = ch->parent; 35054831Scg 35154831Scg if (ch->dir == PCMDIR_PLAY) { 35254831Scg return es1371_dac_rate(es, speed, 3 - ch->num); /* play */ 35354831Scg } else { 35454831Scg return es1371_adc_rate(es, speed, 1); /* record */ 35554831Scg } 35654831Scg} 35754831Scg 35850724Scgstatic int 35950724Scgeschan_setblocksize(void *data, u_int32_t blocksize) 36050724Scg{ 36150724Scg return blocksize; 36250724Scg} 36350724Scg 36450724Scgstatic int 36550724Scgeschan_trigger(void *data, int go) 36650724Scg{ 36750724Scg struct es_chinfo *ch = data; 36850724Scg struct es_info *es = ch->parent; 36960958Scg unsigned ss, cnt; 37050724Scg 37160958Scg if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD) 37260958Scg return 0; 37360958Scg 37460958Scg ss = 1; 37560958Scg ss <<= (ch->fmt & AFMT_STEREO)? 1 : 0; 37660958Scg ss <<= (ch->fmt & AFMT_16BIT)? 1 : 0; 37760958Scg cnt = ch->buffer->dl / ss - 1; 37860958Scg 37950724Scg if (ch->dir == PCMDIR_PLAY) { 38050724Scg if (go == PCMTRIG_START) { 38150724Scg int b = (ch->fmt & AFMT_S16_LE)? 2 : 1; 38250724Scg es->ctrl |= CTRL_DAC2_EN; 38350724Scg es->sctrl &= ~(SCTRL_P2ENDINC | SCTRL_P2STINC | 38450724Scg SCTRL_P2LOOPSEL | SCTRL_P2PAUSE | 38550724Scg SCTRL_P2DACSEN); 38650724Scg es->sctrl |= SCTRL_P2INTEN | (b << SCTRL_SH_P2ENDINC); 38750724Scg bus_space_write_4(es->st, es->sh, 38850724Scg ES1370_REG_DAC2_SCOUNT, cnt); 38959323Scg /* start at beginning of buffer */ 39059323Scg bus_space_write_4(es->st, es->sh, ES1370_REG_MEMPAGE, 39159323Scg ES1370_REG_DAC2_FRAMECNT >> 8); 39259323Scg bus_space_write_4(es->st, es->sh, 39359323Scg ES1370_REG_DAC2_FRAMECNT & 0xff, 39459323Scg (ch->buffer->bufsize >> 2) - 1); 39550724Scg } else es->ctrl &= ~CTRL_DAC2_EN; 39650724Scg } else { 39750724Scg if (go == PCMTRIG_START) { 39850724Scg es->ctrl |= CTRL_ADC_EN; 39950724Scg es->sctrl &= ~SCTRL_R1LOOPSEL; 40050724Scg es->sctrl |= SCTRL_R1INTEN; 40150724Scg bus_space_write_4(es->st, es->sh, 40250724Scg ES1370_REG_ADC_SCOUNT, cnt); 40359323Scg /* start at beginning of buffer */ 40459323Scg bus_space_write_4(es->st, es->sh, ES1370_REG_MEMPAGE, 40559323Scg ES1370_REG_ADC_FRAMECNT >> 8); 40659323Scg bus_space_write_4(es->st, es->sh, 40759323Scg ES1370_REG_ADC_FRAMECNT & 0xff, 40859323Scg (ch->buffer->bufsize >> 2) - 1); 40950724Scg } else es->ctrl &= ~CTRL_ADC_EN; 41050724Scg } 41150724Scg bus_space_write_4(es->st, es->sh, ES1370_REG_SERIAL_CONTROL, es->sctrl); 41250724Scg bus_space_write_4(es->st, es->sh, ES1370_REG_CONTROL, es->ctrl); 41350724Scg return 0; 41450724Scg} 41550724Scg 41650724Scgstatic int 41750724Scgeschan_getptr(void *data) 41850724Scg{ 41950724Scg struct es_chinfo *ch = data; 42050724Scg struct es_info *es = ch->parent; 42159323Scg u_int32_t reg, cnt; 42259323Scg 42359323Scg if (ch->dir == PCMDIR_PLAY) 42459323Scg reg = ES1370_REG_DAC2_FRAMECNT; 42559323Scg else 42659323Scg reg = ES1370_REG_ADC_FRAMECNT; 42759323Scg 42859323Scg bus_space_write_4(es->st, es->sh, ES1370_REG_MEMPAGE, reg >> 8); 42959323Scg cnt = bus_space_read_4(es->st, es->sh, reg & 0x000000ff) >> 16; 43059323Scg /* cnt is longwords */ 43159323Scg return cnt << 2; 43250724Scg} 43350724Scg 43450724Scgstatic pcmchan_caps * 43550724Scgeschan_getcaps(void *data) 43650724Scg{ 43750724Scg struct es_chinfo *ch = data; 43850724Scg return (ch->dir == PCMDIR_PLAY)? &es_playcaps : &es_reccaps; 43950724Scg} 44050724Scg 44150724Scg/* The interrupt handler */ 44250724Scgstatic void 44354831Scges_intr(void *p) 44450724Scg{ 44550724Scg struct es_info *es = p; 44650724Scg unsigned intsrc, sctrl; 44750724Scg 44850724Scg intsrc = bus_space_read_4(es->st, es->sh, ES1370_REG_STATUS); 44950724Scg if ((intsrc & STAT_INTR) == 0) return; 45050724Scg 45150724Scg sctrl = es->sctrl; 45250724Scg if (intsrc & STAT_ADC) sctrl &= ~SCTRL_R1INTEN; 45350724Scg if (intsrc & STAT_DAC1) sctrl &= ~SCTRL_P1INTEN; 45450724Scg if (intsrc & STAT_DAC2) sctrl &= ~SCTRL_P2INTEN; 45550724Scg 45650724Scg bus_space_write_4(es->st, es->sh, ES1370_REG_SERIAL_CONTROL, sctrl); 45750724Scg bus_space_write_4(es->st, es->sh, ES1370_REG_SERIAL_CONTROL, es->sctrl); 45850724Scg 45954831Scg if (intsrc & STAT_ADC) chn_intr(es->rch.channel); 46054831Scg if (intsrc & STAT_DAC1); 46150724Scg if (intsrc & STAT_DAC2) chn_intr(es->pch.channel); 46250724Scg} 46350724Scg 46454831Scg/* ES1370 specific */ 46554831Scgstatic int 46654831Scges1370_init(struct es_info *es) 46754831Scg{ 46854831Scg es->ctrl = CTRL_CDC_EN | CTRL_SERR_DIS | 46954831Scg (DAC2_SRTODIV(DSP_DEFAULT_SPEED) << CTRL_SH_PCLKDIV); 47054831Scg bus_space_write_4(es->st, es->sh, ES1370_REG_CONTROL, es->ctrl); 47153413Sroger 47254831Scg es->sctrl = 0; 47354831Scg bus_space_write_4(es->st, es->sh, ES1370_REG_SERIAL_CONTROL, es->sctrl); 47453413Sroger 47554831Scg es1370_wrcodec(es, CODEC_RES_PD, 3);/* No RST, PD */ 47654831Scg es1370_wrcodec(es, CODEC_CSEL, 0); /* CODEC ADC and CODEC DAC use 47754831Scg * {LR,B}CLK2 and run off the LRCLK2 47854831Scg * PLL; program DAC_SYNC=0! */ 47954831Scg es1370_wrcodec(es, CODEC_ADSEL, 0);/* Recording source is mixer */ 48054831Scg es1370_wrcodec(es, CODEC_MGAIN, 0);/* MIC amp is 0db */ 48153413Sroger 48254831Scg return 0; 48354831Scg} 48453413Sroger 48554831Scg/* ES1371 specific */ 48653413Srogerint 48755209Scges1371_init(struct es_info *es, int rev) 48853413Sroger{ 48953413Sroger int idx; 49053413Sroger 49154831Scg if (debug > 0) printf("es_init\n"); 49254831Scg 49354831Scg es->num = 0; 49453413Sroger es->ctrl = 0; 49553413Sroger es->sctrl = 0; 49653413Sroger /* initialize the chips */ 49762412Sroberto if (rev == 7 || rev >= 9 || rev == 2) { 49855209Scg#define ES1371_BINTSUMM_OFF 0x07 49955209Scg bus_space_write_4(es->st, es->sh, ES1371_BINTSUMM_OFF, 0x20); 50055209Scg if (debug > 0) printf("es_init rev == 7 || rev >= 9\n"); 50155209Scg } else { /* pre ac97 2.1 card */ 50255209Scg bus_space_write_4(es->st, es->sh, ES1370_REG_CONTROL, es->ctrl); 50355209Scg if (debug > 0) printf("es_init pre ac97 2.1\n"); 50455209Scg } 50553413Sroger bus_space_write_4(es->st, es->sh, ES1370_REG_SERIAL_CONTROL, es->sctrl); 50653413Sroger bus_space_write_4(es->st, es->sh, ES1371_REG_LEGACY, 0); 50753413Sroger /* AC'97 warm reset to start the bitclk */ 50853413Sroger bus_space_write_4(es->st, es->sh, ES1371_REG_LEGACY, es->ctrl | ES1371_SYNC_RES); 50953413Sroger DELAY(2000); 51055204Scg bus_space_write_4(es->st, es->sh, ES1370_REG_SERIAL_CONTROL, es->ctrl); 51153413Sroger /* Init the sample rate converter */ 51253413Sroger bus_space_write_4(es->st, es->sh, ES1371_REG_SMPRATE, ES1371_DIS_SRC); 51353413Sroger for (idx = 0; idx < 0x80; idx++) 51454831Scg es1371_src_write(es, idx, 0); 51553413Sroger es1371_src_write(es, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4); 51653413Sroger es1371_src_write(es, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10); 51753413Sroger es1371_src_write(es, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4); 51853413Sroger es1371_src_write(es, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10); 51953413Sroger es1371_src_write(es, ES_SMPREG_VOL_ADC, 1 << 12); 52053413Sroger es1371_src_write(es, ES_SMPREG_VOL_ADC + 1, 1 << 12); 52153413Sroger es1371_src_write(es, ES_SMPREG_VOL_DAC1, 1 << 12); 52253413Sroger es1371_src_write(es, ES_SMPREG_VOL_DAC1 + 1, 1 << 12); 52353413Sroger es1371_src_write(es, ES_SMPREG_VOL_DAC2, 1 << 12); 52453413Sroger es1371_src_write(es, ES_SMPREG_VOL_DAC2 + 1, 1 << 12); 52553413Sroger es1371_adc_rate (es, 22050, 1); 52654831Scg es1371_dac_rate (es, 22050, 1); 52754831Scg es1371_dac_rate (es, 22050, 2); 52853413Sroger /* WARNING: 52953413Sroger * enabling the sample rate converter without properly programming 53053413Sroger * its parameters causes the chip to lock up (the SRC busy bit will 53153413Sroger * be stuck high, and I've found no way to rectify this other than 53253413Sroger * power cycle) 53353413Sroger */ 53453413Sroger bus_space_write_4(es->st, es->sh, ES1371_REG_SMPRATE, 0); 53553413Sroger 53653413Sroger return (0); 53753413Sroger} 53853413Sroger 53954831Scgstatic void 54053413Srogeres1371_wrcodec(void *s, int addr, u_int32_t data) 54153413Sroger{ 54254831Scg int sl; 54354831Scg unsigned t, x; 54453413Sroger struct es_info *es = (struct es_info*)s; 54553413Sroger 54654831Scg if (debug > 0) printf("wrcodec addr 0x%x data 0x%x\n", addr, data); 54753413Sroger 54853413Sroger for (t = 0; t < 0x1000; t++) 54954831Scg if (!(bus_space_read_4(es->st, es->sh,(ES1371_REG_CODEC & CODEC_WIP)))) 55053413Sroger break; 55153413Sroger sl = spltty(); 55253413Sroger /* save the current state for later */ 55354831Scg x = bus_space_read_4(es->st, es->sh, ES1371_REG_SMPRATE); 55453413Sroger /* enable SRC state data in SRC mux */ 55553413Sroger bus_space_write_4(es->st, es->sh, ES1371_REG_SMPRATE, 55654831Scg (es1371_wait_src_ready(s) & 55754831Scg (ES1371_DIS_SRC | ES1371_DIS_P1 | ES1371_DIS_P2 | ES1371_DIS_R1))); 55853413Sroger /* wait for a SAFE time to write addr/data and then do it, dammit */ 55953413Sroger for (t = 0; t < 0x1000; t++) 56054831Scg if ((bus_space_read_4(es->st, es->sh, ES1371_REG_SMPRATE) & 0x00070000) == 0x00010000) 56154831Scg break; 56254831Scg 56354831Scg if (debug > 2) printf("one b_s_w: 0x%x 0x%x 0x%x\n", es->sh, ES1371_REG_CODEC, 56453413Sroger ((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) | 56553413Sroger ((data << CODEC_PODAT_SHIFT) & CODEC_PODAT_MASK)); 56654831Scg 56753413Sroger bus_space_write_4(es->st, es->sh,ES1371_REG_CODEC, 56853413Sroger ((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) | 56953413Sroger ((data << CODEC_PODAT_SHIFT) & CODEC_PODAT_MASK)); 57053413Sroger /* restore SRC reg */ 57153413Sroger es1371_wait_src_ready(s); 57254831Scg if (debug > 2) printf("two b_s_w: 0x%x 0x%x 0x%x\n", es->sh, ES1371_REG_SMPRATE, x); 57354831Scg bus_space_write_4(es->st, es->sh, ES1371_REG_SMPRATE, x); 57453413Sroger splx(sl); 57553413Sroger} 57653413Sroger 57754831Scgstatic u_int32_t 57854831Scges1371_rdcodec(void *s, int addr) 57953413Sroger{ 58054831Scg int sl; 58154831Scg unsigned t, x; 58254831Scg struct es_info *es = (struct es_info *)s; 58353413Sroger 58454831Scg if (debug > 0) printf("rdcodec addr 0x%x ... ", addr); 58553413Sroger 58654831Scg for (t = 0; t < 0x1000; t++) 58754831Scg if (!(x = bus_space_read_4(es->st, es->sh, ES1371_REG_CODEC) & CODEC_WIP)) 58854831Scg break; 58954831Scg if (debug > 0) printf("loop 1 t 0x%x x 0x%x ", t, x); 59053413Sroger 59154831Scg sl = spltty(); 59253413Sroger 59354831Scg /* save the current state for later */ 59454831Scg x = bus_space_read_4(es->st, es->sh, ES1371_REG_SMPRATE); 59554831Scg /* enable SRC state data in SRC mux */ 59654831Scg bus_space_write_4(es->st, es->sh, ES1371_REG_SMPRATE, 59754831Scg (es1371_wait_src_ready(s) & 59854831Scg (ES1371_DIS_SRC | ES1371_DIS_P1 | ES1371_DIS_P2 | ES1371_DIS_R1))); 59954831Scg /* wait for a SAFE time to write addr/data and then do it, dammit */ 60054831Scg for (t = 0; t < 0x5000; t++) 60154831Scg if ((x = bus_space_read_4(es->st, es->sh, ES1371_REG_SMPRATE) & 0x00070000) == 0x00010000) 60254831Scg break; 60354831Scg if (debug > 0) printf("loop 2 t 0x%x x 0x%x ", t, x); 60454831Scg bus_space_write_4(es->st, es->sh, ES1371_REG_CODEC, 60554831Scg ((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) | CODEC_PORD); 60653413Sroger 60754831Scg /* restore SRC reg */ 60854831Scg es1371_wait_src_ready(s); 60954831Scg bus_space_write_4(es->st, es->sh, ES1371_REG_SMPRATE, x); 61053413Sroger 61154831Scg splx(sl); 61253413Sroger 61354831Scg /* now wait for the stinkin' data (RDY) */ 61454831Scg for (t = 0; t < 0x1000; t++) 61554831Scg if ((x = bus_space_read_4(es->st, es->sh, ES1371_REG_CODEC)) & CODEC_RDY) 61654831Scg break; 61754831Scg if (debug > 0) printf("loop 3 t 0x%x 0x%x ret 0x%x\n", t, x, ((x & CODEC_PIDAT_MASK) >> CODEC_PIDAT_SHIFT)); 61854831Scg return ((x & CODEC_PIDAT_MASK) >> CODEC_PIDAT_SHIFT); 61953413Sroger} 62053413Sroger 62153413Srogerstatic u_int 62255209Scges1371_src_read(struct es_info *es, u_short reg) 62354831Scg{ 62454831Scg unsigned int r; 62553413Sroger 62654831Scg r = es1371_wait_src_ready(es) & 62754831Scg (ES1371_DIS_SRC | ES1371_DIS_P1 | ES1371_DIS_P2 | ES1371_DIS_R1); 62854831Scg r |= ES1371_SRC_RAM_ADDRO(reg); 62954831Scg bus_space_write_4(es->st, es->sh, ES1371_REG_SMPRATE,r); 63054831Scg return ES1371_SRC_RAM_DATAI(es1371_wait_src_ready(es)); 63153413Sroger} 63253413Sroger 63353413Srogerstatic void 63455209Scges1371_src_write(struct es_info *es, u_short reg, u_short data){ 63553413Sroger u_int r; 63653413Sroger 63753413Sroger r = es1371_wait_src_ready(es) & 63854831Scg (ES1371_DIS_SRC | ES1371_DIS_P1 | ES1371_DIS_P2 | ES1371_DIS_R1); 63953413Sroger r |= ES1371_SRC_RAM_ADDRO(reg) | ES1371_SRC_RAM_DATAO(data); 64053413Sroger /* printf("es1371_src_write 0x%x 0x%x\n",ES1371_REG_SMPRATE,r | ES1371_SRC_RAM_WE); */ 64154831Scg bus_space_write_4(es->st, es->sh, ES1371_REG_SMPRATE, r | ES1371_SRC_RAM_WE); 64253413Sroger} 64353413Sroger 64454831Scgstatic u_int 64555209Scges1371_adc_rate(struct es_info *es, u_int rate, int set) 64654831Scg{ 64754831Scg u_int n, truncm, freq, result; 64854831Scg 64954831Scg if (rate > 48000) rate = 48000; 65054831Scg if (rate < 4000) rate = 4000; 65154831Scg n = rate / 3000; 65254831Scg if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9))) 65354831Scg n--; 65454831Scg truncm = (21 * n - 1) | 1; 65554831Scg freq = ((48000UL << 15) / rate) * n; 65654831Scg result = (48000UL << 15) / (freq / n); 65754831Scg if (set) { 65854831Scg if (rate >= 24000) { 65954831Scg if (truncm > 239) truncm = 239; 66054831Scg es1371_src_write(es, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N, 66154831Scg (((239 - truncm) >> 1) << 9) | (n << 4)); 66254831Scg } else { 66354831Scg if (truncm > 119) truncm = 119; 66454831Scg es1371_src_write(es, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N, 66554831Scg 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4)); 66654831Scg } 66754831Scg es1371_src_write(es, ES_SMPREG_ADC + ES_SMPREG_INT_REGS, 66854831Scg (es1371_src_read(es, ES_SMPREG_ADC + ES_SMPREG_INT_REGS) & 66954831Scg 0x00ff) | ((freq >> 5) & 0xfc00)); 67054831Scg es1371_src_write(es, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); 67154831Scg es1371_src_write(es, ES_SMPREG_VOL_ADC, n << 8); 67254831Scg es1371_src_write(es, ES_SMPREG_VOL_ADC + 1, n << 8); 67353413Sroger } 67453413Sroger return result; 67553413Sroger} 67653413Sroger 67753413Srogerstatic u_int 67855209Scges1371_dac_rate(struct es_info *es, u_int rate, int set) 67954831Scg{ 68054831Scg u_int freq, r, result, dac, dis; 68153413Sroger 68254831Scg if (rate > 48000) rate = 48000; 68354831Scg if (rate < 4000) rate = 4000; 68454831Scg freq = (rate << 15) / 3000; 68554831Scg result = (freq * 3000) >> 15; 68654831Scg if (set) { 68754831Scg dac = (set == 1)? ES_SMPREG_DAC1 : ES_SMPREG_DAC2; 68854831Scg dis = (set == 1)? ES1371_DIS_P2 : ES1371_DIS_P1; 68954831Scg 69054831Scg r = (es1371_wait_src_ready(es) & (ES1371_DIS_SRC | ES1371_DIS_P1 | ES1371_DIS_P2 | ES1371_DIS_R1)); 69154831Scg bus_space_write_4(es->st, es->sh, ES1371_REG_SMPRATE, r); 69254831Scg es1371_src_write(es, dac + ES_SMPREG_INT_REGS, 69354831Scg (es1371_src_read(es, dac + ES_SMPREG_INT_REGS) & 0x00ff) | ((freq >> 5) & 0xfc00)); 69454831Scg es1371_src_write(es, dac + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); 69554831Scg r = (es1371_wait_src_ready(es) & (ES1371_DIS_SRC | dis | ES1371_DIS_R1)); 69654831Scg bus_space_write_4(es->st, es->sh, ES1371_REG_SMPRATE, r); 69754831Scg } 69854831Scg return result; 69953413Sroger} 70053413Sroger 70153413Srogerstatic u_int 70255209Scges1371_wait_src_ready(struct es_info *es) 70354831Scg{ 70454831Scg u_int t, r; 70553413Sroger 70654831Scg for (t = 0; t < 500; t++) { 70754831Scg if (!((r = bus_space_read_4(es->st, es->sh, ES1371_REG_SMPRATE)) & ES1371_SRC_RAM_BUSY)) 70854831Scg return r; 70954831Scg DELAY(1000); 71054831Scg } 71154831Scg printf("es1371: wait src ready timeout 0x%x [0x%x]\n", ES1371_REG_SMPRATE, r); 71254831Scg return 0; 71353413Sroger} 71453413Sroger 71550724Scg/* -------------------------------------------------------------------- */ 71650724Scg 71750724Scg/* 71850724Scg * Probe and attach the card 71950724Scg */ 72050724Scg 72150724Scgstatic int 72250724Scges_pci_probe(device_t dev) 72350724Scg{ 72450724Scg if (pci_get_devid(dev) == ES1370_PCI_ID) { 72550724Scg device_set_desc(dev, "AudioPCI ES1370"); 72650724Scg return 0; 72756154Speter } else if (pci_get_devid(dev) == ES1371_PCI_ID || 72862412Sroberto pci_get_devid(dev) == ES1371_PCI_ID2 || 72962412Sroberto pci_get_devid(dev) == ES1371_PCI_ID3) { 73053413Sroger device_set_desc(dev, "AudioPCI ES1371"); 73153413Sroger return 0; 73250724Scg } 73350724Scg return ENXIO; 73450724Scg} 73550724Scg 73650724Scgstatic int 73750724Scges_pci_attach(device_t dev) 73850724Scg{ 73950724Scg snddev_info *d; 74050724Scg u_int32_t data; 74150724Scg struct es_info *es = 0; 74250724Scg int type = 0; 74350724Scg int regid; 74450724Scg struct resource *reg = 0; 74550724Scg int mapped; 74650724Scg int irqid; 74750724Scg struct resource *irq = 0; 74850724Scg void *ih = 0; 74950724Scg char status[SND_STATUSLEN]; 75053413Sroger struct ac97_info *codec; 75154831Scg pcm_channel *ct = NULL; 75250724Scg 75350724Scg d = device_get_softc(dev); 75450724Scg if ((es = malloc(sizeof *es, M_DEVBUF, M_NOWAIT)) == NULL) { 75550724Scg device_printf(dev, "cannot allocate softc\n"); 75650724Scg return ENXIO; 75750724Scg } 75850724Scg bzero(es, sizeof *es); 75950724Scg 76059019Scg es->dev = dev; 76150724Scg mapped = 0; 76250724Scg data = pci_read_config(dev, PCIR_COMMAND, 2); 76355426Scg data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 76455426Scg pci_write_config(dev, PCIR_COMMAND, data, 2); 76555426Scg data = pci_read_config(dev, PCIR_COMMAND, 2); 76650724Scg if (mapped == 0 && (data & PCIM_CMD_MEMEN)) { 76750724Scg regid = MEM_MAP_REG; 76850724Scg type = SYS_RES_MEMORY; 76950724Scg reg = bus_alloc_resource(dev, type, ®id, 77050724Scg 0, ~0, 1, RF_ACTIVE); 77150724Scg if (reg) { 77250724Scg es->st = rman_get_bustag(reg); 77350724Scg es->sh = rman_get_bushandle(reg); 77450724Scg mapped++; 77550724Scg } 77650724Scg } 77750724Scg if (mapped == 0 && (data & PCIM_CMD_PORTEN)) { 77861031Speter regid = PCIR_MAPS; 77950724Scg type = SYS_RES_IOPORT; 78050724Scg reg = bus_alloc_resource(dev, type, ®id, 78150724Scg 0, ~0, 1, RF_ACTIVE); 78250724Scg if (reg) { 78350724Scg es->st = rman_get_bustag(reg); 78450724Scg es->sh = rman_get_bushandle(reg); 78550724Scg mapped++; 78650724Scg } 78750724Scg } 78850724Scg if (mapped == 0) { 78950724Scg device_printf(dev, "unable to map register space\n"); 79050724Scg goto bad; 79150724Scg } 79254831Scg 79356154Speter if (pci_get_devid(dev) == ES1371_PCI_ID || 79462412Sroberto pci_get_devid(dev) == ES1371_PCI_ID2 || 79562412Sroberto pci_get_devid(dev) == ES1371_PCI_ID3) { 79655209Scg if(-1 == es1371_init(es, pci_get_revid(dev))) { 79754831Scg device_printf(dev, "unable to initialize the card\n"); 79854831Scg goto bad; 79954831Scg } 80058384Scg codec = ac97_create(dev, es, NULL, es1371_rdcodec, es1371_wrcodec); 80154831Scg if (codec == NULL) goto bad; 80254831Scg /* our init routine does everything for us */ 80354831Scg /* set to NULL; flag mixer_init not to run the ac97_init */ 80454831Scg /* ac97_mixer.init = NULL; */ 80558905Scg if (mixer_init(d, &ac97_mixer, codec) == -1) goto bad; 80654831Scg ct = &es1371_chantemplate; 80754831Scg } else if (pci_get_devid(dev) == ES1370_PCI_ID) { 80854831Scg if (-1 == es1370_init(es)) { 80954831Scg device_printf(dev, "unable to initialize the card\n"); 81054831Scg goto bad; 81154831Scg } 81254831Scg mixer_init(d, &es1370_mixer, es); 81354831Scg ct = &es1370_chantemplate; 81454831Scg } else goto bad; 81550724Scg 81650724Scg irqid = 0; 81750724Scg irq = bus_alloc_resource(dev, SYS_RES_IRQ, &irqid, 81852046Simp 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 81950724Scg if (!irq 82050724Scg || bus_setup_intr(dev, irq, INTR_TYPE_TTY, es_intr, es, &ih)) { 82150724Scg device_printf(dev, "unable to map interrupt\n"); 82250724Scg goto bad; 82350724Scg } 82450724Scg 82550724Scg if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 82650724Scg /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 82750724Scg /*highaddr*/BUS_SPACE_MAXADDR, 82850724Scg /*filter*/NULL, /*filterarg*/NULL, 82950724Scg /*maxsize*/ES_BUFFSIZE, /*nsegments*/1, /*maxsegz*/0x3ffff, 83050724Scg /*flags*/0, &es->parent_dmat) != 0) { 83150724Scg device_printf(dev, "unable to create dma tag\n"); 83250724Scg goto bad; 83350724Scg } 83450724Scg 83550724Scg snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld", 83650724Scg (type == SYS_RES_IOPORT)? "io" : "memory", 83750724Scg rman_get_start(reg), rman_get_start(irq)); 83850724Scg 83950724Scg if (pcm_register(dev, es, 1, 1)) goto bad; 84054831Scg pcm_addchan(dev, PCMDIR_REC, ct, es); 84154831Scg pcm_addchan(dev, PCMDIR_PLAY, ct, es); 84250724Scg pcm_setstatus(dev, status); 84350724Scg 84450724Scg return 0; 84550724Scg 84650724Scg bad: 84750724Scg if (es) free(es, M_DEVBUF); 84850724Scg if (reg) bus_release_resource(dev, type, regid, reg); 84950724Scg if (ih) bus_teardown_intr(dev, irq, ih); 85050724Scg if (irq) bus_release_resource(dev, SYS_RES_IRQ, irqid, irq); 85150724Scg return ENXIO; 85250724Scg} 85350724Scg 85450724Scgstatic device_method_t es_methods[] = { 85550724Scg /* Device interface */ 85650724Scg DEVMETHOD(device_probe, es_pci_probe), 85750724Scg DEVMETHOD(device_attach, es_pci_attach), 85850724Scg 85950724Scg { 0, 0 } 86050724Scg}; 86150724Scg 86250724Scgstatic driver_t es_driver = { 86350724Scg "pcm", 86450724Scg es_methods, 86550724Scg sizeof(snddev_info), 86650724Scg}; 86750724Scg 86850724Scgstatic devclass_t pcm_devclass; 86950724Scg 87062483ScgDRIVER_MODULE(snd_es137x, pci, es_driver, pcm_devclass, 0, 0); 87162483ScgMODULE_DEPEND(snd_es137x, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 87262483ScgMODULE_VERSION(snd_es137x, 1); 873