153553Stanimura/*- 253553Stanimura * Copyright (c) 1999 Seigo Tanimura 353553Stanimura * All rights reserved. 453553Stanimura * 554377Stanimura * Portions of this source are based on hwdefs.h in cwcealdr1.zip, the 654377Stanimura * sample source by Crystal Semiconductor. 754377Stanimura * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 854377Stanimura * 953553Stanimura * Redistribution and use in source and binary forms, with or without 1053553Stanimura * modification, are permitted provided that the following conditions 1153553Stanimura * are met: 1253553Stanimura * 1. Redistributions of source code must retain the above copyright 1353553Stanimura * notice, this list of conditions and the following disclaimer. 1453553Stanimura * 2. Redistributions in binary form must reproduce the above copyright 1553553Stanimura * notice, this list of conditions and the following disclaimer in the 1653553Stanimura * documentation and/or other materials provided with the distribution. 1753553Stanimura * 1853553Stanimura * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1953553Stanimura * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2053553Stanimura * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2153553Stanimura * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2253553Stanimura * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2353553Stanimura * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2453553Stanimura * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2553553Stanimura * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2653553Stanimura * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2753553Stanimura * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2853553Stanimura * SUCH DAMAGE. 2953553Stanimura * 3053553Stanimura * $FreeBSD: releng/11.0/sys/dev/sound/pci/csareg.h 230897 2012-02-01 21:38:01Z pfg $ 3153553Stanimura */ 3253553Stanimura 3353553Stanimura#ifndef _CSA_REG_H 3453553Stanimura#define _CSA_REG_H 3553553Stanimura 3653553Stanimura/* 3753553Stanimura * The following constats are orginally in the sample by Crystal Semiconductor. 3853553Stanimura * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 3953553Stanimura */ 4053553Stanimura 4153553Stanimura/***************************************************************************** 4253553Stanimura * 4353553Stanimura * The following define the offsets of the registers accessed via base address 4453553Stanimura * register zero on the CS461x part. 4553553Stanimura * 4653553Stanimura *****************************************************************************/ 4753553Stanimura#define BA0_HISR 0x00000000L 4853553Stanimura#define BA0_HSR0 0x00000004L 4953553Stanimura#define BA0_HICR 0x00000008L 5053553Stanimura#define BA0_DMSR 0x00000100L 5153553Stanimura#define BA0_HSAR 0x00000110L 5253553Stanimura#define BA0_HDAR 0x00000114L 5353553Stanimura#define BA0_HDMR 0x00000118L 5453553Stanimura#define BA0_HDCR 0x0000011CL 5553553Stanimura#define BA0_PFMC 0x00000200L 5653553Stanimura#define BA0_PFCV1 0x00000204L 5753553Stanimura#define BA0_PFCV2 0x00000208L 5853553Stanimura#define BA0_PCICFG00 0x00000300L 5953553Stanimura#define BA0_PCICFG04 0x00000304L 6053553Stanimura#define BA0_PCICFG08 0x00000308L 6153553Stanimura#define BA0_PCICFG0C 0x0000030CL 6253553Stanimura#define BA0_PCICFG10 0x00000310L 6353553Stanimura#define BA0_PCICFG14 0x00000314L 6453553Stanimura#define BA0_PCICFG18 0x00000318L 6553553Stanimura#define BA0_PCICFG1C 0x0000031CL 6653553Stanimura#define BA0_PCICFG20 0x00000320L 6753553Stanimura#define BA0_PCICFG24 0x00000324L 6853553Stanimura#define BA0_PCICFG28 0x00000328L 6953553Stanimura#define BA0_PCICFG2C 0x0000032CL 7053553Stanimura#define BA0_PCICFG30 0x00000330L 7153553Stanimura#define BA0_PCICFG34 0x00000334L 7253553Stanimura#define BA0_PCICFG38 0x00000338L 7353553Stanimura#define BA0_PCICFG3C 0x0000033CL 7453553Stanimura#define BA0_CLKCR1 0x00000400L 7553553Stanimura#define BA0_CLKCR2 0x00000404L 7653553Stanimura#define BA0_PLLM 0x00000408L 7753553Stanimura#define BA0_PLLCC 0x0000040CL 7853553Stanimura#define BA0_FRR 0x00000410L 7953553Stanimura#define BA0_CFL1 0x00000414L 8053553Stanimura#define BA0_CFL2 0x00000418L 8153553Stanimura#define BA0_SERMC1 0x00000420L 8253553Stanimura#define BA0_SERMC2 0x00000424L 8353553Stanimura#define BA0_SERC1 0x00000428L 8453553Stanimura#define BA0_SERC2 0x0000042CL 8553553Stanimura#define BA0_SERC3 0x00000430L 8653553Stanimura#define BA0_SERC4 0x00000434L 8753553Stanimura#define BA0_SERC5 0x00000438L 8853553Stanimura#define BA0_SERBSP 0x0000043CL 8953553Stanimura#define BA0_SERBST 0x00000440L 9053553Stanimura#define BA0_SERBCM 0x00000444L 9153553Stanimura#define BA0_SERBAD 0x00000448L 9253553Stanimura#define BA0_SERBCF 0x0000044CL 9353553Stanimura#define BA0_SERBWP 0x00000450L 9453553Stanimura#define BA0_SERBRP 0x00000454L 9553553Stanimura#ifndef NO_CS4612 9653553Stanimura#define BA0_ASER_FADDR 0x00000458L 9753553Stanimura#endif 9853553Stanimura#define BA0_ACCTL 0x00000460L 9953553Stanimura#define BA0_ACSTS 0x00000464L 10053553Stanimura#define BA0_ACOSV 0x00000468L 10153553Stanimura#define BA0_ACCAD 0x0000046CL 10253553Stanimura#define BA0_ACCDA 0x00000470L 10353553Stanimura#define BA0_ACISV 0x00000474L 10453553Stanimura#define BA0_ACSAD 0x00000478L 10553553Stanimura#define BA0_ACSDA 0x0000047CL 10653553Stanimura#define BA0_JSPT 0x00000480L 10753553Stanimura#define BA0_JSCTL 0x00000484L 10853553Stanimura#define BA0_JSC1 0x00000488L 10953553Stanimura#define BA0_JSC2 0x0000048CL 11053553Stanimura#define BA0_MIDCR 0x00000490L 11153553Stanimura#define BA0_MIDSR 0x00000494L 11253553Stanimura#define BA0_MIDWP 0x00000498L 11353553Stanimura#define BA0_MIDRP 0x0000049CL 11453553Stanimura#define BA0_JSIO 0x000004A0L 11553553Stanimura#ifndef NO_CS4612 11653553Stanimura#define BA0_ASER_MASTER 0x000004A4L 11753553Stanimura#endif 11853553Stanimura#define BA0_CFGI 0x000004B0L 11953553Stanimura#define BA0_SSVID 0x000004B4L 12053553Stanimura#define BA0_GPIOR 0x000004B8L 12153553Stanimura#ifndef NO_CS4612 12253553Stanimura#define BA0_EGPIODR 0x000004BCL 12353553Stanimura#define BA0_EGPIOPTR 0x000004C0L 12453553Stanimura#define BA0_EGPIOTR 0x000004C4L 12553553Stanimura#define BA0_EGPIOWR 0x000004C8L 12653553Stanimura#define BA0_EGPIOSR 0x000004CCL 12753553Stanimura#define BA0_SERC6 0x000004D0L 12853553Stanimura#define BA0_SERC7 0x000004D4L 12953553Stanimura#define BA0_SERACC 0x000004D8L 13053553Stanimura#define BA0_ACCTL2 0x000004E0L 13153553Stanimura#define BA0_ACSTS2 0x000004E4L 13253553Stanimura#define BA0_ACOSV2 0x000004E8L 13353553Stanimura#define BA0_ACCAD2 0x000004ECL 13453553Stanimura#define BA0_ACCDA2 0x000004F0L 13553553Stanimura#define BA0_ACISV2 0x000004F4L 13653553Stanimura#define BA0_ACSAD2 0x000004F8L 13753553Stanimura#define BA0_ACSDA2 0x000004FCL 13853553Stanimura#define BA0_IOTAC0 0x00000500L 13953553Stanimura#define BA0_IOTAC1 0x00000504L 14053553Stanimura#define BA0_IOTAC2 0x00000508L 14153553Stanimura#define BA0_IOTAC3 0x0000050CL 14253553Stanimura#define BA0_IOTAC4 0x00000510L 14353553Stanimura#define BA0_IOTAC5 0x00000514L 14453553Stanimura#define BA0_IOTAC6 0x00000518L 14553553Stanimura#define BA0_IOTAC7 0x0000051CL 14653553Stanimura#define BA0_IOTAC8 0x00000520L 14753553Stanimura#define BA0_IOTAC9 0x00000524L 14853553Stanimura#define BA0_IOTAC10 0x00000528L 14953553Stanimura#define BA0_IOTAC11 0x0000052CL 15053553Stanimura#define BA0_IOTFR0 0x00000540L 15153553Stanimura#define BA0_IOTFR1 0x00000544L 15253553Stanimura#define BA0_IOTFR2 0x00000548L 15353553Stanimura#define BA0_IOTFR3 0x0000054CL 15453553Stanimura#define BA0_IOTFR4 0x00000550L 15553553Stanimura#define BA0_IOTFR5 0x00000554L 15653553Stanimura#define BA0_IOTFR6 0x00000558L 15753553Stanimura#define BA0_IOTFR7 0x0000055CL 15853553Stanimura#define BA0_IOTFIFO 0x00000580L 15953553Stanimura#define BA0_IOTRRD 0x00000584L 16053553Stanimura#define BA0_IOTFP 0x00000588L 16153553Stanimura#define BA0_IOTCR 0x0000058CL 16253553Stanimura#define BA0_DPCID 0x00000590L 16353553Stanimura#define BA0_DPCIA 0x00000594L 16453553Stanimura#define BA0_DPCIC 0x00000598L 16553553Stanimura#define BA0_PCPCIR 0x00000600L 16653553Stanimura#define BA0_PCPCIG 0x00000604L 16753553Stanimura#define BA0_PCPCIEN 0x00000608L 16853553Stanimura#define BA0_EPCIPMC 0x00000610L 16953553Stanimura#endif 17053553Stanimura 17153553Stanimura/***************************************************************************** 17253553Stanimura * 17353553Stanimura * The following define the offsets of the AC97 shadow registers, which appear 17453553Stanimura * as a virtual extension to the base address register zero memory range. 17553553Stanimura * 17653553Stanimura *****************************************************************************/ 17753553Stanimura#define BA0_AC97_RESET 0x00001000L 17853553Stanimura#define BA0_AC97_MASTER_VOLUME 0x00001002L 17953553Stanimura#define BA0_AC97_HEADPHONE_VOLUME 0x00001004L 18053553Stanimura#define BA0_AC97_MASTER_VOLUME_MONO 0x00001006L 18153553Stanimura#define BA0_AC97_MASTER_TONE 0x00001008L 18253553Stanimura#define BA0_AC97_PC_BEEP_VOLUME 0x0000100AL 18353553Stanimura#define BA0_AC97_PHONE_VOLUME 0x0000100CL 18453553Stanimura#define BA0_AC97_MIC_VOLUME 0x0000100EL 18553553Stanimura#define BA0_AC97_LINE_IN_VOLUME 0x00001010L 18653553Stanimura#define BA0_AC97_CD_VOLUME 0x00001012L 18753553Stanimura#define BA0_AC97_VIDEO_VOLUME 0x00001014L 18853553Stanimura#define BA0_AC97_AUX_VOLUME 0x00001016L 18953553Stanimura#define BA0_AC97_PCM_OUT_VOLUME 0x00001018L 19053553Stanimura#define BA0_AC97_RECORD_SELECT 0x0000101AL 19153553Stanimura#define BA0_AC97_RECORD_GAIN 0x0000101CL 19253553Stanimura#define BA0_AC97_RECORD_GAIN_MIC 0x0000101EL 19353553Stanimura#define BA0_AC97_GENERAL_PURPOSE 0x00001020L 19453553Stanimura#define BA0_AC97_3D_CONTROL 0x00001022L 19553553Stanimura#define BA0_AC97_MODEM_RATE 0x00001024L 19653553Stanimura#define BA0_AC97_POWERDOWN 0x00001026L 19753553Stanimura#define BA0_AC97_RESERVED_28 0x00001028L 19853553Stanimura#define BA0_AC97_RESERVED_2A 0x0000102AL 19953553Stanimura#define BA0_AC97_RESERVED_2C 0x0000102CL 20053553Stanimura#define BA0_AC97_RESERVED_2E 0x0000102EL 20153553Stanimura#define BA0_AC97_RESERVED_30 0x00001030L 20253553Stanimura#define BA0_AC97_RESERVED_32 0x00001032L 20353553Stanimura#define BA0_AC97_RESERVED_34 0x00001034L 20453553Stanimura#define BA0_AC97_RESERVED_36 0x00001036L 20553553Stanimura#define BA0_AC97_RESERVED_38 0x00001038L 20653553Stanimura#define BA0_AC97_RESERVED_3A 0x0000103AL 20753553Stanimura#define BA0_AC97_RESERVED_3C 0x0000103CL 20853553Stanimura#define BA0_AC97_RESERVED_3E 0x0000103EL 20953553Stanimura#define BA0_AC97_RESERVED_40 0x00001040L 21053553Stanimura#define BA0_AC97_RESERVED_42 0x00001042L 21153553Stanimura#define BA0_AC97_RESERVED_44 0x00001044L 21253553Stanimura#define BA0_AC97_RESERVED_46 0x00001046L 21353553Stanimura#define BA0_AC97_RESERVED_48 0x00001048L 21453553Stanimura#define BA0_AC97_RESERVED_4A 0x0000104AL 21553553Stanimura#define BA0_AC97_RESERVED_4C 0x0000104CL 21653553Stanimura#define BA0_AC97_RESERVED_4E 0x0000104EL 21753553Stanimura#define BA0_AC97_RESERVED_50 0x00001050L 21853553Stanimura#define BA0_AC97_RESERVED_52 0x00001052L 21953553Stanimura#define BA0_AC97_RESERVED_54 0x00001054L 22053553Stanimura#define BA0_AC97_RESERVED_56 0x00001056L 22153553Stanimura#define BA0_AC97_RESERVED_58 0x00001058L 22253553Stanimura#define BA0_AC97_VENDOR_RESERVED_5A 0x0000105AL 22353553Stanimura#define BA0_AC97_VENDOR_RESERVED_5C 0x0000105CL 22453553Stanimura#define BA0_AC97_VENDOR_RESERVED_5E 0x0000105EL 22553553Stanimura#define BA0_AC97_VENDOR_RESERVED_60 0x00001060L 22653553Stanimura#define BA0_AC97_VENDOR_RESERVED_62 0x00001062L 22753553Stanimura#define BA0_AC97_VENDOR_RESERVED_64 0x00001064L 22853553Stanimura#define BA0_AC97_VENDOR_RESERVED_66 0x00001066L 22953553Stanimura#define BA0_AC97_VENDOR_RESERVED_68 0x00001068L 23053553Stanimura#define BA0_AC97_VENDOR_RESERVED_6A 0x0000106AL 23153553Stanimura#define BA0_AC97_VENDOR_RESERVED_6C 0x0000106CL 23253553Stanimura#define BA0_AC97_VENDOR_RESERVED_6E 0x0000106EL 23353553Stanimura#define BA0_AC97_VENDOR_RESERVED_70 0x00001070L 23453553Stanimura#define BA0_AC97_VENDOR_RESERVED_72 0x00001072L 23553553Stanimura#define BA0_AC97_VENDOR_RESERVED_74 0x00001074L 23653553Stanimura#define BA0_AC97_VENDOR_RESERVED_76 0x00001076L 23753553Stanimura#define BA0_AC97_VENDOR_RESERVED_78 0x00001078L 23853553Stanimura#define BA0_AC97_VENDOR_RESERVED_7A 0x0000107AL 23953553Stanimura#define BA0_AC97_VENDOR_ID1 0x0000107CL 24053553Stanimura#define BA0_AC97_VENDOR_ID2 0x0000107EL 24153553Stanimura 24253553Stanimura/***************************************************************************** 24353553Stanimura * 24453553Stanimura * The following define the offsets of the registers and memories accessed via 24553553Stanimura * base address register one on the CS461x part. 24653553Stanimura * 24753553Stanimura *****************************************************************************/ 24853553Stanimura#define BA1_SP_DMEM0 0x00000000L 24953553Stanimura#define BA1_SP_DMEM1 0x00010000L 25053553Stanimura#define BA1_SP_PMEM 0x00020000L 25153553Stanimura#define BA1_SPCR 0x00030000L 25253553Stanimura#define BA1_DREG 0x00030004L 25353553Stanimura#define BA1_DSRWP 0x00030008L 25453553Stanimura#define BA1_TWPR 0x0003000CL 25553553Stanimura#define BA1_SPWR 0x00030010L 25653553Stanimura#define BA1_SPIR 0x00030014L 25753553Stanimura#define BA1_FGR1 0x00030020L 25853553Stanimura#define BA1_SPCS 0x00030028L 25953553Stanimura#define BA1_SDSR 0x0003002CL 26053553Stanimura#define BA1_FRMT 0x00030030L 26153553Stanimura#define BA1_FRCC 0x00030034L 26253553Stanimura#define BA1_FRSC 0x00030038L 26353553Stanimura#define BA1_OMNI_MEM 0x000E0000L 26453553Stanimura 26553553Stanimura/***************************************************************************** 26653553Stanimura * 26753553Stanimura * The following defines are for the flags in the PCI interrupt register. 26853553Stanimura * 26953553Stanimura *****************************************************************************/ 27053553Stanimura#define PI_LINE_MASK 0x000000FFL 27153553Stanimura#define PI_PIN_MASK 0x0000FF00L 27253553Stanimura#define PI_MIN_GRANT_MASK 0x00FF0000L 27353553Stanimura#define PI_MAX_LATENCY_MASK 0xFF000000L 27453553Stanimura#define PI_LINE_SHIFT 0L 27553553Stanimura#define PI_PIN_SHIFT 8L 27653553Stanimura#define PI_MIN_GRANT_SHIFT 16L 27753553Stanimura#define PI_MAX_LATENCY_SHIFT 24L 27853553Stanimura 27953553Stanimura/***************************************************************************** 28053553Stanimura * 28153553Stanimura * The following defines are for the flags in the host interrupt status 28253553Stanimura * register. 28353553Stanimura * 28453553Stanimura *****************************************************************************/ 28553553Stanimura#define HISR_VC_MASK 0x0000FFFFL 28653553Stanimura#define HISR_VC0 0x00000001L 28753553Stanimura#define HISR_VC1 0x00000002L 28853553Stanimura#define HISR_VC2 0x00000004L 28953553Stanimura#define HISR_VC3 0x00000008L 29053553Stanimura#define HISR_VC4 0x00000010L 29153553Stanimura#define HISR_VC5 0x00000020L 29253553Stanimura#define HISR_VC6 0x00000040L 29353553Stanimura#define HISR_VC7 0x00000080L 29453553Stanimura#define HISR_VC8 0x00000100L 29553553Stanimura#define HISR_VC9 0x00000200L 29653553Stanimura#define HISR_VC10 0x00000400L 29753553Stanimura#define HISR_VC11 0x00000800L 29853553Stanimura#define HISR_VC12 0x00001000L 29953553Stanimura#define HISR_VC13 0x00002000L 30053553Stanimura#define HISR_VC14 0x00004000L 30153553Stanimura#define HISR_VC15 0x00008000L 30253553Stanimura#define HISR_INT0 0x00010000L 30353553Stanimura#define HISR_INT1 0x00020000L 30453553Stanimura#define HISR_DMAI 0x00040000L 30553553Stanimura#define HISR_FROVR 0x00080000L 30653553Stanimura#define HISR_MIDI 0x00100000L 30753553Stanimura#ifdef NO_CS4612 30853553Stanimura#define HISR_RESERVED 0x0FE00000L 30953553Stanimura#else 31053553Stanimura#define HISR_SBINT 0x00200000L 31153553Stanimura#define HISR_RESERVED 0x0FC00000L 31253553Stanimura#endif 31353553Stanimura#define HISR_H0P 0x40000000L 31453553Stanimura#define HISR_INTENA 0x80000000L 31553553Stanimura 31653553Stanimura/***************************************************************************** 31753553Stanimura * 31853553Stanimura * The following defines are for the flags in the host signal register 0. 31953553Stanimura * 32053553Stanimura *****************************************************************************/ 32153553Stanimura#define HSR0_VC_MASK 0xFFFFFFFFL 32253553Stanimura#define HSR0_VC16 0x00000001L 32353553Stanimura#define HSR0_VC17 0x00000002L 32453553Stanimura#define HSR0_VC18 0x00000004L 32553553Stanimura#define HSR0_VC19 0x00000008L 32653553Stanimura#define HSR0_VC20 0x00000010L 32753553Stanimura#define HSR0_VC21 0x00000020L 32853553Stanimura#define HSR0_VC22 0x00000040L 32953553Stanimura#define HSR0_VC23 0x00000080L 33053553Stanimura#define HSR0_VC24 0x00000100L 33153553Stanimura#define HSR0_VC25 0x00000200L 33253553Stanimura#define HSR0_VC26 0x00000400L 33353553Stanimura#define HSR0_VC27 0x00000800L 33453553Stanimura#define HSR0_VC28 0x00001000L 33553553Stanimura#define HSR0_VC29 0x00002000L 33653553Stanimura#define HSR0_VC30 0x00004000L 33753553Stanimura#define HSR0_VC31 0x00008000L 33853553Stanimura#define HSR0_VC32 0x00010000L 33953553Stanimura#define HSR0_VC33 0x00020000L 34053553Stanimura#define HSR0_VC34 0x00040000L 34153553Stanimura#define HSR0_VC35 0x00080000L 34253553Stanimura#define HSR0_VC36 0x00100000L 34353553Stanimura#define HSR0_VC37 0x00200000L 34453553Stanimura#define HSR0_VC38 0x00400000L 34553553Stanimura#define HSR0_VC39 0x00800000L 34653553Stanimura#define HSR0_VC40 0x01000000L 34753553Stanimura#define HSR0_VC41 0x02000000L 34853553Stanimura#define HSR0_VC42 0x04000000L 34953553Stanimura#define HSR0_VC43 0x08000000L 35053553Stanimura#define HSR0_VC44 0x10000000L 35153553Stanimura#define HSR0_VC45 0x20000000L 35253553Stanimura#define HSR0_VC46 0x40000000L 35353553Stanimura#define HSR0_VC47 0x80000000L 35453553Stanimura 35553553Stanimura/***************************************************************************** 35653553Stanimura * 35753553Stanimura * The following defines are for the flags in the host interrupt control 35853553Stanimura * register. 35953553Stanimura * 36053553Stanimura *****************************************************************************/ 36153553Stanimura#define HICR_IEV 0x00000001L 36253553Stanimura#define HICR_CHGM 0x00000002L 36353553Stanimura 36453553Stanimura/***************************************************************************** 36553553Stanimura * 36653553Stanimura * The following defines are for the flags in the DMA status register. 36753553Stanimura * 36853553Stanimura *****************************************************************************/ 36953553Stanimura#define DMSR_HP 0x00000001L 37053553Stanimura#define DMSR_HR 0x00000002L 37153553Stanimura#define DMSR_SP 0x00000004L 37253553Stanimura#define DMSR_SR 0x00000008L 37353553Stanimura 37453553Stanimura/***************************************************************************** 37553553Stanimura * 37653553Stanimura * The following defines are for the flags in the host DMA source address 37753553Stanimura * register. 37853553Stanimura * 37953553Stanimura *****************************************************************************/ 38053553Stanimura#define HSAR_HOST_ADDR_MASK 0xFFFFFFFFL 38153553Stanimura#define HSAR_DSP_ADDR_MASK 0x0000FFFFL 38253553Stanimura#define HSAR_MEMID_MASK 0x000F0000L 38353553Stanimura#define HSAR_MEMID_SP_DMEM0 0x00000000L 38453553Stanimura#define HSAR_MEMID_SP_DMEM1 0x00010000L 38553553Stanimura#define HSAR_MEMID_SP_PMEM 0x00020000L 38653553Stanimura#define HSAR_MEMID_SP_DEBUG 0x00030000L 38753553Stanimura#define HSAR_MEMID_OMNI_MEM 0x000E0000L 38853553Stanimura#define HSAR_END 0x40000000L 38953553Stanimura#define HSAR_ERR 0x80000000L 39053553Stanimura 39153553Stanimura/***************************************************************************** 39253553Stanimura * 39353553Stanimura * The following defines are for the flags in the host DMA destination address 39453553Stanimura * register. 39553553Stanimura * 39653553Stanimura *****************************************************************************/ 39753553Stanimura#define HDAR_HOST_ADDR_MASK 0xFFFFFFFFL 39853553Stanimura#define HDAR_DSP_ADDR_MASK 0x0000FFFFL 39953553Stanimura#define HDAR_MEMID_MASK 0x000F0000L 40053553Stanimura#define HDAR_MEMID_SP_DMEM0 0x00000000L 40153553Stanimura#define HDAR_MEMID_SP_DMEM1 0x00010000L 40253553Stanimura#define HDAR_MEMID_SP_PMEM 0x00020000L 40353553Stanimura#define HDAR_MEMID_SP_DEBUG 0x00030000L 40453553Stanimura#define HDAR_MEMID_OMNI_MEM 0x000E0000L 40553553Stanimura#define HDAR_END 0x40000000L 40653553Stanimura#define HDAR_ERR 0x80000000L 40753553Stanimura 40853553Stanimura/***************************************************************************** 40953553Stanimura * 41053553Stanimura * The following defines are for the flags in the host DMA control register. 41153553Stanimura * 41253553Stanimura *****************************************************************************/ 41353553Stanimura#define HDMR_AC_MASK 0x0000F000L 41453553Stanimura#define HDMR_AC_8_16 0x00001000L 41553553Stanimura#define HDMR_AC_M_S 0x00002000L 41653553Stanimura#define HDMR_AC_B_L 0x00004000L 41753553Stanimura#define HDMR_AC_S_U 0x00008000L 41853553Stanimura 41953553Stanimura/***************************************************************************** 42053553Stanimura * 42153553Stanimura * The following defines are for the flags in the host DMA control register. 42253553Stanimura * 42353553Stanimura *****************************************************************************/ 42453553Stanimura#define HDCR_COUNT_MASK 0x000003FFL 42553553Stanimura#define HDCR_DONE 0x00004000L 42653553Stanimura#define HDCR_OPT 0x00008000L 42753553Stanimura#define HDCR_WBD 0x00400000L 42853553Stanimura#define HDCR_WBS 0x00800000L 42953553Stanimura#define HDCR_DMS_MASK 0x07000000L 43053553Stanimura#define HDCR_DMS_LINEAR 0x00000000L 43153553Stanimura#define HDCR_DMS_16_DWORDS 0x01000000L 43253553Stanimura#define HDCR_DMS_32_DWORDS 0x02000000L 43353553Stanimura#define HDCR_DMS_64_DWORDS 0x03000000L 43453553Stanimura#define HDCR_DMS_128_DWORDS 0x04000000L 43553553Stanimura#define HDCR_DMS_256_DWORDS 0x05000000L 43653553Stanimura#define HDCR_DMS_512_DWORDS 0x06000000L 43753553Stanimura#define HDCR_DMS_1024_DWORDS 0x07000000L 43853553Stanimura#define HDCR_DH 0x08000000L 43953553Stanimura#define HDCR_SMS_MASK 0x70000000L 44053553Stanimura#define HDCR_SMS_LINEAR 0x00000000L 44153553Stanimura#define HDCR_SMS_16_DWORDS 0x10000000L 44253553Stanimura#define HDCR_SMS_32_DWORDS 0x20000000L 44353553Stanimura#define HDCR_SMS_64_DWORDS 0x30000000L 44453553Stanimura#define HDCR_SMS_128_DWORDS 0x40000000L 44553553Stanimura#define HDCR_SMS_256_DWORDS 0x50000000L 44653553Stanimura#define HDCR_SMS_512_DWORDS 0x60000000L 44753553Stanimura#define HDCR_SMS_1024_DWORDS 0x70000000L 44853553Stanimura#define HDCR_SH 0x80000000L 44953553Stanimura#define HDCR_COUNT_SHIFT 0L 45053553Stanimura 45153553Stanimura/***************************************************************************** 45253553Stanimura * 45353553Stanimura * The following defines are for the flags in the performance monitor control 45453553Stanimura * register. 45553553Stanimura * 45653553Stanimura *****************************************************************************/ 45753553Stanimura#define PFMC_C1SS_MASK 0x0000001FL 45853553Stanimura#define PFMC_C1EV 0x00000020L 45953553Stanimura#define PFMC_C1RS 0x00008000L 46053553Stanimura#define PFMC_C2SS_MASK 0x001F0000L 46153553Stanimura#define PFMC_C2EV 0x00200000L 46253553Stanimura#define PFMC_C2RS 0x80000000L 46353553Stanimura#define PFMC_C1SS_SHIFT 0L 46453553Stanimura#define PFMC_C2SS_SHIFT 16L 46553553Stanimura#define PFMC_BUS_GRANT 0L 46653553Stanimura#define PFMC_GRANT_AFTER_REQ 1L 46753553Stanimura#define PFMC_TRANSACTION 2L 46853553Stanimura#define PFMC_DWORD_TRANSFER 3L 46953553Stanimura#define PFMC_SLAVE_READ 4L 47053553Stanimura#define PFMC_SLAVE_WRITE 5L 47153553Stanimura#define PFMC_PREEMPTION 6L 47253553Stanimura#define PFMC_DISCONNECT_RETRY 7L 47353553Stanimura#define PFMC_INTERRUPT 8L 47453553Stanimura#define PFMC_BUS_OWNERSHIP 9L 47553553Stanimura#define PFMC_TRANSACTION_LAG 10L 47653553Stanimura#define PFMC_PCI_CLOCK 11L 47753553Stanimura#define PFMC_SERIAL_CLOCK 12L 47853553Stanimura#define PFMC_SP_CLOCK 13L 47953553Stanimura 48053553Stanimura/***************************************************************************** 48153553Stanimura * 48253553Stanimura * The following defines are for the flags in the performance counter value 1 48353553Stanimura * register. 48453553Stanimura * 48553553Stanimura *****************************************************************************/ 48653553Stanimura#define PFCV1_PC1V_MASK 0xFFFFFFFFL 48753553Stanimura#define PFCV1_PC1V_SHIFT 0L 48853553Stanimura 48953553Stanimura/***************************************************************************** 49053553Stanimura * 49153553Stanimura * The following defines are for the flags in the performance counter value 2 49253553Stanimura * register. 49353553Stanimura * 49453553Stanimura *****************************************************************************/ 49553553Stanimura#define PFCV2_PC2V_MASK 0xFFFFFFFFL 49653553Stanimura#define PFCV2_PC2V_SHIFT 0L 49753553Stanimura 49853553Stanimura/***************************************************************************** 49953553Stanimura * 50053553Stanimura * The following defines are for the flags in the clock control register 1. 50153553Stanimura * 50253553Stanimura *****************************************************************************/ 50353553Stanimura#define CLKCR1_OSCS 0x00000001L 50453553Stanimura#define CLKCR1_OSCP 0x00000002L 50553553Stanimura#define CLKCR1_PLLSS_MASK 0x0000000CL 50653553Stanimura#define CLKCR1_PLLSS_SERIAL 0x00000000L 50753553Stanimura#define CLKCR1_PLLSS_CRYSTAL 0x00000004L 50853553Stanimura#define CLKCR1_PLLSS_PCI 0x00000008L 50953553Stanimura#define CLKCR1_PLLSS_RESERVED 0x0000000CL 51053553Stanimura#define CLKCR1_PLLP 0x00000010L 51153553Stanimura#define CLKCR1_SWCE 0x00000020L 51253553Stanimura#define CLKCR1_PLLOS 0x00000040L 51353553Stanimura 51453553Stanimura/***************************************************************************** 51553553Stanimura * 51653553Stanimura * The following defines are for the flags in the clock control register 2. 51753553Stanimura * 51853553Stanimura *****************************************************************************/ 51953553Stanimura#define CLKCR2_PDIVS_MASK 0x0000000FL 52053553Stanimura#define CLKCR2_PDIVS_1 0x00000001L 52153553Stanimura#define CLKCR2_PDIVS_2 0x00000002L 52253553Stanimura#define CLKCR2_PDIVS_4 0x00000004L 52353553Stanimura#define CLKCR2_PDIVS_7 0x00000007L 52453553Stanimura#define CLKCR2_PDIVS_8 0x00000008L 52553553Stanimura#define CLKCR2_PDIVS_16 0x00000000L 52653553Stanimura 52753553Stanimura/***************************************************************************** 52853553Stanimura * 52953553Stanimura * The following defines are for the flags in the PLL multiplier register. 53053553Stanimura * 53153553Stanimura *****************************************************************************/ 53253553Stanimura#define PLLM_MASK 0x000000FFL 53353553Stanimura#define PLLM_SHIFT 0L 53453553Stanimura 53553553Stanimura/***************************************************************************** 53653553Stanimura * 53753553Stanimura * The following defines are for the flags in the PLL capacitor coefficient 53853553Stanimura * register. 53953553Stanimura * 54053553Stanimura *****************************************************************************/ 54153553Stanimura#define PLLCC_CDR_MASK 0x00000007L 54253553Stanimura#ifndef NO_CS4610 54353553Stanimura#define PLLCC_CDR_240_350_MHZ 0x00000000L 54453553Stanimura#define PLLCC_CDR_184_265_MHZ 0x00000001L 54553553Stanimura#define PLLCC_CDR_144_205_MHZ 0x00000002L 54653553Stanimura#define PLLCC_CDR_111_160_MHZ 0x00000003L 54753553Stanimura#define PLLCC_CDR_87_123_MHZ 0x00000004L 54853553Stanimura#define PLLCC_CDR_67_96_MHZ 0x00000005L 54953553Stanimura#define PLLCC_CDR_52_74_MHZ 0x00000006L 55053553Stanimura#define PLLCC_CDR_45_58_MHZ 0x00000007L 55153553Stanimura#endif 55253553Stanimura#ifndef NO_CS4612 55353553Stanimura#define PLLCC_CDR_271_398_MHZ 0x00000000L 55453553Stanimura#define PLLCC_CDR_227_330_MHZ 0x00000001L 55553553Stanimura#define PLLCC_CDR_167_239_MHZ 0x00000002L 55653553Stanimura#define PLLCC_CDR_150_215_MHZ 0x00000003L 55753553Stanimura#define PLLCC_CDR_107_154_MHZ 0x00000004L 55853553Stanimura#define PLLCC_CDR_98_140_MHZ 0x00000005L 55953553Stanimura#define PLLCC_CDR_73_104_MHZ 0x00000006L 56053553Stanimura#define PLLCC_CDR_63_90_MHZ 0x00000007L 56153553Stanimura#endif 56253553Stanimura#define PLLCC_LPF_MASK 0x000000F8L 56353553Stanimura#ifndef NO_CS4610 56453553Stanimura#define PLLCC_LPF_23850_60000_KHZ 0x00000000L 56553553Stanimura#define PLLCC_LPF_7960_26290_KHZ 0x00000008L 56653553Stanimura#define PLLCC_LPF_4160_10980_KHZ 0x00000018L 56753553Stanimura#define PLLCC_LPF_1740_4580_KHZ 0x00000038L 56853553Stanimura#define PLLCC_LPF_724_1910_KHZ 0x00000078L 56953553Stanimura#define PLLCC_LPF_317_798_KHZ 0x000000F8L 57053553Stanimura#endif 57153553Stanimura#ifndef NO_CS4612 57253553Stanimura#define PLLCC_LPF_25580_64530_KHZ 0x00000000L 57353553Stanimura#define PLLCC_LPF_14360_37270_KHZ 0x00000008L 57453553Stanimura#define PLLCC_LPF_6100_16020_KHZ 0x00000018L 57553553Stanimura#define PLLCC_LPF_2540_6690_KHZ 0x00000038L 57653553Stanimura#define PLLCC_LPF_1050_2780_KHZ 0x00000078L 57753553Stanimura#define PLLCC_LPF_450_1160_KHZ 0x000000F8L 57853553Stanimura#endif 57953553Stanimura 58053553Stanimura/***************************************************************************** 58153553Stanimura * 58253553Stanimura * The following defines are for the flags in the feature reporting register. 58353553Stanimura * 58453553Stanimura *****************************************************************************/ 58553553Stanimura#define FRR_FAB_MASK 0x00000003L 58653553Stanimura#define FRR_MASK_MASK 0x0000001CL 58753553Stanimura#ifdef NO_CS4612 58853553Stanimura#define FRR_CFOP_MASK 0x000000E0L 58953553Stanimura#else 59053553Stanimura#define FRR_CFOP_MASK 0x00000FE0L 59153553Stanimura#endif 59253553Stanimura#define FRR_CFOP_NOT_DVD 0x00000020L 59353553Stanimura#define FRR_CFOP_A3D 0x00000040L 59453553Stanimura#define FRR_CFOP_128_PIN 0x00000080L 59553553Stanimura#ifndef NO_CS4612 59653553Stanimura#define FRR_CFOP_CS4280 0x00000800L 59753553Stanimura#endif 59853553Stanimura#define FRR_FAB_SHIFT 0L 59953553Stanimura#define FRR_MASK_SHIFT 2L 60053553Stanimura#define FRR_CFOP_SHIFT 5L 60153553Stanimura 60253553Stanimura/***************************************************************************** 60353553Stanimura * 60453553Stanimura * The following defines are for the flags in the configuration load 1 60553553Stanimura * register. 60653553Stanimura * 60753553Stanimura *****************************************************************************/ 60853553Stanimura#define CFL1_CLOCK_SOURCE_MASK 0x00000003L 60953553Stanimura#define CFL1_CLOCK_SOURCE_CS423X 0x00000000L 61053553Stanimura#define CFL1_CLOCK_SOURCE_AC97 0x00000001L 61153553Stanimura#define CFL1_CLOCK_SOURCE_CRYSTAL 0x00000002L 61253553Stanimura#define CFL1_CLOCK_SOURCE_DUAL_AC97 0x00000003L 61353553Stanimura#define CFL1_VALID_DATA_MASK 0x000000FFL 61453553Stanimura 61553553Stanimura/***************************************************************************** 61653553Stanimura * 61753553Stanimura * The following defines are for the flags in the configuration load 2 61853553Stanimura * register. 61953553Stanimura * 62053553Stanimura *****************************************************************************/ 62153553Stanimura#define CFL2_VALID_DATA_MASK 0x000000FFL 62253553Stanimura 62353553Stanimura/***************************************************************************** 62453553Stanimura * 62553553Stanimura * The following defines are for the flags in the serial port master control 62653553Stanimura * register 1. 62753553Stanimura * 62853553Stanimura *****************************************************************************/ 62953553Stanimura#define SERMC1_MSPE 0x00000001L 63053553Stanimura#define SERMC1_PTC_MASK 0x0000000EL 63153553Stanimura#define SERMC1_PTC_CS423X 0x00000000L 63253553Stanimura#define SERMC1_PTC_AC97 0x00000002L 63353553Stanimura#define SERMC1_PTC_DAC 0x00000004L 63453553Stanimura#define SERMC1_PLB 0x00000010L 63553553Stanimura#define SERMC1_XLB 0x00000020L 63653553Stanimura 63753553Stanimura/***************************************************************************** 63853553Stanimura * 63953553Stanimura * The following defines are for the flags in the serial port master control 64053553Stanimura * register 2. 64153553Stanimura * 64253553Stanimura *****************************************************************************/ 64353553Stanimura#define SERMC2_LROE 0x00000001L 64453553Stanimura#define SERMC2_MCOE 0x00000002L 64553553Stanimura#define SERMC2_MCDIV 0x00000004L 64653553Stanimura 64753553Stanimura/***************************************************************************** 64853553Stanimura * 64953553Stanimura * The following defines are for the flags in the serial port 1 configuration 65053553Stanimura * register. 65153553Stanimura * 65253553Stanimura *****************************************************************************/ 65353553Stanimura#define SERC1_SO1EN 0x00000001L 65453553Stanimura#define SERC1_SO1F_MASK 0x0000000EL 65553553Stanimura#define SERC1_SO1F_CS423X 0x00000000L 65653553Stanimura#define SERC1_SO1F_AC97 0x00000002L 65753553Stanimura#define SERC1_SO1F_DAC 0x00000004L 65853553Stanimura#define SERC1_SO1F_SPDIF 0x00000006L 65953553Stanimura 66053553Stanimura/***************************************************************************** 66153553Stanimura * 66253553Stanimura * The following defines are for the flags in the serial port 2 configuration 66353553Stanimura * register. 66453553Stanimura * 66553553Stanimura *****************************************************************************/ 66653553Stanimura#define SERC2_SI1EN 0x00000001L 66753553Stanimura#define SERC2_SI1F_MASK 0x0000000EL 66853553Stanimura#define SERC2_SI1F_CS423X 0x00000000L 66953553Stanimura#define SERC2_SI1F_AC97 0x00000002L 67053553Stanimura#define SERC2_SI1F_ADC 0x00000004L 67153553Stanimura#define SERC2_SI1F_SPDIF 0x00000006L 67253553Stanimura 67353553Stanimura/***************************************************************************** 67453553Stanimura * 67553553Stanimura * The following defines are for the flags in the serial port 3 configuration 67653553Stanimura * register. 67753553Stanimura * 67853553Stanimura *****************************************************************************/ 67953553Stanimura#define SERC3_SO2EN 0x00000001L 68053553Stanimura#define SERC3_SO2F_MASK 0x00000006L 68153553Stanimura#define SERC3_SO2F_DAC 0x00000000L 68253553Stanimura#define SERC3_SO2F_SPDIF 0x00000002L 68353553Stanimura 68453553Stanimura/***************************************************************************** 68553553Stanimura * 68653553Stanimura * The following defines are for the flags in the serial port 4 configuration 68753553Stanimura * register. 68853553Stanimura * 68953553Stanimura *****************************************************************************/ 69053553Stanimura#define SERC4_SO3EN 0x00000001L 69153553Stanimura#define SERC4_SO3F_MASK 0x00000006L 69253553Stanimura#define SERC4_SO3F_DAC 0x00000000L 69353553Stanimura#define SERC4_SO3F_SPDIF 0x00000002L 69453553Stanimura 69553553Stanimura/***************************************************************************** 69653553Stanimura * 69753553Stanimura * The following defines are for the flags in the serial port 5 configuration 69853553Stanimura * register. 69953553Stanimura * 70053553Stanimura *****************************************************************************/ 70153553Stanimura#define SERC5_SI2EN 0x00000001L 70253553Stanimura#define SERC5_SI2F_MASK 0x00000006L 70353553Stanimura#define SERC5_SI2F_ADC 0x00000000L 70453553Stanimura#define SERC5_SI2F_SPDIF 0x00000002L 70553553Stanimura 70653553Stanimura/***************************************************************************** 70753553Stanimura * 70853553Stanimura * The following defines are for the flags in the serial port backdoor sample 70953553Stanimura * pointer register. 71053553Stanimura * 71153553Stanimura *****************************************************************************/ 71253553Stanimura#define SERBSP_FSP_MASK 0x0000000FL 71353553Stanimura#define SERBSP_FSP_SHIFT 0L 71453553Stanimura 71553553Stanimura/***************************************************************************** 71653553Stanimura * 71753553Stanimura * The following defines are for the flags in the serial port backdoor status 71853553Stanimura * register. 71953553Stanimura * 72053553Stanimura *****************************************************************************/ 72153553Stanimura#define SERBST_RRDY 0x00000001L 72253553Stanimura#define SERBST_WBSY 0x00000002L 72353553Stanimura 72453553Stanimura/***************************************************************************** 72553553Stanimura * 72653553Stanimura * The following defines are for the flags in the serial port backdoor command 72753553Stanimura * register. 72853553Stanimura * 72953553Stanimura *****************************************************************************/ 73053553Stanimura#define SERBCM_RDC 0x00000001L 73153553Stanimura#define SERBCM_WRC 0x00000002L 73253553Stanimura 73353553Stanimura/***************************************************************************** 73453553Stanimura * 73553553Stanimura * The following defines are for the flags in the serial port backdoor address 73653553Stanimura * register. 73753553Stanimura * 73853553Stanimura *****************************************************************************/ 73953553Stanimura#ifdef NO_CS4612 74053553Stanimura#define SERBAD_FAD_MASK 0x000000FFL 74153553Stanimura#else 74253553Stanimura#define SERBAD_FAD_MASK 0x000001FFL 74353553Stanimura#endif 74453553Stanimura#define SERBAD_FAD_SHIFT 0L 74553553Stanimura 74653553Stanimura/***************************************************************************** 74753553Stanimura * 74853553Stanimura * The following defines are for the flags in the serial port backdoor 74953553Stanimura * configuration register. 75053553Stanimura * 75153553Stanimura *****************************************************************************/ 75253553Stanimura#define SERBCF_HBP 0x00000001L 75353553Stanimura 75453553Stanimura/***************************************************************************** 75553553Stanimura * 75653553Stanimura * The following defines are for the flags in the serial port backdoor write 75753553Stanimura * port register. 75853553Stanimura * 75953553Stanimura *****************************************************************************/ 76053553Stanimura#define SERBWP_FWD_MASK 0x000FFFFFL 76153553Stanimura#define SERBWP_FWD_SHIFT 0L 76253553Stanimura 76353553Stanimura/***************************************************************************** 76453553Stanimura * 76553553Stanimura * The following defines are for the flags in the serial port backdoor read 76653553Stanimura * port register. 76753553Stanimura * 76853553Stanimura *****************************************************************************/ 76953553Stanimura#define SERBRP_FRD_MASK 0x000FFFFFL 77053553Stanimura#define SERBRP_FRD_SHIFT 0L 77153553Stanimura 77253553Stanimura/***************************************************************************** 77353553Stanimura * 77453553Stanimura * The following defines are for the flags in the async FIFO address register. 77553553Stanimura * 77653553Stanimura *****************************************************************************/ 77753553Stanimura#ifndef NO_CS4612 77853553Stanimura#define ASER_FADDR_A1_MASK 0x000001FFL 77953553Stanimura#define ASER_FADDR_EN1 0x00008000L 78053553Stanimura#define ASER_FADDR_A2_MASK 0x01FF0000L 78153553Stanimura#define ASER_FADDR_EN2 0x80000000L 78253553Stanimura#define ASER_FADDR_A1_SHIFT 0L 78353553Stanimura#define ASER_FADDR_A2_SHIFT 16L 78453553Stanimura#endif 78553553Stanimura 78653553Stanimura/***************************************************************************** 78753553Stanimura * 78853553Stanimura * The following defines are for the flags in the AC97 control register. 78953553Stanimura * 79053553Stanimura *****************************************************************************/ 79153553Stanimura#define ACCTL_RSTN 0x00000001L 79253553Stanimura#define ACCTL_ESYN 0x00000002L 79353553Stanimura#define ACCTL_VFRM 0x00000004L 79453553Stanimura#define ACCTL_DCV 0x00000008L 79553553Stanimura#define ACCTL_CRW 0x00000010L 79653553Stanimura#define ACCTL_ASYN 0x00000020L 79753553Stanimura#ifndef NO_CS4612 79853553Stanimura#define ACCTL_TC 0x00000040L 79953553Stanimura#endif 80053553Stanimura 80153553Stanimura/***************************************************************************** 80253553Stanimura * 80353553Stanimura * The following defines are for the flags in the AC97 status register. 80453553Stanimura * 80553553Stanimura *****************************************************************************/ 80653553Stanimura#define ACSTS_CRDY 0x00000001L 80753553Stanimura#define ACSTS_VSTS 0x00000002L 80853553Stanimura#ifndef NO_CS4612 80953553Stanimura#define ACSTS_WKUP 0x00000004L 81053553Stanimura#endif 81153553Stanimura 81253553Stanimura/***************************************************************************** 81353553Stanimura * 81453553Stanimura * The following defines are for the flags in the AC97 output slot valid 81553553Stanimura * register. 81653553Stanimura * 81753553Stanimura *****************************************************************************/ 81853553Stanimura#define ACOSV_SLV3 0x00000001L 81953553Stanimura#define ACOSV_SLV4 0x00000002L 82053553Stanimura#define ACOSV_SLV5 0x00000004L 82153553Stanimura#define ACOSV_SLV6 0x00000008L 82253553Stanimura#define ACOSV_SLV7 0x00000010L 82353553Stanimura#define ACOSV_SLV8 0x00000020L 82453553Stanimura#define ACOSV_SLV9 0x00000040L 82553553Stanimura#define ACOSV_SLV10 0x00000080L 82653553Stanimura#define ACOSV_SLV11 0x00000100L 82753553Stanimura#define ACOSV_SLV12 0x00000200L 82853553Stanimura 82953553Stanimura/***************************************************************************** 83053553Stanimura * 83153553Stanimura * The following defines are for the flags in the AC97 command address 83253553Stanimura * register. 83353553Stanimura * 83453553Stanimura *****************************************************************************/ 83553553Stanimura#define ACCAD_CI_MASK 0x0000007FL 83653553Stanimura#define ACCAD_CI_SHIFT 0L 83753553Stanimura 83853553Stanimura/***************************************************************************** 83953553Stanimura * 84053553Stanimura * The following defines are for the flags in the AC97 command data register. 84153553Stanimura * 84253553Stanimura *****************************************************************************/ 84353553Stanimura#define ACCDA_CD_MASK 0x0000FFFFL 84453553Stanimura#define ACCDA_CD_SHIFT 0L 84553553Stanimura 84653553Stanimura/***************************************************************************** 84753553Stanimura * 84853553Stanimura * The following defines are for the flags in the AC97 input slot valid 84953553Stanimura * register. 85053553Stanimura * 85153553Stanimura *****************************************************************************/ 85253553Stanimura#define ACISV_ISV3 0x00000001L 85353553Stanimura#define ACISV_ISV4 0x00000002L 85453553Stanimura#define ACISV_ISV5 0x00000004L 85553553Stanimura#define ACISV_ISV6 0x00000008L 85653553Stanimura#define ACISV_ISV7 0x00000010L 85753553Stanimura#define ACISV_ISV8 0x00000020L 85853553Stanimura#define ACISV_ISV9 0x00000040L 85953553Stanimura#define ACISV_ISV10 0x00000080L 86053553Stanimura#define ACISV_ISV11 0x00000100L 86153553Stanimura#define ACISV_ISV12 0x00000200L 86253553Stanimura 86353553Stanimura/***************************************************************************** 86453553Stanimura * 86553553Stanimura * The following defines are for the flags in the AC97 status address 86653553Stanimura * register. 86753553Stanimura * 86853553Stanimura *****************************************************************************/ 86953553Stanimura#define ACSAD_SI_MASK 0x0000007FL 87053553Stanimura#define ACSAD_SI_SHIFT 0L 87153553Stanimura 87253553Stanimura/***************************************************************************** 87353553Stanimura * 87453553Stanimura * The following defines are for the flags in the AC97 status data register. 87553553Stanimura * 87653553Stanimura *****************************************************************************/ 87753553Stanimura#define ACSDA_SD_MASK 0x0000FFFFL 87853553Stanimura#define ACSDA_SD_SHIFT 0L 87953553Stanimura 88053553Stanimura/***************************************************************************** 88153553Stanimura * 88253553Stanimura * The following defines are for the flags in the joystick poll/trigger 88353553Stanimura * register. 88453553Stanimura * 88553553Stanimura *****************************************************************************/ 88653553Stanimura#define JSPT_CAX 0x00000001L 88753553Stanimura#define JSPT_CAY 0x00000002L 88853553Stanimura#define JSPT_CBX 0x00000004L 88953553Stanimura#define JSPT_CBY 0x00000008L 89053553Stanimura#define JSPT_BA1 0x00000010L 89153553Stanimura#define JSPT_BA2 0x00000020L 89253553Stanimura#define JSPT_BB1 0x00000040L 89353553Stanimura#define JSPT_BB2 0x00000080L 89453553Stanimura 89553553Stanimura/***************************************************************************** 89653553Stanimura * 89753553Stanimura * The following defines are for the flags in the joystick control register. 89853553Stanimura * 89953553Stanimura *****************************************************************************/ 90053553Stanimura#define JSCTL_SP_MASK 0x00000003L 90153553Stanimura#define JSCTL_SP_SLOW 0x00000000L 90253553Stanimura#define JSCTL_SP_MEDIUM_SLOW 0x00000001L 90353553Stanimura#define JSCTL_SP_MEDIUM_FAST 0x00000002L 90453553Stanimura#define JSCTL_SP_FAST 0x00000003L 90553553Stanimura#define JSCTL_ARE 0x00000004L 90653553Stanimura 90753553Stanimura/***************************************************************************** 90853553Stanimura * 90953553Stanimura * The following defines are for the flags in the joystick coordinate pair 1 91053553Stanimura * readback register. 91153553Stanimura * 91253553Stanimura *****************************************************************************/ 91353553Stanimura#define JSC1_Y1V_MASK 0x0000FFFFL 91453553Stanimura#define JSC1_X1V_MASK 0xFFFF0000L 91553553Stanimura#define JSC1_Y1V_SHIFT 0L 91653553Stanimura#define JSC1_X1V_SHIFT 16L 91753553Stanimura 91853553Stanimura/***************************************************************************** 91953553Stanimura * 92053553Stanimura * The following defines are for the flags in the joystick coordinate pair 2 92153553Stanimura * readback register. 92253553Stanimura * 92353553Stanimura *****************************************************************************/ 92453553Stanimura#define JSC2_Y2V_MASK 0x0000FFFFL 92553553Stanimura#define JSC2_X2V_MASK 0xFFFF0000L 92653553Stanimura#define JSC2_Y2V_SHIFT 0L 92753553Stanimura#define JSC2_X2V_SHIFT 16L 92853553Stanimura 92953553Stanimura/***************************************************************************** 93053553Stanimura * 93153553Stanimura * The following defines are for the flags in the MIDI control register. 93253553Stanimura * 93353553Stanimura *****************************************************************************/ 93453553Stanimura#define MIDCR_TXE 0x00000001L 93553553Stanimura#define MIDCR_RXE 0x00000002L 93653553Stanimura#define MIDCR_RIE 0x00000004L 93753553Stanimura#define MIDCR_TIE 0x00000008L 93853553Stanimura#define MIDCR_MLB 0x00000010L 93953553Stanimura#define MIDCR_MRST 0x00000020L 94053553Stanimura 94153553Stanimura/***************************************************************************** 94253553Stanimura * 94353553Stanimura * The following defines are for the flags in the MIDI status register. 94453553Stanimura * 94553553Stanimura *****************************************************************************/ 94653553Stanimura#define MIDSR_TBF 0x00000001L 94753553Stanimura#define MIDSR_RBE 0x00000002L 94853553Stanimura 94953553Stanimura/***************************************************************************** 95053553Stanimura * 95153553Stanimura * The following defines are for the flags in the MIDI write port register. 95253553Stanimura * 95353553Stanimura *****************************************************************************/ 95453553Stanimura#define MIDWP_MWD_MASK 0x000000FFL 95553553Stanimura#define MIDWP_MWD_SHIFT 0L 95653553Stanimura 95753553Stanimura/***************************************************************************** 95853553Stanimura * 95953553Stanimura * The following defines are for the flags in the MIDI read port register. 96053553Stanimura * 96153553Stanimura *****************************************************************************/ 96253553Stanimura#define MIDRP_MRD_MASK 0x000000FFL 96353553Stanimura#define MIDRP_MRD_SHIFT 0L 96453553Stanimura 96553553Stanimura/***************************************************************************** 96653553Stanimura * 96753553Stanimura * The following defines are for the flags in the joystick GPIO register. 96853553Stanimura * 96953553Stanimura *****************************************************************************/ 97053553Stanimura#define JSIO_DAX 0x00000001L 97153553Stanimura#define JSIO_DAY 0x00000002L 97253553Stanimura#define JSIO_DBX 0x00000004L 97353553Stanimura#define JSIO_DBY 0x00000008L 97453553Stanimura#define JSIO_AXOE 0x00000010L 97553553Stanimura#define JSIO_AYOE 0x00000020L 97653553Stanimura#define JSIO_BXOE 0x00000040L 97753553Stanimura#define JSIO_BYOE 0x00000080L 97853553Stanimura 97953553Stanimura/***************************************************************************** 98053553Stanimura * 98153553Stanimura * The following defines are for the flags in the master async/sync serial 98253553Stanimura * port enable register. 98353553Stanimura * 98453553Stanimura *****************************************************************************/ 98553553Stanimura#ifndef NO_CS4612 98653553Stanimura#define ASER_MASTER_ME 0x00000001L 98753553Stanimura#endif 98853553Stanimura 98953553Stanimura/***************************************************************************** 99053553Stanimura * 99153553Stanimura * The following defines are for the flags in the configuration interface 99253553Stanimura * register. 99353553Stanimura * 99453553Stanimura *****************************************************************************/ 99553553Stanimura#define CFGI_CLK 0x00000001L 99653553Stanimura#define CFGI_DOUT 0x00000002L 99753553Stanimura#define CFGI_DIN_EEN 0x00000004L 99853553Stanimura#define CFGI_EELD 0x00000008L 99953553Stanimura 100053553Stanimura/***************************************************************************** 100153553Stanimura * 100253553Stanimura * The following defines are for the flags in the subsystem ID and vendor ID 100353553Stanimura * register. 100453553Stanimura * 100553553Stanimura *****************************************************************************/ 100653553Stanimura#define SSVID_VID_MASK 0x0000FFFFL 100753553Stanimura#define SSVID_SID_MASK 0xFFFF0000L 100853553Stanimura#define SSVID_VID_SHIFT 0L 100953553Stanimura#define SSVID_SID_SHIFT 16L 101053553Stanimura 101153553Stanimura/***************************************************************************** 101253553Stanimura * 101353553Stanimura * The following defines are for the flags in the GPIO pin interface register. 101453553Stanimura * 101553553Stanimura *****************************************************************************/ 101653553Stanimura#define GPIOR_VOLDN 0x00000001L 101753553Stanimura#define GPIOR_VOLUP 0x00000002L 101853553Stanimura#define GPIOR_SI2D 0x00000004L 101953553Stanimura#define GPIOR_SI2OE 0x00000008L 102053553Stanimura 102153553Stanimura/***************************************************************************** 102253553Stanimura * 102353553Stanimura * The following defines are for the flags in the extended GPIO pin direction 102453553Stanimura * register. 102553553Stanimura * 102653553Stanimura *****************************************************************************/ 102753553Stanimura#ifndef NO_CS4612 102853553Stanimura#define EGPIODR_GPOE0 0x00000001L 102953553Stanimura#define EGPIODR_GPOE1 0x00000002L 103053553Stanimura#define EGPIODR_GPOE2 0x00000004L 103153553Stanimura#define EGPIODR_GPOE3 0x00000008L 103253553Stanimura#define EGPIODR_GPOE4 0x00000010L 103353553Stanimura#define EGPIODR_GPOE5 0x00000020L 103453553Stanimura#define EGPIODR_GPOE6 0x00000040L 103553553Stanimura#define EGPIODR_GPOE7 0x00000080L 103653553Stanimura#define EGPIODR_GPOE8 0x00000100L 103753553Stanimura#endif 103853553Stanimura 103953553Stanimura/***************************************************************************** 104053553Stanimura * 104153553Stanimura * The following defines are for the flags in the extended GPIO pin polarity/ 104253553Stanimura * type register. 104353553Stanimura * 104453553Stanimura *****************************************************************************/ 104553553Stanimura#ifndef NO_CS4612 104653553Stanimura#define EGPIOPTR_GPPT0 0x00000001L 104753553Stanimura#define EGPIOPTR_GPPT1 0x00000002L 104853553Stanimura#define EGPIOPTR_GPPT2 0x00000004L 104953553Stanimura#define EGPIOPTR_GPPT3 0x00000008L 105053553Stanimura#define EGPIOPTR_GPPT4 0x00000010L 105153553Stanimura#define EGPIOPTR_GPPT5 0x00000020L 105253553Stanimura#define EGPIOPTR_GPPT6 0x00000040L 105353553Stanimura#define EGPIOPTR_GPPT7 0x00000080L 105453553Stanimura#define EGPIOPTR_GPPT8 0x00000100L 105553553Stanimura#endif 105653553Stanimura 105753553Stanimura/***************************************************************************** 105853553Stanimura * 105953553Stanimura * The following defines are for the flags in the extended GPIO pin sticky 106053553Stanimura * register. 106153553Stanimura * 106253553Stanimura *****************************************************************************/ 106353553Stanimura#ifndef NO_CS4612 106453553Stanimura#define EGPIOTR_GPS0 0x00000001L 106553553Stanimura#define EGPIOTR_GPS1 0x00000002L 106653553Stanimura#define EGPIOTR_GPS2 0x00000004L 106753553Stanimura#define EGPIOTR_GPS3 0x00000008L 106853553Stanimura#define EGPIOTR_GPS4 0x00000010L 106953553Stanimura#define EGPIOTR_GPS5 0x00000020L 107053553Stanimura#define EGPIOTR_GPS6 0x00000040L 107153553Stanimura#define EGPIOTR_GPS7 0x00000080L 107253553Stanimura#define EGPIOTR_GPS8 0x00000100L 107353553Stanimura#endif 107453553Stanimura 107553553Stanimura/***************************************************************************** 107653553Stanimura * 107753553Stanimura * The following defines are for the flags in the extended GPIO ping wakeup 107853553Stanimura * register. 107953553Stanimura * 108053553Stanimura *****************************************************************************/ 108153553Stanimura#ifndef NO_CS4612 108253553Stanimura#define EGPIOWR_GPW0 0x00000001L 108353553Stanimura#define EGPIOWR_GPW1 0x00000002L 108453553Stanimura#define EGPIOWR_GPW2 0x00000004L 108553553Stanimura#define EGPIOWR_GPW3 0x00000008L 108653553Stanimura#define EGPIOWR_GPW4 0x00000010L 108753553Stanimura#define EGPIOWR_GPW5 0x00000020L 108853553Stanimura#define EGPIOWR_GPW6 0x00000040L 108953553Stanimura#define EGPIOWR_GPW7 0x00000080L 109053553Stanimura#define EGPIOWR_GPW8 0x00000100L 109153553Stanimura#endif 109253553Stanimura 109353553Stanimura/***************************************************************************** 109453553Stanimura * 109553553Stanimura * The following defines are for the flags in the extended GPIO pin status 109653553Stanimura * register. 109753553Stanimura * 109853553Stanimura *****************************************************************************/ 109953553Stanimura#ifndef NO_CS4612 110053553Stanimura#define EGPIOSR_GPS0 0x00000001L 110153553Stanimura#define EGPIOSR_GPS1 0x00000002L 110253553Stanimura#define EGPIOSR_GPS2 0x00000004L 110353553Stanimura#define EGPIOSR_GPS3 0x00000008L 110453553Stanimura#define EGPIOSR_GPS4 0x00000010L 110553553Stanimura#define EGPIOSR_GPS5 0x00000020L 110653553Stanimura#define EGPIOSR_GPS6 0x00000040L 110753553Stanimura#define EGPIOSR_GPS7 0x00000080L 110853553Stanimura#define EGPIOSR_GPS8 0x00000100L 110953553Stanimura#endif 111053553Stanimura 111153553Stanimura/***************************************************************************** 111253553Stanimura * 111353553Stanimura * The following defines are for the flags in the serial port 6 configuration 111453553Stanimura * register. 111553553Stanimura * 111653553Stanimura *****************************************************************************/ 111753553Stanimura#ifndef NO_CS4612 111853553Stanimura#define SERC6_ASDO2EN 0x00000001L 111953553Stanimura#endif 112053553Stanimura 112153553Stanimura/***************************************************************************** 112253553Stanimura * 112353553Stanimura * The following defines are for the flags in the serial port 7 configuration 112453553Stanimura * register. 112553553Stanimura * 112653553Stanimura *****************************************************************************/ 112753553Stanimura#ifndef NO_CS4612 112853553Stanimura#define SERC7_ASDI2EN 0x00000001L 112953553Stanimura#define SERC7_POSILB 0x00000002L 113053553Stanimura#define SERC7_SIPOLB 0x00000004L 113153553Stanimura#define SERC7_SOSILB 0x00000008L 113253553Stanimura#define SERC7_SISOLB 0x00000010L 113353553Stanimura#endif 113453553Stanimura 113553553Stanimura/***************************************************************************** 113653553Stanimura * 113753553Stanimura * The following defines are for the flags in the serial port AC link 113853553Stanimura * configuration register. 113953553Stanimura * 114053553Stanimura *****************************************************************************/ 114153553Stanimura#ifndef NO_CS4612 114253553Stanimura#define SERACC_CODEC_TYPE_MASK 0x00000001L 114353553Stanimura#define SERACC_CODEC_TYPE_1_03 0x00000000L 114453553Stanimura#define SERACC_CODEC_TYPE_2_0 0x00000001L 114553553Stanimura#define SERACC_TWO_CODECS 0x00000002L 114653553Stanimura#define SERACC_MDM 0x00000004L 114753553Stanimura#define SERACC_HSP 0x00000008L 114853553Stanimura#endif 114953553Stanimura 115053553Stanimura/***************************************************************************** 115153553Stanimura * 115253553Stanimura * The following defines are for the flags in the AC97 control register 2. 115353553Stanimura * 115453553Stanimura *****************************************************************************/ 115553553Stanimura#ifndef NO_CS4612 115653553Stanimura#define ACCTL2_RSTN 0x00000001L 115753553Stanimura#define ACCTL2_ESYN 0x00000002L 115853553Stanimura#define ACCTL2_VFRM 0x00000004L 115953553Stanimura#define ACCTL2_DCV 0x00000008L 116053553Stanimura#define ACCTL2_CRW 0x00000010L 116153553Stanimura#define ACCTL2_ASYN 0x00000020L 116253553Stanimura#endif 116353553Stanimura 116453553Stanimura/***************************************************************************** 116553553Stanimura * 116653553Stanimura * The following defines are for the flags in the AC97 status register 2. 116753553Stanimura * 116853553Stanimura *****************************************************************************/ 116953553Stanimura#ifndef NO_CS4612 117053553Stanimura#define ACSTS2_CRDY 0x00000001L 117153553Stanimura#define ACSTS2_VSTS 0x00000002L 117253553Stanimura#endif 117353553Stanimura 117453553Stanimura/***************************************************************************** 117553553Stanimura * 117653553Stanimura * The following defines are for the flags in the AC97 output slot valid 117753553Stanimura * register 2. 117853553Stanimura * 117953553Stanimura *****************************************************************************/ 118053553Stanimura#ifndef NO_CS4612 118153553Stanimura#define ACOSV2_SLV3 0x00000001L 118253553Stanimura#define ACOSV2_SLV4 0x00000002L 118353553Stanimura#define ACOSV2_SLV5 0x00000004L 118453553Stanimura#define ACOSV2_SLV6 0x00000008L 118553553Stanimura#define ACOSV2_SLV7 0x00000010L 118653553Stanimura#define ACOSV2_SLV8 0x00000020L 118753553Stanimura#define ACOSV2_SLV9 0x00000040L 118853553Stanimura#define ACOSV2_SLV10 0x00000080L 118953553Stanimura#define ACOSV2_SLV11 0x00000100L 119053553Stanimura#define ACOSV2_SLV12 0x00000200L 119153553Stanimura#endif 119253553Stanimura 119353553Stanimura/***************************************************************************** 119453553Stanimura * 119553553Stanimura * The following defines are for the flags in the AC97 command address 119653553Stanimura * register 2. 119753553Stanimura * 119853553Stanimura *****************************************************************************/ 119953553Stanimura#ifndef NO_CS4612 120053553Stanimura#define ACCAD2_CI_MASK 0x0000007FL 120153553Stanimura#define ACCAD2_CI_SHIFT 0L 120253553Stanimura#endif 120353553Stanimura 120453553Stanimura/***************************************************************************** 120553553Stanimura * 120653553Stanimura * The following defines are for the flags in the AC97 command data register 120753553Stanimura * 2. 120853553Stanimura * 120953553Stanimura *****************************************************************************/ 121053553Stanimura#ifndef NO_CS4612 121153553Stanimura#define ACCDA2_CD_MASK 0x0000FFFFL 121253553Stanimura#define ACCDA2_CD_SHIFT 0L 121353553Stanimura#endif 121453553Stanimura 121553553Stanimura/***************************************************************************** 121653553Stanimura * 121753553Stanimura * The following defines are for the flags in the AC97 input slot valid 121853553Stanimura * register 2. 121953553Stanimura * 122053553Stanimura *****************************************************************************/ 122153553Stanimura#ifndef NO_CS4612 122253553Stanimura#define ACISV2_ISV3 0x00000001L 122353553Stanimura#define ACISV2_ISV4 0x00000002L 122453553Stanimura#define ACISV2_ISV5 0x00000004L 122553553Stanimura#define ACISV2_ISV6 0x00000008L 122653553Stanimura#define ACISV2_ISV7 0x00000010L 122753553Stanimura#define ACISV2_ISV8 0x00000020L 122853553Stanimura#define ACISV2_ISV9 0x00000040L 122953553Stanimura#define ACISV2_ISV10 0x00000080L 123053553Stanimura#define ACISV2_ISV11 0x00000100L 123153553Stanimura#define ACISV2_ISV12 0x00000200L 123253553Stanimura#endif 123353553Stanimura 123453553Stanimura/***************************************************************************** 123553553Stanimura * 123653553Stanimura * The following defines are for the flags in the AC97 status address 123753553Stanimura * register 2. 123853553Stanimura * 123953553Stanimura *****************************************************************************/ 124053553Stanimura#ifndef NO_CS4612 124153553Stanimura#define ACSAD2_SI_MASK 0x0000007FL 124253553Stanimura#define ACSAD2_SI_SHIFT 0L 124353553Stanimura#endif 124453553Stanimura 124553553Stanimura/***************************************************************************** 124653553Stanimura * 124753553Stanimura * The following defines are for the flags in the AC97 status data register 2. 124853553Stanimura * 124953553Stanimura *****************************************************************************/ 125053553Stanimura#ifndef NO_CS4612 125153553Stanimura#define ACSDA2_SD_MASK 0x0000FFFFL 125253553Stanimura#define ACSDA2_SD_SHIFT 0L 125353553Stanimura#endif 125453553Stanimura 125553553Stanimura/***************************************************************************** 125653553Stanimura * 125753553Stanimura * The following defines are for the flags in the I/O trap address and control 125853553Stanimura * registers (all 12). 125953553Stanimura * 126053553Stanimura *****************************************************************************/ 126153553Stanimura#ifndef NO_CS4612 126253553Stanimura#define IOTAC_SA_MASK 0x0000FFFFL 126353553Stanimura#define IOTAC_MSK_MASK 0x000F0000L 126453553Stanimura#define IOTAC_IODC_MASK 0x06000000L 126553553Stanimura#define IOTAC_IODC_16_BIT 0x00000000L 126653553Stanimura#define IOTAC_IODC_10_BIT 0x02000000L 126753553Stanimura#define IOTAC_IODC_12_BIT 0x04000000L 126853553Stanimura#define IOTAC_WSPI 0x08000000L 126953553Stanimura#define IOTAC_RSPI 0x10000000L 127053553Stanimura#define IOTAC_WSE 0x20000000L 127153553Stanimura#define IOTAC_WE 0x40000000L 127253553Stanimura#define IOTAC_RE 0x80000000L 127353553Stanimura#define IOTAC_SA_SHIFT 0L 127453553Stanimura#define IOTAC_MSK_SHIFT 16L 127553553Stanimura#endif 127653553Stanimura 127753553Stanimura/***************************************************************************** 127853553Stanimura * 127953553Stanimura * The following defines are for the flags in the I/O trap fast read registers 128053553Stanimura * (all 8). 128153553Stanimura * 128253553Stanimura *****************************************************************************/ 128353553Stanimura#ifndef NO_CS4612 128453553Stanimura#define IOTFR_D_MASK 0x0000FFFFL 128553553Stanimura#define IOTFR_A_MASK 0x000F0000L 128653553Stanimura#define IOTFR_R_MASK 0x0F000000L 128753553Stanimura#define IOTFR_ALL 0x40000000L 128853553Stanimura#define IOTFR_VL 0x80000000L 128953553Stanimura#define IOTFR_D_SHIFT 0L 129053553Stanimura#define IOTFR_A_SHIFT 16L 129153553Stanimura#define IOTFR_R_SHIFT 24L 129253553Stanimura#endif 129353553Stanimura 129453553Stanimura/***************************************************************************** 129553553Stanimura * 129653553Stanimura * The following defines are for the flags in the I/O trap FIFO register. 129753553Stanimura * 129853553Stanimura *****************************************************************************/ 129953553Stanimura#ifndef NO_CS4612 130053553Stanimura#define IOTFIFO_BA_MASK 0x00003FFFL 130153553Stanimura#define IOTFIFO_S_MASK 0x00FF0000L 130253553Stanimura#define IOTFIFO_OF 0x40000000L 130353553Stanimura#define IOTFIFO_SPIOF 0x80000000L 130453553Stanimura#define IOTFIFO_BA_SHIFT 0L 130553553Stanimura#define IOTFIFO_S_SHIFT 16L 130653553Stanimura#endif 130753553Stanimura 130853553Stanimura/***************************************************************************** 130953553Stanimura * 131053553Stanimura * The following defines are for the flags in the I/O trap retry read data 131153553Stanimura * register. 131253553Stanimura * 131353553Stanimura *****************************************************************************/ 131453553Stanimura#ifndef NO_CS4612 131553553Stanimura#define IOTRRD_D_MASK 0x0000FFFFL 131653553Stanimura#define IOTRRD_RDV 0x80000000L 131753553Stanimura#define IOTRRD_D_SHIFT 0L 131853553Stanimura#endif 131953553Stanimura 132053553Stanimura/***************************************************************************** 132153553Stanimura * 132253553Stanimura * The following defines are for the flags in the I/O trap FIFO pointer 132353553Stanimura * register. 132453553Stanimura * 132553553Stanimura *****************************************************************************/ 132653553Stanimura#ifndef NO_CS4612 132753553Stanimura#define IOTFP_CA_MASK 0x00003FFFL 132853553Stanimura#define IOTFP_PA_MASK 0x3FFF0000L 132953553Stanimura#define IOTFP_CA_SHIFT 0L 133053553Stanimura#define IOTFP_PA_SHIFT 16L 133153553Stanimura#endif 133253553Stanimura 133353553Stanimura/***************************************************************************** 133453553Stanimura * 133553553Stanimura * The following defines are for the flags in the I/O trap control register. 133653553Stanimura * 133753553Stanimura *****************************************************************************/ 133853553Stanimura#ifndef NO_CS4612 133953553Stanimura#define IOTCR_ITD 0x00000001L 134053553Stanimura#define IOTCR_HRV 0x00000002L 134153553Stanimura#define IOTCR_SRV 0x00000004L 134253553Stanimura#define IOTCR_DTI 0x00000008L 134353553Stanimura#define IOTCR_DFI 0x00000010L 134453553Stanimura#define IOTCR_DDP 0x00000020L 134553553Stanimura#define IOTCR_JTE 0x00000040L 134653553Stanimura#define IOTCR_PPE 0x00000080L 134753553Stanimura#endif 134853553Stanimura 134953553Stanimura/***************************************************************************** 135053553Stanimura * 135153553Stanimura * The following defines are for the flags in the direct PCI data register. 135253553Stanimura * 135353553Stanimura *****************************************************************************/ 135453553Stanimura#ifndef NO_CS4612 135553553Stanimura#define DPCID_D_MASK 0xFFFFFFFFL 135653553Stanimura#define DPCID_D_SHIFT 0L 135753553Stanimura#endif 135853553Stanimura 135953553Stanimura/***************************************************************************** 136053553Stanimura * 136153553Stanimura * The following defines are for the flags in the direct PCI address register. 136253553Stanimura * 136353553Stanimura *****************************************************************************/ 136453553Stanimura#ifndef NO_CS4612 136553553Stanimura#define DPCIA_A_MASK 0xFFFFFFFFL 136653553Stanimura#define DPCIA_A_SHIFT 0L 136753553Stanimura#endif 136853553Stanimura 136953553Stanimura/***************************************************************************** 137053553Stanimura * 137153553Stanimura * The following defines are for the flags in the direct PCI command register. 137253553Stanimura * 137353553Stanimura *****************************************************************************/ 137453553Stanimura#ifndef NO_CS4612 137553553Stanimura#define DPCIC_C_MASK 0x0000000FL 137653553Stanimura#define DPCIC_C_IOREAD 0x00000002L 137753553Stanimura#define DPCIC_C_IOWRITE 0x00000003L 137853553Stanimura#define DPCIC_BE_MASK 0x000000F0L 137953553Stanimura#endif 138053553Stanimura 138153553Stanimura/***************************************************************************** 138253553Stanimura * 138353553Stanimura * The following defines are for the flags in the PC/PCI request register. 138453553Stanimura * 138553553Stanimura *****************************************************************************/ 138653553Stanimura#ifndef NO_CS4612 138753553Stanimura#define PCPCIR_RDC_MASK 0x00000007L 138853553Stanimura#define PCPCIR_C_MASK 0x00007000L 138953553Stanimura#define PCPCIR_REQ 0x00008000L 139053553Stanimura#define PCPCIR_RDC_SHIFT 0L 139153553Stanimura#define PCPCIR_C_SHIFT 12L 139253553Stanimura#endif 139353553Stanimura 139453553Stanimura/***************************************************************************** 139553553Stanimura * 139653553Stanimura * The following defines are for the flags in the PC/PCI grant register. 139753553Stanimura * 139853553Stanimura *****************************************************************************/ 139953553Stanimura#ifndef NO_CS4612 140053553Stanimura#define PCPCIG_GDC_MASK 0x00000007L 140153553Stanimura#define PCPCIG_VL 0x00008000L 140253553Stanimura#define PCPCIG_GDC_SHIFT 0L 140353553Stanimura#endif 140453553Stanimura 140553553Stanimura/***************************************************************************** 140653553Stanimura * 140753553Stanimura * The following defines are for the flags in the PC/PCI master enable 140853553Stanimura * register. 140953553Stanimura * 141053553Stanimura *****************************************************************************/ 141153553Stanimura#ifndef NO_CS4612 141253553Stanimura#define PCPCIEN_EN 0x00000001L 141353553Stanimura#endif 141453553Stanimura 141553553Stanimura/***************************************************************************** 141653553Stanimura * 141753553Stanimura * The following defines are for the flags in the extended PCI power 141853553Stanimura * management control register. 141953553Stanimura * 142053553Stanimura *****************************************************************************/ 142153553Stanimura#ifndef NO_CS4612 142253553Stanimura#define EPCIPMC_GWU 0x00000001L 142353553Stanimura#define EPCIPMC_FSPC 0x00000002L 142453553Stanimura#endif 142553553Stanimura 142653553Stanimura/***************************************************************************** 142753553Stanimura * 142853553Stanimura * The following defines are for the flags in the SP control register. 142953553Stanimura * 143053553Stanimura *****************************************************************************/ 143153553Stanimura#define SPCR_RUN 0x00000001L 143253553Stanimura#define SPCR_STPFR 0x00000002L 143353553Stanimura#define SPCR_RUNFR 0x00000004L 143453553Stanimura#define SPCR_TICK 0x00000008L 143553553Stanimura#define SPCR_DRQEN 0x00000020L 143653553Stanimura#define SPCR_RSTSP 0x00000040L 143753553Stanimura#define SPCR_OREN 0x00000080L 143853553Stanimura#ifndef NO_CS4612 143953553Stanimura#define SPCR_PCIINT 0x00000100L 144053553Stanimura#define SPCR_OINTD 0x00000200L 144153553Stanimura#define SPCR_CRE 0x00008000L 144253553Stanimura#endif 144353553Stanimura 144453553Stanimura/***************************************************************************** 144553553Stanimura * 144653553Stanimura * The following defines are for the flags in the debug index register. 144753553Stanimura * 144853553Stanimura *****************************************************************************/ 144953553Stanimura#define DREG_REGID_MASK 0x0000007FL 145053553Stanimura#define DREG_DEBUG 0x00000080L 145153553Stanimura#define DREG_RGBK_MASK 0x00000700L 145253553Stanimura#define DREG_TRAP 0x00000800L 145353553Stanimura#if !defined(NO_CS4612) 145453553Stanimura#if !defined(NO_CS4615) 145553553Stanimura#define DREG_TRAPX 0x00001000L 145653553Stanimura#endif 145753553Stanimura#endif 145853553Stanimura#define DREG_REGID_SHIFT 0L 145953553Stanimura#define DREG_RGBK_SHIFT 8L 146053553Stanimura#define DREG_RGBK_REGID_MASK 0x0000077FL 146153553Stanimura#define DREG_REGID_R0 0x00000010L 146253553Stanimura#define DREG_REGID_R1 0x00000011L 146353553Stanimura#define DREG_REGID_R2 0x00000012L 146453553Stanimura#define DREG_REGID_R3 0x00000013L 146553553Stanimura#define DREG_REGID_R4 0x00000014L 146653553Stanimura#define DREG_REGID_R5 0x00000015L 146753553Stanimura#define DREG_REGID_R6 0x00000016L 146853553Stanimura#define DREG_REGID_R7 0x00000017L 146953553Stanimura#define DREG_REGID_R8 0x00000018L 147053553Stanimura#define DREG_REGID_R9 0x00000019L 147153553Stanimura#define DREG_REGID_RA 0x0000001AL 147253553Stanimura#define DREG_REGID_RB 0x0000001BL 147353553Stanimura#define DREG_REGID_RC 0x0000001CL 147453553Stanimura#define DREG_REGID_RD 0x0000001DL 147553553Stanimura#define DREG_REGID_RE 0x0000001EL 147653553Stanimura#define DREG_REGID_RF 0x0000001FL 147753553Stanimura#define DREG_REGID_RA_BUS_LOW 0x00000020L 147853553Stanimura#define DREG_REGID_RA_BUS_HIGH 0x00000038L 147953553Stanimura#define DREG_REGID_YBUS_LOW 0x00000050L 148053553Stanimura#define DREG_REGID_YBUS_HIGH 0x00000058L 148153553Stanimura#define DREG_REGID_TRAP_0 0x00000100L 148253553Stanimura#define DREG_REGID_TRAP_1 0x00000101L 148353553Stanimura#define DREG_REGID_TRAP_2 0x00000102L 148453553Stanimura#define DREG_REGID_TRAP_3 0x00000103L 148553553Stanimura#define DREG_REGID_TRAP_4 0x00000104L 148653553Stanimura#define DREG_REGID_TRAP_5 0x00000105L 148753553Stanimura#define DREG_REGID_TRAP_6 0x00000106L 148853553Stanimura#define DREG_REGID_TRAP_7 0x00000107L 148953553Stanimura#define DREG_REGID_INDIRECT_ADDRESS 0x0000010EL 149053553Stanimura#define DREG_REGID_TOP_OF_STACK 0x0000010FL 149153553Stanimura#if !defined(NO_CS4612) 149253553Stanimura#if !defined(NO_CS4615) 149353553Stanimura#define DREG_REGID_TRAP_8 0x00000110L 149453553Stanimura#define DREG_REGID_TRAP_9 0x00000111L 149553553Stanimura#define DREG_REGID_TRAP_10 0x00000112L 149653553Stanimura#define DREG_REGID_TRAP_11 0x00000113L 149753553Stanimura#define DREG_REGID_TRAP_12 0x00000114L 149853553Stanimura#define DREG_REGID_TRAP_13 0x00000115L 149953553Stanimura#define DREG_REGID_TRAP_14 0x00000116L 150053553Stanimura#define DREG_REGID_TRAP_15 0x00000117L 150153553Stanimura#define DREG_REGID_TRAP_16 0x00000118L 150253553Stanimura#define DREG_REGID_TRAP_17 0x00000119L 150353553Stanimura#define DREG_REGID_TRAP_18 0x0000011AL 150453553Stanimura#define DREG_REGID_TRAP_19 0x0000011BL 150553553Stanimura#define DREG_REGID_TRAP_20 0x0000011CL 150653553Stanimura#define DREG_REGID_TRAP_21 0x0000011DL 150753553Stanimura#define DREG_REGID_TRAP_22 0x0000011EL 150853553Stanimura#define DREG_REGID_TRAP_23 0x0000011FL 150953553Stanimura#endif 151053553Stanimura#endif 151153553Stanimura#define DREG_REGID_RSA0_LOW 0x00000200L 151253553Stanimura#define DREG_REGID_RSA0_HIGH 0x00000201L 151353553Stanimura#define DREG_REGID_RSA1_LOW 0x00000202L 151453553Stanimura#define DREG_REGID_RSA1_HIGH 0x00000203L 151553553Stanimura#define DREG_REGID_RSA2 0x00000204L 151653553Stanimura#define DREG_REGID_RSA3 0x00000205L 151753553Stanimura#define DREG_REGID_RSI0_LOW 0x00000206L 151853553Stanimura#define DREG_REGID_RSI0_HIGH 0x00000207L 151953553Stanimura#define DREG_REGID_RSI1 0x00000208L 152053553Stanimura#define DREG_REGID_RSI2 0x00000209L 152153553Stanimura#define DREG_REGID_SAGUSTATUS 0x0000020AL 152253553Stanimura#define DREG_REGID_RSCONFIG01_LOW 0x0000020BL 152353553Stanimura#define DREG_REGID_RSCONFIG01_HIGH 0x0000020CL 152453553Stanimura#define DREG_REGID_RSCONFIG23_LOW 0x0000020DL 152553553Stanimura#define DREG_REGID_RSCONFIG23_HIGH 0x0000020EL 152653553Stanimura#define DREG_REGID_RSDMA01E 0x0000020FL 152753553Stanimura#define DREG_REGID_RSDMA23E 0x00000210L 152853553Stanimura#define DREG_REGID_RSD0_LOW 0x00000211L 152953553Stanimura#define DREG_REGID_RSD0_HIGH 0x00000212L 153053553Stanimura#define DREG_REGID_RSD1_LOW 0x00000213L 153153553Stanimura#define DREG_REGID_RSD1_HIGH 0x00000214L 153253553Stanimura#define DREG_REGID_RSD2_LOW 0x00000215L 153353553Stanimura#define DREG_REGID_RSD2_HIGH 0x00000216L 153453553Stanimura#define DREG_REGID_RSD3_LOW 0x00000217L 153553553Stanimura#define DREG_REGID_RSD3_HIGH 0x00000218L 153653553Stanimura#define DREG_REGID_SRAR_HIGH 0x0000021AL 153753553Stanimura#define DREG_REGID_SRAR_LOW 0x0000021BL 153853553Stanimura#define DREG_REGID_DMA_STATE 0x0000021CL 153953553Stanimura#define DREG_REGID_CURRENT_DMA_STREAM 0x0000021DL 154053553Stanimura#define DREG_REGID_NEXT_DMA_STREAM 0x0000021EL 154153553Stanimura#define DREG_REGID_CPU_STATUS 0x00000300L 154253553Stanimura#define DREG_REGID_MAC_MODE 0x00000301L 154353553Stanimura#define DREG_REGID_STACK_AND_REPEAT 0x00000302L 154453553Stanimura#define DREG_REGID_INDEX0 0x00000304L 154553553Stanimura#define DREG_REGID_INDEX1 0x00000305L 154653553Stanimura#define DREG_REGID_DMA_STATE_0_3 0x00000400L 154753553Stanimura#define DREG_REGID_DMA_STATE_4_7 0x00000404L 154853553Stanimura#define DREG_REGID_DMA_STATE_8_11 0x00000408L 154953553Stanimura#define DREG_REGID_DMA_STATE_12_15 0x0000040CL 155053553Stanimura#define DREG_REGID_DMA_STATE_16_19 0x00000410L 155153553Stanimura#define DREG_REGID_DMA_STATE_20_23 0x00000414L 155253553Stanimura#define DREG_REGID_DMA_STATE_24_27 0x00000418L 155353553Stanimura#define DREG_REGID_DMA_STATE_28_31 0x0000041CL 155453553Stanimura#define DREG_REGID_DMA_STATE_32_35 0x00000420L 155553553Stanimura#define DREG_REGID_DMA_STATE_36_39 0x00000424L 155653553Stanimura#define DREG_REGID_DMA_STATE_40_43 0x00000428L 155753553Stanimura#define DREG_REGID_DMA_STATE_44_47 0x0000042CL 155853553Stanimura#define DREG_REGID_DMA_STATE_48_51 0x00000430L 155953553Stanimura#define DREG_REGID_DMA_STATE_52_55 0x00000434L 156053553Stanimura#define DREG_REGID_DMA_STATE_56_59 0x00000438L 156153553Stanimura#define DREG_REGID_DMA_STATE_60_63 0x0000043CL 156253553Stanimura#define DREG_REGID_DMA_STATE_64_67 0x00000440L 156353553Stanimura#define DREG_REGID_DMA_STATE_68_71 0x00000444L 156453553Stanimura#define DREG_REGID_DMA_STATE_72_75 0x00000448L 156553553Stanimura#define DREG_REGID_DMA_STATE_76_79 0x0000044CL 156653553Stanimura#define DREG_REGID_DMA_STATE_80_83 0x00000450L 156753553Stanimura#define DREG_REGID_DMA_STATE_84_87 0x00000454L 156853553Stanimura#define DREG_REGID_DMA_STATE_88_91 0x00000458L 156953553Stanimura#define DREG_REGID_DMA_STATE_92_95 0x0000045CL 157053553Stanimura#define DREG_REGID_TRAP_SELECT 0x00000500L 157153553Stanimura#define DREG_REGID_TRAP_WRITE_0 0x00000500L 157253553Stanimura#define DREG_REGID_TRAP_WRITE_1 0x00000501L 157353553Stanimura#define DREG_REGID_TRAP_WRITE_2 0x00000502L 157453553Stanimura#define DREG_REGID_TRAP_WRITE_3 0x00000503L 157553553Stanimura#define DREG_REGID_TRAP_WRITE_4 0x00000504L 157653553Stanimura#define DREG_REGID_TRAP_WRITE_5 0x00000505L 157753553Stanimura#define DREG_REGID_TRAP_WRITE_6 0x00000506L 157853553Stanimura#define DREG_REGID_TRAP_WRITE_7 0x00000507L 157953553Stanimura#if !defined(NO_CS4612) 158053553Stanimura#if !defined(NO_CS4615) 158153553Stanimura#define DREG_REGID_TRAP_WRITE_8 0x00000510L 158253553Stanimura#define DREG_REGID_TRAP_WRITE_9 0x00000511L 158353553Stanimura#define DREG_REGID_TRAP_WRITE_10 0x00000512L 158453553Stanimura#define DREG_REGID_TRAP_WRITE_11 0x00000513L 158553553Stanimura#define DREG_REGID_TRAP_WRITE_12 0x00000514L 158653553Stanimura#define DREG_REGID_TRAP_WRITE_13 0x00000515L 158753553Stanimura#define DREG_REGID_TRAP_WRITE_14 0x00000516L 158853553Stanimura#define DREG_REGID_TRAP_WRITE_15 0x00000517L 158953553Stanimura#define DREG_REGID_TRAP_WRITE_16 0x00000518L 159053553Stanimura#define DREG_REGID_TRAP_WRITE_17 0x00000519L 159153553Stanimura#define DREG_REGID_TRAP_WRITE_18 0x0000051AL 159253553Stanimura#define DREG_REGID_TRAP_WRITE_19 0x0000051BL 159353553Stanimura#define DREG_REGID_TRAP_WRITE_20 0x0000051CL 159453553Stanimura#define DREG_REGID_TRAP_WRITE_21 0x0000051DL 159553553Stanimura#define DREG_REGID_TRAP_WRITE_22 0x0000051EL 159653553Stanimura#define DREG_REGID_TRAP_WRITE_23 0x0000051FL 159753553Stanimura#endif 159853553Stanimura#endif 159953553Stanimura#define DREG_REGID_MAC0_ACC0_LOW 0x00000600L 160053553Stanimura#define DREG_REGID_MAC0_ACC1_LOW 0x00000601L 160153553Stanimura#define DREG_REGID_MAC0_ACC2_LOW 0x00000602L 160253553Stanimura#define DREG_REGID_MAC0_ACC3_LOW 0x00000603L 160353553Stanimura#define DREG_REGID_MAC1_ACC0_LOW 0x00000604L 160453553Stanimura#define DREG_REGID_MAC1_ACC1_LOW 0x00000605L 160553553Stanimura#define DREG_REGID_MAC1_ACC2_LOW 0x00000606L 160653553Stanimura#define DREG_REGID_MAC1_ACC3_LOW 0x00000607L 160753553Stanimura#define DREG_REGID_MAC0_ACC0_MID 0x00000608L 160853553Stanimura#define DREG_REGID_MAC0_ACC1_MID 0x00000609L 160953553Stanimura#define DREG_REGID_MAC0_ACC2_MID 0x0000060AL 161053553Stanimura#define DREG_REGID_MAC0_ACC3_MID 0x0000060BL 161153553Stanimura#define DREG_REGID_MAC1_ACC0_MID 0x0000060CL 161253553Stanimura#define DREG_REGID_MAC1_ACC1_MID 0x0000060DL 161353553Stanimura#define DREG_REGID_MAC1_ACC2_MID 0x0000060EL 161453553Stanimura#define DREG_REGID_MAC1_ACC3_MID 0x0000060FL 161553553Stanimura#define DREG_REGID_MAC0_ACC0_HIGH 0x00000610L 161653553Stanimura#define DREG_REGID_MAC0_ACC1_HIGH 0x00000611L 161753553Stanimura#define DREG_REGID_MAC0_ACC2_HIGH 0x00000612L 161853553Stanimura#define DREG_REGID_MAC0_ACC3_HIGH 0x00000613L 161953553Stanimura#define DREG_REGID_MAC1_ACC0_HIGH 0x00000614L 162053553Stanimura#define DREG_REGID_MAC1_ACC1_HIGH 0x00000615L 162153553Stanimura#define DREG_REGID_MAC1_ACC2_HIGH 0x00000616L 162253553Stanimura#define DREG_REGID_MAC1_ACC3_HIGH 0x00000617L 162353553Stanimura#define DREG_REGID_RSHOUT_LOW 0x00000620L 162453553Stanimura#define DREG_REGID_RSHOUT_MID 0x00000628L 162553553Stanimura#define DREG_REGID_RSHOUT_HIGH 0x00000630L 162653553Stanimura 162753553Stanimura/***************************************************************************** 162853553Stanimura * 162953553Stanimura * The following defines are for the flags in the DMA stream requestor write 163053553Stanimura * port register. 163153553Stanimura * 163253553Stanimura *****************************************************************************/ 163353553Stanimura#define DSRWP_DSR_MASK 0x0000000FL 163453553Stanimura#define DSRWP_DSR_BG_RQ 0x00000001L 163553553Stanimura#define DSRWP_DSR_PRIORITY_MASK 0x00000006L 163653553Stanimura#define DSRWP_DSR_PRIORITY_0 0x00000000L 163753553Stanimura#define DSRWP_DSR_PRIORITY_1 0x00000002L 163853553Stanimura#define DSRWP_DSR_PRIORITY_2 0x00000004L 163953553Stanimura#define DSRWP_DSR_PRIORITY_3 0x00000006L 164053553Stanimura#define DSRWP_DSR_RQ_PENDING 0x00000008L 164153553Stanimura 164253553Stanimura/***************************************************************************** 164353553Stanimura * 164453553Stanimura * The following defines are for the flags in the trap write port register. 164553553Stanimura * 164653553Stanimura *****************************************************************************/ 164753553Stanimura#define TWPR_TW_MASK 0x0000FFFFL 164853553Stanimura#define TWPR_TW_SHIFT 0L 164953553Stanimura 165053553Stanimura/***************************************************************************** 165153553Stanimura * 165253553Stanimura * The following defines are for the flags in the stack pointer write 165353553Stanimura * register. 165453553Stanimura * 165553553Stanimura *****************************************************************************/ 165653553Stanimura#define SPWR_STKP_MASK 0x0000000FL 165753553Stanimura#define SPWR_STKP_SHIFT 0L 165853553Stanimura 165953553Stanimura/***************************************************************************** 166053553Stanimura * 166153553Stanimura * The following defines are for the flags in the SP interrupt register. 166253553Stanimura * 166353553Stanimura *****************************************************************************/ 166453553Stanimura#define SPIR_FRI 0x00000001L 166553553Stanimura#define SPIR_DOI 0x00000002L 166653553Stanimura#define SPIR_GPI2 0x00000004L 166753553Stanimura#define SPIR_GPI3 0x00000008L 166853553Stanimura#define SPIR_IP0 0x00000010L 166953553Stanimura#define SPIR_IP1 0x00000020L 167053553Stanimura#define SPIR_IP2 0x00000040L 167153553Stanimura#define SPIR_IP3 0x00000080L 167253553Stanimura 167353553Stanimura/***************************************************************************** 167453553Stanimura * 167553553Stanimura * The following defines are for the flags in the functional group 1 register. 167653553Stanimura * 167753553Stanimura *****************************************************************************/ 167853553Stanimura#define FGR1_F1S_MASK 0x0000FFFFL 167953553Stanimura#define FGR1_F1S_SHIFT 0L 168053553Stanimura 168153553Stanimura/***************************************************************************** 168253553Stanimura * 168353553Stanimura * The following defines are for the flags in the SP clock status register. 168453553Stanimura * 168553553Stanimura *****************************************************************************/ 168653553Stanimura#define SPCS_FRI 0x00000001L 168753553Stanimura#define SPCS_DOI 0x00000002L 168853553Stanimura#define SPCS_GPI2 0x00000004L 168953553Stanimura#define SPCS_GPI3 0x00000008L 169053553Stanimura#define SPCS_IP0 0x00000010L 169153553Stanimura#define SPCS_IP1 0x00000020L 169253553Stanimura#define SPCS_IP2 0x00000040L 169353553Stanimura#define SPCS_IP3 0x00000080L 169453553Stanimura#define SPCS_SPRUN 0x00000100L 169553553Stanimura#define SPCS_SLEEP 0x00000200L 169653553Stanimura#define SPCS_FG 0x00000400L 169753553Stanimura#define SPCS_ORUN 0x00000800L 169853553Stanimura#define SPCS_IRQ 0x00001000L 169953553Stanimura#define SPCS_FGN_MASK 0x0000E000L 170053553Stanimura#define SPCS_FGN_SHIFT 13L 170153553Stanimura 170253553Stanimura/***************************************************************************** 170353553Stanimura * 170453553Stanimura * The following defines are for the flags in the SP DMA requestor status 170553553Stanimura * register. 170653553Stanimura * 170753553Stanimura *****************************************************************************/ 170853553Stanimura#define SDSR_DCS_MASK 0x000000FFL 170953553Stanimura#define SDSR_DCS_SHIFT 0L 171053553Stanimura#define SDSR_DCS_NONE 0x00000007L 171153553Stanimura 171253553Stanimura/***************************************************************************** 171353553Stanimura * 171453553Stanimura * The following defines are for the flags in the frame timer register. 171553553Stanimura * 171653553Stanimura *****************************************************************************/ 171753553Stanimura#define FRMT_FTV_MASK 0x0000FFFFL 171853553Stanimura#define FRMT_FTV_SHIFT 0L 171953553Stanimura 172053553Stanimura/***************************************************************************** 172153553Stanimura * 172253553Stanimura * The following defines are for the flags in the frame timer current count 172353553Stanimura * register. 172453553Stanimura * 172553553Stanimura *****************************************************************************/ 172653553Stanimura#define FRCC_FCC_MASK 0x0000FFFFL 172753553Stanimura#define FRCC_FCC_SHIFT 0L 172853553Stanimura 172953553Stanimura/***************************************************************************** 173053553Stanimura * 173153553Stanimura * The following defines are for the flags in the frame timer save count 173253553Stanimura * register. 173353553Stanimura * 173453553Stanimura *****************************************************************************/ 173553553Stanimura#define FRSC_FCS_MASK 0x0000FFFFL 173653553Stanimura#define FRSC_FCS_SHIFT 0L 173753553Stanimura 173853553Stanimura/***************************************************************************** 173953553Stanimura * 174053553Stanimura * The following define the various flags stored in the scatter/gather 174153553Stanimura * descriptors. 174253553Stanimura * 174353553Stanimura *****************************************************************************/ 174453553Stanimura#define DMA_SG_NEXT_ENTRY_MASK 0x00000FF8L 174553553Stanimura#define DMA_SG_SAMPLE_END_MASK 0x0FFF0000L 174653553Stanimura#define DMA_SG_SAMPLE_END_FLAG 0x10000000L 174753553Stanimura#define DMA_SG_LOOP_END_FLAG 0x20000000L 174853553Stanimura#define DMA_SG_SIGNAL_END_FLAG 0x40000000L 174953553Stanimura#define DMA_SG_SIGNAL_PAGE_FLAG 0x80000000L 175053553Stanimura#define DMA_SG_NEXT_ENTRY_SHIFT 3L 175153553Stanimura#define DMA_SG_SAMPLE_END_SHIFT 16L 175253553Stanimura 175353553Stanimura/***************************************************************************** 175453553Stanimura * 175553553Stanimura * The following define the offsets of the fields within the on-chip generic 175653553Stanimura * DMA requestor. 175753553Stanimura * 175853553Stanimura *****************************************************************************/ 175953553Stanimura#define DMA_RQ_CONTROL1 0x00000000L 176053553Stanimura#define DMA_RQ_CONTROL2 0x00000004L 176153553Stanimura#define DMA_RQ_SOURCE_ADDR 0x00000008L 176253553Stanimura#define DMA_RQ_DESTINATION_ADDR 0x0000000CL 176353553Stanimura#define DMA_RQ_NEXT_PAGE_ADDR 0x00000010L 176453553Stanimura#define DMA_RQ_NEXT_PAGE_SGDESC 0x00000014L 176553553Stanimura#define DMA_RQ_LOOP_START_ADDR 0x00000018L 176653553Stanimura#define DMA_RQ_POST_LOOP_ADDR 0x0000001CL 176753553Stanimura#define DMA_RQ_PAGE_MAP_ADDR 0x00000020L 176853553Stanimura 176953553Stanimura/***************************************************************************** 177053553Stanimura * 177153553Stanimura * The following defines are for the flags in the first control word of the 177253553Stanimura * on-chip generic DMA requestor. 177353553Stanimura * 177453553Stanimura *****************************************************************************/ 177553553Stanimura#define DMA_RQ_C1_COUNT_MASK 0x000003FFL 177653553Stanimura#define DMA_RQ_C1_DESTINATION_SCATTER 0x00001000L 177753553Stanimura#define DMA_RQ_C1_SOURCE_GATHER 0x00002000L 177853553Stanimura#define DMA_RQ_C1_DONE_FLAG 0x00004000L 177953553Stanimura#define DMA_RQ_C1_OPTIMIZE_STATE 0x00008000L 178053553Stanimura#define DMA_RQ_C1_SAMPLE_END_STATE_MASK 0x00030000L 178153553Stanimura#define DMA_RQ_C1_FULL_PAGE 0x00000000L 178253553Stanimura#define DMA_RQ_C1_BEFORE_SAMPLE_END 0x00010000L 178353553Stanimura#define DMA_RQ_C1_PAGE_MAP_ERROR 0x00020000L 178453553Stanimura#define DMA_RQ_C1_AT_SAMPLE_END 0x00030000L 178553553Stanimura#define DMA_RQ_C1_LOOP_END_STATE_MASK 0x000C0000L 178653553Stanimura#define DMA_RQ_C1_NOT_LOOP_END 0x00000000L 178753553Stanimura#define DMA_RQ_C1_BEFORE_LOOP_END 0x00040000L 178853553Stanimura#define DMA_RQ_C1_2PAGE_LOOP_BEGIN 0x00080000L 178953553Stanimura#define DMA_RQ_C1_LOOP_BEGIN 0x000C0000L 179053553Stanimura#define DMA_RQ_C1_PAGE_MAP_MASK 0x00300000L 179153553Stanimura#define DMA_RQ_C1_PM_NONE_PENDING 0x00000000L 179253553Stanimura#define DMA_RQ_C1_PM_NEXT_PENDING 0x00100000L 179353553Stanimura#define DMA_RQ_C1_PM_RESERVED 0x00200000L 179453553Stanimura#define DMA_RQ_C1_PM_LOOP_NEXT_PENDING 0x00300000L 179553553Stanimura#define DMA_RQ_C1_WRITEBACK_DEST_FLAG 0x00400000L 179653553Stanimura#define DMA_RQ_C1_WRITEBACK_SRC_FLAG 0x00800000L 179753553Stanimura#define DMA_RQ_C1_DEST_SIZE_MASK 0x07000000L 179853553Stanimura#define DMA_RQ_C1_DEST_LINEAR 0x00000000L 179953553Stanimura#define DMA_RQ_C1_DEST_MOD16 0x01000000L 180053553Stanimura#define DMA_RQ_C1_DEST_MOD32 0x02000000L 180153553Stanimura#define DMA_RQ_C1_DEST_MOD64 0x03000000L 180253553Stanimura#define DMA_RQ_C1_DEST_MOD128 0x04000000L 180353553Stanimura#define DMA_RQ_C1_DEST_MOD256 0x05000000L 180453553Stanimura#define DMA_RQ_C1_DEST_MOD512 0x06000000L 180553553Stanimura#define DMA_RQ_C1_DEST_MOD1024 0x07000000L 180653553Stanimura#define DMA_RQ_C1_DEST_ON_HOST 0x08000000L 180753553Stanimura#define DMA_RQ_C1_SOURCE_SIZE_MASK 0x70000000L 180853553Stanimura#define DMA_RQ_C1_SOURCE_LINEAR 0x00000000L 180953553Stanimura#define DMA_RQ_C1_SOURCE_MOD16 0x10000000L 181053553Stanimura#define DMA_RQ_C1_SOURCE_MOD32 0x20000000L 181153553Stanimura#define DMA_RQ_C1_SOURCE_MOD64 0x30000000L 181253553Stanimura#define DMA_RQ_C1_SOURCE_MOD128 0x40000000L 181353553Stanimura#define DMA_RQ_C1_SOURCE_MOD256 0x50000000L 181453553Stanimura#define DMA_RQ_C1_SOURCE_MOD512 0x60000000L 181553553Stanimura#define DMA_RQ_C1_SOURCE_MOD1024 0x70000000L 181653553Stanimura#define DMA_RQ_C1_SOURCE_ON_HOST 0x80000000L 181753553Stanimura#define DMA_RQ_C1_COUNT_SHIFT 0L 181853553Stanimura 181953553Stanimura/***************************************************************************** 182053553Stanimura * 182153553Stanimura * The following defines are for the flags in the second control word of the 182253553Stanimura * on-chip generic DMA requestor. 182353553Stanimura * 182453553Stanimura *****************************************************************************/ 182553553Stanimura#define DMA_RQ_C2_VIRTUAL_CHANNEL_MASK 0x0000003FL 182653553Stanimura#define DMA_RQ_C2_VIRTUAL_SIGNAL_MASK 0x00000300L 182753553Stanimura#define DMA_RQ_C2_NO_VIRTUAL_SIGNAL 0x00000000L 182853553Stanimura#define DMA_RQ_C2_SIGNAL_EVERY_DMA 0x00000100L 182953553Stanimura#define DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG 0x00000200L 183053553Stanimura#define DMA_RQ_C2_SIGNAL_DEST_PINGPONG 0x00000300L 183153553Stanimura#define DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000L 183253553Stanimura#define DMA_RQ_C2_AC_NONE 0x00000000L 183353553Stanimura#define DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000L 183453553Stanimura#define DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000L 183553553Stanimura#define DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000L 183653553Stanimura#define DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000L 183753553Stanimura#define DMA_RQ_C2_LOOP_END_MASK 0x0FFF0000L 183853553Stanimura#define DMA_RQ_C2_LOOP_MASK 0x30000000L 183953553Stanimura#define DMA_RQ_C2_NO_LOOP 0x00000000L 184053553Stanimura#define DMA_RQ_C2_ONE_PAGE_LOOP 0x10000000L 184153553Stanimura#define DMA_RQ_C2_TWO_PAGE_LOOP 0x20000000L 184253553Stanimura#define DMA_RQ_C2_MULTI_PAGE_LOOP 0x30000000L 184353553Stanimura#define DMA_RQ_C2_SIGNAL_LOOP_BACK 0x40000000L 184453553Stanimura#define DMA_RQ_C2_SIGNAL_POST_BEGIN_PAGE 0x80000000L 184553553Stanimura#define DMA_RQ_C2_VIRTUAL_CHANNEL_SHIFT 0L 184653553Stanimura#define DMA_RQ_C2_LOOP_END_SHIFT 16L 184753553Stanimura 184853553Stanimura/***************************************************************************** 184953553Stanimura * 185053553Stanimura * The following defines are for the flags in the source and destination words 185153553Stanimura * of the on-chip generic DMA requestor. 185253553Stanimura * 185353553Stanimura *****************************************************************************/ 185453553Stanimura#define DMA_RQ_SD_ADDRESS_MASK 0x0000FFFFL 185553553Stanimura#define DMA_RQ_SD_MEMORY_ID_MASK 0x000F0000L 185653553Stanimura#define DMA_RQ_SD_SP_PARAM_ADDR 0x00000000L 185753553Stanimura#define DMA_RQ_SD_SP_SAMPLE_ADDR 0x00010000L 185853553Stanimura#define DMA_RQ_SD_SP_PROGRAM_ADDR 0x00020000L 185953553Stanimura#define DMA_RQ_SD_SP_DEBUG_ADDR 0x00030000L 186053553Stanimura#define DMA_RQ_SD_OMNIMEM_ADDR 0x000E0000L 186153553Stanimura#define DMA_RQ_SD_END_FLAG 0x40000000L 186253553Stanimura#define DMA_RQ_SD_ERROR_FLAG 0x80000000L 186353553Stanimura#define DMA_RQ_SD_ADDRESS_SHIFT 0L 186453553Stanimura 186553553Stanimura/***************************************************************************** 186653553Stanimura * 186753553Stanimura * The following defines are for the flags in the page map address word of the 186853553Stanimura * on-chip generic DMA requestor. 186953553Stanimura * 187053553Stanimura *****************************************************************************/ 187153553Stanimura#define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_MASK 0x00000FF8L 187253553Stanimura#define DMA_RQ_PMA_PAGE_TABLE_MASK 0xFFFFF000L 187353553Stanimura#define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_SHIFT 3L 187453553Stanimura#define DMA_RQ_PMA_PAGE_TABLE_SHIFT 12L 187553553Stanimura 187653553Stanimura/***************************************************************************** 187753553Stanimura * 187853553Stanimura * The following defines are for the flags in the rsConfig01/23 registers of 187953553Stanimura * the SP. 188053553Stanimura * 188153553Stanimura *****************************************************************************/ 188253553Stanimura#define RSCONFIG_MODULO_SIZE_MASK 0x0000000FL 188353553Stanimura#define RSCONFIG_MODULO_16 0x00000001L 188453553Stanimura#define RSCONFIG_MODULO_32 0x00000002L 188553553Stanimura#define RSCONFIG_MODULO_64 0x00000003L 188653553Stanimura#define RSCONFIG_MODULO_128 0x00000004L 188753553Stanimura#define RSCONFIG_MODULO_256 0x00000005L 188853553Stanimura#define RSCONFIG_MODULO_512 0x00000006L 188953553Stanimura#define RSCONFIG_MODULO_1024 0x00000007L 189053553Stanimura#define RSCONFIG_MODULO_4 0x00000008L 189153553Stanimura#define RSCONFIG_MODULO_8 0x00000009L 189253553Stanimura#define RSCONFIG_SAMPLE_SIZE_MASK 0x000000C0L 189353553Stanimura#define RSCONFIG_SAMPLE_8MONO 0x00000000L 189453553Stanimura#define RSCONFIG_SAMPLE_8STEREO 0x00000040L 189553553Stanimura#define RSCONFIG_SAMPLE_16MONO 0x00000080L 189653553Stanimura#define RSCONFIG_SAMPLE_16STEREO 0x000000C0L 189753553Stanimura#define RSCONFIG_UNDERRUN_ZERO 0x00004000L 189853553Stanimura#define RSCONFIG_DMA_TO_HOST 0x00008000L 189953553Stanimura#define RSCONFIG_STREAM_NUM_MASK 0x00FF0000L 190053553Stanimura#define RSCONFIG_MAX_DMA_SIZE_MASK 0x1F000000L 190153553Stanimura#define RSCONFIG_DMA_ENABLE 0x20000000L 190253553Stanimura#define RSCONFIG_PRIORITY_MASK 0xC0000000L 190353553Stanimura#define RSCONFIG_PRIORITY_HIGH 0x00000000L 190453553Stanimura#define RSCONFIG_PRIORITY_MEDIUM_HIGH 0x40000000L 190553553Stanimura#define RSCONFIG_PRIORITY_MEDIUM_LOW 0x80000000L 190653553Stanimura#define RSCONFIG_PRIORITY_LOW 0xC0000000L 190753553Stanimura#define RSCONFIG_STREAM_NUM_SHIFT 16L 190853553Stanimura#define RSCONFIG_MAX_DMA_SIZE_SHIFT 24L 190953553Stanimura 191053553Stanimura#define BA1_VARIDEC_BUF_1 0x000 191153553Stanimura 191253553Stanimura#define BA1_PDTC 0x0c0 /* BA1_PLAY_DMA_TRANSACTION_COUNT_REG */ 191353553Stanimura#define BA1_PFIE 0x0c4 /* BA1_PLAY_FORMAT_&_INTERRUPT_ENABLE_REG */ 191453553Stanimura#define BA1_PBA 0x0c8 /* BA1_PLAY_BUFFER_ADDRESS */ 191553553Stanimura#define BA1_PVOL 0x0f8 /* BA1_PLAY_VOLUME_REG */ 191653553Stanimura#define BA1_PSRC 0x288 /* BA1_PLAY_SAMPLE_RATE_CORRECTION_REG */ 191753553Stanimura#define BA1_PCTL 0x2a4 /* BA1_PLAY_CONTROL_REG */ 191853553Stanimura#define BA1_PPI 0x2b4 /* BA1_PLAY_PHASE_INCREMENT_REG */ 191953553Stanimura 192053553Stanimura#define BA1_CCTL 0x064 /* BA1_CAPTURE_CONTROL_REG */ 192153553Stanimura#define BA1_CIE 0x104 /* BA1_CAPTURE_INTERRUPT_ENABLE_REG */ 192253553Stanimura#define BA1_CBA 0x10c /* BA1_CAPTURE_BUFFER_ADDRESS */ 192353553Stanimura#define BA1_CSRC 0x2c8 /* BA1_CAPTURE_SAMPLE_RATE_CORRECTION_REG */ 192453553Stanimura#define BA1_CCI 0x2d8 /* BA1_CAPTURE_COEFFICIENT_INCREMENT_REG */ 192553553Stanimura#define BA1_CD 0x2e0 /* BA1_CAPTURE_DELAY_REG */ 192653553Stanimura#define BA1_CPI 0x2f4 /* BA1_CAPTURE_PHASE_INCREMENT_REG */ 192753553Stanimura#define BA1_CVOL 0x2f8 /* BA1_CAPTURE_VOLUME_REG */ 192853553Stanimura 192953553Stanimura#define BA1_CFG1 0x134 /* BA1_CAPTURE_FRAME_GROUP_1_REG */ 193053553Stanimura#define BA1_CFG2 0x138 /* BA1_CAPTURE_FRAME_GROUP_2_REG */ 193153553Stanimura#define BA1_CCST 0x13c /* BA1_CAPTURE_CONSTANT_REG */ 193253553Stanimura#define BA1_CSPB 0x340 /* BA1_CAPTURE_SPB_ADDRESS */ 193353553Stanimura 1934147626Sglebius/* PM state definitions */ 1935147626Sglebius#define CS461x_AC97_HIGHESTREGTORESTORE 0x26 1936147626Sglebius#define CS461x_AC97_NUMBER_RESTORE_REGS (CS461x_AC97_HIGHESTREGTORESTORE/2-1) 1937147626Sglebius 1938147626Sglebius#define CS_POWER_DAC 0x0001 1939147626Sglebius#define CS_POWER_ADC 0x0002 1940147626Sglebius#define CS_POWER_MIXVON 0x0004 1941147626Sglebius#define CS_POWER_MIXVOFF 0x0008 1942147626Sglebius#define CS_AC97_POWER_CONTROL_ON 0xf000 /* always on bits (inverted) */ 1943147626Sglebius#define CS_AC97_POWER_CONTROL_ADC 0x0100 1944147626Sglebius#define CS_AC97_POWER_CONTROL_DAC 0x0200 1945147626Sglebius#define CS_AC97_POWER_CONTROL_MIXVON 0x0400 1946147626Sglebius#define CS_AC97_POWER_CONTROL_MIXVOFF 0x0800 1947147626Sglebius#define CS_AC97_POWER_CONTROL_ADC_ON 0x0001 1948147626Sglebius#define CS_AC97_POWER_CONTROL_DAC_ON 0x0002 1949147626Sglebius#define CS_AC97_POWER_CONTROL_MIXVON_ON 0x0004 1950147626Sglebius#define CS_AC97_POWER_CONTROL_MIXVOFF_ON 0x0008 1951147626Sglebius 1952230897Spfg/* 1953230897Spfg * this is 3*1024 for parameter, 3.5*1024 for sample and 2*3.5*1024 1954230897Spfg * for code since each instruction is 40 bits and takes two dwords 1955230897Spfg */ 1956230897Spfg 1957230897Spfg/* The following struct holds the initialization array. */ 1958230897Spfg#define INKY_BA1_DWORD_SIZE (13*1024+512) 1959230897Spfg/* this is parameter, sample, and code */ 1960230897Spfg#define INKY_MEMORY_COUNT 3 1961230897Spfg 1962230897Spfgstruct cs461x_firmware_struct 1963230897Spfg{ 1964230897Spfg struct 1965230897Spfg { 1966230897Spfg u_int32_t ulDestAddr, ulSourceSize; 1967230897Spfg } MemoryStat[INKY_MEMORY_COUNT]; 1968230897Spfg 1969230897Spfg u_int32_t BA1Array[INKY_BA1_DWORD_SIZE]; 1970230897Spfg}; 1971230897Spfg 1972230897Spfg 197353553Stanimura#endif /* _CSA_REG_H */ 1974