mss.h revision 51766
1/* 2 * file: mss.h 3 * 4 * (C) 1997 Luigi Rizzo (luigi@iet.unipi.it) 5 * 6 * This file contains information and macro definitions for 7 * AD1848-compatible devices, used in the MSS/WSS compatible boards. 8 * 9 */ 10 11/* 12 * 13 14The codec part of the board is seen as a set of 4 registers mapped 15at the base address for the board (default 0x534). Note that some 16(early) boards implemented 4 additional registers 4 location before 17(usually 0x530) to store configuration information. This is a source 18of confusion in that one never knows what address to specify. The 19(current) convention is to use the old address (0x530) in the kernel 20configuration file and consider MSS registers start four location 21ahead. 22 23 * 24 */ 25 26/* 27 * The four visible registers of the MSS : 28 * 29 */ 30 31#define MSS_INDEX (0 + 4) 32#define MSS_IDXBUSY 0x80 /* readonly, set when busy */ 33#define MSS_MCE 0x40 /* the MCE bit. */ 34 /* 35 * the MCE bit must be set whenever the current mode of the 36 * codec is changed; this in particular is true for the 37 * Data Format (I8, I28) and Interface Config(I9) registers. 38 * Only exception are CEN and PEN which can be changed on the fly. 39 * The DAC output is muted when MCE is set. 40 */ 41#define MSS_TRD 0x20 /* Transfer request disable */ 42 /* 43 * When TRD is set, DMA transfers cease when the INT bit in 44 * the MSS status reg is set. Must be cleared for automode 45 * DMA, set otherwise. 46 */ 47#define MSS_IDXMASK 0x1f /* mask for indirect address */ 48 49#define MSS_IDATA (1 + 4) 50 /* 51 * data to be transferred to the indirect register addressed 52 * by index addr. During init and sw. powerdown, cannot be 53 * written to, and is always read as 0x80 (consistent with the 54 * busy flag). 55 */ 56 57#define MSS_STATUS (2 + 4) 58 59#define IS_CUL 0x80 /* capture upper/lower */ 60#define IS_CLR 0x40 /* capture left/right */ 61#define IS_CRDY 0x20 /* capture ready for programmed i/o */ 62#define IS_SER 0x10 /* sample error (overrun/underrun) */ 63#define IS_PUL 0x08 /* playback upper/lower */ 64#define IS_PLR 0x04 /* playback left/right */ 65#define IS_PRDY 0x02 /* playback ready for programmed i/o */ 66#define IS_INT 0x01 /* int status (1 = active) */ 67 /* 68 * IS_INT is clreared by any write to the status register. 69 */ 70#if 0 71#define io_Polled_IO(d) ((d)->io_base+3+4) 72 /* 73 * this register is used in case of polled i/o 74 */ 75#endif 76 77/* 78 * The MSS has a set of 16 (or 32 depending on the model) indirect 79 * registers accessible through the data port by specifying the 80 * appropriate address in the address register. 81 * 82 * The 16 low registers are uniformly handled in AD1848/CS4248 compatible 83 * mode (often called MODE1). For the upper 16 registers there are 84 * some differences among different products, mainly Crystal uses them 85 * differently from OPTi. 86 * 87 */ 88 89/* 90 * volume registers 91 */ 92 93#define I6_MUTE 0x80 94 95/* 96 * register I9 -- interface configuration. 97 */ 98 99#define I9_PEN 0x01 /* playback enable */ 100#define I9_CEN 0x02 /* capture enable */ 101 102/* 103 * values used in bd_flags 104 */ 105#define BD_F_MCE_BIT 0x0001 106#define BD_F_IRQ_OK 0x0002 107#define BD_F_TMR_RUN 0x0004 108#define BD_F_MSS_OFFSET 0x0008 /* offset mss writes by -4 */ 109#define BD_F_DUPLEX 0x0010 110 111/* 112 * sound/ad1848_mixer.h 113 * 114 * Definitions for the mixer of AD1848 and compatible codecs. 115 * 116 * Copyright by Hannu Savolainen 1994 117 * 118 * Redistribution and use in source and binary forms, with or without 119 * modification, are permitted provided that the following conditions are 120 * met: 1. Redistributions of source code must retain the above copyright 121 * notice, this list of conditions and the following disclaimer. 2. 122 * Redistributions in binary form must reproduce the above copyright notice, 123 * this list of conditions and the following disclaimer in the documentation 124 * and/or other materials provided with the distribution. 125 * 126 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 127 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 128 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 129 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 130 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 131 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 132 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 133 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 134 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 135 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 136 * SUCH DAMAGE. 137 */ 138/* 139 * The AD1848 codec has generic input lines called Line, Aux1 and Aux2. 140 * Soundcard manufacturers have connected actual inputs (CD, synth, line, 141 * etc) to these inputs in different order. Therefore it's difficult 142 * to assign mixer channels to to these inputs correctly. The following 143 * contains two alternative mappings. The first one is for GUS MAX and 144 * the second is just a generic one (line1, line2 and line3). 145 * (Actually this is not a mapping but rather some kind of interleaving 146 * solution). 147 */ 148 149#define MSS_REC_DEVICES \ 150 (SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD|SOUND_MASK_IMIX) 151 152 153/* 154 * Table of mixer registers. There is a default table for the 155 * AD1848/CS423x clones, and one for the OPTI931. As more MSS 156 * clones come out, there ought to be more tables. 157 * 158 * Fields in the table are : polarity, register, offset, bits 159 * 160 * The channel numbering used by individual soundcards is not fixed. 161 * Some cards have assigned different meanings for the AUX1, AUX2 162 * and LINE inputs. Some have different features... 163 * 164 * Following there is a macro ...MIXER_DEVICES which is a bitmap 165 * of all non-zero fields in the table. 166 * MODE1_MIXER_DEVICES is the basic mixer of the 1848 in mode 1 167 * registers I0..I15) 168 * 169 */ 170 171mixer_ent mix_devices[32][2] = { 172MIX_NONE(SOUND_MIXER_VOLUME), 173MIX_NONE(SOUND_MIXER_BASS), 174MIX_NONE(SOUND_MIXER_TREBLE), 175MIX_ENT(SOUND_MIXER_SYNTH, 2, 1, 0, 5, 3, 1, 0, 5), 176MIX_ENT(SOUND_MIXER_PCM, 6, 1, 0, 6, 7, 1, 0, 6), 177MIX_ENT(SOUND_MIXER_SPEAKER, 26, 1, 0, 4, 0, 0, 0, 0), 178MIX_ENT(SOUND_MIXER_LINE, 18, 1, 0, 5, 19, 1, 0, 5), 179MIX_ENT(SOUND_MIXER_MIC, 0, 0, 5, 1, 1, 0, 5, 1), 180MIX_ENT(SOUND_MIXER_CD, 4, 1, 0, 5, 5, 1, 0, 5), 181MIX_ENT(SOUND_MIXER_IMIX, 13, 1, 2, 6, 0, 0, 0, 0), 182MIX_NONE(SOUND_MIXER_ALTPCM), 183MIX_NONE(SOUND_MIXER_RECLEV), 184MIX_ENT(SOUND_MIXER_IGAIN, 0, 0, 0, 4, 1, 0, 0, 4), 185MIX_NONE(SOUND_MIXER_OGAIN), 186MIX_NONE(SOUND_MIXER_LINE1), 187MIX_NONE(SOUND_MIXER_LINE2), 188MIX_NONE(SOUND_MIXER_LINE3), 189}; 190 191#define MODE2_MIXER_DEVICES \ 192 (SOUND_MASK_SYNTH | SOUND_MASK_PCM | SOUND_MASK_SPEAKER | \ 193 SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD | \ 194 SOUND_MASK_IMIX | SOUND_MASK_IGAIN ) 195 196#define MODE1_MIXER_DEVICES \ 197 (SOUND_MASK_SYNTH | SOUND_MASK_PCM | SOUND_MASK_MIC | \ 198 SOUND_MASK_CD | SOUND_MASK_IMIX | SOUND_MASK_IGAIN ) 199 200 201/* 202 * entries for the opti931... 203 */ 204 205mixer_ent opti931_devices[32][2] = { /* for the opti931 */ 206MIX_ENT(SOUND_MIXER_VOLUME, 22, 1, 1, 5, 23, 1, 1, 5), 207MIX_NONE(SOUND_MIXER_BASS), 208MIX_NONE(SOUND_MIXER_TREBLE), 209MIX_ENT(SOUND_MIXER_SYNTH, 4, 1, 1, 4, 5, 1, 1, 4), 210MIX_ENT(SOUND_MIXER_PCM, 6, 1, 0, 5, 7, 1, 0, 5), 211MIX_NONE(SOUND_MIXER_SPEAKER), 212MIX_ENT(SOUND_MIXER_LINE, 18, 1, 1, 4, 19, 1, 1, 4), 213MIX_ENT(SOUND_MIXER_MIC, 0, 0, 5, 1, 1, 0, 5, 1), 214MIX_ENT(SOUND_MIXER_CD, 2, 1, 1, 4, 3, 1, 1, 4), 215MIX_NONE(SOUND_MIXER_IMIX), 216MIX_NONE(SOUND_MIXER_ALTPCM), 217MIX_NONE(SOUND_MIXER_RECLEV), 218MIX_ENT(SOUND_MIXER_IGAIN, 0, 0, 0, 4, 1, 0, 0, 4), 219MIX_NONE(SOUND_MIXER_OGAIN), 220MIX_ENT(SOUND_MIXER_LINE1, 16, 1, 1, 4, 17, 1, 1, 4), 221MIX_NONE(SOUND_MIXER_LINE2), 222MIX_NONE(SOUND_MIXER_LINE3), 223}; 224 225#define OPTI931_MIXER_DEVICES \ 226 (SOUND_MASK_VOLUME | SOUND_MASK_SYNTH | SOUND_MASK_PCM | \ 227 SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD | \ 228 SOUND_MASK_IGAIN | SOUND_MASK_LINE1 ) 229 230/*- 231 * Copyright (c) 1999 Doug Rabson 232 * All rights reserved. 233 * 234 * Redistribution and use in source and binary forms, with or without 235 * modification, are permitted provided that the following conditions 236 * are met: 237 * 1. Redistributions of source code must retain the above copyright 238 * notice, this list of conditions and the following disclaimer. 239 * 2. Redistributions in binary form must reproduce the above copyright 240 * notice, this list of conditions and the following disclaimer in the 241 * documentation and/or other materials provided with the distribution. 242 * 243 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 244 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 245 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 246 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 247 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 248 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 249 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 250 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 251 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 252 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 253 * SUCH DAMAGE. 254 * 255 * $FreeBSD: head/sys/dev/sound/isa/mss.h 51766 1999-09-28 20:00:06Z cg $ 256 */ 257 258/* 259 * Register definitions for the Yamaha OPL3-SA[23x]. 260 */ 261#define OPL3SAx_POWER 0x01 /* Power Management (R/W) */ 262#define OPL3SAx_POWER_PDX 0x01 /* Set to 1 to halt oscillator */ 263#define OPL3SAx_POWER_PDN 0x02 /* Set to 1 to power down */ 264#define OPL3SAx_POWER_PSV 0x04 /* Set to 1 to power save */ 265#define OPL3SAx_POWER_ADOWN 0x20 /* Analog power (?) */ 266 267#define OPL3SAx_SYSTEM 0x02 /* System control (R/W) */ 268#define OPL3SAx_SYSTEM_VZE 0x01 /* I2S audio routing */ 269#define OPL3SAx_SYSTEM_IDSEL 0x03 /* SB compat version select */ 270#define OPL3SAx_SYSTEM_SBHE 0x80 /* 0 for AT bus, 1 for XT bus */ 271 272#define OPL3SAx_IRQCONF 0x03 /* Interrupt configuration (R/W */ 273#define OPL3SAx_IRQCONF_WSSA 0x01 /* WSS interrupts through IRQA */ 274#define OPL3SAx_IRQCONF_SBA 0x02 /* WSS interrupts through IRQA */ 275#define OPL3SAx_IRQCONF_MPUA 0x04 /* WSS interrupts through IRQA */ 276#define OPL3SAx_IRQCONF_OPL3A 0x08 /* WSS interrupts through IRQA */ 277#define OPL3SAx_IRQCONF_WSSB 0x10 /* WSS interrupts through IRQB */ 278#define OPL3SAx_IRQCONF_SBB 0x20 /* WSS interrupts through IRQB */ 279#define OPL3SAx_IRQCONF_MPUB 0x40 /* WSS interrupts through IRQB */ 280#define OPL3SAx_IRQCONF_OPL3B 0x80 /* WSS interrupts through IRQB */ 281 282#define OPL3SAx_IRQSTATUSA 0x04 /* Interrupt (IRQ-A) Status (RO) */ 283#define OPL3SAx_IRQSTATUSB 0x05 /* Interrupt (IRQ-B) Status (RO) */ 284#define OPL3SAx_IRQSTATUS_PI 0x01 /* Playback Flag of CODEC */ 285#define OPL3SAx_IRQSTATUS_CI 0x02 /* Recording Flag of CODEC */ 286#define OPL3SAx_IRQSTATUS_TI 0x04 /* Timer Flag of CODEC */ 287#define OPL3SAx_IRQSTATUS_SB 0x08 /* SB compat Playback Interrupt Flag */ 288#define OPL3SAx_IRQSTATUS_MPU 0x10 /* MPU401 Interrupt Flag */ 289#define OPL3SAx_IRQSTATUS_OPL3 0x20 /* Internal FM Timer Flag */ 290#define OPL3SAx_IRQSTATUS_MV 0x40 /* HW Volume Interrupt Flag */ 291#define OPL3SAx_IRQSTATUS_PI 0x01 /* Playback Flag of CODEC */ 292#define OPL3SAx_IRQSTATUS_CI 0x02 /* Recording Flag of CODEC */ 293#define OPL3SAx_IRQSTATUS_TI 0x04 /* Timer Flag of CODEC */ 294#define OPL3SAx_IRQSTATUS_SB 0x08 /* SB compat Playback Interrupt Flag */ 295#define OPL3SAx_IRQSTATUS_MPU 0x10 /* MPU401 Interrupt Flag */ 296#define OPL3SAx_IRQSTATUS_OPL3 0x20 /* Internal FM Timer Flag */ 297#define OPL3SAx_IRQSTATUS_MV 0x40 /* HW Volume Interrupt Flag */ 298 299#define OPL3SAx_DMACONF 0x06 /* DMA configuration (R/W) */ 300#define OPL3SAx_DMACONF_WSSPA 0x01 /* WSS Playback on DMA-A */ 301#define OPL3SAx_DMACONF_WSSRA 0x02 /* WSS Recording on DMA-A */ 302#define OPL3SAx_DMACONF_SBA 0x02 /* SB Playback on DMA-A */ 303#define OPL3SAx_DMACONF_WSSPB 0x10 /* WSS Playback on DMA-A */ 304#define OPL3SAx_DMACONF_WSSRB 0x20 /* WSS Recording on DMA-A */ 305#define OPL3SAx_DMACONF_SBB 0x20 /* SB Playback on DMA-A */ 306 307#define OPL3SAx_VOLUMEL 0x07 /* Master Volume Left (R/W) */ 308#define OPL3SAx_VOLUMEL_MVL 0x0f /* Attenuation level */ 309#define OPL3SAx_VOLUMEL_MVLM 0x80 /* Mute */ 310 311#define OPL3SAx_VOLUMER 0x08 /* Master Volume Right (R/W) */ 312#define OPL3SAx_VOLUMER_MVR 0x0f /* Attenuation level */ 313#define OPL3SAx_VOLUMER_MVRM 0x80 /* Mute */ 314 315#define OPL3SAx_MIC 0x09 /* MIC Volume (R/W) */ 316#define OPL3SAx_VOLUMER_MCV 0x1f /* Attenuation level */ 317#define OPL3SAx_VOLUMER_MICM 0x80 /* Mute */ 318 319#define OPL3SAx_MISC 0x0a /* Miscellaneous */ 320#define OPL3SAx_MISC_VER 0x07 /* Version */ 321#define OPL3SAx_MISC_MODE 0x08 /* SB or WSS mode */ 322#define OPL3SAx_MISC_MCSW 0x10 /* */ 323#define OPL3SAx_MISC_VEN 0x80 /* Enable hardware volume control */ 324 325#define OPL3SAx_WSSDMA 0x0b /* WSS DMA Counter (RW) (4 regs) */ 326 327#define OPL3SAx_WSSIRQSCAN 0x0f /* WSS Interrupt Scan out/in (R/W) */ 328#define OPL3SAx_WSSIRQSCAN_SPI 0x01 329#define OPL3SAx_WSSIRQSCAN_SCI 0x02 330#define OPL3SAx_WSSIRQSCAN_STI 0x04 331 332#define OPL3SAx_SBSTATE 0x10 /* SB compat Internal State (R/W) */ 333#define OPL3SAx_SBSTATE_SBPDR 0x01 /* SB Power Down Request */ 334#define OPL3SAx_SBSTATE_SE 0x02 /* Scan Enable */ 335#define OPL3SAx_SBSTATE_SM 0x04 /* Scan Mode */ 336#define OPL3SAx_SBSTATE_SS 0x08 /* Scan Select */ 337#define OPL3SAx_SBSTATE_SBPDA 0x80 /* SB Power Down Acknowledge */ 338 339#define OPL3SAx_SBDATA 0x11 /* SB compat State Scan Data (R/W) */ 340 341#define OPL3SAx_DIGITALPOWER 0x12 /* Digital Partial Power Down (R/W) */ 342#define OPL3SAx_DIGITALPOWER_PnP 0x01 343#define OPL3SAx_DIGITALPOWER_SB 0x02 344#define OPL3SAx_DIGITALPOWER_WSSP 0x04 345#define OPL3SAx_DIGITALPOWER_WSSR 0x08 346#define OPL3SAx_DIGITALPOWER_FM 0x10 347#define OPL3SAx_DIGITALPOWER_MCLK0 0x20 348#define OPL3SAx_DIGITALPOWER_MPU 0x40 349#define OPL3SAx_DIGITALPOWER_JOY 0x80 350 351#define OPL3SAx_ANALOGPOWER 0x13 /* Analog Partial Power Down (R/W) */ 352#define OPL3SAx_ANALOGPOWER_WIDE 0x01 353#define OPL3SAx_ANALOGPOWER_SBDAC 0x02 354#define OPL3SAx_ANALOGPOWER_DA 0x04 355#define OPL3SAx_ANALOGPOWER_AD 0x08 356#define OPL3SAx_ANALOGPOWER_FMDAC 0x10 357 358#define OPL3SAx_WIDE 0x14 /* Enhanced control(WIDE) (R/W) */ 359#define OPL3SAx_WIDE_WIDEL 0x07 /* Wide level on Left Channel */ 360#define OPL3SAx_WIDE_WIDER 0x70 /* Wide level on Right Channel */ 361 362#define OPL3SAx_BASS 0x15 /* Enhanced control(BASS) (R/W) */ 363#define OPL3SAx_BASS_BASSL 0x07 /* Bass level on Left Channel */ 364#define OPL3SAx_BASS_BASSR 0x70 /* Bass level on Right Channel */ 365 366#define OPL3SAx_TREBLE 0x16 /* Enhanced control(TREBLE) (R/W) */ 367#define OPL3SAx_TREBLE_TREBLEL 0x07 /* Treble level on Left Channel */ 368#define OPL3SAx_TREBLE_TREBLER 0x70 /* Treble level on Right Channel */ 369 370#define OPL3SAx_HWVOL 0x17 /* HW Volume IRQ Configuration (R/W) */ 371#define OPL3SAx_HWVOL_IRQA 0x10 /* HW Volume IRQ on IRQ-A */ 372#define OPL3SAx_HWVOL_IRQB 0x20 /* HW Volume IRQ on IRQ-B */ 373 374 375