yukonreg.h revision 120286
1120286Swilko/* $OpenBSD: yukonreg.h,v 1.2 2003/08/12 05:23:06 nate Exp $ */ 2120286Swilko/* 3120286Swilko * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 4120286Swilko * 5120286Swilko * Permission to use, copy, modify, and distribute this software for any 6120286Swilko * purpose with or without fee is hereby granted, provided that the above 7120286Swilko * copyright notice and this permission notice appear in all copies. 8120286Swilko * 9120286Swilko * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10120286Swilko * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11120286Swilko * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12120286Swilko * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13120286Swilko * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14120286Swilko * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15120286Swilko * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16120286Swilko * 17120286Swilko * $FreeBSD: head/sys/dev/sk/yukonreg.h 120286 2003-09-20 15:49:22Z wilko $ 18120286Swilko */ 19120286Swilko 20120286Swilko/* General Purpose Status Register (GPSR) */ 21120286Swilko#define YUKON_GPSR 0x0000 22120286Swilko 23120286Swilko#define YU_GPSR_SPEED 0x8000 /* speed 0 - 10Mbps, 1 - 100Mbps */ 24120286Swilko#define YU_GPSR_DUPLEX 0x4000 /* 0 - half duplex, 1 - full duplex */ 25120286Swilko#define YU_GPSR_FCTL_TX 0x2000 /* flow control */ 26120286Swilko#define YU_GPSR_LINK 0x1000 /* link status (down/up) */ 27120286Swilko#define YU_GPSR_PAUSE 0x0800 /* flow control enable/disable */ 28120286Swilko#define YU_GPSR_TX_IN_PROG 0x0400 /* transmit in progress */ 29120286Swilko#define YU_GPSR_EXCESS_COL 0x0200 /* excessive collisions occurred */ 30120286Swilko#define YU_GPSR_LATE_COL 0x0100 /* late collision occurred */ 31120286Swilko#define YU_GPSR_MII_PHY_STC 0x0020 /* MII PHY status change */ 32120286Swilko#define YU_GPSR_GIG_SPEED 0x0010 /* Gigabit Speed (0 - use speed bit) */ 33120286Swilko#define YU_GPSR_PARTITION 0x0008 /* partition mode */ 34120286Swilko#define YU_GPSR_FCTL_RX 0x0004 /* flow control enable/disable */ 35120286Swilko#define YU_GPSR_PROMS_EN 0x0002 /* promiscuous mode enable/disable */ 36120286Swilko 37120286Swilko/* General Purpose Control Register (GPCR) */ 38120286Swilko#define YUKON_GPCR 0x0004 39120286Swilko 40120286Swilko#define YU_GPCR_FCTL_TX 0x2000 /* Transmit flow control 802.3x */ 41120286Swilko#define YU_GPCR_TXEN 0x1000 /* Transmit Enable */ 42120286Swilko#define YU_GPCR_RXEN 0x0800 /* Receive Enable */ 43120286Swilko#define YU_GPCR_LPBK 0x0200 /* Loopback Enable */ 44120286Swilko#define YU_GPCR_PAR 0x0100 /* Partition Enable */ 45120286Swilko#define YU_GPCR_GIG 0x0080 /* Gigabit Speed */ 46120286Swilko#define YU_GPCR_FLP 0x0040 /* Force Link Pass */ 47120286Swilko#define YU_GPCR_DUPLEX 0x0020 /* Duplex Enable */ 48120286Swilko#define YU_GPCR_FCTL_RX 0x0010 /* Receive flow control 802.3x */ 49120286Swilko#define YU_GPCR_SPEED 0x0008 /* Port Speed */ 50120286Swilko#define YU_GPCR_DPLX_EN 0x0004 /* Enable Auto-Update for duplex */ 51120286Swilko#define YU_GPCR_FCTL_EN 0x0002 /* Enabel Auto-Update for 802.3x */ 52120286Swilko#define YU_GPCR_SPEED_EN 0x0001 /* Enable Auto-Update for speed */ 53120286Swilko 54120286Swilko/* Transmit Control Register (TCR) */ 55120286Swilko#define YUKON_TCR 0x0008 56120286Swilko 57120286Swilko#define YU_TCR_FJ 0x8000 /* force jam / flow control */ 58120286Swilko#define YU_TCR_CRCD 0x4000 /* insert CRC (0 - enable) */ 59120286Swilko#define YU_TCR_PADD 0x2000 /* pad packets to 64b (0 - enable) */ 60120286Swilko#define YU_TCR_COLTH 0x1c00 /* collision threshold */ 61120286Swilko 62120286Swilko/* Receive Control Register (RCR) */ 63120286Swilko#define YUKON_RCR 0x000c 64120286Swilko 65120286Swilko#define YU_RCR_UFLEN 0x8000 /* unicast filter enable */ 66120286Swilko#define YU_RCR_MUFLEN 0x4000 /* multicast filter enable */ 67120286Swilko#define YU_RCR_CRCR 0x2000 /* remove CRC */ 68120286Swilko#define YU_RCR_PASSFC 0x1000 /* pass flow control packets */ 69120286Swilko 70120286Swilko/* Transmit Flow Control Register (TFCR) */ 71120286Swilko#define YUKON_TFCR 0x0010 /* Pause Time */ 72120286Swilko 73120286Swilko/* Transmit Parameter Register (TPR) */ 74120286Swilko#define YUKON_TPR 0x0014 75120286Swilko 76120286Swilko#define YU_TPR_JAM_LEN(x) (((x) & 0x3) << 14) 77120286Swilko#define YU_TPR_JAM_IPG(x) (((x) & 0x1f) << 9) 78120286Swilko#define YU_TPR_JAM2DATA_IPG(x) (((x) & 0x1f) << 4) 79120286Swilko 80120286Swilko/* Serial Mode Register (SMR) */ 81120286Swilko#define YUKON_SMR 0x0018 82120286Swilko 83120286Swilko#define YU_SMR_DATA_BLIND(x) (((x) & 0x1f) << 11) 84120286Swilko#define YU_SMR_LIMIT4 0x0400 /* reset after 16 / 4 collisions */ 85120286Swilko#define YU_SMR_MFL_JUMBO 0x0100 /* max frame length for jumbo frames */ 86120286Swilko#define YU_SMR_MFL_VLAN 0x0200 /* max frame length + vlan tag */ 87120286Swilko#define YU_SMR_IPG_DATA(x) ((x) & 0x1f) 88120286Swilko 89120286Swilko/* Source Address Low #1 (SAL1) */ 90120286Swilko#define YUKON_SAL1 0x001c /* SA1[15:0] */ 91120286Swilko 92120286Swilko/* Source Address Middle #1 (SAM1) */ 93120286Swilko#define YUKON_SAM1 0x0020 /* SA1[31:16] */ 94120286Swilko 95120286Swilko/* Source Address High #1 (SAH1) */ 96120286Swilko#define YUKON_SAH1 0x0024 /* SA1[47:32] */ 97120286Swilko 98120286Swilko/* Source Address Low #2 (SAL2) */ 99120286Swilko#define YUKON_SAL2 0x0028 /* SA2[15:0] */ 100120286Swilko 101120286Swilko/* Source Address Middle #2 (SAM2) */ 102120286Swilko#define YUKON_SAM2 0x002c /* SA2[31:16] */ 103120286Swilko 104120286Swilko/* Source Address High #2 (SAH2) */ 105120286Swilko#define YUKON_SAH2 0x0030 /* SA2[47:32] */ 106120286Swilko 107120286Swilko/* Multicatst Address Hash Register 1 (MCAH1) */ 108120286Swilko#define YUKON_MCAH1 0x0034 109120286Swilko 110120286Swilko/* Multicatst Address Hash Register 2 (MCAH2) */ 111120286Swilko#define YUKON_MCAH2 0x0038 112120286Swilko 113120286Swilko/* Multicatst Address Hash Register 3 (MCAH3) */ 114120286Swilko#define YUKON_MCAH3 0x003c 115120286Swilko 116120286Swilko/* Multicatst Address Hash Register 4 (MCAH4) */ 117120286Swilko#define YUKON_MCAH4 0x0040 118120286Swilko 119120286Swilko/* Transmit Interrupt Register (TIR) */ 120120286Swilko#define YUKON_TIR 0x0044 121120286Swilko 122120286Swilko#define YU_TIR_OUT_UNICAST 0x0001 /* Num Unicast Packets Transmitted */ 123120286Swilko#define YU_TIR_OUT_BROADCAST 0x0002 /* Num Broadcast Packets Transmitted */ 124120286Swilko#define YU_TIR_OUT_PAUSE 0x0004 /* Num Pause Packets Transmitted */ 125120286Swilko#define YU_TIR_OUT_MULTICAST 0x0008 /* Num Multicast Packets Transmitted */ 126120286Swilko#define YU_TIR_OUT_OCTETS 0x0030 /* Num Bytes Transmitted */ 127120286Swilko#define YU_TIR_OUT_64_OCTETS 0x0000 /* Num Packets Transmitted */ 128120286Swilko#define YU_TIR_OUT_127_OCTETS 0x0000 /* Num Packets Transmitted */ 129120286Swilko#define YU_TIR_OUT_255_OCTETS 0x0000 /* Num Packets Transmitted */ 130120286Swilko#define YU_TIR_OUT_511_OCTETS 0x0000 /* Num Packets Transmitted */ 131120286Swilko#define YU_TIR_OUT_1023_OCTETS 0x0000 /* Num Packets Transmitted */ 132120286Swilko#define YU_TIR_OUT_1518_OCTETS 0x0000 /* Num Packets Transmitted */ 133120286Swilko#define YU_TIR_OUT_MAX_OCTETS 0x0000 /* Num Packets Transmitted */ 134120286Swilko#define YU_TIR_OUT_SPARE 0x0000 /* Num Packets Transmitted */ 135120286Swilko#define YU_TIR_OUT_COLLISIONS 0x0000 /* Num Packets Transmitted */ 136120286Swilko#define YU_TIR_OUT_LATE 0x0000 /* Num Packets Transmitted */ 137120286Swilko 138120286Swilko/* Receive Interrupt Register (RIR) */ 139120286Swilko#define YUKON_RIR 0x0048 140120286Swilko 141120286Swilko/* Transmit and Receive Interrupt Register (TRIR) */ 142120286Swilko#define YUKON_TRIR 0x004c 143120286Swilko 144120286Swilko/* Transmit Interrupt Mask Register (TIMR) */ 145120286Swilko#define YUKON_TIMR 0x0050 146120286Swilko 147120286Swilko/* Receive Interrupt Mask Register (RIMR) */ 148120286Swilko#define YUKON_RIMR 0x0054 149120286Swilko 150120286Swilko/* Transmit and Receive Interrupt Mask Register (TRIMR) */ 151120286Swilko#define YUKON_TRIMR 0x0058 152120286Swilko 153120286Swilko/* SMI Control Register (SMICR) */ 154120286Swilko#define YUKON_SMICR 0x0080 155120286Swilko 156120286Swilko#define YU_SMICR_PHYAD(x) (((x) & 0x1f) << 11) 157120286Swilko#define YU_SMICR_REGAD(x) (((x) & 0x1f) << 6) 158120286Swilko#define YU_SMICR_OPCODE 0x0020 /* opcode (0 - write, 1 - read) */ 159120286Swilko#define YU_SMICR_OP_READ 0x0020 /* opcode read */ 160120286Swilko#define YU_SMICR_OP_WRITE 0x0000 /* opcode write */ 161120286Swilko#define YU_SMICR_READ_VALID 0x0010 /* read valid */ 162120286Swilko#define YU_SMICR_BUSY 0x0008 /* busy (writing) */ 163120286Swilko 164120286Swilko/* SMI Data Register (SMIDR) */ 165120286Swilko#define YUKON_SMIDR 0x0084 166120286Swilko 167120286Swilko/* PHY Addres Register (PAR) */ 168120286Swilko#define YUKON_PAR 0x0088 169120286Swilko 170120286Swilko#define YU_PAR_MIB_CLR 0x0020 /* MIB Counters Clear Mode */ 171120286Swilko#define YU_PAR_LOAD_TSTCNT 0x0010 /* Load count 0xfffffff0 into cntr */ 172