xmaciireg.h revision 59478
148693Swpaul/* 259478Swpaul * Copyright (c) 1997, 1998, 1999, 2000 348693Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 448693Swpaul * 548693Swpaul * Redistribution and use in source and binary forms, with or without 648693Swpaul * modification, are permitted provided that the following conditions 748693Swpaul * are met: 848693Swpaul * 1. Redistributions of source code must retain the above copyright 948693Swpaul * notice, this list of conditions and the following disclaimer. 1048693Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1148693Swpaul * notice, this list of conditions and the following disclaimer in the 1248693Swpaul * documentation and/or other materials provided with the distribution. 1348693Swpaul * 3. All advertising materials mentioning features or use of this software 1448693Swpaul * must display the following acknowledgement: 1548693Swpaul * This product includes software developed by Bill Paul. 1648693Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1748693Swpaul * may be used to endorse or promote products derived from this software 1848693Swpaul * without specific prior written permission. 1948693Swpaul * 2048693Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2148693Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2248693Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2348693Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2448693Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2548693Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2648693Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2748693Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2848693Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2948693Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3048693Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3148693Swpaul * 3250477Speter * $FreeBSD: head/sys/dev/sk/xmaciireg.h 59478 2000-04-22 02:16:41Z wpaul $ 3348693Swpaul */ 3448693Swpaul 3548693Swpaul/* 3648693Swpaul * Registers and data structures for the XaQti Corporation XMAC II 3748693Swpaul * Gigabit Ethernet MAC. Datasheet is available from http://www.xaqti.com. 3848693Swpaul * The XMAC can be programmed for 16-bit or 32-bit register access modes. 3948693Swpaul * The SysKonnect gigabit ethernet adapters use 16-bit mode, so that's 4048693Swpaul * how the registers are laid out here. 4148693Swpaul */ 4248693Swpaul 4348693Swpaul#define XM_DEVICEID 0x00E0AE20 4448693Swpaul#define XM_XAQTI_OUI 0x00E0AE 4548693Swpaul 4648693Swpaul#define XM_XMAC_REV(x) (((x) & 0x000000E0) >> 5) 4748693Swpaul 4848693Swpaul#define XM_XMAC_REV_B2 0x0 4948693Swpaul#define XM_XMAC_REV_C1 0x1 5048693Swpaul 5148693Swpaul#define XM_MMUCMD 0x0000 5248693Swpaul#define XM_POFF 0x0008 5348693Swpaul#define XM_BURST 0x000C 5448693Swpaul#define XM_VLAN_TAGLEV1 0x0010 5548693Swpaul#define XM_VLAN_TAGLEV2 0x0014 5648693Swpaul#define XM_TXCMD 0x0020 5748693Swpaul#define XM_TX_RETRYLIMIT 0x0024 5848693Swpaul#define XM_TX_SLOTTIME 0x0028 5948693Swpaul#define XM_TX_IPG 0x003C 6048693Swpaul#define XM_RXCMD 0x0030 6148693Swpaul#define XM_PHY_ADDR 0x0034 6248693Swpaul#define XM_PHY_DATA 0x0038 6348693Swpaul#define XM_GPIO 0x0040 6448693Swpaul#define XM_IMR 0x0044 6548693Swpaul#define XM_ISR 0x0048 6648693Swpaul#define XM_HWCFG 0x004C 6748693Swpaul#define XM_TX_LOWAT 0x0060 6848693Swpaul#define XM_TX_HIWAT 0x0062 6948693Swpaul#define XM_TX_REQTHRESH_LO 0x0064 7048693Swpaul#define XM_TX_REQTHRESH_HI 0x0066 7148693Swpaul#define XM_TX_REQTHRESH XM_TX_REQTHRESH_LO 7248693Swpaul#define XM_PAUSEDST0 0x0068 7348693Swpaul#define XM_PAUSEDST1 0x006A 7448693Swpaul#define XM_PAUSEDST2 0x006C 7548693Swpaul#define XM_CTLPARM_LO 0x0070 7648693Swpaul#define XM_CTLPARM_HI 0x0072 7748693Swpaul#define XM_CTLPARM XM_CTLPARM_LO 7848693Swpaul#define XM_OPCODE_PAUSE_TIMER 0x0074 7948693Swpaul#define XM_TXSTAT_LIFO 0x0078 8048693Swpaul 8148693Swpaul/* 8248693Swpaul * Perfect filter registers. The XMAC has a table of 16 perfect 8348693Swpaul * filter entries, spaced 8 bytes apart. This is in addition to 8448693Swpaul * the station address registers, which appear below. 8548693Swpaul */ 8648693Swpaul#define XM_RXFILT_BASE 0x0080 8748693Swpaul#define XM_RXFILT_END 0x0107 8848693Swpaul#define XM_RXFILT_MAX 16 8948693Swpaul#define XM_RXFILT_ENTRY(ent) (XM_RXFILT_BASE + ((ent * 8))) 9048693Swpaul 9148693Swpaul/* Primary station address. */ 9248693Swpaul#define XM_PAR0 0x0108 9348693Swpaul#define XM_PAR1 0x010A 9448693Swpaul#define XM_PAR2 0x010C 9548693Swpaul 9648693Swpaul/* 64-bit multicast hash table registers */ 9748693Swpaul#define XM_MAR0 0x0110 9848693Swpaul#define XM_MAR1 0x0112 9948693Swpaul#define XM_MAR2 0x0114 10048693Swpaul#define XM_MAR3 0x0116 10148693Swpaul#define XM_RX_LOWAT 0x0118 10248693Swpaul#define XM_RX_HIWAT 0x011A 10348693Swpaul#define XM_RX_REQTHRESH_LO 0x011C 10448693Swpaul#define XM_RX_REQTHRESH_HI 0x011E 10548693Swpaul#define XM_RX_REQTHRESH XM_RX_REQTHRESH_LO 10648693Swpaul#define XM_DEVID_LO 0x0120 10748693Swpaul#define XM_DEVID_HI 0x0122 10848693Swpaul#define XM_DEVID XM_DEVID_LO 10948693Swpaul#define XM_MODE_LO 0x0124 11048693Swpaul#define XM_MODE_HI 0x0126 11148693Swpaul#define XM_MODE XM_MODE_LO 11248693Swpaul#define XM_LASTSRC0 0x0128 11348693Swpaul#define XM_LASTSRC1 0x012A 11448693Swpaul#define XM_LASTSRC2 0x012C 11548693Swpaul#define XM_TSTAMP_READ 0x0130 11648693Swpaul#define XM_TSTAMP_LOAD 0x0134 11748693Swpaul#define XM_STATS_CMD 0x0200 11848693Swpaul#define XM_RXCNT_EVENT_LO 0x0204 11948693Swpaul#define XM_RXCNT_EVENT_HI 0x0206 12048693Swpaul#define XM_RXCNT_EVENT XM_RXCNT_EVENT_LO 12148693Swpaul#define XM_TXCNT_EVENT_LO 0x0208 12248693Swpaul#define XM_TXCNT_EVENT_HI 0x020A 12348693Swpaul#define XM_TXCNT_EVENT XM_TXCNT_EVENT_LO 12448693Swpaul#define XM_RXCNT_EVMASK_LO 0x020C 12548693Swpaul#define XM_RXCNT_EVMASK_HI 0x020E 12648693Swpaul#define XM_RXCNT_EVMASK XM_RXCNT_EVMASK_LO 12748693Swpaul#define XM_TXCNT_EVMASK_LO 0x0210 12848693Swpaul#define XM_TXCNT_EVMASK_HI 0x0212 12948693Swpaul#define XM_TXCNT_EVMASK XM_TXCNT_EVMASK_LO 13048693Swpaul 13148693Swpaul/* Statistics command register */ 13248693Swpaul#define XM_STATCMD_CLR_TX 0x0001 13348693Swpaul#define XM_STATCMD_CLR_RX 0x0002 13448693Swpaul#define XM_STATCMD_COPY_TX 0x0004 13548693Swpaul#define XM_STATCMD_COPY_RX 0x0008 13648693Swpaul#define XM_STATCMD_SNAP_TX 0x0010 13748693Swpaul#define XM_STATCMD_SNAP_RX 0x0020 13848693Swpaul 13948693Swpaul/* TX statistics registers */ 14048693Swpaul#define XM_TXSTATS_PKTSOK 0x280 14148693Swpaul#define XM_TXSTATS_BYTESOK_HI 0x284 14248693Swpaul#define XM_TXSTATS_BYTESOK_LO 0x288 14348693Swpaul#define XM_TXSTATS_BCASTSOK 0x28C 14448693Swpaul#define XM_TXSTATS_MCASTSOK 0x290 14548693Swpaul#define XM_TXSTATS_UCASTSOK 0x294 14648693Swpaul#define XM_TXSTATS_GIANTS 0x298 14748693Swpaul#define XM_TXSTATS_BURSTCNT 0x29C 14848693Swpaul#define XM_TXSTATS_PAUSEPKTS 0x2A0 14948693Swpaul#define XM_TXSTATS_MACCTLPKTS 0x2A4 15048693Swpaul#define XM_TXSTATS_SINGLECOLS 0x2A8 15148693Swpaul#define XM_TXSTATS_MULTICOLS 0x2AC 15248693Swpaul#define XM_TXSTATS_EXCESSCOLS 0x2B0 15348693Swpaul#define XM_TXSTATS_LATECOLS 0x2B4 15448693Swpaul#define XM_TXSTATS_DEFER 0x2B8 15548693Swpaul#define XM_TXSTATS_EXCESSDEFER 0x2BC 15648693Swpaul#define XM_TXSTATS_UNDERRUN 0x2C0 15748693Swpaul#define XM_TXSTATS_CARRIERSENSE 0x2C4 15848693Swpaul#define XM_TXSTATS_UTILIZATION 0x2C8 15948693Swpaul#define XM_TXSTATS_64 0x2D0 16048693Swpaul#define XM_TXSTATS_65_127 0x2D4 16148693Swpaul#define XM_TXSTATS_128_255 0x2D8 16248693Swpaul#define XM_TXSTATS_256_511 0x2DC 16348693Swpaul#define XM_TXSTATS_512_1023 0x2E0 16448693Swpaul#define XM_TXSTATS_1024_MAX 0x2E4 16548693Swpaul 16648693Swpaul/* RX statistics registers */ 16748693Swpaul#define XM_RXSTATS_PKTSOK 0x300 16848693Swpaul#define XM_RXSTATS_BYTESOK_HI 0x304 16948693Swpaul#define XM_RXSTATS_BYTESOK_LO 0x308 17048693Swpaul#define XM_RXSTATS_BCASTSOK 0x30C 17148693Swpaul#define XM_RXSTATS_MCASTSOK 0x310 17248693Swpaul#define XM_RXSTATS_UCASTSOK 0x314 17348693Swpaul#define XM_RXSTATS_PAUSEPKTS 0x318 17448693Swpaul#define XM_RXSTATS_MACCTLPKTS 0x31C 17548693Swpaul#define XM_RXSTATS_BADPAUSEPKTS 0x320 17648693Swpaul#define XM_RXSTATS_BADMACCTLPKTS 0x324 17748693Swpaul#define XM_RXSTATS_BURSTCNT 0x328 17848693Swpaul#define XM_RXSTATS_MISSEDPKTS 0x32C 17948693Swpaul#define XM_RXSTATS_FRAMEERRS 0x330 18048693Swpaul#define XM_RXSTATS_OVERRUN 0x334 18148693Swpaul#define XM_RXSTATS_JABBER 0x338 18248693Swpaul#define XM_RXSTATS_CARRLOSS 0x33C 18348693Swpaul#define XM_RXSTATS_INRNGLENERR 0x340 18448693Swpaul#define XM_RXSTATS_SYMERR 0x344 18548693Swpaul#define XM_RXSTATS_SHORTEVENT 0x348 18648693Swpaul#define XM_RXSTATS_RUNTS 0x34C 18748693Swpaul#define XM_RXSTATS_GIANTS 0x350 18848693Swpaul#define XM_RXSTATS_CRCERRS 0x354 18948693Swpaul#define XM_RXSTATS_CEXTERRS 0x35C 19048693Swpaul#define XM_RXSTATS_UTILIZATION 0x360 19148693Swpaul#define XM_RXSTATS_64 0x368 19248693Swpaul#define XM_RXSTATS_65_127 0x36C 19348693Swpaul#define XM_RXSTATS_128_255 0x370 19448693Swpaul#define XM_RXSTATS_256_511 0x374 19548693Swpaul#define XM_RXSTATS_512_1023 0x378 19648693Swpaul#define XM_RXSTATS_1024_MAX 0x37C 19748693Swpaul 19848693Swpaul#define XM_MMUCMD_TX_ENB 0x0001 19948693Swpaul#define XM_MMUCMD_RX_ENB 0x0002 20048693Swpaul#define XM_MMUCMD_GMIILOOP 0x0004 20148693Swpaul#define XM_MMUCMD_RATECTL 0x0008 20248693Swpaul#define XM_MMUCMD_GMIIFDX 0x0010 20348693Swpaul#define XM_MMUCMD_NO_MGMT_PRMB 0x0020 20448693Swpaul#define XM_MMUCMD_SIMCOL 0x0040 20548693Swpaul#define XM_MMUCMD_FORCETX 0x0080 20648693Swpaul#define XM_MMUCMD_LOOPENB 0x0200 20748693Swpaul#define XM_MMUCMD_IGNPAUSE 0x0400 20848693Swpaul#define XM_MMUCMD_PHYBUSY 0x0800 20948693Swpaul#define XM_MMUCMD_PHYDATARDY 0x1000 21048693Swpaul 21148693Swpaul#define XM_TXCMD_AUTOPAD 0x0001 21248693Swpaul#define XM_TXCMD_NOCRC 0x0002 21348693Swpaul#define XM_TXCMD_NOPREAMBLE 0x0004 21448693Swpaul#define XM_TXCMD_NOGIGAMODE 0x0008 21548693Swpaul#define XM_TXCMD_SAMPLELINE 0x0010 21648693Swpaul#define XM_TXCMD_ENCBYPASS 0x0020 21748693Swpaul#define XM_TXCMD_XMITBK2BK 0x0040 21848693Swpaul#define XM_TXCMD_FAIRSHARE 0x0080 21948693Swpaul 22048693Swpaul#define XM_RXCMD_DISABLE_CEXT 0x0001 22148693Swpaul#define XM_RXCMD_STRIPPAD 0x0002 22248693Swpaul#define XM_RXCMD_SAMPLELINE 0x0004 22348693Swpaul#define XM_RXCMD_SELFRX 0x0008 22448693Swpaul#define XM_RXCMD_STRIPFCS 0x0010 22548693Swpaul#define XM_RXCMD_TRANSPARENT 0x0020 22648693Swpaul#define XM_RXCMD_IPGCAPTURE 0x0040 22748693Swpaul#define XM_RXCMD_BIGPKTOK 0x0080 22848693Swpaul#define XM_RXCMD_LENERROK 0x0100 22948693Swpaul 23059478Swpaul#define XM_GPIO_GP0_SET 0x0001 23159478Swpaul#define XM_GPIO_RESETSTATS 0x0004 23259478Swpaul#define XM_GPIO_RESETMAC 0x0008 23359478Swpaul#define XM_GPIO_FORCEINT 0x0020 23459478Swpaul#define XM_GPIO_ANEGINPROG 0x0040 23559478Swpaul 23648693Swpaul#define XM_IMR_RX_EOF 0x0001 23748693Swpaul#define XM_IMR_TX_EOF 0x0002 23848693Swpaul#define XM_IMR_TX_UNDERRUN 0x0004 23948693Swpaul#define XM_IMR_RX_OVERRUN 0x0008 24048693Swpaul#define XM_IMR_TX_STATS_OFLOW 0x0010 24148693Swpaul#define XM_IMR_RX_STATS_OFLOW 0x0020 24248693Swpaul#define XM_IMR_TSTAMP_OFLOW 0x0040 24348693Swpaul#define XM_IMR_AUTONEG_DONE 0x0080 24448693Swpaul#define XM_IMR_NEXTPAGE_RDY 0x0100 24548693Swpaul#define XM_IMR_PAGE_RECEIVED 0x0200 24648693Swpaul#define XM_IMR_LP_REQCFG 0x0400 24748693Swpaul#define XM_IMR_GP0_SET 0x0800 24848693Swpaul#define XM_IMR_FORCEINTR 0x1000 24948693Swpaul#define XM_IMR_TX_ABORT 0x2000 25048693Swpaul#define XM_IMR_LINKEVENT 0x4000 25148693Swpaul 25248693Swpaul#define XM_INTRS \ 25359478Swpaul (~(XM_IMR_GP0_SET|XM_IMR_AUTONEG_DONE|XM_IMR_TX_UNDERRUN)) 25448693Swpaul 25548693Swpaul#define XM_ISR_RX_EOF 0x0001 25648693Swpaul#define XM_ISR_TX_EOF 0x0002 25748693Swpaul#define XM_ISR_TX_UNDERRUN 0x0004 25848693Swpaul#define XM_ISR_RX_OVERRUN 0x0008 25948693Swpaul#define XM_ISR_TX_STATS_OFLOW 0x0010 26048693Swpaul#define XM_ISR_RX_STATS_OFLOW 0x0020 26148693Swpaul#define XM_ISR_TSTAMP_OFLOW 0x0040 26248693Swpaul#define XM_ISR_AUTONEG_DONE 0x0080 26348693Swpaul#define XM_ISR_NEXTPAGE_RDY 0x0100 26448693Swpaul#define XM_ISR_PAGE_RECEIVED 0x0200 26548693Swpaul#define XM_ISR_LP_REQCFG 0x0400 26648693Swpaul#define XM_ISR_GP0_SET 0x0800 26748693Swpaul#define XM_ISR_FORCEINTR 0x1000 26848693Swpaul#define XM_ISR_TX_ABORT 0x2000 26948693Swpaul#define XM_ISR_LINKEVENT 0x4000 27048693Swpaul 27159478Swpaul#define XM_HWCFG_GENEOP 0x0008 27259478Swpaul#define XM_HWCFG_SIGSTATCKH 0x0004 27359478Swpaul#define XM_HWCFG_GMIIMODE 0x0001 27459478Swpaul 27548693Swpaul#define XM_MODE_FLUSH_RXFIFO 0x00000001 27648693Swpaul#define XM_MODE_FLUSH_TXFIFO 0x00000002 27748693Swpaul#define XM_MODE_BIGENDIAN 0x00000004 27848693Swpaul#define XM_MODE_RX_PROMISC 0x00000008 27948693Swpaul#define XM_MODE_RX_NOBROAD 0x00000010 28048693Swpaul#define XM_MODE_RX_NOMULTI 0x00000020 28148693Swpaul#define XM_MODE_RX_NOUNI 0x00000040 28248693Swpaul#define XM_MODE_RX_BADFRAMES 0x00000080 28348693Swpaul#define XM_MODE_RX_CRCERRS 0x00000100 28448693Swpaul#define XM_MODE_RX_GIANTS 0x00000200 28548693Swpaul#define XM_MODE_RX_INRANGELEN 0x00000400 28648693Swpaul#define XM_MODE_RX_RUNTS 0x00000800 28748693Swpaul#define XM_MODE_RX_MACCTL 0x00001000 28848693Swpaul#define XM_MODE_RX_USE_PERFECT 0x00002000 28948693Swpaul#define XM_MODE_RX_USE_STATION 0x00004000 29048693Swpaul#define XM_MODE_RX_USE_HASH 0x00008000 29148693Swpaul#define XM_MODE_RX_ADDRPAIR 0x00010000 29248693Swpaul#define XM_MODE_PAUSEONHI 0x00020000 29348693Swpaul#define XM_MODE_PAUSEONLO 0x00040000 29448693Swpaul#define XM_MODE_TIMESTAMP 0x00080000 29548693Swpaul#define XM_MODE_SENDPAUSE 0x00100000 29648693Swpaul#define XM_MODE_SENDCONTINUOUS 0x00200000 29748693Swpaul#define XM_MODE_LE_STATUSWORD 0x00400000 29848693Swpaul#define XM_MODE_AUTOFIFOPAUSE 0x00800000 29948693Swpaul#define XM_MODE_EXPAUSEGEN 0x02000000 30048693Swpaul#define XM_MODE_RX_INVERSE 0x04000000 30148693Swpaul 30248693Swpaul#define XM_RXSTAT_MACCTL 0x00000001 30348693Swpaul#define XM_RXSTAT_ERRFRAME 0x00000002 30448693Swpaul#define XM_RXSTAT_CRCERR 0x00000004 30548693Swpaul#define XM_RXSTAT_GIANT 0x00000008 30648693Swpaul#define XM_RXSTAT_RUNT 0x00000010 30748693Swpaul#define XM_RXSTAT_FRAMEERR 0x00000020 30848693Swpaul#define XM_RXSTAT_INRANGEERR 0x00000040 30948693Swpaul#define XM_RXSTAT_CARRIERERR 0x00000080 31048693Swpaul#define XM_RXSTAT_COLLERR 0x00000100 31148693Swpaul#define XM_RXSTAT_802_3 0x00000200 31248693Swpaul#define XM_RXSTAT_CARREXTERR 0x00000400 31348693Swpaul#define XM_RXSTAT_BURSTMODE 0x00000800 31448693Swpaul#define XM_RXSTAT_UNICAST 0x00002000 31548693Swpaul#define XM_RXSTAT_MULTICAST 0x00004000 31648693Swpaul#define XM_RXSTAT_BROADCAST 0x00008000 31748693Swpaul#define XM_RXSTAT_VLAN_LEV1 0x00010000 31848693Swpaul#define XM_RXSTAT_VLAN_LEV2 0x00020000 31948693Swpaul#define XM_RXSTAT_LEN 0xFFFC0000 32048693Swpaul 32148693Swpaul/* 32248693Swpaul * XMAC PHY registers, indirectly accessed through 32348693Swpaul * XM_PHY_ADDR and XM_PHY_REG. 32448693Swpaul */ 32548693Swpaul 32648693Swpaul#define XM_PHY_BMCR 0x0000 /* control */ 32748693Swpaul#define XM_PHY_BMSR 0x0001 /* status */ 32848693Swpaul#define XM_PHY_VENID 0x0002 /* vendor id */ 32948693Swpaul#define XM_PHY_DEVID 0x0003 /* device id */ 33048693Swpaul#define XM_PHY_ANAR 0x0004 /* autoneg advertisenemt */ 33148693Swpaul#define XM_PHY_LPAR 0x0005 /* link partner ability */ 33248693Swpaul#define XM_PHY_ANEXP 0x0006 /* autoneg expansion */ 33348693Swpaul#define XM_PHY_NEXTP 0x0007 /* nextpage */ 33448693Swpaul#define XM_PHY_LPNEXTP 0x0008 /* link partner's nextpage */ 33548693Swpaul#define XM_PHY_EXTSTS 0x000F /* extented status */ 33648693Swpaul#define XM_PHY_RESAB 0x0010 /* resolved ability */ 33748693Swpaul 33848693Swpaul#define XM_BMCR_DUPLEX 0x0100 33948693Swpaul#define XM_BMCR_RENEGOTIATE 0x0200 34048693Swpaul#define XM_BMCR_AUTONEGENBL 0x1000 34148693Swpaul#define XM_BMCR_LOOPBACK 0x4000 34248693Swpaul#define XM_BMCR_RESET 0x8000 34348693Swpaul 34448693Swpaul#define XM_BMSR_EXTCAP 0x0001 34548693Swpaul#define XM_BMSR_LINKSTAT 0x0004 34648693Swpaul#define XM_BMSR_AUTONEGABLE 0x0008 34748693Swpaul#define XM_BMSR_REMFAULT 0x0010 34848693Swpaul#define XM_BMSR_AUTONEGDONE 0x0020 34948693Swpaul#define XM_BMSR_EXTSTAT 0x0100 35048693Swpaul 35148693Swpaul#define XM_VENID_XAQTI 0xD14C 35248693Swpaul#define XM_DEVID_XMAC 0x0002 35348693Swpaul 35448693Swpaul#define XM_ANAR_FULLDUPLEX 0x0020 35548693Swpaul#define XM_ANAR_HALFDUPLEX 0x0040 35648693Swpaul#define XM_ANAR_PAUSEBITS 0x0180 35748693Swpaul#define XM_ANAR_REMFAULTBITS 0x1800 35848693Swpaul#define XM_ANAR_ACK 0x4000 35948693Swpaul#define XM_ANAR_NEXTPAGE 0x8000 36048693Swpaul 36148693Swpaul#define XM_LPAR_FULLDUPLEX 0x0020 36248693Swpaul#define XM_LPAR_HALFDUPLEX 0x0040 36348693Swpaul#define XM_LPAR_PAUSEBITS 0x0180 36448693Swpaul#define XM_LPAR_REMFAULTBITS 0x1800 36548693Swpaul#define XM_LPAR_ACK 0x4000 36648693Swpaul#define XM_LPAR_NEXTPAGE 0x8000 36748693Swpaul 36848693Swpaul#define XM_PAUSE_NOPAUSE 0x0000 36948693Swpaul#define XM_PAUSE_SYMPAUSE 0x0080 37048693Swpaul#define XM_PAUSE_ASYMPAUSE 0x0100 37148693Swpaul#define XM_PAUSE_BOTH 0x0180 37248693Swpaul 37348693Swpaul#define XM_REMFAULT_LINKOK 0x0000 37448693Swpaul#define XM_REMFAULT_LINKFAIL 0x0800 37548693Swpaul#define XM_REMFAULT_OFFLINE 0x1000 37648693Swpaul#define XM_REMFAULT_ANEGERR 0x1800 37748693Swpaul 37848693Swpaul#define XM_ANEXP_GOTPAGE 0x0002 37948693Swpaul#define XM_ANEXP_NEXTPAGE_SELF 0x0004 38048693Swpaul#define XM_ANEXP_NEXTPAGE_LP 0x0008 38148693Swpaul 38248693Swpaul#define XM_NEXTP_MESSAGE 0x07FF 38348693Swpaul#define XM_NEXTP_TOGGLE 0x0800 38448693Swpaul#define XM_NEXTP_ACK2 0x1000 38548693Swpaul#define XM_NEXTP_MPAGE 0x2000 38648693Swpaul#define XM_NEXTP_ACK1 0x4000 38748693Swpaul#define XM_NEXTP_NPAGE 0x8000 38848693Swpaul 38948693Swpaul#define XM_LPNEXTP_MESSAGE 0x07FF 39048693Swpaul#define XM_LPNEXTP_TOGGLE 0x0800 39148693Swpaul#define XM_LPNEXTP_ACK2 0x1000 39248693Swpaul#define XM_LPNEXTP_MPAGE 0x2000 39348693Swpaul#define XM_LPNEXTP_ACK1 0x4000 39448693Swpaul#define XM_LPNEXTP_NPAGE 0x8000 39548693Swpaul 39648693Swpaul#define XM_EXTSTS_HALFDUPLEX 0x4000 39748693Swpaul#define XM_EXTSTS_FULLDUPLEX 0x8000 39848693Swpaul 39948693Swpaul#define XM_RESAB_PAUSEMISMATCH 0x0008 40048693Swpaul#define XM_RESAB_ABLMISMATCH 0x0010 40148693Swpaul#define XM_RESAB_FDMODESEL 0x0020 40248693Swpaul#define XM_RESAB_HDMODESEL 0x0040 40348693Swpaul#define XM_RESAB_PAUSEBITS 0x0180 404