sibareg.h revision 203319
1183371Simp/*- 2183371Simp * Copyright (c) 2007 Bruce M. Simpson. 3183371Simp * All rights reserved. 4183371Simp * 5183371Simp * Redistribution and use in source and binary forms, with or without 6183371Simp * modification, are permitted provided that the following conditions 7183371Simp * are met: 8183371Simp * 1. Redistributions of source code must retain the above copyright 9183371Simp * notice, this list of conditions and the following disclaimer. 10183371Simp * 2. Redistributions in binary form must reproduce the above copyright 11183371Simp * notice, this list of conditions and the following disclaimer in the 12183371Simp * documentation and/or other materials provided with the distribution. 13183371Simp * 14183371Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15183371Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16183371Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17183371Simp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18183371Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19183371Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20183371Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21183371Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22183371Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23183371Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24183371Simp * SUCH DAMAGE. 25183371Simp * 26183371Simp * $FreeBSD: head/sys/dev/siba/sibareg.h 203319 2010-01-31 21:18:22Z weongyo $ 27183371Simp */ 28183371Simp 29183371Simp/* 30183371Simp * TODO: sprom 31183371Simp * TODO: implement dma translation bits (if needed for system bus) 32183371Simp */ 33183371Simp 34183371Simp#ifndef _SIBA_SIBAREG_H_ 35183371Simp#define _SIBA_SIBAREG_H_ 36183371Simp 37203319Sweongyo#define PCI_DEVICE_ID_BCM4401 0x4401 38203319Sweongyo#define PCI_DEVICE_ID_BCM4401B0 0x4402 39203319Sweongyo#define PCI_DEVICE_ID_BCM4401B1 0x170c 40203319Sweongyo#define SIBA_PCIR_BAR PCIR_BAR(0) 41203319Sweongyo#define SIBA_CCID_BCM4710 0x4710 42203319Sweongyo#define SIBA_CCID_BCM4704 0x4704 43203319Sweongyo#define SIBA_CCID_SENTRY5 0x5365 44203319Sweongyo 45203319Sweongyo/* 46203319Sweongyo * ChipCommon registers. 47203319Sweongyo */ 48203319Sweongyo#define SIBA_CC_CHIPID 0x0000 49203319Sweongyo#define SIBA_CC_IDMASK 0x0000ffff 50203319Sweongyo#define SIBA_CC_ID(id) (id & SIBA_CC_IDMASK) 51203319Sweongyo#define SIBA_CC_REVMASK 0x000f0000 52203319Sweongyo#define SIBA_CC_REVSHIFT 16 53203319Sweongyo#define SIBA_CC_REV(id) \ 54203319Sweongyo ((id & SIBA_CC_REVMASK) >> SIBA_CC_REVSHIFT) 55203319Sweongyo#define SIBA_CC_PKGMASK 0x00F00000 56203319Sweongyo#define SIBA_CC_PKGSHIFT 20 57203319Sweongyo#define SIBA_CC_PKG(id) \ 58203319Sweongyo ((id & SIBA_CC_PKGMASK) >> SIBA_CC_PKGSHIFT) 59203319Sweongyo#define SIBA_CC_NCORESMASK 0x0F000000 60203319Sweongyo#define SIBA_CC_NCORESSHIFT 24 61203319Sweongyo#define SIBA_CC_NCORES(id) \ 62203319Sweongyo ((id & SIBA_CC_NCORESMASK) >> SIBA_CC_NCORESSHIFT) 63203319Sweongyo#define SIBA_CC_CAPS 0x0004 64203319Sweongyo#define SIBA_CC_CAPS_PWCTL 0x00040000 65203319Sweongyo#define SIBA_CC_CAPS_PMU 0x10000000 /* PMU (rev >= 20) */ 66203319Sweongyo#define SIBA_CC_CHIPCTL 0x0028 /* rev >= 11 */ 67203319Sweongyo#define SIBA_CC_CHIPSTAT 0x002C /* rev >= 11 */ 68203319Sweongyo#define SIBA_CC_BCAST_ADDR 0x0050 /* Broadcast Address */ 69203319Sweongyo#define SIBA_CC_BCAST_DATA 0x0054 /* Broadcast Data */ 70203319Sweongyo#define SIBA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */ 71203319Sweongyo#define SIBA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */ 72203319Sweongyo#define SIBA_CC_CLKSLOW 0x00b8 /* 6 <= Rev <= 9 only */ 73203319Sweongyo#define SIBA_CC_CLKSLOW_SRC 0x00000007 74203319Sweongyo#define SIBA_CC_CLKSLOW_SRC_CRYSTAL 0x00000001 75203319Sweongyo#define SIBA_CC_CLKSLOW_FSLOW 0x00000800 76203319Sweongyo#define SIBA_CC_CLKSLOW_IPLL 0x00001000 77203319Sweongyo#define SIBA_CC_CLKSLOW_ENXTAL 0x00002000 78203319Sweongyo#define SIBA_CC_CLKSYSCTL 0x00C0 /* Rev >= 3 only */ 79203319Sweongyo#define SIBA_CC_CLKCTLSTATUS 0x01e0 80203319Sweongyo#define SIBA_CC_CLKCTLSTATUS_HT 0x00010000 81203319Sweongyo#define SIBA_CC_UART0 0x0300 /* offset of UART0 */ 82203319Sweongyo#define SIBA_CC_UART1 0x0400 /* offset of UART1 */ 83203319Sweongyo#define SIBA_CC_PMUCTL 0x0600 /* PMU control */ 84203319Sweongyo#define SIBA_CC_PMUCTL_ILP 0xffff0000 /* mask */ 85203319Sweongyo#define SIBA_CC_PMUCTL_NOILP 0x00000200 86203319Sweongyo#define SIBA_CC_PMUCTL_XF 0x0000007c /* crystal freq */ 87203319Sweongyo#define SIBA_CC_PMUCTL_XF_VAL(id) ((id & 0x0000007c) >> 2) 88203319Sweongyo#define SIBA_CC_PMUCAPS 0x0604 89203319Sweongyo#define SIBA_CC_PMUCAPS_REV 0x000000ff 90203319Sweongyo#define SIBA_CC_PMU_MINRES 0x0618 91203319Sweongyo#define SIBA_CC_PMU_MAXRES 0x061c 92203319Sweongyo#define SIBA_CC_PMU_TABSEL 0x0620 93203319Sweongyo#define SIBA_CC_PMU_DEPMSK 0x0624 94203319Sweongyo#define SIBA_CC_PMU_UPDNTM 0x0628 95203319Sweongyo#define SIBA_CC_PLLCTL_ADDR 0x0660 96203319Sweongyo#define SIBA_CC_PLLCTL_DATA 0x0664 97203319Sweongyo 98203319Sweongyo#define SIBA_CC_PMU0_PLL0 0 99203319Sweongyo#define SIBA_CC_PMU0_PLL0_PDIV_MSK 0x00000001 100203319Sweongyo#define SIBA_CC_PMU0_PLL0_PDIV_FREQ 25000 101203319Sweongyo#define SIBA_CC_PMU0_PLL1 1 102203319Sweongyo#define SIBA_CC_PMU0_PLL1_IMSK 0xf0000000 103203319Sweongyo#define SIBA_CC_PMU0_PLL1_FMSK 0x0fffff00 104203319Sweongyo#define SIBA_CC_PMU0_PLL1_STOPMOD 0x00000040 105203319Sweongyo#define SIBA_CC_PMU0_PLL2 2 106203319Sweongyo#define SIBA_CC_PMU0_PLL2_IMSKHI 0x0000000f 107203319Sweongyo#define SIBA_CC_PMU1_PLL0 0 108203319Sweongyo#define SIBA_CC_PMU1_PLL0_P1DIV 0x00f00000 109203319Sweongyo#define SIBA_CC_PMU1_PLL0_P2DIV 0x0f000000 110203319Sweongyo#define SIBA_CC_PMU1_PLL2 2 111203319Sweongyo#define SIBA_CC_PMU1_PLL2_NDIVMODE 0x000e0000 112203319Sweongyo#define SIBA_CC_PMU1_PLL2_NDIVINT 0x1ff00000 113203319Sweongyo#define SIBA_CC_PMU1_PLL3 3 114203319Sweongyo#define SIBA_CC_PMU1_PLL3_NDIVFRAC 0x00ffffff 115203319Sweongyo#define SIBA_CC_PMU1_PLL5 5 116203319Sweongyo#define SIBA_CC_PMU1_PLL5_CLKDRV 0xffffff00 117203319Sweongyo 118203319Sweongyo#define SIBA_CC_PMU0_DEFAULT_XTALFREQ 20000 119203319Sweongyo#define SIBA_CC_PMU1_DEFAULT_FREQ 15360 120203319Sweongyo 121203319Sweongyo#define SIBA_CC_PMU1_PLLTAB_ENTRY \ 122203319Sweongyo{ \ 123203319Sweongyo { 12000, 1, 3, 22, 0x9, 0xffffef }, \ 124203319Sweongyo { 13000, 2, 1, 6, 0xb, 0x483483 }, \ 125203319Sweongyo { 14400, 3, 1, 10, 0xa, 0x1c71c7 }, \ 126203319Sweongyo { 15360, 4, 1, 5, 0xb, 0x755555 }, \ 127203319Sweongyo { 16200, 5, 1, 10, 0x5, 0x6e9e06 }, \ 128203319Sweongyo { 16800, 6, 1, 10, 0x5, 0x3cf3cf }, \ 129203319Sweongyo { 19200, 7, 1, 9, 0x5, 0x17b425 }, \ 130203319Sweongyo { 19800, 8, 1, 11, 0x4, 0xa57eb }, \ 131203319Sweongyo { 20000, 9, 1, 11, 0x4, 0 }, \ 132203319Sweongyo { 24000, 10, 3, 11, 0xa, 0 }, \ 133203319Sweongyo { 25000, 11, 5, 16, 0xb, 0 }, \ 134203319Sweongyo { 26000, 12, 1, 2, 0x10, 0xec4ec4 }, \ 135203319Sweongyo { 30000, 13, 3, 8, 0xb, 0 }, \ 136203319Sweongyo { 38400, 14, 1, 5, 0x4, 0x955555 }, \ 137203319Sweongyo { 40000, 15, 1, 2, 0xb, 0 } \ 138203319Sweongyo} 139203319Sweongyo 140203319Sweongyo#define SIBA_CC_PMU0_PLLTAB_ENTRY \ 141203319Sweongyo{ \ 142203319Sweongyo { 12000, 1, 73, 349525, }, { 13000, 2, 67, 725937, }, \ 143203319Sweongyo { 14400, 3, 61, 116508, }, { 15360, 4, 57, 305834, }, \ 144203319Sweongyo { 16200, 5, 54, 336579, }, { 16800, 6, 52, 399457, }, \ 145203319Sweongyo { 19200, 7, 45, 873813, }, { 19800, 8, 44, 466033, }, \ 146203319Sweongyo { 20000, 9, 44, 0, }, { 25000, 10, 70, 419430, }, \ 147203319Sweongyo { 26000, 11, 67, 725937, }, { 30000, 12, 58, 699050, }, \ 148203319Sweongyo { 38400, 13, 45, 873813, }, { 40000, 14, 45, 0, }, \ 149203319Sweongyo} 150203319Sweongyo 151203319Sweongyo#define SIBA_CC_PMU_4325_BURST 1 152203319Sweongyo#define SIBA_CC_PMU_4325_CLBURST 3 153203319Sweongyo#define SIBA_CC_PMU_4325_LN 10 154203319Sweongyo#define SIBA_CC_PMU_4325_CRYSTAL 13 155203319Sweongyo#define SIBA_CC_PMU_4325_RX_PWR 15 156203319Sweongyo#define SIBA_CC_PMU_4325_TX_PWR 16 157203319Sweongyo#define SIBA_CC_PMU_4325_LOGEN_PWR 18 158203319Sweongyo#define SIBA_CC_PMU_4325_AFE_PWR 19 159203319Sweongyo#define SIBA_CC_PMU_4325_BBPLL_PWR 20 160203319Sweongyo#define SIBA_CC_PMU_4325_HT 21 161203319Sweongyo#define SIBA_CC_PMU_4328_EXT_SWITCH_PWM 0 162203319Sweongyo#define SIBA_CC_PMU_4328_BB_SWITCH_PWM 1 163203319Sweongyo#define SIBA_CC_PMU_4328_BB_SWITCH_BURST 2 164203319Sweongyo#define SIBA_CC_PMU_4328_BB_EXT_SWITCH_BURST 3 165203319Sweongyo#define SIBA_CC_PMU_4328_ILP_REQUEST 4 166203319Sweongyo#define SIBA_CC_PMU_4328_RADSWITCH_PWM 5 /* radio switch */ 167203319Sweongyo#define SIBA_CC_PMU_4328_RADSWITCH_BURST 6 168203319Sweongyo#define SIBA_CC_PMU_4328_ROM_SWITCH 7 169203319Sweongyo#define SIBA_CC_PMU_4328_PA_REF 8 170203319Sweongyo#define SIBA_CC_PMU_4328_RADIO 9 171203319Sweongyo#define SIBA_CC_PMU_4328_AFE 10 172203319Sweongyo#define SIBA_CC_PMU_4328_PLL 11 173203319Sweongyo#define SIBA_CC_PMU_4328_BG_FILTBYP 12 174203319Sweongyo#define SIBA_CC_PMU_4328_TX_FILTBYP 13 175203319Sweongyo#define SIBA_CC_PMU_4328_RX_FILTBYP 14 176203319Sweongyo#define SIBA_CC_PMU_4328_CRYSTAL_PU 15 177203319Sweongyo#define SIBA_CC_PMU_4328_CRYSTAL_EN 16 178203319Sweongyo#define SIBA_CC_PMU_4328_BB_PLL_FILTBYP 17 179203319Sweongyo#define SIBA_CC_PMU_4328_RF_PLL_FILTBYP 18 180203319Sweongyo#define SIBA_CC_PMU_4328_BB_PLL_PU 19 181203319Sweongyo#define SIBA_CC_PMU_5354_BB_PLL_PU 19 182203319Sweongyo 183203319Sweongyo#define SIBA_CC_PMU_4325_RES_UPDOWN \ 184203319Sweongyo{ \ 185203319Sweongyo { SIBA_CC_PMU_4325_CRYSTAL, 0x1501 } \ 186203319Sweongyo} 187203319Sweongyo 188203319Sweongyo#define SIBA_CC_PMU_4325_RES_DEPEND \ 189203319Sweongyo{ \ 190203319Sweongyo { SIBA_CC_PMU_4325_HT, SIBA_CC_PMU_DEP_ADD, \ 191203319Sweongyo ((1 << SIBA_CC_PMU_4325_RX_PWR) | \ 192203319Sweongyo (1 << SIBA_CC_PMU_4325_TX_PWR) | \ 193203319Sweongyo (1 << SIBA_CC_PMU_4325_LOGEN_PWR) | \ 194203319Sweongyo (1 << SIBA_CC_PMU_4325_AFE_PWR)) } \ 195203319Sweongyo} 196203319Sweongyo 197203319Sweongyo#define SIBA_CC_PMU_4328_RES_UPDOWN \ 198203319Sweongyo{ \ 199203319Sweongyo { SIBA_CC_PMU_4328_EXT_SWITCH_PWM, 0x0101 }, \ 200203319Sweongyo { SIBA_CC_PMU_4328_BB_SWITCH_PWM, 0x1f01 }, \ 201203319Sweongyo { SIBA_CC_PMU_4328_BB_SWITCH_BURST, 0x010f }, \ 202203319Sweongyo { SIBA_CC_PMU_4328_BB_EXT_SWITCH_BURST, 0x0101 }, \ 203203319Sweongyo { SIBA_CC_PMU_4328_ILP_REQUEST, 0x0202 }, \ 204203319Sweongyo { SIBA_CC_PMU_4328_RADSWITCH_PWM, 0x0f01 }, \ 205203319Sweongyo { SIBA_CC_PMU_4328_RADSWITCH_BURST, 0x0f01 }, \ 206203319Sweongyo { SIBA_CC_PMU_4328_ROM_SWITCH, 0x0101 }, \ 207203319Sweongyo { SIBA_CC_PMU_4328_PA_REF, 0x0f01 }, \ 208203319Sweongyo { SIBA_CC_PMU_4328_RADIO, 0x0f01 }, \ 209203319Sweongyo { SIBA_CC_PMU_4328_AFE, 0x0f01 }, \ 210203319Sweongyo { SIBA_CC_PMU_4328_PLL, 0x0f01 }, \ 211203319Sweongyo { SIBA_CC_PMU_4328_BG_FILTBYP, 0x0101 }, \ 212203319Sweongyo { SIBA_CC_PMU_4328_TX_FILTBYP, 0x0101 }, \ 213203319Sweongyo { SIBA_CC_PMU_4328_RX_FILTBYP, 0x0101 }, \ 214203319Sweongyo { SIBA_CC_PMU_4328_CRYSTAL_PU, 0x0101 }, \ 215203319Sweongyo { SIBA_CC_PMU_4328_CRYSTAL_EN, 0xa001 }, \ 216203319Sweongyo { SIBA_CC_PMU_4328_BB_PLL_FILTBYP, 0x0101 }, \ 217203319Sweongyo { SIBA_CC_PMU_4328_RF_PLL_FILTBYP, 0x0101 }, \ 218203319Sweongyo { SIBA_CC_PMU_4328_BB_PLL_PU, 0x0701 }, \ 219203319Sweongyo} 220203319Sweongyo 221203319Sweongyo#define SIBA_CC_PMU_4328_RES_DEPEND \ 222203319Sweongyo{ \ 223203319Sweongyo { SIBA_CC_PMU_4328_ILP_REQUEST, SIBA_CC_PMU_DEP_SET, \ 224203319Sweongyo ((1 << SIBA_CC_PMU_4328_EXT_SWITCH_PWM) | \ 225203319Sweongyo (1 << SIBA_CC_PMU_4328_BB_SWITCH_PWM)) }, \ 226203319Sweongyo} 227203319Sweongyo 228203319Sweongyo#define SIBA_CC_CHST_4325_PMUTOP_2B 0x00000200 229203319Sweongyo 230203319Sweongyo#define SIBA_BAR0 0x80 231203319Sweongyo#define SIBA_IRQMASK 0x94 232203319Sweongyo#define SIBA_GPIO_IN 0xb0 233203319Sweongyo#define SIBA_GPIO_OUT 0xb4 234203319Sweongyo#define SIBA_GPIO_OUT_EN 0xb8 235203319Sweongyo#define SIBA_GPIO_CRYSTAL 0x40 236203319Sweongyo#define SIBA_GPIO_PLL 0x80 237203319Sweongyo 238203319Sweongyo#define SIBA_REGWIN(x) \ 239203319Sweongyo (SIBA_ENUM_START + ((x) * SIBA_CORE_LEN)) 240183371Simp#define SIBA_CORE_LEN 0x00001000 /* Size of cfg per core */ 241183371Simp#define SIBA_CFG_END 0x00010000 /* Upper bound of cfg space */ 242183371Simp#define SIBA_MAX_CORES (SIBA_CFG_END/SIBA_CORE_LEN) /* #max cores */ 243203319Sweongyo#define SIBA_ENUM_START 0x18000000U 244203319Sweongyo#define SIBA_ENUM_END 0x18010000U 245183371Simp 246203319Sweongyo#define SIBA_DMA_TRANSLATION_MASK 0xc0000000 247183371Simp 248203319Sweongyo#define SIBA_PCI_DMA 0x40000000U 249203319Sweongyo#define SIBA_TPS 0x0f18 250203319Sweongyo#define SIBA_TPS_BPFLAG 0x0000003f 251203319Sweongyo#define SIBA_IAS 0x0f90 /* Initiator Agent State */ 252203319Sweongyo#define SIBA_IAS_INBAND_ERR 0x00020000 253203319Sweongyo#define SIBA_IAS_TIMEOUT 0x00040000 254203319Sweongyo#define SIBA_INTR_MASK 0x0f94 255203319Sweongyo#define SIBA_TGSLOW 0x0f98 256203319Sweongyo#define SIBA_TGSLOW_RESET 0x00000001 /* target state low */ 257203319Sweongyo#define SIBA_TGSLOW_REJECT_22 0x00000002 258203319Sweongyo#define SIBA_TGSLOW_REJECT_23 0x00000004 259203319Sweongyo#define SIBA_TGSLOW_CLOCK 0x00010000 260203319Sweongyo#define SIBA_TGSLOW_FGC 0x00020000 261203319Sweongyo#define SIBA_TGSHIGH 0x0f9c 262203319Sweongyo#define SIBA_TGSHIGH_SERR 0x00000001 263203319Sweongyo#define SIBA_TGSHIGH_BUSY 0x00000004 264203319Sweongyo#define SIBA_TGSHIGH_DMA64 0x10000000 265203319Sweongyo#define SIBA_IMCFGLO 0x0fa8 266203319Sweongyo#define SIBA_IMCFGLO_SERTO 0x00000007 267203319Sweongyo#define SIBA_IMCFGLO_REQTO 0x00000070 268203319Sweongyo#define SIBA_IDLOW 0x0ff8 269203319Sweongyo#define SIBA_IDLOW_SSBREV 0xf0000000 270203319Sweongyo#define SIBA_IDLOW_SSBREV_22 0x00000000 271203319Sweongyo#define SIBA_IDLOW_SSBREV_23 0x10000000 272203319Sweongyo#define SIBA_IDLOW_SSBREV_24 0x40000000 273203319Sweongyo#define SIBA_IDLOW_SSBREV_25 0x50000000 274203319Sweongyo#define SIBA_IDLOW_SSBREV_26 0x60000000 275203319Sweongyo#define SIBA_IDLOW_SSBREV_27 0x70000000 276203319Sweongyo#define SIBA_IDHIGH 0x0ffc 277203319Sweongyo#define SIBA_IDHIGH_CORECODEMASK 0x00008FF0 /* Core Code */ 278203319Sweongyo#define SIBA_IDHIGH_CORECODE_SHIFT 4 279203319Sweongyo#define SIBA_IDHIGH_CORECODE(id) \ 280203319Sweongyo ((id & SIBA_IDHIGH_CORECODEMASK) >> SIBA_IDHIGH_CORECODE_SHIFT) 281203319Sweongyo/* Revision Code (low part) */ 282203319Sweongyo#define SIBA_IDHIGH_REVLO 0x0000000f 283203319Sweongyo/* Revision Code (high part) */ 284203319Sweongyo#define SIBA_IDHIGH_REVHI 0x00007000 285203319Sweongyo#define SIBA_IDHIGH_REVHI_SHIFT 8 286203319Sweongyo#define SIBA_IDHIGH_REV(id) \ 287203319Sweongyo ((id & SIBA_IDHIGH_REVLO) | ((id & SIBA_IDHIGH_REVHI) >> \ 288203319Sweongyo SIBA_IDHIGH_REVHI_SHIFT)) 289203319Sweongyo#define SIBA_IDHIGH_VENDORMASK 0xFFFF0000 /* Vendor Code */ 290203319Sweongyo#define SIBA_IDHIGH_VENDOR_SHIFT 16 291203319Sweongyo#define SIBA_IDHIGH_VENDOR(id) \ 292203319Sweongyo ((id & SIBA_IDHIGH_VENDORMASK) >> SIBA_IDHIGH_VENDOR_SHIFT) 293183371Simp 294203319Sweongyo#define SIBA_SPROMSIZE_R123 64 295203319Sweongyo#define SIBA_SPROMSIZE_R4 220 296203319Sweongyo#define SIBA_SPROM_BASE 0x1000 297203319Sweongyo#define SIBA_SPROM_REV_CRC 0xff00 298203319Sweongyo#define SIBA_SPROM1_MAC_80211BG 0x1048 299203319Sweongyo#define SIBA_SPROM1_MAC_ETH 0x104e 300203319Sweongyo#define SIBA_SPROM1_MAC_80211A 0x1054 301203319Sweongyo#define SIBA_SPROM1_ETHPHY 0x105a 302203319Sweongyo#define SIBA_SPROM1_ETHPHY_MII_ETH0 0x001f 303203319Sweongyo#define SIBA_SPROM1_ETHPHY_MII_ETH1 0x03e0 304203319Sweongyo#define SIBA_SPROM1_ETHPHY_MDIO_ETH0 (1 << 14) 305203319Sweongyo#define SIBA_SPROM1_ETHPHY_MDIO_ETH1 (1 << 15) 306203319Sweongyo#define SIBA_SPROM1_BOARDINFO 0x105c 307203319Sweongyo#define SIBA_SPROM1_BOARDINFO_BREV 0x00ff 308203319Sweongyo#define SIBA_SPROM1_BOARDINFO_CCODE 0x0f00 309203319Sweongyo#define SIBA_SPROM1_BOARDINFO_ANTBG 0x3000 310203319Sweongyo#define SIBA_SPROM1_BOARDINFO_ANTA 0xc000 311203319Sweongyo#define SIBA_SPROM1_PA0B0 0x105e 312203319Sweongyo#define SIBA_SPROM1_PA0B1 0x1060 313203319Sweongyo#define SIBA_SPROM1_PA0B2 0x1062 314203319Sweongyo#define SIBA_SPROM1_GPIOA 0x1064 315203319Sweongyo#define SIBA_SPROM1_GPIOA_P0 0x00ff 316203319Sweongyo#define SIBA_SPROM1_GPIOA_P1 0xff00 317203319Sweongyo#define SIBA_SPROM1_GPIOB 0x1066 318203319Sweongyo#define SIBA_SPROM1_GPIOB_P2 0x00ff 319203319Sweongyo#define SIBA_SPROM1_GPIOB_P3 0xff00 320203319Sweongyo#define SIBA_SPROM1_MAXPWR 0x1068 321203319Sweongyo#define SIBA_SPROM1_MAXPWR_BG 0x00ff 322203319Sweongyo#define SIBA_SPROM1_MAXPWR_A 0xff00 323203319Sweongyo#define SIBA_SPROM1_PA1B0 0x106a 324203319Sweongyo#define SIBA_SPROM1_PA1B1 0x106c 325203319Sweongyo#define SIBA_SPROM1_PA1B2 0x106e 326203319Sweongyo#define SIBA_SPROM1_TSSI 0x1070 327203319Sweongyo#define SIBA_SPROM1_TSSI_BG 0x00ff 328203319Sweongyo#define SIBA_SPROM1_TSSI_A 0xff00 329203319Sweongyo#define SIBA_SPROM1_BFLOW 0x1072 330203319Sweongyo#define SIBA_SPROM1_AGAIN 0x1074 331203319Sweongyo#define SIBA_SPROM1_AGAIN_BG 0x00ff 332203319Sweongyo#define SIBA_SPROM1_AGAIN_A 0xff00 333203319Sweongyo#define SIBA_SPROM2_BFHIGH 0x1038 334203319Sweongyo#define SIBA_SPROM3_MAC_80211BG 0x104a 335203319Sweongyo#define SIBA_SPROM4_MAC_80211BG 0x104c 336203319Sweongyo#define SIBA_SPROM4_ETHPHY 0x105a 337203319Sweongyo#define SIBA_SPROM4_ETHPHY_ET0A 0x001f 338203319Sweongyo#define SIBA_SPROM4_ETHPHY_ET1A 0x03e0 339203319Sweongyo#define SIBA_SPROM4_CCODE 0x1052 340203319Sweongyo#define SIBA_SPROM4_ANTAVAIL 0x105d 341203319Sweongyo#define SIBA_SPROM4_ANTAVAIL_A 0x00ff 342203319Sweongyo#define SIBA_SPROM4_ANTAVAIL_BG 0xff00 343203319Sweongyo#define SIBA_SPROM4_BFLOW 0x1044 344203319Sweongyo#define SIBA_SPROM4_AGAIN01 0x105e 345203319Sweongyo#define SIBA_SPROM4_AGAIN0 0x00ff 346203319Sweongyo#define SIBA_SPROM4_AGAIN1 0xff00 347203319Sweongyo#define SIBA_SPROM4_AGAIN23 0x1060 348203319Sweongyo#define SIBA_SPROM4_AGAIN2 0x00ff 349203319Sweongyo#define SIBA_SPROM4_AGAIN3 0xff00 350203319Sweongyo#define SIBA_SPROM4_BFHIGH 0x1046 351203319Sweongyo#define SIBA_SPROM4_MAXP_BG 0x1080 352203319Sweongyo#define SIBA_SPROM4_MAXP_BG_MASK 0x00ff 353203319Sweongyo#define SIBA_SPROM4_TSSI_BG 0xff00 354203319Sweongyo#define SIBA_SPROM4_MAXP_A 0x108a 355203319Sweongyo#define SIBA_SPROM4_MAXP_A_MASK 0x00ff 356203319Sweongyo#define SIBA_SPROM4_TSSI_A 0xff00 357203319Sweongyo#define SIBA_SPROM4_GPIOA 0x1056 358203319Sweongyo#define SIBA_SPROM4_GPIOA_P0 0x00ff 359203319Sweongyo#define SIBA_SPROM4_GPIOA_P1 0xff00 360203319Sweongyo#define SIBA_SPROM4_GPIOB 0x1058 361203319Sweongyo#define SIBA_SPROM4_GPIOB_P2 0x00ff 362203319Sweongyo#define SIBA_SPROM4_GPIOB_P3 0xff00 363203319Sweongyo#define SIBA_SPROM5_BFLOW 0x104a 364203319Sweongyo#define SIBA_SPROM5_BFHIGH 0x104c 365203319Sweongyo#define SIBA_SPROM5_MAC_80211BG 0x1052 366203319Sweongyo#define SIBA_SPROM5_CCODE 0x1044 367203319Sweongyo#define SIBA_SPROM5_GPIOA 0x1076 368203319Sweongyo#define SIBA_SPROM5_GPIOA_P0 0x00ff 369203319Sweongyo#define SIBA_SPROM5_GPIOA_P1 0xff00 370203319Sweongyo#define SIBA_SPROM5_GPIOB 0x1078 371203319Sweongyo#define SIBA_SPROM5_GPIOB_P2 0x00ff 372203319Sweongyo#define SIBA_SPROM5_GPIOB_P3 0xff00 373203319Sweongyo#define SIBA_SPROM8_BFLOW 0x1084 374203319Sweongyo#define SIBA_SPROM8_BFHIGH 0x1086 375203319Sweongyo#define SIBA_SPROM8_CCODE 0x1092 376203319Sweongyo#define SIBA_SPROM8_ANTAVAIL 0x109c 377203319Sweongyo#define SIBA_SPROM8_ANTAVAIL_A 0xff00 378203319Sweongyo#define SIBA_SPROM8_ANTAVAIL_BG 0x00ff 379203319Sweongyo#define SIBA_SPROM8_AGAIN01 0x109e 380203319Sweongyo#define SIBA_SPROM8_AGAIN0 0x00ff 381203319Sweongyo#define SIBA_SPROM8_AGAIN1 0xff00 382203319Sweongyo#define SIBA_SPROM8_AGAIN23 0x10a0 383203319Sweongyo#define SIBA_SPROM8_AGAIN2 0x00ff 384203319Sweongyo#define SIBA_SPROM8_AGAIN3 0xff00 385203319Sweongyo#define SIBA_SPROM8_GPIOA 0x1096 386203319Sweongyo#define SIBA_SPROM8_GPIOA_P0 0x00ff 387203319Sweongyo#define SIBA_SPROM8_GPIOA_P1 0xff00 388203319Sweongyo#define SIBA_SPROM8_GPIOB 0x1098 389203319Sweongyo#define SIBA_SPROM8_GPIOB_P2 0x00ff 390203319Sweongyo#define SIBA_SPROM8_GPIOB_P3 0xff00 391203319Sweongyo#define SIBA_SPROM8_MAXP_BG 0x10c0 392203319Sweongyo#define SIBA_SPROM8_MAXP_BG_MASK 0x00ff 393203319Sweongyo#define SIBA_SPROM8_TSSI_BG 0xff00 394203319Sweongyo#define SIBA_SPROM8_MAXP_A 0x10c8 395203319Sweongyo#define SIBA_SPROM8_MAXP_A_MASK 0x00ff 396203319Sweongyo#define SIBA_SPROM8_TSSI_A 0xff00 397183371Simp 398203319Sweongyo#define SIBA_BOARDVENDOR_DELL 0x1028 399203319Sweongyo#define SIBA_BOARDVENDOR_BCM 0x14e4 400203319Sweongyo#define SIBA_BOARD_BCM4309G 0x0421 401203319Sweongyo#define SIBA_BOARD_MP4318 0x044a 402203319Sweongyo#define SIBA_BOARD_BU4306 0x0416 403203319Sweongyo#define SIBA_BOARD_BU4309 0x040a 404183371Simp 405203319Sweongyo#define SIBA_PCICORE_BCAST_ADDR SIBA_CC_BCAST_ADDR 406203319Sweongyo#define SIBA_PCICORE_BCAST_DATA SIBA_CC_BCAST_DATA 407203319Sweongyo#define SIBA_PCICORE_SBTOPCI0 0x0100 408203319Sweongyo#define SIBA_PCICORE_SBTOPCI1 0x0104 409203319Sweongyo#define SIBA_PCICORE_SBTOPCI2 0x0108 410203319Sweongyo#define SIBA_PCICORE_MDIO_CTL 0x0128 411203319Sweongyo#define SIBA_PCICORE_MDIO_DATA 0x012c 412203319Sweongyo#define SIBA_PCICORE_SBTOPCI_PREF 0x00000004 413203319Sweongyo#define SIBA_PCICORE_SBTOPCI_BURST 0x00000008 414203319Sweongyo#define SIBA_PCICORE_SBTOPCI_MRM 0x00000020 415183371Simp 416183371Simp#endif /* _SIBA_SIBAREG_H_ */ 417