1183371Simp/*- 2183371Simp * Copyright (c) 2007 Bruce M. Simpson. 3183371Simp * All rights reserved. 4183371Simp * 5183371Simp * Redistribution and use in source and binary forms, with or without 6183371Simp * modification, are permitted provided that the following conditions 7183371Simp * are met: 8183371Simp * 1. Redistributions of source code must retain the above copyright 9183371Simp * notice, this list of conditions and the following disclaimer. 10183371Simp * 2. Redistributions in binary form must reproduce the above copyright 11183371Simp * notice, this list of conditions and the following disclaimer in the 12183371Simp * documentation and/or other materials provided with the distribution. 13183371Simp * 14183371Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15183371Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16183371Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17183371Simp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18183371Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19183371Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20183371Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21183371Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22183371Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23183371Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24183371Simp * SUCH DAMAGE. 25183371Simp * 26183371Simp * $FreeBSD: releng/11.0/sys/dev/siba/sibareg.h 300185 2016-05-19 04:11:49Z adrian $ 27183371Simp */ 28183371Simp 29183371Simp/* 30183371Simp * TODO: sprom 31183371Simp * TODO: implement dma translation bits (if needed for system bus) 32183371Simp */ 33183371Simp 34183371Simp#ifndef _SIBA_SIBAREG_H_ 35203944Sweongyo#define _SIBA_SIBAREG_H_ 36183371Simp 37203319Sweongyo#define PCI_DEVICE_ID_BCM4401 0x4401 38203319Sweongyo#define PCI_DEVICE_ID_BCM4401B0 0x4402 39203319Sweongyo#define PCI_DEVICE_ID_BCM4401B1 0x170c 40203319Sweongyo#define SIBA_PCIR_BAR PCIR_BAR(0) 41203319Sweongyo#define SIBA_CCID_BCM4710 0x4710 42203319Sweongyo#define SIBA_CCID_BCM4704 0x4704 43203319Sweongyo#define SIBA_CCID_SENTRY5 0x5365 44203319Sweongyo 45203319Sweongyo/* 46203319Sweongyo * ChipCommon registers. 47203319Sweongyo */ 48203319Sweongyo#define SIBA_CC_CHIPID 0x0000 49203319Sweongyo#define SIBA_CC_IDMASK 0x0000ffff 50203319Sweongyo#define SIBA_CC_ID(id) (id & SIBA_CC_IDMASK) 51203319Sweongyo#define SIBA_CC_REVMASK 0x000f0000 52203319Sweongyo#define SIBA_CC_REVSHIFT 16 53203319Sweongyo#define SIBA_CC_REV(id) \ 54203319Sweongyo ((id & SIBA_CC_REVMASK) >> SIBA_CC_REVSHIFT) 55203319Sweongyo#define SIBA_CC_PKGMASK 0x00F00000 56203319Sweongyo#define SIBA_CC_PKGSHIFT 20 57203319Sweongyo#define SIBA_CC_PKG(id) \ 58203319Sweongyo ((id & SIBA_CC_PKGMASK) >> SIBA_CC_PKGSHIFT) 59203319Sweongyo#define SIBA_CC_NCORESMASK 0x0F000000 60203319Sweongyo#define SIBA_CC_NCORESSHIFT 24 61203319Sweongyo#define SIBA_CC_NCORES(id) \ 62203319Sweongyo ((id & SIBA_CC_NCORESMASK) >> SIBA_CC_NCORESSHIFT) 63203319Sweongyo#define SIBA_CC_CAPS 0x0004 64203319Sweongyo#define SIBA_CC_CAPS_PWCTL 0x00040000 65203319Sweongyo#define SIBA_CC_CAPS_PMU 0x10000000 /* PMU (rev >= 20) */ 66203319Sweongyo#define SIBA_CC_CHIPCTL 0x0028 /* rev >= 11 */ 67203319Sweongyo#define SIBA_CC_CHIPSTAT 0x002C /* rev >= 11 */ 68203319Sweongyo#define SIBA_CC_BCAST_ADDR 0x0050 /* Broadcast Address */ 69203319Sweongyo#define SIBA_CC_BCAST_DATA 0x0054 /* Broadcast Data */ 70203319Sweongyo#define SIBA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */ 71203319Sweongyo#define SIBA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */ 72203319Sweongyo#define SIBA_CC_CLKSLOW 0x00b8 /* 6 <= Rev <= 9 only */ 73203319Sweongyo#define SIBA_CC_CLKSLOW_SRC 0x00000007 74203319Sweongyo#define SIBA_CC_CLKSLOW_SRC_CRYSTAL 0x00000001 75203319Sweongyo#define SIBA_CC_CLKSLOW_FSLOW 0x00000800 76203319Sweongyo#define SIBA_CC_CLKSLOW_IPLL 0x00001000 77203319Sweongyo#define SIBA_CC_CLKSLOW_ENXTAL 0x00002000 78203319Sweongyo#define SIBA_CC_CLKSYSCTL 0x00C0 /* Rev >= 3 only */ 79203319Sweongyo#define SIBA_CC_CLKCTLSTATUS 0x01e0 80203319Sweongyo#define SIBA_CC_CLKCTLSTATUS_HT 0x00010000 81203319Sweongyo#define SIBA_CC_UART0 0x0300 /* offset of UART0 */ 82203319Sweongyo#define SIBA_CC_UART1 0x0400 /* offset of UART1 */ 83203319Sweongyo#define SIBA_CC_PMUCTL 0x0600 /* PMU control */ 84299534Sadrian#define SIBA_CC_PMUCTL_PLL_UPD 0x00000400 85203319Sweongyo#define SIBA_CC_PMUCTL_ILP 0xffff0000 /* mask */ 86203319Sweongyo#define SIBA_CC_PMUCTL_NOILP 0x00000200 87203319Sweongyo#define SIBA_CC_PMUCTL_XF 0x0000007c /* crystal freq */ 88203319Sweongyo#define SIBA_CC_PMUCTL_XF_VAL(id) ((id & 0x0000007c) >> 2) 89203319Sweongyo#define SIBA_CC_PMUCAPS 0x0604 90203319Sweongyo#define SIBA_CC_PMUCAPS_REV 0x000000ff 91203319Sweongyo#define SIBA_CC_PMU_MINRES 0x0618 92203319Sweongyo#define SIBA_CC_PMU_MAXRES 0x061c 93203319Sweongyo#define SIBA_CC_PMU_TABSEL 0x0620 94203319Sweongyo#define SIBA_CC_PMU_DEPMSK 0x0624 95203319Sweongyo#define SIBA_CC_PMU_UPDNTM 0x0628 96299534Sadrian#define SIBA_CC_CHIPCTL_ADDR 0x0650 97299534Sadrian#define SIBA_CC_CHIPCTL_DATA 0x0654 98203944Sweongyo#define SIBA_CC_REGCTL_ADDR 0x0658 99203944Sweongyo#define SIBA_CC_REGCTL_DATA 0x065c 100203319Sweongyo#define SIBA_CC_PLLCTL_ADDR 0x0660 101203319Sweongyo#define SIBA_CC_PLLCTL_DATA 0x0664 102203319Sweongyo 103203319Sweongyo#define SIBA_CC_PMU0_PLL0 0 104203319Sweongyo#define SIBA_CC_PMU0_PLL0_PDIV_MSK 0x00000001 105203319Sweongyo#define SIBA_CC_PMU0_PLL0_PDIV_FREQ 25000 106203319Sweongyo#define SIBA_CC_PMU0_PLL1 1 107203319Sweongyo#define SIBA_CC_PMU0_PLL1_IMSK 0xf0000000 108203319Sweongyo#define SIBA_CC_PMU0_PLL1_FMSK 0x0fffff00 109203319Sweongyo#define SIBA_CC_PMU0_PLL1_STOPMOD 0x00000040 110203319Sweongyo#define SIBA_CC_PMU0_PLL2 2 111203319Sweongyo#define SIBA_CC_PMU0_PLL2_IMSKHI 0x0000000f 112203319Sweongyo#define SIBA_CC_PMU1_PLL0 0 113203319Sweongyo#define SIBA_CC_PMU1_PLL0_P1DIV 0x00f00000 114203319Sweongyo#define SIBA_CC_PMU1_PLL0_P2DIV 0x0f000000 115299534Sadrian#define SIBA_CC_PMU1_PLL1 1 116203319Sweongyo#define SIBA_CC_PMU1_PLL2 2 117203319Sweongyo#define SIBA_CC_PMU1_PLL2_NDIVMODE 0x000e0000 118203319Sweongyo#define SIBA_CC_PMU1_PLL2_NDIVINT 0x1ff00000 119203319Sweongyo#define SIBA_CC_PMU1_PLL3 3 120203319Sweongyo#define SIBA_CC_PMU1_PLL3_NDIVFRAC 0x00ffffff 121299534Sadrian#define SIBA_CC_PMU1_PLL4 4 122203319Sweongyo#define SIBA_CC_PMU1_PLL5 5 123203319Sweongyo#define SIBA_CC_PMU1_PLL5_CLKDRV 0xffffff00 124203319Sweongyo 125203319Sweongyo#define SIBA_CC_PMU0_DEFAULT_XTALFREQ 20000 126203319Sweongyo#define SIBA_CC_PMU1_DEFAULT_FREQ 15360 127203319Sweongyo 128203319Sweongyo#define SIBA_CC_PMU1_PLLTAB_ENTRY \ 129203319Sweongyo{ \ 130203319Sweongyo { 12000, 1, 3, 22, 0x9, 0xffffef }, \ 131203319Sweongyo { 13000, 2, 1, 6, 0xb, 0x483483 }, \ 132203319Sweongyo { 14400, 3, 1, 10, 0xa, 0x1c71c7 }, \ 133203319Sweongyo { 15360, 4, 1, 5, 0xb, 0x755555 }, \ 134203319Sweongyo { 16200, 5, 1, 10, 0x5, 0x6e9e06 }, \ 135203319Sweongyo { 16800, 6, 1, 10, 0x5, 0x3cf3cf }, \ 136203319Sweongyo { 19200, 7, 1, 9, 0x5, 0x17b425 }, \ 137203319Sweongyo { 19800, 8, 1, 11, 0x4, 0xa57eb }, \ 138203319Sweongyo { 20000, 9, 1, 11, 0x4, 0 }, \ 139203319Sweongyo { 24000, 10, 3, 11, 0xa, 0 }, \ 140203319Sweongyo { 25000, 11, 5, 16, 0xb, 0 }, \ 141203319Sweongyo { 26000, 12, 1, 2, 0x10, 0xec4ec4 }, \ 142203319Sweongyo { 30000, 13, 3, 8, 0xb, 0 }, \ 143203319Sweongyo { 38400, 14, 1, 5, 0x4, 0x955555 }, \ 144203319Sweongyo { 40000, 15, 1, 2, 0xb, 0 } \ 145203319Sweongyo} 146203319Sweongyo 147203319Sweongyo#define SIBA_CC_PMU0_PLLTAB_ENTRY \ 148203319Sweongyo{ \ 149203319Sweongyo { 12000, 1, 73, 349525, }, { 13000, 2, 67, 725937, }, \ 150203319Sweongyo { 14400, 3, 61, 116508, }, { 15360, 4, 57, 305834, }, \ 151203319Sweongyo { 16200, 5, 54, 336579, }, { 16800, 6, 52, 399457, }, \ 152203319Sweongyo { 19200, 7, 45, 873813, }, { 19800, 8, 44, 466033, }, \ 153203319Sweongyo { 20000, 9, 44, 0, }, { 25000, 10, 70, 419430, }, \ 154203319Sweongyo { 26000, 11, 67, 725937, }, { 30000, 12, 58, 699050, }, \ 155203319Sweongyo { 38400, 13, 45, 873813, }, { 40000, 14, 45, 0, }, \ 156203319Sweongyo} 157203319Sweongyo 158203944Sweongyo#define SIBA_CC_PMU_4312_PA_REF 2 159203319Sweongyo#define SIBA_CC_PMU_4325_BURST 1 160203319Sweongyo#define SIBA_CC_PMU_4325_CLBURST 3 161203319Sweongyo#define SIBA_CC_PMU_4325_LN 10 162203319Sweongyo#define SIBA_CC_PMU_4325_CRYSTAL 13 163203319Sweongyo#define SIBA_CC_PMU_4325_RX_PWR 15 164203319Sweongyo#define SIBA_CC_PMU_4325_TX_PWR 16 165203319Sweongyo#define SIBA_CC_PMU_4325_LOGEN_PWR 18 166203319Sweongyo#define SIBA_CC_PMU_4325_AFE_PWR 19 167203319Sweongyo#define SIBA_CC_PMU_4325_BBPLL_PWR 20 168203319Sweongyo#define SIBA_CC_PMU_4325_HT 21 169203319Sweongyo#define SIBA_CC_PMU_4328_EXT_SWITCH_PWM 0 170203319Sweongyo#define SIBA_CC_PMU_4328_BB_SWITCH_PWM 1 171203319Sweongyo#define SIBA_CC_PMU_4328_BB_SWITCH_BURST 2 172203319Sweongyo#define SIBA_CC_PMU_4328_BB_EXT_SWITCH_BURST 3 173203319Sweongyo#define SIBA_CC_PMU_4328_ILP_REQUEST 4 174203319Sweongyo#define SIBA_CC_PMU_4328_RADSWITCH_PWM 5 /* radio switch */ 175203319Sweongyo#define SIBA_CC_PMU_4328_RADSWITCH_BURST 6 176203319Sweongyo#define SIBA_CC_PMU_4328_ROM_SWITCH 7 177203319Sweongyo#define SIBA_CC_PMU_4328_PA_REF 8 178203319Sweongyo#define SIBA_CC_PMU_4328_RADIO 9 179203319Sweongyo#define SIBA_CC_PMU_4328_AFE 10 180203319Sweongyo#define SIBA_CC_PMU_4328_PLL 11 181203319Sweongyo#define SIBA_CC_PMU_4328_BG_FILTBYP 12 182203319Sweongyo#define SIBA_CC_PMU_4328_TX_FILTBYP 13 183203319Sweongyo#define SIBA_CC_PMU_4328_RX_FILTBYP 14 184203319Sweongyo#define SIBA_CC_PMU_4328_CRYSTAL_PU 15 185203319Sweongyo#define SIBA_CC_PMU_4328_CRYSTAL_EN 16 186203319Sweongyo#define SIBA_CC_PMU_4328_BB_PLL_FILTBYP 17 187203319Sweongyo#define SIBA_CC_PMU_4328_RF_PLL_FILTBYP 18 188203319Sweongyo#define SIBA_CC_PMU_4328_BB_PLL_PU 19 189203944Sweongyo#define SIBA_CC_PMU_5354_PA_REF 8 190203319Sweongyo#define SIBA_CC_PMU_5354_BB_PLL_PU 19 191203319Sweongyo 192203319Sweongyo#define SIBA_CC_PMU_4325_RES_UPDOWN \ 193203319Sweongyo{ \ 194203319Sweongyo { SIBA_CC_PMU_4325_CRYSTAL, 0x1501 } \ 195203319Sweongyo} 196203319Sweongyo 197203319Sweongyo#define SIBA_CC_PMU_4325_RES_DEPEND \ 198203319Sweongyo{ \ 199203319Sweongyo { SIBA_CC_PMU_4325_HT, SIBA_CC_PMU_DEP_ADD, \ 200203319Sweongyo ((1 << SIBA_CC_PMU_4325_RX_PWR) | \ 201203319Sweongyo (1 << SIBA_CC_PMU_4325_TX_PWR) | \ 202203319Sweongyo (1 << SIBA_CC_PMU_4325_LOGEN_PWR) | \ 203203319Sweongyo (1 << SIBA_CC_PMU_4325_AFE_PWR)) } \ 204203319Sweongyo} 205203319Sweongyo 206203319Sweongyo#define SIBA_CC_PMU_4328_RES_UPDOWN \ 207203319Sweongyo{ \ 208203319Sweongyo { SIBA_CC_PMU_4328_EXT_SWITCH_PWM, 0x0101 }, \ 209203319Sweongyo { SIBA_CC_PMU_4328_BB_SWITCH_PWM, 0x1f01 }, \ 210203319Sweongyo { SIBA_CC_PMU_4328_BB_SWITCH_BURST, 0x010f }, \ 211203319Sweongyo { SIBA_CC_PMU_4328_BB_EXT_SWITCH_BURST, 0x0101 }, \ 212203319Sweongyo { SIBA_CC_PMU_4328_ILP_REQUEST, 0x0202 }, \ 213203319Sweongyo { SIBA_CC_PMU_4328_RADSWITCH_PWM, 0x0f01 }, \ 214203319Sweongyo { SIBA_CC_PMU_4328_RADSWITCH_BURST, 0x0f01 }, \ 215203319Sweongyo { SIBA_CC_PMU_4328_ROM_SWITCH, 0x0101 }, \ 216203319Sweongyo { SIBA_CC_PMU_4328_PA_REF, 0x0f01 }, \ 217203319Sweongyo { SIBA_CC_PMU_4328_RADIO, 0x0f01 }, \ 218203319Sweongyo { SIBA_CC_PMU_4328_AFE, 0x0f01 }, \ 219203319Sweongyo { SIBA_CC_PMU_4328_PLL, 0x0f01 }, \ 220203319Sweongyo { SIBA_CC_PMU_4328_BG_FILTBYP, 0x0101 }, \ 221203319Sweongyo { SIBA_CC_PMU_4328_TX_FILTBYP, 0x0101 }, \ 222203319Sweongyo { SIBA_CC_PMU_4328_RX_FILTBYP, 0x0101 }, \ 223203319Sweongyo { SIBA_CC_PMU_4328_CRYSTAL_PU, 0x0101 }, \ 224203319Sweongyo { SIBA_CC_PMU_4328_CRYSTAL_EN, 0xa001 }, \ 225203319Sweongyo { SIBA_CC_PMU_4328_BB_PLL_FILTBYP, 0x0101 }, \ 226203319Sweongyo { SIBA_CC_PMU_4328_RF_PLL_FILTBYP, 0x0101 }, \ 227203319Sweongyo { SIBA_CC_PMU_4328_BB_PLL_PU, 0x0701 }, \ 228203319Sweongyo} 229203319Sweongyo 230203319Sweongyo#define SIBA_CC_PMU_4328_RES_DEPEND \ 231203319Sweongyo{ \ 232203319Sweongyo { SIBA_CC_PMU_4328_ILP_REQUEST, SIBA_CC_PMU_DEP_SET, \ 233203319Sweongyo ((1 << SIBA_CC_PMU_4328_EXT_SWITCH_PWM) | \ 234203319Sweongyo (1 << SIBA_CC_PMU_4328_BB_SWITCH_PWM)) }, \ 235203319Sweongyo} 236203319Sweongyo 237203319Sweongyo#define SIBA_CC_CHST_4325_PMUTOP_2B 0x00000200 238203319Sweongyo 239203319Sweongyo#define SIBA_BAR0 0x80 240203319Sweongyo#define SIBA_IRQMASK 0x94 241203319Sweongyo#define SIBA_GPIO_IN 0xb0 242203319Sweongyo#define SIBA_GPIO_OUT 0xb4 243203319Sweongyo#define SIBA_GPIO_OUT_EN 0xb8 244203319Sweongyo#define SIBA_GPIO_CRYSTAL 0x40 245203319Sweongyo#define SIBA_GPIO_PLL 0x80 246203319Sweongyo 247203319Sweongyo#define SIBA_REGWIN(x) \ 248203319Sweongyo (SIBA_ENUM_START + ((x) * SIBA_CORE_LEN)) 249203944Sweongyo#define SIBA_CORE_LEN 0x00001000 /* Size of cfg per core */ 250203944Sweongyo#define SIBA_CFG_END 0x00010000 /* Upper bound of cfg space */ 251203944Sweongyo#define SIBA_MAX_CORES (SIBA_CFG_END/SIBA_CORE_LEN) /* #max cores */ 252203319Sweongyo#define SIBA_ENUM_START 0x18000000U 253203319Sweongyo#define SIBA_ENUM_END 0x18010000U 254183371Simp 255203319Sweongyo#define SIBA_DMA_TRANSLATION_MASK 0xc0000000 256183371Simp 257203319Sweongyo#define SIBA_PCI_DMA 0x40000000U 258203319Sweongyo#define SIBA_TPS 0x0f18 259203319Sweongyo#define SIBA_TPS_BPFLAG 0x0000003f 260203319Sweongyo#define SIBA_IAS 0x0f90 /* Initiator Agent State */ 261203319Sweongyo#define SIBA_IAS_INBAND_ERR 0x00020000 262203319Sweongyo#define SIBA_IAS_TIMEOUT 0x00040000 263203319Sweongyo#define SIBA_INTR_MASK 0x0f94 264203319Sweongyo#define SIBA_TGSLOW 0x0f98 265203319Sweongyo#define SIBA_TGSLOW_RESET 0x00000001 /* target state low */ 266203319Sweongyo#define SIBA_TGSLOW_REJECT_22 0x00000002 267203319Sweongyo#define SIBA_TGSLOW_REJECT_23 0x00000004 268203319Sweongyo#define SIBA_TGSLOW_CLOCK 0x00010000 269203319Sweongyo#define SIBA_TGSLOW_FGC 0x00020000 270203319Sweongyo#define SIBA_TGSHIGH 0x0f9c 271203319Sweongyo#define SIBA_TGSHIGH_SERR 0x00000001 272203319Sweongyo#define SIBA_TGSHIGH_BUSY 0x00000004 273203319Sweongyo#define SIBA_TGSHIGH_DMA64 0x10000000 274203319Sweongyo#define SIBA_IMCFGLO 0x0fa8 275203319Sweongyo#define SIBA_IMCFGLO_SERTO 0x00000007 276203319Sweongyo#define SIBA_IMCFGLO_REQTO 0x00000070 277203319Sweongyo#define SIBA_IDLOW 0x0ff8 278203319Sweongyo#define SIBA_IDLOW_SSBREV 0xf0000000 279203319Sweongyo#define SIBA_IDLOW_SSBREV_22 0x00000000 280203319Sweongyo#define SIBA_IDLOW_SSBREV_23 0x10000000 281203319Sweongyo#define SIBA_IDLOW_SSBREV_24 0x40000000 282203319Sweongyo#define SIBA_IDLOW_SSBREV_25 0x50000000 283203319Sweongyo#define SIBA_IDLOW_SSBREV_26 0x60000000 284203319Sweongyo#define SIBA_IDLOW_SSBREV_27 0x70000000 285203319Sweongyo#define SIBA_IDHIGH 0x0ffc 286203319Sweongyo#define SIBA_IDHIGH_CORECODEMASK 0x00008FF0 /* Core Code */ 287203319Sweongyo#define SIBA_IDHIGH_CORECODE_SHIFT 4 288203319Sweongyo#define SIBA_IDHIGH_CORECODE(id) \ 289203319Sweongyo ((id & SIBA_IDHIGH_CORECODEMASK) >> SIBA_IDHIGH_CORECODE_SHIFT) 290203319Sweongyo/* Revision Code (low part) */ 291203319Sweongyo#define SIBA_IDHIGH_REVLO 0x0000000f 292203319Sweongyo/* Revision Code (high part) */ 293203319Sweongyo#define SIBA_IDHIGH_REVHI 0x00007000 294203319Sweongyo#define SIBA_IDHIGH_REVHI_SHIFT 8 295203319Sweongyo#define SIBA_IDHIGH_REV(id) \ 296203319Sweongyo ((id & SIBA_IDHIGH_REVLO) | ((id & SIBA_IDHIGH_REVHI) >> \ 297299409Sadrian SIBA_IDHIGH_REVHI_SHIFT)) 298203319Sweongyo#define SIBA_IDHIGH_VENDORMASK 0xFFFF0000 /* Vendor Code */ 299203319Sweongyo#define SIBA_IDHIGH_VENDOR_SHIFT 16 300203319Sweongyo#define SIBA_IDHIGH_VENDOR(id) \ 301203319Sweongyo ((id & SIBA_IDHIGH_VENDORMASK) >> SIBA_IDHIGH_VENDOR_SHIFT) 302183371Simp 303203319Sweongyo#define SIBA_SPROMSIZE_R123 64 304203319Sweongyo#define SIBA_SPROMSIZE_R4 220 305203319Sweongyo#define SIBA_SPROM_BASE 0x1000 306203319Sweongyo#define SIBA_SPROM_REV_CRC 0xff00 307299409Sadrian 308203319Sweongyo#define SIBA_SPROM1_MAC_80211BG 0x1048 309203319Sweongyo#define SIBA_SPROM1_MAC_ETH 0x104e 310203319Sweongyo#define SIBA_SPROM1_MAC_80211A 0x1054 311203319Sweongyo#define SIBA_SPROM1_ETHPHY 0x105a 312203319Sweongyo#define SIBA_SPROM1_ETHPHY_MII_ETH0 0x001f 313203319Sweongyo#define SIBA_SPROM1_ETHPHY_MII_ETH1 0x03e0 314203319Sweongyo#define SIBA_SPROM1_ETHPHY_MDIO_ETH0 (1 << 14) 315203319Sweongyo#define SIBA_SPROM1_ETHPHY_MDIO_ETH1 (1 << 15) 316203319Sweongyo#define SIBA_SPROM1_BOARDINFO 0x105c 317203319Sweongyo#define SIBA_SPROM1_BOARDINFO_BREV 0x00ff 318203319Sweongyo#define SIBA_SPROM1_BOARDINFO_CCODE 0x0f00 319203319Sweongyo#define SIBA_SPROM1_BOARDINFO_ANTBG 0x3000 320203319Sweongyo#define SIBA_SPROM1_BOARDINFO_ANTA 0xc000 321203319Sweongyo#define SIBA_SPROM1_PA0B0 0x105e 322203319Sweongyo#define SIBA_SPROM1_PA0B1 0x1060 323203319Sweongyo#define SIBA_SPROM1_PA0B2 0x1062 324203319Sweongyo#define SIBA_SPROM1_GPIOA 0x1064 325203319Sweongyo#define SIBA_SPROM1_GPIOA_P0 0x00ff 326203319Sweongyo#define SIBA_SPROM1_GPIOA_P1 0xff00 327203319Sweongyo#define SIBA_SPROM1_GPIOB 0x1066 328203319Sweongyo#define SIBA_SPROM1_GPIOB_P2 0x00ff 329203319Sweongyo#define SIBA_SPROM1_GPIOB_P3 0xff00 330203319Sweongyo#define SIBA_SPROM1_MAXPWR 0x1068 331203319Sweongyo#define SIBA_SPROM1_MAXPWR_BG 0x00ff 332203319Sweongyo#define SIBA_SPROM1_MAXPWR_A 0xff00 333203319Sweongyo#define SIBA_SPROM1_PA1B0 0x106a 334203319Sweongyo#define SIBA_SPROM1_PA1B1 0x106c 335203319Sweongyo#define SIBA_SPROM1_PA1B2 0x106e 336203319Sweongyo#define SIBA_SPROM1_TSSI 0x1070 337203319Sweongyo#define SIBA_SPROM1_TSSI_BG 0x00ff 338203319Sweongyo#define SIBA_SPROM1_TSSI_A 0xff00 339203319Sweongyo#define SIBA_SPROM1_BFLOW 0x1072 340203319Sweongyo#define SIBA_SPROM1_AGAIN 0x1074 341203319Sweongyo#define SIBA_SPROM1_AGAIN_BG 0x00ff 342203319Sweongyo#define SIBA_SPROM1_AGAIN_A 0xff00 343299409Sadrian 344203319Sweongyo#define SIBA_SPROM2_BFHIGH 0x1038 345299409Sadrian 346203319Sweongyo#define SIBA_SPROM3_MAC_80211BG 0x104a 347299409Sadrian 348203319Sweongyo#define SIBA_SPROM4_MAC_80211BG 0x104c 349203319Sweongyo#define SIBA_SPROM4_ETHPHY 0x105a 350203319Sweongyo#define SIBA_SPROM4_ETHPHY_ET0A 0x001f 351203319Sweongyo#define SIBA_SPROM4_ETHPHY_ET1A 0x03e0 352203319Sweongyo#define SIBA_SPROM4_CCODE 0x1052 353203319Sweongyo#define SIBA_SPROM4_ANTAVAIL 0x105d 354203319Sweongyo#define SIBA_SPROM4_ANTAVAIL_A 0x00ff 355203319Sweongyo#define SIBA_SPROM4_ANTAVAIL_BG 0xff00 356203319Sweongyo#define SIBA_SPROM4_BFLOW 0x1044 357203319Sweongyo#define SIBA_SPROM4_AGAIN01 0x105e 358203319Sweongyo#define SIBA_SPROM4_AGAIN0 0x00ff 359203319Sweongyo#define SIBA_SPROM4_AGAIN1 0xff00 360203319Sweongyo#define SIBA_SPROM4_AGAIN23 0x1060 361203319Sweongyo#define SIBA_SPROM4_AGAIN2 0x00ff 362203319Sweongyo#define SIBA_SPROM4_AGAIN3 0xff00 363299538Sadrian#define SIBA_SPROM4_TXPID2G01 0x0062 364299538Sadrian#define SIBA_SPROM4_TXPID2G0 0x00ff 365299538Sadrian#define SIBA_SPROM4_TXPID2G1 0xff00 366299538Sadrian#define SIBA_SPROM4_TXPID2G23 0x0064 367299538Sadrian#define SIBA_SPROM4_TXPID2G2 0x00ff 368299538Sadrian#define SIBA_SPROM4_TXPID2G3 0xff00 369299538Sadrian#define SIBA_SPROM4_TXPID5G01 0x0066 370299538Sadrian#define SIBA_SPROM4_TXPID5G0 0x00ff 371299538Sadrian#define SIBA_SPROM4_TXPID5G1 0xff00 372299538Sadrian#define SIBA_SPROM4_TXPID5G23 0x0068 373299538Sadrian#define SIBA_SPROM4_TXPID5G2 0x00ff 374299538Sadrian#define SIBA_SPROM4_TXPID5G3 0xff00 375299538Sadrian#define SIBA_SPROM4_TXPID5GL01 0x006a 376299538Sadrian#define SIBA_SPROM4_TXPID5GL0 0x00ff 377299538Sadrian#define SIBA_SPROM4_TXPID5GL1 0xff00 378299538Sadrian#define SIBA_SPROM4_TXPID5GL23 0x006c 379299538Sadrian#define SIBA_SPROM4_TXPID5GL2 0x00ff 380299538Sadrian#define SIBA_SPROM4_TXPID5GL3 0xff00 381299538Sadrian#define SIBA_SPROM4_TXPID5GH01 0x006e 382299538Sadrian#define SIBA_SPROM4_TXPID5GH0 0x00ff 383299538Sadrian#define SIBA_SPROM4_TXPID5GH1 0xff00 384299538Sadrian#define SIBA_SPROM4_TXPID5GH23 0x0070 385299538Sadrian#define SIBA_SPROM4_TXPID5GH2 0x00ff 386299538Sadrian#define SIBA_SPROM4_TXPID5GH3 0xff00 387203319Sweongyo#define SIBA_SPROM4_BFHIGH 0x1046 388203319Sweongyo#define SIBA_SPROM4_MAXP_BG 0x1080 389203319Sweongyo#define SIBA_SPROM4_MAXP_BG_MASK 0x00ff 390203319Sweongyo#define SIBA_SPROM4_TSSI_BG 0xff00 391203319Sweongyo#define SIBA_SPROM4_MAXP_A 0x108a 392203319Sweongyo#define SIBA_SPROM4_MAXP_A_MASK 0x00ff 393203319Sweongyo#define SIBA_SPROM4_TSSI_A 0xff00 394203319Sweongyo#define SIBA_SPROM4_GPIOA 0x1056 395203319Sweongyo#define SIBA_SPROM4_GPIOA_P0 0x00ff 396203319Sweongyo#define SIBA_SPROM4_GPIOA_P1 0xff00 397203319Sweongyo#define SIBA_SPROM4_GPIOB 0x1058 398203319Sweongyo#define SIBA_SPROM4_GPIOB_P2 0x00ff 399203319Sweongyo#define SIBA_SPROM4_GPIOB_P3 0xff00 400299409Sadrian 401299409Sadrian/* The following four blocks share the same structure */ 402300125Sadrian#define SIBA_SPROM4_PWR_INFO_CORE0 0x1080 403300125Sadrian#define SIBA_SPROM4_PWR_INFO_CORE1 0x10AE 404300125Sadrian#define SIBA_SPROM4_PWR_INFO_CORE2 0x10DC 405300125Sadrian#define SIBA_SPROM4_PWR_INFO_CORE3 0x110A 406299409Sadrian 407299409Sadrian#define SIBA_SPROM4_2G_MAXP_ITSSI 0x00 /* 2 GHz ITSSI and 2 GHz Max Power */ 408299409Sadrian#define SIBA_SPROM4_2G_MAXP 0x00FF 409299409Sadrian#define SIBA_SPROM4_2G_ITSSI 0xFF00 410299409Sadrian#define SIBA_SPROM4_2G_ITSSI_SHIFT 8 411299409Sadrian#define SIBA_SPROM4_2G_PA_0 0x02 /* 2 GHz power amp */ 412299409Sadrian#define SIBA_SPROM4_2G_PA_1 0x04 413299409Sadrian#define SIBA_SPROM4_2G_PA_2 0x06 414299409Sadrian#define SIBA_SPROM4_2G_PA_3 0x08 415299409Sadrian#define SIBA_SPROM4_5G_MAXP_ITSSI 0x0A /* 5 GHz ITSSI and 5.3 GHz Max Power */ 416299409Sadrian#define SIBA_SPROM4_5G_MAXP 0x00FF 417299409Sadrian#define SIBA_SPROM4_5G_ITSSI 0xFF00 418299409Sadrian#define SIBA_SPROM4_5G_ITSSI_SHIFT 8 419299409Sadrian#define SIBA_SPROM4_5GHL_MAXP 0x0C /* 5.2 GHz and 5.8 GHz Max Power */ 420299409Sadrian#define SIBA_SPROM4_5GH_MAXP 0x00FF 421299409Sadrian#define SIBA_SPROM4_5GL_MAXP 0xFF00 422299409Sadrian#define SIBA_SPROM4_5GL_MAXP_SHIFT 8 423299409Sadrian#define SIBA_SPROM4_5G_PA_0 0x0E /* 5.3 GHz power amp */ 424299409Sadrian#define SIBA_SPROM4_5G_PA_1 0x10 425299409Sadrian#define SIBA_SPROM4_5G_PA_2 0x12 426299409Sadrian#define SIBA_SPROM4_5G_PA_3 0x14 427299409Sadrian#define SIBA_SPROM4_5GL_PA_0 0x16 /* 5.2 GHz power amp */ 428299409Sadrian#define SIBA_SPROM4_5GL_PA_1 0x18 429299409Sadrian#define SIBA_SPROM4_5GL_PA_2 0x1A 430299409Sadrian#define SIBA_SPROM4_5GL_PA_3 0x1C 431299409Sadrian#define SIBA_SPROM4_5GH_PA_0 0x1E /* 5.8 GHz power amp */ 432299409Sadrian#define SIBA_SPROM4_5GH_PA_1 0x20 433299409Sadrian#define SIBA_SPROM4_5GH_PA_2 0x22 434299409Sadrian#define SIBA_SPROM4_5GH_PA_3 0x24 435299409Sadrian 436203319Sweongyo#define SIBA_SPROM5_BFLOW 0x104a 437203319Sweongyo#define SIBA_SPROM5_BFHIGH 0x104c 438203319Sweongyo#define SIBA_SPROM5_MAC_80211BG 0x1052 439203319Sweongyo#define SIBA_SPROM5_CCODE 0x1044 440203319Sweongyo#define SIBA_SPROM5_GPIOA 0x1076 441203319Sweongyo#define SIBA_SPROM5_GPIOA_P0 0x00ff 442203319Sweongyo#define SIBA_SPROM5_GPIOA_P1 0xff00 443203319Sweongyo#define SIBA_SPROM5_GPIOB 0x1078 444203319Sweongyo#define SIBA_SPROM5_GPIOB_P2 0x00ff 445203319Sweongyo#define SIBA_SPROM5_GPIOB_P3 0xff00 446299409Sadrian 447203319Sweongyo#define SIBA_SPROM8_BFLOW 0x1084 448203319Sweongyo#define SIBA_SPROM8_BFHIGH 0x1086 449203944Sweongyo#define SIBA_SPROM8_BFL2LO 0x1088 450203944Sweongyo#define SIBA_SPROM8_BFL2HI 0x108a 451203944Sweongyo#define SIBA_SPROM8_MAC_80211BG 0x108c 452203319Sweongyo#define SIBA_SPROM8_CCODE 0x1092 453203319Sweongyo#define SIBA_SPROM8_ANTAVAIL 0x109c 454203319Sweongyo#define SIBA_SPROM8_ANTAVAIL_A 0xff00 455203319Sweongyo#define SIBA_SPROM8_ANTAVAIL_BG 0x00ff 456203319Sweongyo#define SIBA_SPROM8_AGAIN01 0x109e 457203319Sweongyo#define SIBA_SPROM8_AGAIN0 0x00ff 458203319Sweongyo#define SIBA_SPROM8_AGAIN1 0xff00 459203319Sweongyo#define SIBA_SPROM8_GPIOA 0x1096 460203319Sweongyo#define SIBA_SPROM8_GPIOA_P0 0x00ff 461203319Sweongyo#define SIBA_SPROM8_GPIOA_P1 0xff00 462203319Sweongyo#define SIBA_SPROM8_GPIOB 0x1098 463203319Sweongyo#define SIBA_SPROM8_GPIOB_P2 0x00ff 464203319Sweongyo#define SIBA_SPROM8_GPIOB_P3 0xff00 465203944Sweongyo#define SIBA_SPROM8_AGAIN23 0x10a0 466203944Sweongyo#define SIBA_SPROM8_AGAIN2 0x00ff 467203944Sweongyo#define SIBA_SPROM8_AGAIN3 0xff00 468203944Sweongyo#define SIBA_SPROM8_RSSIPARM2G 0x10a4 469203944Sweongyo#define SIBA_SPROM8_RSSISMF2G 0x000f 470203944Sweongyo#define SIBA_SPROM8_RSSISMC2G 0x00f0 471203944Sweongyo#define SIBA_SPROM8_RSSISAV2G 0x0700 /* BITMASK */ 472203944Sweongyo#define SIBA_SPROM8_BXA2G 0x1800 /* BITMASK */ 473203944Sweongyo#define SIBA_SPROM8_RSSIPARM5G 0x10a6 474203944Sweongyo#define SIBA_SPROM8_RSSISMF5G 0x000f 475203944Sweongyo#define SIBA_SPROM8_RSSISMC5G 0x00f0 476203944Sweongyo#define SIBA_SPROM8_RSSISAV5G 0x0700 /* BITMASK */ 477203944Sweongyo#define SIBA_SPROM8_BXA5G 0x1800 /* BITMASK */ 478203944Sweongyo#define SIBA_SPROM8_TRI25G 0x10a8 479203944Sweongyo#define SIBA_SPROM8_TRI2G 0x00ff 480203944Sweongyo#define SIBA_SPROM8_TRI5G 0xff00 481203944Sweongyo#define SIBA_SPROM8_TRI5GHL 0x10aa 482203944Sweongyo#define SIBA_SPROM8_TRI5GL 0x00ff 483203944Sweongyo#define SIBA_SPROM8_TRI5GH 0xff00 484203944Sweongyo#define SIBA_SPROM8_RXPO 0x10ac 485203944Sweongyo#define SIBA_SPROM8_RXPO2G 0x00ff 486203944Sweongyo#define SIBA_SPROM8_RXPO5G 0xff00 487299409Sadrian 488299409Sadrian/* The FEM blocks share the same structure */ 489300125Sadrian#define SIBA_SPROM8_FEM2G 0x10ae 490300125Sadrian#define SIBA_SPROM8_FEM5G 0x10b0 491300185Sadrian#define SIBA_SROM8_FEM_TSSIPOS 0x0001 492300185Sadrian#define SIBA_SROM8_FEM_EXTPA_GAIN 0x0006 493300185Sadrian#define SIBA_SROM8_FEM_PDET_RANGE 0x00F8 494300185Sadrian#define SIBA_SROM8_FEM_TR_ISO 0x0700 495300185Sadrian#define SIBA_SROM8_FEM_ANTSWLUT 0xF800 496299409Sadrian 497203319Sweongyo#define SIBA_SPROM8_MAXP_BG 0x10c0 498203319Sweongyo#define SIBA_SPROM8_MAXP_BG_MASK 0x00ff 499203319Sweongyo#define SIBA_SPROM8_TSSI_BG 0xff00 500203944Sweongyo#define SIBA_SPROM8_PA0B0 0x10c2 501203944Sweongyo#define SIBA_SPROM8_PA0B1 0x10c4 502203944Sweongyo#define SIBA_SPROM8_PA0B2 0x10c6 503203319Sweongyo#define SIBA_SPROM8_MAXP_A 0x10c8 504203319Sweongyo#define SIBA_SPROM8_MAXP_A_MASK 0x00ff 505203319Sweongyo#define SIBA_SPROM8_TSSI_A 0xff00 506203944Sweongyo#define SIBA_SPROM8_MAXP_AHL 0x10ca 507203944Sweongyo#define SIBA_SPROM8_MAXP_AH_MASK 0x00ff 508203944Sweongyo#define SIBA_SPROM8_MAXP_AL_MASK 0xff00 509203944Sweongyo#define SIBA_SPROM8_PA1B0 0x10cc 510203944Sweongyo#define SIBA_SPROM8_PA1B1 0x10ce 511203944Sweongyo#define SIBA_SPROM8_PA1B2 0x10d0 512203944Sweongyo#define SIBA_SPROM8_PA1LOB0 0x10d2 513203944Sweongyo#define SIBA_SPROM8_PA1LOB1 0x10d4 514203944Sweongyo#define SIBA_SPROM8_PA1LOB2 0x10d6 515203944Sweongyo#define SIBA_SPROM8_PA1HIB0 0x10d8 516203944Sweongyo#define SIBA_SPROM8_PA1HIB1 0x10da 517203944Sweongyo#define SIBA_SPROM8_PA1HIB2 0x10dc 518203944Sweongyo#define SIBA_SPROM8_CCK2GPO 0x1140 519203944Sweongyo#define SIBA_SPROM8_OFDM2GPO 0x1142 520203944Sweongyo#define SIBA_SPROM8_OFDM5GPO 0x1146 521203944Sweongyo#define SIBA_SPROM8_OFDM5GLPO 0x114a 522203944Sweongyo#define SIBA_SPROM8_OFDM5GHPO 0x114e 523300185Sadrian#define SIBA_SPROM8_CDDPO 0x0192 524300185Sadrian#define SIBA_SPROM8_STBCPO 0x0194 525300185Sadrian#define SIBA_SPROM8_BW40PO 0x0196 526300185Sadrian#define SIBA_SPROM8_BWDUPPO 0x0198 527183371Simp 528299409Sadrian/* There are 4 blocks with power info sharing the same layout */ 529300125Sadrian#define SIBA_SROM8_PWR_INFO_CORE0 0x10C0 530300125Sadrian#define SIBA_SROM8_PWR_INFO_CORE1 0x10E0 531300125Sadrian#define SIBA_SROM8_PWR_INFO_CORE2 0x1100 532300125Sadrian#define SIBA_SROM8_PWR_INFO_CORE3 0x1120 533299409Sadrian 534299409Sadrian#define SIBA_SROM8_2G_MAXP_ITSSI 0x00 535299409Sadrian#define SIBA_SPROM8_2G_MAXP 0x00FF 536299409Sadrian#define SIBA_SPROM8_2G_ITSSI 0xFF00 537299409Sadrian#define SIBA_SPROM8_2G_ITSSI_SHIFT 8 538299409Sadrian#define SIBA_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */ 539299409Sadrian#define SIBA_SROM8_2G_PA_1 0x04 540299409Sadrian#define SIBA_SROM8_2G_PA_2 0x06 541299409Sadrian#define SIBA_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */ 542299409Sadrian#define SIBA_SPROM8_5G_MAXP 0x00FF 543299409Sadrian#define SIBA_SPROM8_5G_ITSSI 0xFF00 544299409Sadrian#define SIBA_SPROM8_5G_ITSSI_SHIFT 8 545299409Sadrian#define SIBA_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */ 546299409Sadrian#define SIBA_SPROM8_5GH_MAXP 0x00FF 547299409Sadrian#define SIBA_SPROM8_5GL_MAXP 0xFF00 548299409Sadrian#define SIBA_SPROM8_5GL_MAXP_SHIFT 8 549299409Sadrian#define SIBA_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */ 550299409Sadrian#define SIBA_SROM8_5G_PA_1 0x0E 551299409Sadrian#define SIBA_SROM8_5G_PA_2 0x10 552299409Sadrian#define SIBA_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */ 553299409Sadrian#define SIBA_SROM8_5GL_PA_1 0x14 554299409Sadrian#define SIBA_SROM8_5GL_PA_2 0x16 555299409Sadrian#define SIBA_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */ 556299409Sadrian#define SIBA_SROM8_5GH_PA_1 0x1A 557299409Sadrian#define SIBA_SROM8_5GH_PA_2 0x1C 558299409Sadrian 559203319Sweongyo#define SIBA_BOARDVENDOR_DELL 0x1028 560203319Sweongyo#define SIBA_BOARDVENDOR_BCM 0x14e4 561203319Sweongyo#define SIBA_BOARD_BCM4309G 0x0421 562203319Sweongyo#define SIBA_BOARD_MP4318 0x044a 563203319Sweongyo#define SIBA_BOARD_BU4306 0x0416 564203319Sweongyo#define SIBA_BOARD_BU4309 0x040a 565299409Sadrian#define SIBA_BOARD_BCM4321 0x046d 566183371Simp 567203319Sweongyo#define SIBA_PCICORE_BCAST_ADDR SIBA_CC_BCAST_ADDR 568203319Sweongyo#define SIBA_PCICORE_BCAST_DATA SIBA_CC_BCAST_DATA 569203319Sweongyo#define SIBA_PCICORE_SBTOPCI0 0x0100 570203319Sweongyo#define SIBA_PCICORE_SBTOPCI1 0x0104 571203319Sweongyo#define SIBA_PCICORE_SBTOPCI2 0x0108 572203319Sweongyo#define SIBA_PCICORE_MDIO_CTL 0x0128 573203319Sweongyo#define SIBA_PCICORE_MDIO_DATA 0x012c 574203319Sweongyo#define SIBA_PCICORE_SBTOPCI_PREF 0x00000004 575203319Sweongyo#define SIBA_PCICORE_SBTOPCI_BURST 0x00000008 576203319Sweongyo#define SIBA_PCICORE_SBTOPCI_MRM 0x00000020 577183371Simp 578203944Sweongyo#define SIBA_CHIPPACK_BCM4712S 1 /* Small 200pin 4712 */ 579203944Sweongyo 580183371Simp#endif /* _SIBA_SIBAREG_H_ */ 581