sfxge_port.c revision 278838
1/*- 2 * Copyright (c) 2010-2011 Solarflare Communications, Inc. 3 * All rights reserved. 4 * 5 * This software was developed in part by Philip Paeps under contract for 6 * Solarflare Communications, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/sfxge/sfxge_port.c 278838 2015-02-16 06:10:17Z arybchik $"); 32 33#include <sys/types.h> 34#include <sys/limits.h> 35#include <net/ethernet.h> 36#include <net/if_dl.h> 37 38#include "common/efx.h" 39 40#include "sfxge.h" 41 42static int 43sfxge_mac_stat_update(struct sfxge_softc *sc) 44{ 45 struct sfxge_port *port = &sc->port; 46 efsys_mem_t *esmp = &(port->mac_stats.dma_buf); 47 clock_t now; 48 unsigned int count; 49 int rc; 50 51 SFXGE_PORT_LOCK_ASSERT_OWNED(port); 52 53 if (port->init_state != SFXGE_PORT_STARTED) { 54 rc = 0; 55 goto out; 56 } 57 58 now = ticks; 59 if (now - port->mac_stats.update_time < hz) { 60 rc = 0; 61 goto out; 62 } 63 64 port->mac_stats.update_time = now; 65 66 /* If we're unlucky enough to read statistics wduring the DMA, wait 67 * up to 10ms for it to finish (typically takes <500us) */ 68 for (count = 0; count < 100; ++count) { 69 EFSYS_PROBE1(wait, unsigned int, count); 70 71 /* Synchronize the DMA memory for reading */ 72 bus_dmamap_sync(esmp->esm_tag, esmp->esm_map, 73 BUS_DMASYNC_POSTREAD); 74 75 /* Try to update the cached counters */ 76 if ((rc = efx_mac_stats_update(sc->enp, esmp, 77 port->mac_stats.decode_buf, NULL)) != EAGAIN) 78 goto out; 79 80 DELAY(100); 81 } 82 83 rc = ETIMEDOUT; 84out: 85 return (rc); 86} 87 88static int 89sfxge_mac_stat_handler(SYSCTL_HANDLER_ARGS) 90{ 91 struct sfxge_softc *sc = arg1; 92 unsigned int id = arg2; 93 int rc; 94 uint64_t val; 95 96 SFXGE_PORT_LOCK(&sc->port); 97 if ((rc = sfxge_mac_stat_update(sc)) == 0) 98 val = ((uint64_t *)sc->port.mac_stats.decode_buf)[id]; 99 SFXGE_PORT_UNLOCK(&sc->port); 100 101 if (rc == 0) 102 rc = SYSCTL_OUT(req, &val, sizeof(val)); 103 return (rc); 104} 105 106static void 107sfxge_mac_stat_init(struct sfxge_softc *sc) 108{ 109 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev); 110 struct sysctl_oid_list *stat_list; 111 unsigned int id; 112 const char *name; 113 114 stat_list = SYSCTL_CHILDREN(sc->stats_node); 115 116 /* Initialise the named stats */ 117 for (id = 0; id < EFX_MAC_NSTATS; id++) { 118 name = efx_mac_stat_name(sc->enp, id); 119 SYSCTL_ADD_PROC( 120 ctx, stat_list, 121 OID_AUTO, name, CTLTYPE_U64|CTLFLAG_RD, 122 sc, id, sfxge_mac_stat_handler, "Q", 123 ""); 124 } 125} 126 127#ifdef SFXGE_HAVE_PAUSE_MEDIAOPTS 128 129static unsigned int 130sfxge_port_wanted_fc(struct sfxge_softc *sc) 131{ 132 struct ifmedia_entry *ifm = sc->media.ifm_cur; 133 134 if (ifm->ifm_media == (IFM_ETHER | IFM_AUTO)) 135 return (EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE); 136 return (((ifm->ifm_media & IFM_ETH_RXPAUSE) ? EFX_FCNTL_RESPOND : 0) | 137 ((ifm->ifm_media & IFM_ETH_TXPAUSE) ? EFX_FCNTL_GENERATE : 0)); 138} 139 140static unsigned int 141sfxge_port_link_fc_ifm(struct sfxge_softc *sc) 142{ 143 unsigned int wanted_fc, link_fc; 144 145 efx_mac_fcntl_get(sc->enp, &wanted_fc, &link_fc); 146 return ((link_fc & EFX_FCNTL_RESPOND) ? IFM_ETH_RXPAUSE : 0) | 147 ((link_fc & EFX_FCNTL_GENERATE) ? IFM_ETH_TXPAUSE : 0); 148} 149 150#else /* !SFXGE_HAVE_PAUSE_MEDIAOPTS */ 151 152static unsigned int 153sfxge_port_wanted_fc(struct sfxge_softc *sc) 154{ 155 return (sc->port.wanted_fc); 156} 157 158static unsigned int 159sfxge_port_link_fc_ifm(struct sfxge_softc *sc) 160{ 161 return (0); 162} 163 164static int 165sfxge_port_wanted_fc_handler(SYSCTL_HANDLER_ARGS) 166{ 167 struct sfxge_softc *sc; 168 struct sfxge_port *port; 169 unsigned int fcntl; 170 int error; 171 172 sc = arg1; 173 port = &sc->port; 174 175 if (req->newptr != NULL) { 176 if ((error = SYSCTL_IN(req, &fcntl, sizeof(fcntl))) != 0) 177 return (error); 178 179 SFXGE_PORT_LOCK(port); 180 181 if (port->wanted_fc != fcntl) { 182 if (port->init_state == SFXGE_PORT_STARTED) 183 error = efx_mac_fcntl_set(sc->enp, 184 port->wanted_fc, 185 B_TRUE); 186 if (error == 0) 187 port->wanted_fc = fcntl; 188 } 189 190 SFXGE_PORT_UNLOCK(port); 191 } else { 192 SFXGE_PORT_LOCK(port); 193 fcntl = port->wanted_fc; 194 SFXGE_PORT_UNLOCK(port); 195 196 error = SYSCTL_OUT(req, &fcntl, sizeof(fcntl)); 197 } 198 199 return (error); 200} 201 202static int 203sfxge_port_link_fc_handler(SYSCTL_HANDLER_ARGS) 204{ 205 struct sfxge_softc *sc; 206 struct sfxge_port *port; 207 unsigned int wanted_fc, link_fc; 208 209 sc = arg1; 210 port = &sc->port; 211 212 SFXGE_PORT_LOCK(port); 213 if (port->init_state == SFXGE_PORT_STARTED && SFXGE_LINK_UP(sc)) 214 efx_mac_fcntl_get(sc->enp, &wanted_fc, &link_fc); 215 else 216 link_fc = 0; 217 SFXGE_PORT_UNLOCK(port); 218 219 return (SYSCTL_OUT(req, &link_fc, sizeof(link_fc))); 220} 221 222#endif /* SFXGE_HAVE_PAUSE_MEDIAOPTS */ 223 224static const uint64_t sfxge_link_baudrate[EFX_LINK_NMODES] = { 225 [EFX_LINK_10HDX] = IF_Mbps(10), 226 [EFX_LINK_10FDX] = IF_Mbps(10), 227 [EFX_LINK_100HDX] = IF_Mbps(100), 228 [EFX_LINK_100FDX] = IF_Mbps(100), 229 [EFX_LINK_1000HDX] = IF_Gbps(1), 230 [EFX_LINK_1000FDX] = IF_Gbps(1), 231 [EFX_LINK_10000FDX] = IF_Gbps(10), 232}; 233 234void 235sfxge_mac_link_update(struct sfxge_softc *sc, efx_link_mode_t mode) 236{ 237 struct sfxge_port *port; 238 int link_state; 239 240 port = &sc->port; 241 242 if (port->link_mode == mode) 243 return; 244 245 port->link_mode = mode; 246 247 /* Push link state update to the OS */ 248 link_state = (port->link_mode != EFX_LINK_DOWN ? 249 LINK_STATE_UP : LINK_STATE_DOWN); 250 sc->ifnet->if_baudrate = sfxge_link_baudrate[port->link_mode]; 251 if_link_state_change(sc->ifnet, link_state); 252} 253 254static void 255sfxge_mac_poll_work(void *arg, int npending) 256{ 257 struct sfxge_softc *sc; 258 efx_nic_t *enp; 259 struct sfxge_port *port; 260 efx_link_mode_t mode; 261 262 sc = (struct sfxge_softc *)arg; 263 enp = sc->enp; 264 port = &sc->port; 265 266 SFXGE_PORT_LOCK(port); 267 268 if (port->init_state != SFXGE_PORT_STARTED) 269 goto done; 270 271 /* This may sleep waiting for MCDI completion */ 272 (void)efx_port_poll(enp, &mode); 273 sfxge_mac_link_update(sc, mode); 274 275done: 276 SFXGE_PORT_UNLOCK(port); 277} 278 279static int 280sfxge_mac_filter_set_locked(struct sfxge_softc *sc) 281{ 282 unsigned int bucket[EFX_MAC_HASH_BITS]; 283 struct ifnet *ifp = sc->ifnet; 284 struct ifmultiaddr *ifma; 285 struct sockaddr_dl *sa; 286 efx_nic_t *enp = sc->enp; 287 unsigned int index; 288 int rc; 289 290 /* Set promisc-unicast and broadcast filter bits */ 291 if ((rc = efx_mac_filter_set(enp, !!(ifp->if_flags & IFF_PROMISC), 292 B_TRUE)) != 0) 293 return (rc); 294 295 /* Set multicast hash filter */ 296 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 297 for (index = 0; index < EFX_MAC_HASH_BITS; index++) 298 bucket[index] = 1; 299 } else { 300 /* Broadcast frames also go through the multicast 301 * filter, and the broadcast address hashes to 302 * 0xff. */ 303 bucket[0xff] = 1; 304 305 if_maddr_rlock(ifp); 306 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 307 if (ifma->ifma_addr->sa_family == AF_LINK) { 308 sa = (struct sockaddr_dl *)ifma->ifma_addr; 309 index = ether_crc32_le(LLADDR(sa), 6) & 0xff; 310 bucket[index] = 1; 311 } 312 } 313 if_maddr_runlock(ifp); 314 } 315 return (efx_mac_hash_set(enp, bucket)); 316} 317 318int 319sfxge_mac_filter_set(struct sfxge_softc *sc) 320{ 321 struct sfxge_port *port = &sc->port; 322 int rc; 323 324 SFXGE_PORT_LOCK(port); 325 /* 326 * The function may be called without softc_lock held in the 327 * case of SIOCADDMULTI and SIOCDELMULTI ioctls. ioctl handler 328 * checks IFF_DRV_RUNNING flag which implies port started, but 329 * it is not guaranteed to remain. softc_lock shared lock can't 330 * be held in the case of these ioctls processing, since it 331 * results in failure where kernel complains that non-sleepable 332 * lock is held in sleeping thread. Both problems are repeatable 333 * on LAG with LACP proto bring up. 334 */ 335 if (port->init_state == SFXGE_PORT_STARTED) 336 rc = sfxge_mac_filter_set_locked(sc); 337 else 338 rc = 0; 339 SFXGE_PORT_UNLOCK(port); 340 return (rc); 341} 342 343void 344sfxge_port_stop(struct sfxge_softc *sc) 345{ 346 struct sfxge_port *port; 347 efx_nic_t *enp; 348 349 port = &sc->port; 350 enp = sc->enp; 351 352 SFXGE_PORT_LOCK(port); 353 354 KASSERT(port->init_state == SFXGE_PORT_STARTED, 355 ("port not started")); 356 357 port->init_state = SFXGE_PORT_INITIALIZED; 358 359 port->mac_stats.update_time = 0; 360 361 /* This may call MCDI */ 362 (void)efx_mac_drain(enp, B_TRUE); 363 364 (void)efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf, 0, B_FALSE); 365 366 port->link_mode = EFX_LINK_UNKNOWN; 367 368 /* Destroy the common code port object. */ 369 efx_port_fini(sc->enp); 370 371 SFXGE_PORT_UNLOCK(port); 372} 373 374int 375sfxge_port_start(struct sfxge_softc *sc) 376{ 377 uint8_t mac_addr[ETHER_ADDR_LEN]; 378 struct ifnet *ifp = sc->ifnet; 379 struct sfxge_port *port; 380 efx_nic_t *enp; 381 size_t pdu; 382 int rc; 383 384 port = &sc->port; 385 enp = sc->enp; 386 387 SFXGE_PORT_LOCK(port); 388 389 KASSERT(port->init_state == SFXGE_PORT_INITIALIZED, 390 ("port not initialized")); 391 392 /* Initialize the port object in the common code. */ 393 if ((rc = efx_port_init(sc->enp)) != 0) 394 goto fail; 395 396 /* Set the SDU */ 397 pdu = EFX_MAC_PDU(ifp->if_mtu); 398 if ((rc = efx_mac_pdu_set(enp, pdu)) != 0) 399 goto fail2; 400 401 if ((rc = efx_mac_fcntl_set(enp, sfxge_port_wanted_fc(sc), B_TRUE)) 402 != 0) 403 goto fail2; 404 405 /* Set the unicast address */ 406 if_addr_rlock(ifp); 407 bcopy(LLADDR((struct sockaddr_dl *)ifp->if_addr->ifa_addr), 408 mac_addr, sizeof(mac_addr)); 409 if_addr_runlock(ifp); 410 if ((rc = efx_mac_addr_set(enp, mac_addr)) != 0) 411 goto fail; 412 413 sfxge_mac_filter_set_locked(sc); 414 415 /* Update MAC stats by DMA every second */ 416 if ((rc = efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf, 417 1000, B_FALSE)) != 0) 418 goto fail2; 419 420 if ((rc = efx_mac_drain(enp, B_FALSE)) != 0) 421 goto fail3; 422 423 if ((rc = efx_phy_adv_cap_set(sc->enp, sc->media.ifm_cur->ifm_data)) 424 != 0) 425 goto fail4; 426 427 port->init_state = SFXGE_PORT_STARTED; 428 429 /* Single poll in case there were missing initial events */ 430 SFXGE_PORT_UNLOCK(port); 431 sfxge_mac_poll_work(sc, 0); 432 433 return (0); 434 435fail4: 436 (void)efx_mac_drain(enp, B_TRUE); 437fail3: 438 (void)efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf, 439 0, B_FALSE); 440fail2: 441 efx_port_fini(sc->enp); 442fail: 443 SFXGE_PORT_UNLOCK(port); 444 445 return (rc); 446} 447 448static int 449sfxge_phy_stat_update(struct sfxge_softc *sc) 450{ 451 struct sfxge_port *port = &sc->port; 452 efsys_mem_t *esmp = &port->phy_stats.dma_buf; 453 clock_t now; 454 unsigned int count; 455 int rc; 456 457 SFXGE_PORT_LOCK_ASSERT_OWNED(port); 458 459 if (port->init_state != SFXGE_PORT_STARTED) { 460 rc = 0; 461 goto out; 462 } 463 464 now = ticks; 465 if (now - port->phy_stats.update_time < hz) { 466 rc = 0; 467 goto out; 468 } 469 470 port->phy_stats.update_time = now; 471 472 /* If we're unlucky enough to read statistics wduring the DMA, wait 473 * up to 10ms for it to finish (typically takes <500us) */ 474 for (count = 0; count < 100; ++count) { 475 EFSYS_PROBE1(wait, unsigned int, count); 476 477 /* Synchronize the DMA memory for reading */ 478 bus_dmamap_sync(esmp->esm_tag, esmp->esm_map, 479 BUS_DMASYNC_POSTREAD); 480 481 /* Try to update the cached counters */ 482 if ((rc = efx_phy_stats_update(sc->enp, esmp, 483 port->phy_stats.decode_buf)) != EAGAIN) 484 goto out; 485 486 DELAY(100); 487 } 488 489 rc = ETIMEDOUT; 490out: 491 return (rc); 492} 493 494static int 495sfxge_phy_stat_handler(SYSCTL_HANDLER_ARGS) 496{ 497 struct sfxge_softc *sc = arg1; 498 unsigned int id = arg2; 499 int rc; 500 uint32_t val; 501 502 SFXGE_PORT_LOCK(&sc->port); 503 if ((rc = sfxge_phy_stat_update(sc)) == 0) 504 val = ((uint32_t *)sc->port.phy_stats.decode_buf)[id]; 505 SFXGE_PORT_UNLOCK(&sc->port); 506 507 if (rc == 0) 508 rc = SYSCTL_OUT(req, &val, sizeof(val)); 509 return (rc); 510} 511 512static void 513sfxge_phy_stat_init(struct sfxge_softc *sc) 514{ 515 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev); 516 struct sysctl_oid_list *stat_list; 517 unsigned int id; 518 const char *name; 519 uint64_t stat_mask = efx_nic_cfg_get(sc->enp)->enc_phy_stat_mask; 520 521 stat_list = SYSCTL_CHILDREN(sc->stats_node); 522 523 /* Initialise the named stats */ 524 for (id = 0; id < EFX_PHY_NSTATS; id++) { 525 if (!(stat_mask & ((uint64_t)1 << id))) 526 continue; 527 name = efx_phy_stat_name(sc->enp, id); 528 SYSCTL_ADD_PROC( 529 ctx, stat_list, 530 OID_AUTO, name, CTLTYPE_UINT|CTLFLAG_RD, 531 sc, id, sfxge_phy_stat_handler, 532 id == EFX_PHY_STAT_OUI ? "IX" : "IU", 533 ""); 534 } 535} 536 537void 538sfxge_port_fini(struct sfxge_softc *sc) 539{ 540 struct sfxge_port *port; 541 efsys_mem_t *esmp; 542 543 port = &sc->port; 544 esmp = &port->mac_stats.dma_buf; 545 546 KASSERT(port->init_state == SFXGE_PORT_INITIALIZED, 547 ("Port not initialized")); 548 549 port->init_state = SFXGE_PORT_UNINITIALIZED; 550 551 port->link_mode = EFX_LINK_UNKNOWN; 552 553 /* Finish with PHY DMA memory */ 554 sfxge_dma_free(&port->phy_stats.dma_buf); 555 free(port->phy_stats.decode_buf, M_SFXGE); 556 557 sfxge_dma_free(esmp); 558 free(port->mac_stats.decode_buf, M_SFXGE); 559 560 SFXGE_PORT_LOCK_DESTROY(port); 561 562 port->sc = NULL; 563} 564 565int 566sfxge_port_init(struct sfxge_softc *sc) 567{ 568 struct sfxge_port *port; 569 struct sysctl_ctx_list *sysctl_ctx; 570 struct sysctl_oid *sysctl_tree; 571 efsys_mem_t *mac_stats_buf, *phy_stats_buf; 572 int rc; 573 574 port = &sc->port; 575 mac_stats_buf = &port->mac_stats.dma_buf; 576 phy_stats_buf = &port->phy_stats.dma_buf; 577 578 KASSERT(port->init_state == SFXGE_PORT_UNINITIALIZED, 579 ("Port already initialized")); 580 581 port->sc = sc; 582 583 SFXGE_PORT_LOCK_INIT(port, device_get_nameunit(sc->dev)); 584 585 port->phy_stats.decode_buf = malloc(EFX_PHY_NSTATS * sizeof(uint32_t), 586 M_SFXGE, M_WAITOK | M_ZERO); 587 if ((rc = sfxge_dma_alloc(sc, EFX_PHY_STATS_SIZE, phy_stats_buf)) != 0) 588 goto fail; 589 sfxge_phy_stat_init(sc); 590 591 sysctl_ctx = device_get_sysctl_ctx(sc->dev); 592 sysctl_tree = device_get_sysctl_tree(sc->dev); 593 594#ifndef SFXGE_HAVE_PAUSE_MEDIAOPTS 595 /* If flow control cannot be configured or reported through 596 * ifmedia, provide sysctls for it. */ 597 port->wanted_fc = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE; 598 SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO, 599 "wanted_fc", CTLTYPE_UINT|CTLFLAG_RW, sc, 0, 600 sfxge_port_wanted_fc_handler, "IU", "wanted flow control mode"); 601 SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO, 602 "link_fc", CTLTYPE_UINT|CTLFLAG_RD, sc, 0, 603 sfxge_port_link_fc_handler, "IU", "link flow control mode"); 604#endif 605 606 port->mac_stats.decode_buf = malloc(EFX_MAC_NSTATS * sizeof(uint64_t), 607 M_SFXGE, M_WAITOK | M_ZERO); 608 if ((rc = sfxge_dma_alloc(sc, EFX_MAC_STATS_SIZE, mac_stats_buf)) != 0) 609 goto fail2; 610 sfxge_mac_stat_init(sc); 611 612 port->init_state = SFXGE_PORT_INITIALIZED; 613 614 return (0); 615 616fail2: 617 free(port->mac_stats.decode_buf, M_SFXGE); 618 sfxge_dma_free(phy_stats_buf); 619fail: 620 free(port->phy_stats.decode_buf, M_SFXGE); 621 SFXGE_PORT_LOCK_DESTROY(port); 622 port->sc = NULL; 623 return (rc); 624} 625 626static int sfxge_link_mode[EFX_PHY_MEDIA_NTYPES][EFX_LINK_NMODES] = { 627 [EFX_PHY_MEDIA_CX4] = { 628 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_CX4, 629 }, 630 [EFX_PHY_MEDIA_KX4] = { 631 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_KX4, 632 }, 633 [EFX_PHY_MEDIA_XFP] = { 634 /* Don't know the module type, but assume SR for now. */ 635 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_SR, 636 }, 637 [EFX_PHY_MEDIA_SFP_PLUS] = { 638 /* Don't know the module type, but assume SX/SR for now. */ 639 [EFX_LINK_1000FDX] = IFM_ETHER | IFM_FDX | IFM_1000_SX, 640 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_SR, 641 }, 642 [EFX_PHY_MEDIA_BASE_T] = { 643 [EFX_LINK_10HDX] = IFM_ETHER | IFM_HDX | IFM_10_T, 644 [EFX_LINK_10FDX] = IFM_ETHER | IFM_FDX | IFM_10_T, 645 [EFX_LINK_100HDX] = IFM_ETHER | IFM_HDX | IFM_100_TX, 646 [EFX_LINK_100FDX] = IFM_ETHER | IFM_FDX | IFM_100_TX, 647 [EFX_LINK_1000HDX] = IFM_ETHER | IFM_HDX | IFM_1000_T, 648 [EFX_LINK_1000FDX] = IFM_ETHER | IFM_FDX | IFM_1000_T, 649 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_T, 650 }, 651}; 652 653static void 654sfxge_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 655{ 656 struct sfxge_softc *sc; 657 efx_phy_media_type_t medium_type; 658 efx_link_mode_t mode; 659 660 sc = ifp->if_softc; 661 SFXGE_ADAPTER_LOCK(sc); 662 663 ifmr->ifm_status = IFM_AVALID; 664 ifmr->ifm_active = IFM_ETHER; 665 666 if (SFXGE_RUNNING(sc) && SFXGE_LINK_UP(sc)) { 667 ifmr->ifm_status |= IFM_ACTIVE; 668 669 efx_phy_media_type_get(sc->enp, &medium_type); 670 mode = sc->port.link_mode; 671 ifmr->ifm_active |= sfxge_link_mode[medium_type][mode]; 672 ifmr->ifm_active |= sfxge_port_link_fc_ifm(sc); 673 } 674 675 SFXGE_ADAPTER_UNLOCK(sc); 676} 677 678static int 679sfxge_media_change(struct ifnet *ifp) 680{ 681 struct sfxge_softc *sc; 682 struct ifmedia_entry *ifm; 683 int rc; 684 685 sc = ifp->if_softc; 686 ifm = sc->media.ifm_cur; 687 688 SFXGE_ADAPTER_LOCK(sc); 689 690 if (!SFXGE_RUNNING(sc)) { 691 rc = 0; 692 goto out; 693 } 694 695 rc = efx_mac_fcntl_set(sc->enp, sfxge_port_wanted_fc(sc), B_TRUE); 696 if (rc != 0) 697 goto out; 698 699 rc = efx_phy_adv_cap_set(sc->enp, ifm->ifm_data); 700out: 701 SFXGE_ADAPTER_UNLOCK(sc); 702 703 return (rc); 704} 705 706int sfxge_port_ifmedia_init(struct sfxge_softc *sc) 707{ 708 efx_phy_media_type_t medium_type; 709 uint32_t cap_mask, mode_cap_mask; 710 efx_link_mode_t mode; 711 int mode_ifm, best_mode_ifm = 0; 712 int rc; 713 714 /* We need port state to initialise the ifmedia list. */ 715 if ((rc = efx_nic_init(sc->enp)) != 0) 716 goto out; 717 if ((rc = efx_port_init(sc->enp)) != 0) 718 goto out2; 719 720 /* 721 * Register ifconfig callbacks for querying and setting the 722 * link mode and link status. 723 */ 724 ifmedia_init(&sc->media, IFM_IMASK, sfxge_media_change, 725 sfxge_media_status); 726 727 /* 728 * Map firmware medium type and capabilities to ifmedia types. 729 * ifmedia does not distinguish between forcing the link mode 730 * and disabling auto-negotiation. 1000BASE-T and 10GBASE-T 731 * require AN even if only one link mode is enabled, and for 732 * 100BASE-TX it is useful even if the link mode is forced. 733 * Therefore we never disable auto-negotiation. 734 * 735 * Also enable and advertise flow control by default. 736 */ 737 738 efx_phy_media_type_get(sc->enp, &medium_type); 739 efx_phy_adv_cap_get(sc->enp, EFX_PHY_CAP_PERM, &cap_mask); 740 741 EFX_STATIC_ASSERT(EFX_LINK_10HDX == EFX_PHY_CAP_10HDX + 1); 742 EFX_STATIC_ASSERT(EFX_LINK_10FDX == EFX_PHY_CAP_10FDX + 1); 743 EFX_STATIC_ASSERT(EFX_LINK_100HDX == EFX_PHY_CAP_100HDX + 1); 744 EFX_STATIC_ASSERT(EFX_LINK_100FDX == EFX_PHY_CAP_100FDX + 1); 745 EFX_STATIC_ASSERT(EFX_LINK_1000HDX == EFX_PHY_CAP_1000HDX + 1); 746 EFX_STATIC_ASSERT(EFX_LINK_1000FDX == EFX_PHY_CAP_1000FDX + 1); 747 EFX_STATIC_ASSERT(EFX_LINK_10000FDX == EFX_PHY_CAP_10000FDX + 1); 748 749 for (mode = EFX_LINK_10HDX; mode <= EFX_LINK_10000FDX; mode++) { 750 mode_cap_mask = 1 << (mode - 1); 751 mode_ifm = sfxge_link_mode[medium_type][mode]; 752 753 if ((cap_mask & mode_cap_mask) && mode_ifm) { 754 mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_AN); 755 756#ifdef SFXGE_HAVE_PAUSE_MEDIAOPTS 757 /* No flow-control */ 758 ifmedia_add(&sc->media, mode_ifm, mode_cap_mask, NULL); 759 760 /* Respond-only. If using AN, we implicitly 761 * offer symmetric as well, but that doesn't 762 * mean we *have* to generate pause frames. 763 */ 764 mode_cap_mask |= cap_mask & ((1 << EFX_PHY_CAP_PAUSE) | 765 (1 << EFX_PHY_CAP_ASYM)); 766 mode_ifm |= IFM_ETH_RXPAUSE; 767 ifmedia_add(&sc->media, mode_ifm, mode_cap_mask, NULL); 768 769 /* Symmetric */ 770 mode_cap_mask &= ~(1 << EFX_PHY_CAP_ASYM); 771 mode_ifm |= IFM_ETH_TXPAUSE; 772#else /* !SFXGE_HAVE_PAUSE_MEDIAOPTS */ 773 mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_PAUSE); 774#endif 775 ifmedia_add(&sc->media, mode_ifm, mode_cap_mask, NULL); 776 777 /* Link modes are numbered in order of speed, 778 * so assume the last one available is the best. 779 */ 780 best_mode_ifm = mode_ifm; 781 } 782 } 783 784 if (cap_mask & (1 << EFX_PHY_CAP_AN)) { 785 /* Add autoselect mode. */ 786 mode_ifm = IFM_ETHER | IFM_AUTO; 787 ifmedia_add(&sc->media, mode_ifm, 788 cap_mask & ~(1 << EFX_PHY_CAP_ASYM), NULL); 789 best_mode_ifm = mode_ifm; 790 } 791 792 if (best_mode_ifm != 0) 793 ifmedia_set(&sc->media, best_mode_ifm); 794 795 /* Now discard port state until interface is started. */ 796 efx_port_fini(sc->enp); 797out2: 798 efx_nic_fini(sc->enp); 799out: 800 return (rc); 801} 802