efx_rx.c revision 299320
1/*- 2 * Copyright (c) 2007-2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/sfxge/common/efx_rx.c 299320 2016-05-10 07:01:06Z arybchik $"); 33 34#include "efx.h" 35#include "efx_impl.h" 36 37 38#if EFSYS_OPT_SIENA 39 40static __checkReturn efx_rc_t 41falconsiena_rx_init( 42 __in efx_nic_t *enp); 43 44static void 45falconsiena_rx_fini( 46 __in efx_nic_t *enp); 47 48#if EFSYS_OPT_RX_SCATTER 49static __checkReturn efx_rc_t 50falconsiena_rx_scatter_enable( 51 __in efx_nic_t *enp, 52 __in unsigned int buf_size); 53#endif /* EFSYS_OPT_RX_SCATTER */ 54 55#if EFSYS_OPT_RX_SCALE 56static __checkReturn efx_rc_t 57falconsiena_rx_scale_mode_set( 58 __in efx_nic_t *enp, 59 __in efx_rx_hash_alg_t alg, 60 __in efx_rx_hash_type_t type, 61 __in boolean_t insert); 62 63static __checkReturn efx_rc_t 64falconsiena_rx_scale_key_set( 65 __in efx_nic_t *enp, 66 __in_ecount(n) uint8_t *key, 67 __in size_t n); 68 69static __checkReturn efx_rc_t 70falconsiena_rx_scale_tbl_set( 71 __in efx_nic_t *enp, 72 __in_ecount(n) unsigned int *table, 73 __in size_t n); 74 75static __checkReturn uint32_t 76falconsiena_rx_prefix_hash( 77 __in efx_nic_t *enp, 78 __in efx_rx_hash_alg_t func, 79 __in uint8_t *buffer); 80 81#endif /* EFSYS_OPT_RX_SCALE */ 82 83static __checkReturn efx_rc_t 84falconsiena_rx_prefix_pktlen( 85 __in efx_nic_t *enp, 86 __in uint8_t *buffer, 87 __out uint16_t *lengthp); 88 89static void 90falconsiena_rx_qpost( 91 __in efx_rxq_t *erp, 92 __in_ecount(n) efsys_dma_addr_t *addrp, 93 __in size_t size, 94 __in unsigned int n, 95 __in unsigned int completed, 96 __in unsigned int added); 97 98static void 99falconsiena_rx_qpush( 100 __in efx_rxq_t *erp, 101 __in unsigned int added, 102 __inout unsigned int *pushedp); 103 104static __checkReturn efx_rc_t 105falconsiena_rx_qflush( 106 __in efx_rxq_t *erp); 107 108static void 109falconsiena_rx_qenable( 110 __in efx_rxq_t *erp); 111 112static __checkReturn efx_rc_t 113falconsiena_rx_qcreate( 114 __in efx_nic_t *enp, 115 __in unsigned int index, 116 __in unsigned int label, 117 __in efx_rxq_type_t type, 118 __in efsys_mem_t *esmp, 119 __in size_t n, 120 __in uint32_t id, 121 __in efx_evq_t *eep, 122 __in efx_rxq_t *erp); 123 124static void 125falconsiena_rx_qdestroy( 126 __in efx_rxq_t *erp); 127 128#endif /* EFSYS_OPT_SIENA */ 129 130 131#if EFSYS_OPT_SIENA 132static efx_rx_ops_t __efx_rx_siena_ops = { 133 falconsiena_rx_init, /* erxo_init */ 134 falconsiena_rx_fini, /* erxo_fini */ 135#if EFSYS_OPT_RX_SCATTER 136 falconsiena_rx_scatter_enable, /* erxo_scatter_enable */ 137#endif 138#if EFSYS_OPT_RX_SCALE 139 falconsiena_rx_scale_mode_set, /* erxo_scale_mode_set */ 140 falconsiena_rx_scale_key_set, /* erxo_scale_key_set */ 141 falconsiena_rx_scale_tbl_set, /* erxo_scale_tbl_set */ 142 falconsiena_rx_prefix_hash, /* erxo_prefix_hash */ 143#endif 144 falconsiena_rx_prefix_pktlen, /* erxo_prefix_pktlen */ 145 falconsiena_rx_qpost, /* erxo_qpost */ 146 falconsiena_rx_qpush, /* erxo_qpush */ 147 falconsiena_rx_qflush, /* erxo_qflush */ 148 falconsiena_rx_qenable, /* erxo_qenable */ 149 falconsiena_rx_qcreate, /* erxo_qcreate */ 150 falconsiena_rx_qdestroy, /* erxo_qdestroy */ 151}; 152#endif /* EFSYS_OPT_SIENA */ 153 154#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 155static efx_rx_ops_t __efx_rx_ef10_ops = { 156 ef10_rx_init, /* erxo_init */ 157 ef10_rx_fini, /* erxo_fini */ 158#if EFSYS_OPT_RX_SCATTER 159 ef10_rx_scatter_enable, /* erxo_scatter_enable */ 160#endif 161#if EFSYS_OPT_RX_SCALE 162 ef10_rx_scale_mode_set, /* erxo_scale_mode_set */ 163 ef10_rx_scale_key_set, /* erxo_scale_key_set */ 164 ef10_rx_scale_tbl_set, /* erxo_scale_tbl_set */ 165 ef10_rx_prefix_hash, /* erxo_prefix_hash */ 166#endif 167 ef10_rx_prefix_pktlen, /* erxo_prefix_pktlen */ 168 ef10_rx_qpost, /* erxo_qpost */ 169 ef10_rx_qpush, /* erxo_qpush */ 170 ef10_rx_qflush, /* erxo_qflush */ 171 ef10_rx_qenable, /* erxo_qenable */ 172 ef10_rx_qcreate, /* erxo_qcreate */ 173 ef10_rx_qdestroy, /* erxo_qdestroy */ 174}; 175#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ 176 177 178 __checkReturn efx_rc_t 179efx_rx_init( 180 __inout efx_nic_t *enp) 181{ 182 efx_rx_ops_t *erxop; 183 efx_rc_t rc; 184 185 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 186 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); 187 188 if (!(enp->en_mod_flags & EFX_MOD_EV)) { 189 rc = EINVAL; 190 goto fail1; 191 } 192 193 if (enp->en_mod_flags & EFX_MOD_RX) { 194 rc = EINVAL; 195 goto fail2; 196 } 197 198 switch (enp->en_family) { 199#if EFSYS_OPT_SIENA 200 case EFX_FAMILY_SIENA: 201 erxop = (efx_rx_ops_t *)&__efx_rx_siena_ops; 202 break; 203#endif /* EFSYS_OPT_SIENA */ 204 205#if EFSYS_OPT_HUNTINGTON 206 case EFX_FAMILY_HUNTINGTON: 207 erxop = (efx_rx_ops_t *)&__efx_rx_ef10_ops; 208 break; 209#endif /* EFSYS_OPT_HUNTINGTON */ 210 211#if EFSYS_OPT_MEDFORD 212 case EFX_FAMILY_MEDFORD: 213 erxop = (efx_rx_ops_t *)&__efx_rx_ef10_ops; 214 break; 215#endif /* EFSYS_OPT_MEDFORD */ 216 217 default: 218 EFSYS_ASSERT(0); 219 rc = ENOTSUP; 220 goto fail3; 221 } 222 223 if ((rc = erxop->erxo_init(enp)) != 0) 224 goto fail4; 225 226 enp->en_erxop = erxop; 227 enp->en_mod_flags |= EFX_MOD_RX; 228 return (0); 229 230fail4: 231 EFSYS_PROBE(fail4); 232fail3: 233 EFSYS_PROBE(fail3); 234fail2: 235 EFSYS_PROBE(fail2); 236fail1: 237 EFSYS_PROBE1(fail1, efx_rc_t, rc); 238 239 enp->en_erxop = NULL; 240 enp->en_mod_flags &= ~EFX_MOD_RX; 241 return (rc); 242} 243 244 void 245efx_rx_fini( 246 __in efx_nic_t *enp) 247{ 248 efx_rx_ops_t *erxop = enp->en_erxop; 249 250 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 251 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); 252 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); 253 EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0); 254 255 erxop->erxo_fini(enp); 256 257 enp->en_erxop = NULL; 258 enp->en_mod_flags &= ~EFX_MOD_RX; 259} 260 261#if EFSYS_OPT_RX_SCATTER 262 __checkReturn efx_rc_t 263efx_rx_scatter_enable( 264 __in efx_nic_t *enp, 265 __in unsigned int buf_size) 266{ 267 efx_rx_ops_t *erxop = enp->en_erxop; 268 efx_rc_t rc; 269 270 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 271 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); 272 273 if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0) 274 goto fail1; 275 276 return (0); 277 278fail1: 279 EFSYS_PROBE1(fail1, efx_rc_t, rc); 280 return (rc); 281} 282#endif /* EFSYS_OPT_RX_SCATTER */ 283 284#if EFSYS_OPT_RX_SCALE 285 __checkReturn efx_rc_t 286efx_rx_hash_support_get( 287 __in efx_nic_t *enp, 288 __out efx_rx_hash_support_t *supportp) 289{ 290 efx_rc_t rc; 291 292 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 293 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); 294 295 if (supportp == NULL) { 296 rc = EINVAL; 297 goto fail1; 298 } 299 300 /* Report if resources are available to insert RX hash value */ 301 *supportp = enp->en_hash_support; 302 303 return (0); 304 305fail1: 306 EFSYS_PROBE1(fail1, efx_rc_t, rc); 307 308 return (rc); 309} 310 311 __checkReturn efx_rc_t 312efx_rx_scale_support_get( 313 __in efx_nic_t *enp, 314 __out efx_rx_scale_support_t *supportp) 315{ 316 efx_rc_t rc; 317 318 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 319 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); 320 321 if (supportp == NULL) { 322 rc = EINVAL; 323 goto fail1; 324 } 325 326 /* Report if resources are available to support RSS */ 327 *supportp = enp->en_rss_support; 328 329 return (0); 330 331fail1: 332 EFSYS_PROBE1(fail1, efx_rc_t, rc); 333 334 return (rc); 335} 336 337 __checkReturn efx_rc_t 338efx_rx_scale_mode_set( 339 __in efx_nic_t *enp, 340 __in efx_rx_hash_alg_t alg, 341 __in efx_rx_hash_type_t type, 342 __in boolean_t insert) 343{ 344 efx_rx_ops_t *erxop = enp->en_erxop; 345 efx_rc_t rc; 346 347 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 348 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); 349 350 if (erxop->erxo_scale_mode_set != NULL) { 351 if ((rc = erxop->erxo_scale_mode_set(enp, alg, 352 type, insert)) != 0) 353 goto fail1; 354 } 355 356 return (0); 357 358fail1: 359 EFSYS_PROBE1(fail1, efx_rc_t, rc); 360 return (rc); 361} 362#endif /* EFSYS_OPT_RX_SCALE */ 363 364#if EFSYS_OPT_RX_SCALE 365 __checkReturn efx_rc_t 366efx_rx_scale_key_set( 367 __in efx_nic_t *enp, 368 __in_ecount(n) uint8_t *key, 369 __in size_t n) 370{ 371 efx_rx_ops_t *erxop = enp->en_erxop; 372 efx_rc_t rc; 373 374 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 375 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); 376 377 if ((rc = erxop->erxo_scale_key_set(enp, key, n)) != 0) 378 goto fail1; 379 380 return (0); 381 382fail1: 383 EFSYS_PROBE1(fail1, efx_rc_t, rc); 384 385 return (rc); 386} 387#endif /* EFSYS_OPT_RX_SCALE */ 388 389#if EFSYS_OPT_RX_SCALE 390 __checkReturn efx_rc_t 391efx_rx_scale_tbl_set( 392 __in efx_nic_t *enp, 393 __in_ecount(n) unsigned int *table, 394 __in size_t n) 395{ 396 efx_rx_ops_t *erxop = enp->en_erxop; 397 efx_rc_t rc; 398 399 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 400 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); 401 402 if ((rc = erxop->erxo_scale_tbl_set(enp, table, n)) != 0) 403 goto fail1; 404 405 return (0); 406 407fail1: 408 EFSYS_PROBE1(fail1, efx_rc_t, rc); 409 410 return (rc); 411} 412#endif /* EFSYS_OPT_RX_SCALE */ 413 414 void 415efx_rx_qpost( 416 __in efx_rxq_t *erp, 417 __in_ecount(n) efsys_dma_addr_t *addrp, 418 __in size_t size, 419 __in unsigned int n, 420 __in unsigned int completed, 421 __in unsigned int added) 422{ 423 efx_nic_t *enp = erp->er_enp; 424 efx_rx_ops_t *erxop = enp->en_erxop; 425 426 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); 427 428 erxop->erxo_qpost(erp, addrp, size, n, completed, added); 429} 430 431 void 432efx_rx_qpush( 433 __in efx_rxq_t *erp, 434 __in unsigned int added, 435 __inout unsigned int *pushedp) 436{ 437 efx_nic_t *enp = erp->er_enp; 438 efx_rx_ops_t *erxop = enp->en_erxop; 439 440 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); 441 442 erxop->erxo_qpush(erp, added, pushedp); 443} 444 445 __checkReturn efx_rc_t 446efx_rx_qflush( 447 __in efx_rxq_t *erp) 448{ 449 efx_nic_t *enp = erp->er_enp; 450 efx_rx_ops_t *erxop = enp->en_erxop; 451 efx_rc_t rc; 452 453 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); 454 455 if ((rc = erxop->erxo_qflush(erp)) != 0) 456 goto fail1; 457 458 return (0); 459 460fail1: 461 EFSYS_PROBE1(fail1, efx_rc_t, rc); 462 463 return (rc); 464} 465 466 void 467efx_rx_qenable( 468 __in efx_rxq_t *erp) 469{ 470 efx_nic_t *enp = erp->er_enp; 471 efx_rx_ops_t *erxop = enp->en_erxop; 472 473 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); 474 475 erxop->erxo_qenable(erp); 476} 477 478 __checkReturn efx_rc_t 479efx_rx_qcreate( 480 __in efx_nic_t *enp, 481 __in unsigned int index, 482 __in unsigned int label, 483 __in efx_rxq_type_t type, 484 __in efsys_mem_t *esmp, 485 __in size_t n, 486 __in uint32_t id, 487 __in efx_evq_t *eep, 488 __deref_out efx_rxq_t **erpp) 489{ 490 efx_rx_ops_t *erxop = enp->en_erxop; 491 efx_rxq_t *erp; 492 efx_rc_t rc; 493 494 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 495 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); 496 497 /* Allocate an RXQ object */ 498 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp); 499 500 if (erp == NULL) { 501 rc = ENOMEM; 502 goto fail1; 503 } 504 505 erp->er_magic = EFX_RXQ_MAGIC; 506 erp->er_enp = enp; 507 erp->er_index = index; 508 erp->er_mask = n - 1; 509 erp->er_esmp = esmp; 510 511 if ((rc = erxop->erxo_qcreate(enp, index, label, type, esmp, n, id, 512 eep, erp)) != 0) 513 goto fail2; 514 515 enp->en_rx_qcount++; 516 *erpp = erp; 517 518 return (0); 519 520fail2: 521 EFSYS_PROBE(fail2); 522 523 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp); 524fail1: 525 EFSYS_PROBE1(fail1, efx_rc_t, rc); 526 527 return (rc); 528} 529 530 void 531efx_rx_qdestroy( 532 __in efx_rxq_t *erp) 533{ 534 efx_nic_t *enp = erp->er_enp; 535 efx_rx_ops_t *erxop = enp->en_erxop; 536 537 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); 538 539 erxop->erxo_qdestroy(erp); 540} 541 542 __checkReturn efx_rc_t 543efx_psuedo_hdr_pkt_length_get( 544 __in efx_nic_t *enp, 545 __in uint8_t *buffer, 546 __out uint16_t *lengthp) 547{ 548 efx_rx_ops_t *erxop = enp->en_erxop; 549 550 return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp)); 551} 552 553#if EFSYS_OPT_RX_SCALE 554 __checkReturn uint32_t 555efx_psuedo_hdr_hash_get( 556 __in efx_nic_t *enp, 557 __in efx_rx_hash_alg_t func, 558 __in uint8_t *buffer) 559{ 560 efx_rx_ops_t *erxop = enp->en_erxop; 561 562 EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE); 563 return (erxop->erxo_prefix_hash(enp, func, buffer)); 564} 565#endif /* EFSYS_OPT_RX_SCALE */ 566 567#if EFSYS_OPT_SIENA 568 569static __checkReturn efx_rc_t 570falconsiena_rx_init( 571 __in efx_nic_t *enp) 572{ 573 efx_oword_t oword; 574 unsigned int index; 575 576 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword); 577 578 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0); 579 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); 580 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); 581 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); 582 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0); 583 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32); 584 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword); 585 586 /* Zero the RSS table */ 587 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; 588 index++) { 589 EFX_ZERO_OWORD(oword); 590 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL, 591 index, &oword, B_TRUE); 592 } 593 594#if EFSYS_OPT_RX_SCALE 595 /* The RSS key and indirection table are writable. */ 596 enp->en_rss_support = EFX_RX_SCALE_EXCLUSIVE; 597 598 /* Hardware can insert RX hash with/without RSS */ 599 enp->en_hash_support = EFX_RX_HASH_AVAILABLE; 600#endif /* EFSYS_OPT_RX_SCALE */ 601 602 return (0); 603} 604 605#if EFSYS_OPT_RX_SCATTER 606static __checkReturn efx_rc_t 607falconsiena_rx_scatter_enable( 608 __in efx_nic_t *enp, 609 __in unsigned int buf_size) 610{ 611 unsigned int nbuf32; 612 efx_oword_t oword; 613 efx_rc_t rc; 614 615 nbuf32 = buf_size / 32; 616 if ((nbuf32 == 0) || 617 (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) || 618 ((buf_size % 32) != 0)) { 619 rc = EINVAL; 620 goto fail1; 621 } 622 623 if (enp->en_rx_qcount > 0) { 624 rc = EBUSY; 625 goto fail2; 626 } 627 628 /* Set scatter buffer size */ 629 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword); 630 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32); 631 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword); 632 633 /* Enable scatter for packets not matching a filter */ 634 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword); 635 EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1); 636 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword); 637 638 return (0); 639 640fail2: 641 EFSYS_PROBE(fail2); 642fail1: 643 EFSYS_PROBE1(fail1, efx_rc_t, rc); 644 645 return (rc); 646} 647#endif /* EFSYS_OPT_RX_SCATTER */ 648 649 650#define EFX_RX_LFSR_HASH(_enp, _insert) \ 651 do { \ 652 efx_oword_t oword; \ 653 \ 654 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \ 655 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \ 656 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \ 657 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \ 658 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \ 659 (_insert) ? 1 : 0); \ 660 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \ 661 \ 662 if ((_enp)->en_family == EFX_FAMILY_SIENA) { \ 663 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \ 664 &oword); \ 665 EFX_SET_OWORD_FIELD(oword, \ 666 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \ 667 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \ 668 &oword); \ 669 } \ 670 \ 671 _NOTE(CONSTANTCONDITION) \ 672 } while (B_FALSE) 673 674#define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \ 675 do { \ 676 efx_oword_t oword; \ 677 \ 678 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \ 679 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \ 680 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \ 681 (_ip) ? 1 : 0); \ 682 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \ 683 (_tcp) ? 0 : 1); \ 684 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \ 685 (_insert) ? 1 : 0); \ 686 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \ 687 \ 688 _NOTE(CONSTANTCONDITION) \ 689 } while (B_FALSE) 690 691#define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \ 692 do { \ 693 efx_oword_t oword; \ 694 \ 695 if ((_enp)->en_family == EFX_FAMILY_FALCON) { \ 696 (_rc) = ((_ip) || (_tcp)) ? ENOTSUP : 0; \ 697 break; \ 698 } \ 699 \ 700 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \ 701 EFX_SET_OWORD_FIELD(oword, \ 702 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \ 703 EFX_SET_OWORD_FIELD(oword, \ 704 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \ 705 EFX_SET_OWORD_FIELD(oword, \ 706 FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \ 707 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \ 708 \ 709 (_rc) = 0; \ 710 \ 711 _NOTE(CONSTANTCONDITION) \ 712 } while (B_FALSE) 713 714 715#if EFSYS_OPT_RX_SCALE 716 717static __checkReturn efx_rc_t 718falconsiena_rx_scale_mode_set( 719 __in efx_nic_t *enp, 720 __in efx_rx_hash_alg_t alg, 721 __in efx_rx_hash_type_t type, 722 __in boolean_t insert) 723{ 724 efx_rc_t rc; 725 726 switch (alg) { 727 case EFX_RX_HASHALG_LFSR: 728 EFX_RX_LFSR_HASH(enp, insert); 729 break; 730 731 case EFX_RX_HASHALG_TOEPLITZ: 732 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert, 733 type & (1 << EFX_RX_HASH_IPV4), 734 type & (1 << EFX_RX_HASH_TCPIPV4)); 735 736 EFX_RX_TOEPLITZ_IPV6_HASH(enp, 737 type & (1 << EFX_RX_HASH_IPV6), 738 type & (1 << EFX_RX_HASH_TCPIPV6), 739 rc); 740 if (rc != 0) 741 goto fail1; 742 743 break; 744 745 default: 746 rc = EINVAL; 747 goto fail2; 748 } 749 750 return (0); 751 752fail2: 753 EFSYS_PROBE(fail2); 754fail1: 755 EFSYS_PROBE1(fail1, efx_rc_t, rc); 756 757 EFX_RX_LFSR_HASH(enp, B_FALSE); 758 759 return (rc); 760} 761#endif 762 763#if EFSYS_OPT_RX_SCALE 764static __checkReturn efx_rc_t 765falconsiena_rx_scale_key_set( 766 __in efx_nic_t *enp, 767 __in_ecount(n) uint8_t *key, 768 __in size_t n) 769{ 770 efx_oword_t oword; 771 unsigned int byte; 772 unsigned int offset; 773 efx_rc_t rc; 774 775 byte = 0; 776 777 /* Write Toeplitz IPv4 hash key */ 778 EFX_ZERO_OWORD(oword); 779 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8; 780 offset > 0 && byte < n; 781 --offset) 782 oword.eo_u8[offset - 1] = key[byte++]; 783 784 EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword); 785 786 byte = 0; 787 788 /* Verify Toeplitz IPv4 hash key */ 789 EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword); 790 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8; 791 offset > 0 && byte < n; 792 --offset) { 793 if (oword.eo_u8[offset - 1] != key[byte++]) { 794 rc = EFAULT; 795 goto fail1; 796 } 797 } 798 799 if ((enp->en_features & EFX_FEATURE_IPV6) == 0) 800 goto done; 801 802 EFSYS_ASSERT3U(enp->en_family, !=, EFX_FAMILY_FALCON); 803 804 byte = 0; 805 806 /* Write Toeplitz IPv6 hash key 3 */ 807 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword); 808 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN + 809 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8; 810 offset > 0 && byte < n; 811 --offset) 812 oword.eo_u8[offset - 1] = key[byte++]; 813 814 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword); 815 816 /* Write Toeplitz IPv6 hash key 2 */ 817 EFX_ZERO_OWORD(oword); 818 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN + 819 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8; 820 offset > 0 && byte < n; 821 --offset) 822 oword.eo_u8[offset - 1] = key[byte++]; 823 824 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword); 825 826 /* Write Toeplitz IPv6 hash key 1 */ 827 EFX_ZERO_OWORD(oword); 828 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN + 829 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8; 830 offset > 0 && byte < n; 831 --offset) 832 oword.eo_u8[offset - 1] = key[byte++]; 833 834 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword); 835 836 byte = 0; 837 838 /* Verify Toeplitz IPv6 hash key 3 */ 839 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword); 840 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN + 841 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8; 842 offset > 0 && byte < n; 843 --offset) { 844 if (oword.eo_u8[offset - 1] != key[byte++]) { 845 rc = EFAULT; 846 goto fail2; 847 } 848 } 849 850 /* Verify Toeplitz IPv6 hash key 2 */ 851 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword); 852 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN + 853 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8; 854 offset > 0 && byte < n; 855 --offset) { 856 if (oword.eo_u8[offset - 1] != key[byte++]) { 857 rc = EFAULT; 858 goto fail3; 859 } 860 } 861 862 /* Verify Toeplitz IPv6 hash key 1 */ 863 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword); 864 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN + 865 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8; 866 offset > 0 && byte < n; 867 --offset) { 868 if (oword.eo_u8[offset - 1] != key[byte++]) { 869 rc = EFAULT; 870 goto fail4; 871 } 872 } 873 874done: 875 return (0); 876 877fail4: 878 EFSYS_PROBE(fail4); 879fail3: 880 EFSYS_PROBE(fail3); 881fail2: 882 EFSYS_PROBE(fail2); 883fail1: 884 EFSYS_PROBE1(fail1, efx_rc_t, rc); 885 886 return (rc); 887} 888#endif 889 890#if EFSYS_OPT_RX_SCALE 891static __checkReturn efx_rc_t 892falconsiena_rx_scale_tbl_set( 893 __in efx_nic_t *enp, 894 __in_ecount(n) unsigned int *table, 895 __in size_t n) 896{ 897 efx_oword_t oword; 898 int index; 899 efx_rc_t rc; 900 901 EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS); 902 EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH)); 903 904 if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) { 905 rc = EINVAL; 906 goto fail1; 907 } 908 909 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) { 910 uint32_t byte; 911 912 /* Calculate the entry to place in the table */ 913 byte = (n > 0) ? (uint32_t)table[index % n] : 0; 914 915 EFSYS_PROBE2(table, int, index, uint32_t, byte); 916 917 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte); 918 919 /* Write the table */ 920 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL, 921 index, &oword, B_TRUE); 922 } 923 924 for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) { 925 uint32_t byte; 926 927 /* Determine if we're starting a new batch */ 928 byte = (n > 0) ? (uint32_t)table[index % n] : 0; 929 930 /* Read the table */ 931 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL, 932 index, &oword, B_TRUE); 933 934 /* Verify the entry */ 935 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) { 936 rc = EFAULT; 937 goto fail2; 938 } 939 } 940 941 return (0); 942 943fail2: 944 EFSYS_PROBE(fail2); 945fail1: 946 EFSYS_PROBE1(fail1, efx_rc_t, rc); 947 948 return (rc); 949} 950#endif 951 952/* 953 * Falcon/Siena psuedo-header 954 * -------------------------- 955 * 956 * Receive packets are prefixed by an optional 16 byte pseudo-header. 957 * The psuedo-header is a byte array of one of the forms: 958 * 959 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 960 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT 961 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL 962 * 963 * where: 964 * TT.TT.TT.TT Toeplitz hash (32-bit big-endian) 965 * LL.LL LFSR hash (16-bit big-endian) 966 */ 967 968#if EFSYS_OPT_RX_SCALE 969static __checkReturn uint32_t 970falconsiena_rx_prefix_hash( 971 __in efx_nic_t *enp, 972 __in efx_rx_hash_alg_t func, 973 __in uint8_t *buffer) 974{ 975 switch (func) { 976 case EFX_RX_HASHALG_TOEPLITZ: 977 return ((buffer[12] << 24) | 978 (buffer[13] << 16) | 979 (buffer[14] << 8) | 980 buffer[15]); 981 982 case EFX_RX_HASHALG_LFSR: 983 return ((buffer[14] << 8) | buffer[15]); 984 985 default: 986 EFSYS_ASSERT(0); 987 return (0); 988 } 989} 990#endif /* EFSYS_OPT_RX_SCALE */ 991 992static __checkReturn efx_rc_t 993falconsiena_rx_prefix_pktlen( 994 __in efx_nic_t *enp, 995 __in uint8_t *buffer, 996 __out uint16_t *lengthp) 997{ 998 /* Not supported by Falcon/Siena hardware */ 999 EFSYS_ASSERT(0); 1000 return (ENOTSUP); 1001} 1002 1003 1004static void 1005falconsiena_rx_qpost( 1006 __in efx_rxq_t *erp, 1007 __in_ecount(n) efsys_dma_addr_t *addrp, 1008 __in size_t size, 1009 __in unsigned int n, 1010 __in unsigned int completed, 1011 __in unsigned int added) 1012{ 1013 efx_qword_t qword; 1014 unsigned int i; 1015 unsigned int offset; 1016 unsigned int id; 1017 1018 /* The client driver must not overfill the queue */ 1019 EFSYS_ASSERT3U(added - completed + n, <=, 1020 EFX_RXQ_LIMIT(erp->er_mask + 1)); 1021 1022 id = added & (erp->er_mask); 1023 for (i = 0; i < n; i++) { 1024 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index, 1025 unsigned int, id, efsys_dma_addr_t, addrp[i], 1026 size_t, size); 1027 1028 EFX_POPULATE_QWORD_3(qword, 1029 FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size), 1030 FSF_AZ_RX_KER_BUF_ADDR_DW0, 1031 (uint32_t)(addrp[i] & 0xffffffff), 1032 FSF_AZ_RX_KER_BUF_ADDR_DW1, 1033 (uint32_t)(addrp[i] >> 32)); 1034 1035 offset = id * sizeof (efx_qword_t); 1036 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword); 1037 1038 id = (id + 1) & (erp->er_mask); 1039 } 1040} 1041 1042static void 1043falconsiena_rx_qpush( 1044 __in efx_rxq_t *erp, 1045 __in unsigned int added, 1046 __inout unsigned int *pushedp) 1047{ 1048 efx_nic_t *enp = erp->er_enp; 1049 unsigned int pushed = *pushedp; 1050 uint32_t wptr; 1051 efx_oword_t oword; 1052 efx_dword_t dword; 1053 1054 /* All descriptors are pushed */ 1055 *pushedp = added; 1056 1057 /* Push the populated descriptors out */ 1058 wptr = added & erp->er_mask; 1059 1060 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr); 1061 1062 /* Only write the third DWORD */ 1063 EFX_POPULATE_DWORD_1(dword, 1064 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3)); 1065 1066 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */ 1067 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1, 1068 wptr, pushed & erp->er_mask); 1069 EFSYS_PIO_WRITE_BARRIER(); 1070 EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0, 1071 erp->er_index, &dword, B_FALSE); 1072} 1073 1074static __checkReturn efx_rc_t 1075falconsiena_rx_qflush( 1076 __in efx_rxq_t *erp) 1077{ 1078 efx_nic_t *enp = erp->er_enp; 1079 efx_oword_t oword; 1080 uint32_t label; 1081 1082 label = erp->er_index; 1083 1084 /* Flush the queue */ 1085 EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1, 1086 FRF_AZ_RX_FLUSH_DESCQ, label); 1087 EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword); 1088 1089 return (0); 1090} 1091 1092static void 1093falconsiena_rx_qenable( 1094 __in efx_rxq_t *erp) 1095{ 1096 efx_nic_t *enp = erp->er_enp; 1097 efx_oword_t oword; 1098 1099 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); 1100 1101 EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL, 1102 erp->er_index, &oword, B_TRUE); 1103 1104 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0); 1105 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0); 1106 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1); 1107 1108 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL, 1109 erp->er_index, &oword, B_TRUE); 1110} 1111 1112static __checkReturn efx_rc_t 1113falconsiena_rx_qcreate( 1114 __in efx_nic_t *enp, 1115 __in unsigned int index, 1116 __in unsigned int label, 1117 __in efx_rxq_type_t type, 1118 __in efsys_mem_t *esmp, 1119 __in size_t n, 1120 __in uint32_t id, 1121 __in efx_evq_t *eep, 1122 __in efx_rxq_t *erp) 1123{ 1124 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 1125 efx_oword_t oword; 1126 uint32_t size; 1127 boolean_t jumbo; 1128 efx_rc_t rc; 1129 1130 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS == 1131 (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH)); 1132 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS); 1133 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit); 1134 1135 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS)); 1136 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS)); 1137 1138 if (!ISP2(n) || (n < EFX_RXQ_MINNDESCS) || (n > EFX_RXQ_MAXNDESCS)) { 1139 rc = EINVAL; 1140 goto fail1; 1141 } 1142 if (index >= encp->enc_rxq_limit) { 1143 rc = EINVAL; 1144 goto fail2; 1145 } 1146 for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS); 1147 size++) 1148 if ((1 << size) == (int)(n / EFX_RXQ_MINNDESCS)) 1149 break; 1150 if (id + (1 << size) >= encp->enc_buftbl_limit) { 1151 rc = EINVAL; 1152 goto fail3; 1153 } 1154 1155 switch (type) { 1156 case EFX_RXQ_TYPE_DEFAULT: 1157 jumbo = B_FALSE; 1158 break; 1159 1160#if EFSYS_OPT_RX_SCATTER 1161 case EFX_RXQ_TYPE_SCATTER: 1162 if (enp->en_family < EFX_FAMILY_SIENA) { 1163 rc = EINVAL; 1164 goto fail4; 1165 } 1166 jumbo = B_TRUE; 1167 break; 1168#endif /* EFSYS_OPT_RX_SCATTER */ 1169 1170 default: 1171 rc = EINVAL; 1172 goto fail4; 1173 } 1174 1175 /* Set up the new descriptor queue */ 1176 EFX_POPULATE_OWORD_7(oword, 1177 FRF_AZ_RX_DESCQ_BUF_BASE_ID, id, 1178 FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index, 1179 FRF_AZ_RX_DESCQ_OWNER_ID, 0, 1180 FRF_AZ_RX_DESCQ_LABEL, label, 1181 FRF_AZ_RX_DESCQ_SIZE, size, 1182 FRF_AZ_RX_DESCQ_TYPE, 0, 1183 FRF_AZ_RX_DESCQ_JUMBO, jumbo); 1184 1185 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL, 1186 erp->er_index, &oword, B_TRUE); 1187 1188 return (0); 1189 1190fail4: 1191 EFSYS_PROBE(fail4); 1192fail3: 1193 EFSYS_PROBE(fail3); 1194fail2: 1195 EFSYS_PROBE(fail2); 1196fail1: 1197 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1198 1199 return (rc); 1200} 1201 1202static void 1203falconsiena_rx_qdestroy( 1204 __in efx_rxq_t *erp) 1205{ 1206 efx_nic_t *enp = erp->er_enp; 1207 efx_oword_t oword; 1208 1209 EFSYS_ASSERT(enp->en_rx_qcount != 0); 1210 --enp->en_rx_qcount; 1211 1212 /* Purge descriptor queue */ 1213 EFX_ZERO_OWORD(oword); 1214 1215 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL, 1216 erp->er_index, &oword, B_TRUE); 1217 1218 /* Free the RXQ object */ 1219 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp); 1220} 1221 1222static void 1223falconsiena_rx_fini( 1224 __in efx_nic_t *enp) 1225{ 1226 _NOTE(ARGUNUSED(enp)) 1227} 1228 1229#endif /* EFSYS_OPT_SIENA */ 1230