efx_regs.h revision 279183
1/*- 2 * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: head/sys/dev/sfxge/common/efx_regs.h 279183 2015-02-22 19:24:08Z arybchik $ 26 */ 27 28#ifndef _SYS_EFX_REGS_H 29#define _SYS_EFX_REGS_H 30 31 32#ifdef __cplusplus 33extern "C" { 34#endif 35 36 37/************************************************************************** 38 * 39 * Falcon/Siena registers and descriptors 40 * 41 ************************************************************************** 42 */ 43 44/* 45 * FR_AB_EE_VPD_CFG0_REG_SF(128bit): 46 * SPI/VPD configuration register 0 47 */ 48#define FR_AB_EE_VPD_CFG0_REG_SF_OFST 0x00000300 49/* falcona0,falconb0=eeprom_flash */ 50/* 51 * FR_AB_EE_VPD_CFG0_REG(128bit): 52 * SPI/VPD configuration register 0 53 */ 54#define FR_AB_EE_VPD_CFG0_REG_OFST 0x00000140 55/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 56 57#define FRF_AB_EE_SF_FASTRD_EN_LBN 127 58#define FRF_AB_EE_SF_FASTRD_EN_WIDTH 1 59#define FRF_AB_EE_SF_CLOCK_DIV_LBN 120 60#define FRF_AB_EE_SF_CLOCK_DIV_WIDTH 7 61#define FRF_AB_EE_VPD_WIP_POLL_LBN 119 62#define FRF_AB_EE_VPD_WIP_POLL_WIDTH 1 63#define FRF_AB_EE_EE_CLOCK_DIV_LBN 112 64#define FRF_AB_EE_EE_CLOCK_DIV_WIDTH 7 65#define FRF_AB_EE_EE_WR_TMR_VALUE_LBN 96 66#define FRF_AB_EE_EE_WR_TMR_VALUE_WIDTH 16 67#define FRF_AB_EE_VPDW_LENGTH_LBN 80 68#define FRF_AB_EE_VPDW_LENGTH_WIDTH 15 69#define FRF_AB_EE_VPDW_BASE_LBN 64 70#define FRF_AB_EE_VPDW_BASE_WIDTH 15 71#define FRF_AB_EE_VPD_WR_CMD_EN_LBN 56 72#define FRF_AB_EE_VPD_WR_CMD_EN_WIDTH 8 73#define FRF_AB_EE_VPD_BASE_LBN 32 74#define FRF_AB_EE_VPD_BASE_WIDTH 24 75#define FRF_AB_EE_VPD_LENGTH_LBN 16 76#define FRF_AB_EE_VPD_LENGTH_WIDTH 15 77#define FRF_AB_EE_VPD_AD_SIZE_LBN 8 78#define FRF_AB_EE_VPD_AD_SIZE_WIDTH 5 79#define FRF_AB_EE_VPD_ACCESS_ON_LBN 5 80#define FRF_AB_EE_VPD_ACCESS_ON_WIDTH 1 81#define FRF_AB_EE_VPD_ACCESS_BLOCK_LBN 4 82#define FRF_AB_EE_VPD_ACCESS_BLOCK_WIDTH 1 83#define FRF_AB_EE_VPD_DEV_SF_SEL_LBN 2 84#define FRF_AB_EE_VPD_DEV_SF_SEL_WIDTH 1 85#define FRF_AB_EE_VPD_EN_AD9_MODE_LBN 1 86#define FRF_AB_EE_VPD_EN_AD9_MODE_WIDTH 1 87#define FRF_AB_EE_VPD_EN_LBN 0 88#define FRF_AB_EE_VPD_EN_WIDTH 1 89 90 91/* 92 * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit): 93 * PCIE SerDes control register 0 to 3 94 */ 95#define FR_AB_PCIE_SD_CTL0123_REG_SF_OFST 0x00000320 96/* falcona0,falconb0=eeprom_flash */ 97/* 98 * FR_AB_PCIE_SD_CTL0123_REG(128bit): 99 * PCIE SerDes control register 0 to 3 100 */ 101#define FR_AB_PCIE_SD_CTL0123_REG_OFST 0x00000320 102/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 103 104#define FRF_AB_PCIE_TESTSIG_H_LBN 96 105#define FRF_AB_PCIE_TESTSIG_H_WIDTH 19 106#define FRF_AB_PCIE_TESTSIG_L_LBN 64 107#define FRF_AB_PCIE_TESTSIG_L_WIDTH 19 108#define FRF_AB_PCIE_OFFSET_LBN 56 109#define FRF_AB_PCIE_OFFSET_WIDTH 8 110#define FRF_AB_PCIE_OFFSETEN_H_LBN 55 111#define FRF_AB_PCIE_OFFSETEN_H_WIDTH 1 112#define FRF_AB_PCIE_OFFSETEN_L_LBN 54 113#define FRF_AB_PCIE_OFFSETEN_L_WIDTH 1 114#define FRF_AB_PCIE_HIVMODE_H_LBN 53 115#define FRF_AB_PCIE_HIVMODE_H_WIDTH 1 116#define FRF_AB_PCIE_HIVMODE_L_LBN 52 117#define FRF_AB_PCIE_HIVMODE_L_WIDTH 1 118#define FRF_AB_PCIE_PARRESET_H_LBN 51 119#define FRF_AB_PCIE_PARRESET_H_WIDTH 1 120#define FRF_AB_PCIE_PARRESET_L_LBN 50 121#define FRF_AB_PCIE_PARRESET_L_WIDTH 1 122#define FRF_AB_PCIE_LPBKWDRV_H_LBN 49 123#define FRF_AB_PCIE_LPBKWDRV_H_WIDTH 1 124#define FRF_AB_PCIE_LPBKWDRV_L_LBN 48 125#define FRF_AB_PCIE_LPBKWDRV_L_WIDTH 1 126#define FRF_AB_PCIE_LPBK_LBN 40 127#define FRF_AB_PCIE_LPBK_WIDTH 8 128#define FRF_AB_PCIE_PARLPBK_LBN 32 129#define FRF_AB_PCIE_PARLPBK_WIDTH 8 130#define FRF_AB_PCIE_RXTERMADJ_H_LBN 30 131#define FRF_AB_PCIE_RXTERMADJ_H_WIDTH 2 132#define FRF_AB_PCIE_RXTERMADJ_L_LBN 28 133#define FRF_AB_PCIE_RXTERMADJ_L_WIDTH 2 134#define FFE_AB_PCIE_RXTERMADJ_MIN15PCNT 3 135#define FFE_AB_PCIE_RXTERMADJ_PL10PCNT 2 136#define FFE_AB_PCIE_RXTERMADJ_MIN17PCNT 1 137#define FFE_AB_PCIE_RXTERMADJ_NOMNL 0 138#define FRF_AB_PCIE_TXTERMADJ_H_LBN 26 139#define FRF_AB_PCIE_TXTERMADJ_H_WIDTH 2 140#define FRF_AB_PCIE_TXTERMADJ_L_LBN 24 141#define FRF_AB_PCIE_TXTERMADJ_L_WIDTH 2 142#define FFE_AB_PCIE_TXTERMADJ_MIN15PCNT 3 143#define FFE_AB_PCIE_TXTERMADJ_PL10PCNT 2 144#define FFE_AB_PCIE_TXTERMADJ_MIN17PCNT 1 145#define FFE_AB_PCIE_TXTERMADJ_NOMNL 0 146#define FRF_AB_PCIE_RXEQCTL_H_LBN 18 147#define FRF_AB_PCIE_RXEQCTL_H_WIDTH 2 148#define FRF_AB_PCIE_RXEQCTL_L_LBN 16 149#define FRF_AB_PCIE_RXEQCTL_L_WIDTH 2 150#define FFE_AB_PCIE_RXEQCTL_OFF_ALT 3 151#define FFE_AB_PCIE_RXEQCTL_OFF 2 152#define FFE_AB_PCIE_RXEQCTL_MIN 1 153#define FFE_AB_PCIE_RXEQCTL_MAX 0 154#define FRF_AB_PCIE_HIDRV_LBN 8 155#define FRF_AB_PCIE_HIDRV_WIDTH 8 156#define FRF_AB_PCIE_LODRV_LBN 0 157#define FRF_AB_PCIE_LODRV_WIDTH 8 158 159 160/* 161 * FR_AB_PCIE_SD_CTL45_REG_SF(128bit): 162 * PCIE SerDes control register 4 and 5 163 */ 164#define FR_AB_PCIE_SD_CTL45_REG_SF_OFST 0x00000330 165/* falcona0,falconb0=eeprom_flash */ 166/* 167 * FR_AB_PCIE_SD_CTL45_REG(128bit): 168 * PCIE SerDes control register 4 and 5 169 */ 170#define FR_AB_PCIE_SD_CTL45_REG_OFST 0x00000330 171/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 172 173#define FRF_AB_PCIE_DTX7_LBN 60 174#define FRF_AB_PCIE_DTX7_WIDTH 4 175#define FRF_AB_PCIE_DTX6_LBN 56 176#define FRF_AB_PCIE_DTX6_WIDTH 4 177#define FRF_AB_PCIE_DTX5_LBN 52 178#define FRF_AB_PCIE_DTX5_WIDTH 4 179#define FRF_AB_PCIE_DTX4_LBN 48 180#define FRF_AB_PCIE_DTX4_WIDTH 4 181#define FRF_AB_PCIE_DTX3_LBN 44 182#define FRF_AB_PCIE_DTX3_WIDTH 4 183#define FRF_AB_PCIE_DTX2_LBN 40 184#define FRF_AB_PCIE_DTX2_WIDTH 4 185#define FRF_AB_PCIE_DTX1_LBN 36 186#define FRF_AB_PCIE_DTX1_WIDTH 4 187#define FRF_AB_PCIE_DTX0_LBN 32 188#define FRF_AB_PCIE_DTX0_WIDTH 4 189#define FRF_AB_PCIE_DEQ7_LBN 28 190#define FRF_AB_PCIE_DEQ7_WIDTH 4 191#define FRF_AB_PCIE_DEQ6_LBN 24 192#define FRF_AB_PCIE_DEQ6_WIDTH 4 193#define FRF_AB_PCIE_DEQ5_LBN 20 194#define FRF_AB_PCIE_DEQ5_WIDTH 4 195#define FRF_AB_PCIE_DEQ4_LBN 16 196#define FRF_AB_PCIE_DEQ4_WIDTH 4 197#define FRF_AB_PCIE_DEQ3_LBN 12 198#define FRF_AB_PCIE_DEQ3_WIDTH 4 199#define FRF_AB_PCIE_DEQ2_LBN 8 200#define FRF_AB_PCIE_DEQ2_WIDTH 4 201#define FRF_AB_PCIE_DEQ1_LBN 4 202#define FRF_AB_PCIE_DEQ1_WIDTH 4 203#define FRF_AB_PCIE_DEQ0_LBN 0 204#define FRF_AB_PCIE_DEQ0_WIDTH 4 205 206 207/* 208 * FR_AB_PCIE_PCS_CTL_STAT_REG_SF(128bit): 209 * PCIE PCS control and status register 210 */ 211#define FR_AB_PCIE_PCS_CTL_STAT_REG_SF_OFST 0x00000340 212/* falcona0,falconb0=eeprom_flash */ 213/* 214 * FR_AB_PCIE_PCS_CTL_STAT_REG(128bit): 215 * PCIE PCS control and status register 216 */ 217#define FR_AB_PCIE_PCS_CTL_STAT_REG_OFST 0x00000340 218/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 219 220#define FRF_AB_PCIE_PRBSERRCOUNT0_H_LBN 52 221#define FRF_AB_PCIE_PRBSERRCOUNT0_H_WIDTH 4 222#define FRF_AB_PCIE_PRBSERRCOUNT0_L_LBN 48 223#define FRF_AB_PCIE_PRBSERRCOUNT0_L_WIDTH 4 224#define FRF_AB_PCIE_PRBSERR_LBN 40 225#define FRF_AB_PCIE_PRBSERR_WIDTH 8 226#define FRF_AB_PCIE_PRBSERRH0_LBN 32 227#define FRF_AB_PCIE_PRBSERRH0_WIDTH 8 228#define FRF_AB_PCIE_FASTINIT_H_LBN 15 229#define FRF_AB_PCIE_FASTINIT_H_WIDTH 1 230#define FRF_AB_PCIE_FASTINIT_L_LBN 14 231#define FRF_AB_PCIE_FASTINIT_L_WIDTH 1 232#define FRF_AB_PCIE_CTCDISABLE_H_LBN 13 233#define FRF_AB_PCIE_CTCDISABLE_H_WIDTH 1 234#define FRF_AB_PCIE_CTCDISABLE_L_LBN 12 235#define FRF_AB_PCIE_CTCDISABLE_L_WIDTH 1 236#define FRF_AB_PCIE_PRBSSYNC_H_LBN 11 237#define FRF_AB_PCIE_PRBSSYNC_H_WIDTH 1 238#define FRF_AB_PCIE_PRBSSYNC_L_LBN 10 239#define FRF_AB_PCIE_PRBSSYNC_L_WIDTH 1 240#define FRF_AB_PCIE_PRBSERRACK_H_LBN 9 241#define FRF_AB_PCIE_PRBSERRACK_H_WIDTH 1 242#define FRF_AB_PCIE_PRBSERRACK_L_LBN 8 243#define FRF_AB_PCIE_PRBSERRACK_L_WIDTH 1 244#define FRF_AB_PCIE_PRBSSEL_LBN 0 245#define FRF_AB_PCIE_PRBSSEL_WIDTH 8 246 247 248/* 249 * FR_AB_HW_INIT_REG_SF(128bit): 250 * Hardware initialization register 251 */ 252#define FR_AB_HW_INIT_REG_SF_OFST 0x00000350 253/* falcona0,falconb0=eeprom_flash */ 254/* 255 * FR_AZ_HW_INIT_REG(128bit): 256 * Hardware initialization register 257 */ 258#define FR_AZ_HW_INIT_REG_OFST 0x000000c0 259/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 260 261#define FRF_BB_BDMRD_CPLF_FULL_LBN 124 262#define FRF_BB_BDMRD_CPLF_FULL_WIDTH 1 263#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_LBN 121 264#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_WIDTH 3 265#define FRF_CZ_TX_MRG_TAGS_LBN 120 266#define FRF_CZ_TX_MRG_TAGS_WIDTH 1 267#define FRF_AZ_TRGT_MASK_ALL_LBN 100 268#define FRF_AZ_TRGT_MASK_ALL_WIDTH 1 269#define FRF_AZ_DOORBELL_DROP_LBN 92 270#define FRF_AZ_DOORBELL_DROP_WIDTH 8 271#define FRF_AB_TX_RREQ_MASK_EN_LBN 76 272#define FRF_AB_TX_RREQ_MASK_EN_WIDTH 1 273#define FRF_AB_PE_EIDLE_DIS_LBN 75 274#define FRF_AB_PE_EIDLE_DIS_WIDTH 1 275#define FRF_AZ_FC_BLOCKING_EN_LBN 45 276#define FRF_AZ_FC_BLOCKING_EN_WIDTH 1 277#define FRF_AZ_B2B_REQ_EN_LBN 44 278#define FRF_AZ_B2B_REQ_EN_WIDTH 1 279#define FRF_AZ_POST_WR_MASK_LBN 40 280#define FRF_AZ_POST_WR_MASK_WIDTH 4 281#define FRF_AZ_TLP_TC_LBN 34 282#define FRF_AZ_TLP_TC_WIDTH 3 283#define FRF_AZ_TLP_ATTR_LBN 32 284#define FRF_AZ_TLP_ATTR_WIDTH 2 285#define FRF_AB_INTB_VEC_LBN 24 286#define FRF_AB_INTB_VEC_WIDTH 5 287#define FRF_AB_INTA_VEC_LBN 16 288#define FRF_AB_INTA_VEC_WIDTH 5 289#define FRF_AZ_WD_TIMER_LBN 8 290#define FRF_AZ_WD_TIMER_WIDTH 8 291#define FRF_AZ_US_DISABLE_LBN 5 292#define FRF_AZ_US_DISABLE_WIDTH 1 293#define FRF_AZ_TLP_EP_LBN 4 294#define FRF_AZ_TLP_EP_WIDTH 1 295#define FRF_AZ_ATTR_SEL_LBN 3 296#define FRF_AZ_ATTR_SEL_WIDTH 1 297#define FRF_AZ_TD_SEL_LBN 1 298#define FRF_AZ_TD_SEL_WIDTH 1 299#define FRF_AZ_TLP_TD_LBN 0 300#define FRF_AZ_TLP_TD_WIDTH 1 301 302 303/* 304 * FR_AB_NIC_STAT_REG_SF(128bit): 305 * NIC status register 306 */ 307#define FR_AB_NIC_STAT_REG_SF_OFST 0x00000360 308/* falcona0,falconb0=eeprom_flash */ 309/* 310 * FR_AB_NIC_STAT_REG(128bit): 311 * NIC status register 312 */ 313#define FR_AB_NIC_STAT_REG_OFST 0x00000200 314/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 315 316#define FRF_BB_AER_DIS_LBN 34 317#define FRF_BB_AER_DIS_WIDTH 1 318#define FRF_BB_EE_STRAP_EN_LBN 31 319#define FRF_BB_EE_STRAP_EN_WIDTH 1 320#define FRF_BB_EE_STRAP_LBN 24 321#define FRF_BB_EE_STRAP_WIDTH 4 322#define FRF_BB_REVISION_ID_LBN 17 323#define FRF_BB_REVISION_ID_WIDTH 7 324#define FRF_AB_ONCHIP_SRAM_LBN 16 325#define FRF_AB_ONCHIP_SRAM_WIDTH 1 326#define FRF_AB_SF_PRST_LBN 9 327#define FRF_AB_SF_PRST_WIDTH 1 328#define FRF_AB_EE_PRST_LBN 8 329#define FRF_AB_EE_PRST_WIDTH 1 330#define FRF_AB_ATE_MODE_LBN 3 331#define FRF_AB_ATE_MODE_WIDTH 1 332#define FRF_AB_STRAP_PINS_LBN 0 333#define FRF_AB_STRAP_PINS_WIDTH 3 334 335 336/* 337 * FR_AB_GLB_CTL_REG_SF(128bit): 338 * Global control register 339 */ 340#define FR_AB_GLB_CTL_REG_SF_OFST 0x00000370 341/* falcona0,falconb0=eeprom_flash */ 342/* 343 * FR_AB_GLB_CTL_REG(128bit): 344 * Global control register 345 */ 346#define FR_AB_GLB_CTL_REG_OFST 0x00000220 347/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 348 349#define FRF_AB_EXT_PHY_RST_CTL_LBN 63 350#define FRF_AB_EXT_PHY_RST_CTL_WIDTH 1 351#define FRF_AB_XAUI_SD_RST_CTL_LBN 62 352#define FRF_AB_XAUI_SD_RST_CTL_WIDTH 1 353#define FRF_AB_PCIE_SD_RST_CTL_LBN 61 354#define FRF_AB_PCIE_SD_RST_CTL_WIDTH 1 355#define FRF_AA_PCIX_RST_CTL_LBN 60 356#define FRF_AA_PCIX_RST_CTL_WIDTH 1 357#define FRF_BB_BIU_RST_CTL_LBN 60 358#define FRF_BB_BIU_RST_CTL_WIDTH 1 359#define FRF_AB_PCIE_STKY_RST_CTL_LBN 59 360#define FRF_AB_PCIE_STKY_RST_CTL_WIDTH 1 361#define FRF_AB_PCIE_NSTKY_RST_CTL_LBN 58 362#define FRF_AB_PCIE_NSTKY_RST_CTL_WIDTH 1 363#define FRF_AB_PCIE_CORE_RST_CTL_LBN 57 364#define FRF_AB_PCIE_CORE_RST_CTL_WIDTH 1 365#define FRF_AB_XGRX_RST_CTL_LBN 56 366#define FRF_AB_XGRX_RST_CTL_WIDTH 1 367#define FRF_AB_XGTX_RST_CTL_LBN 55 368#define FRF_AB_XGTX_RST_CTL_WIDTH 1 369#define FRF_AB_EM_RST_CTL_LBN 54 370#define FRF_AB_EM_RST_CTL_WIDTH 1 371#define FRF_AB_EV_RST_CTL_LBN 53 372#define FRF_AB_EV_RST_CTL_WIDTH 1 373#define FRF_AB_SR_RST_CTL_LBN 52 374#define FRF_AB_SR_RST_CTL_WIDTH 1 375#define FRF_AB_RX_RST_CTL_LBN 51 376#define FRF_AB_RX_RST_CTL_WIDTH 1 377#define FRF_AB_TX_RST_CTL_LBN 50 378#define FRF_AB_TX_RST_CTL_WIDTH 1 379#define FRF_AB_EE_RST_CTL_LBN 49 380#define FRF_AB_EE_RST_CTL_WIDTH 1 381#define FRF_AB_CS_RST_CTL_LBN 48 382#define FRF_AB_CS_RST_CTL_WIDTH 1 383#define FRF_AB_HOT_RST_CTL_LBN 40 384#define FRF_AB_HOT_RST_CTL_WIDTH 2 385#define FRF_AB_RST_EXT_PHY_LBN 31 386#define FRF_AB_RST_EXT_PHY_WIDTH 1 387#define FRF_AB_RST_XAUI_SD_LBN 30 388#define FRF_AB_RST_XAUI_SD_WIDTH 1 389#define FRF_AB_RST_PCIE_SD_LBN 29 390#define FRF_AB_RST_PCIE_SD_WIDTH 1 391#define FRF_AA_RST_PCIX_LBN 28 392#define FRF_AA_RST_PCIX_WIDTH 1 393#define FRF_BB_RST_BIU_LBN 28 394#define FRF_BB_RST_BIU_WIDTH 1 395#define FRF_AB_RST_PCIE_STKY_LBN 27 396#define FRF_AB_RST_PCIE_STKY_WIDTH 1 397#define FRF_AB_RST_PCIE_NSTKY_LBN 26 398#define FRF_AB_RST_PCIE_NSTKY_WIDTH 1 399#define FRF_AB_RST_PCIE_CORE_LBN 25 400#define FRF_AB_RST_PCIE_CORE_WIDTH 1 401#define FRF_AB_RST_XGRX_LBN 24 402#define FRF_AB_RST_XGRX_WIDTH 1 403#define FRF_AB_RST_XGTX_LBN 23 404#define FRF_AB_RST_XGTX_WIDTH 1 405#define FRF_AB_RST_EM_LBN 22 406#define FRF_AB_RST_EM_WIDTH 1 407#define FRF_AB_RST_EV_LBN 21 408#define FRF_AB_RST_EV_WIDTH 1 409#define FRF_AB_RST_SR_LBN 20 410#define FRF_AB_RST_SR_WIDTH 1 411#define FRF_AB_RST_RX_LBN 19 412#define FRF_AB_RST_RX_WIDTH 1 413#define FRF_AB_RST_TX_LBN 18 414#define FRF_AB_RST_TX_WIDTH 1 415#define FRF_AB_RST_SF_LBN 17 416#define FRF_AB_RST_SF_WIDTH 1 417#define FRF_AB_RST_CS_LBN 16 418#define FRF_AB_RST_CS_WIDTH 1 419#define FRF_AB_INT_RST_DUR_LBN 4 420#define FRF_AB_INT_RST_DUR_WIDTH 3 421#define FRF_AB_EXT_PHY_RST_DUR_LBN 1 422#define FRF_AB_EXT_PHY_RST_DUR_WIDTH 3 423#define FFE_AB_EXT_PHY_RST_DUR_10240US 7 424#define FFE_AB_EXT_PHY_RST_DUR_5120US 6 425#define FFE_AB_EXT_PHY_RST_DUR_2560US 5 426#define FFE_AB_EXT_PHY_RST_DUR_1280US 4 427#define FFE_AB_EXT_PHY_RST_DUR_640US 3 428#define FFE_AB_EXT_PHY_RST_DUR_320US 2 429#define FFE_AB_EXT_PHY_RST_DUR_160US 1 430#define FFE_AB_EXT_PHY_RST_DUR_80US 0 431#define FRF_AB_SWRST_LBN 0 432#define FRF_AB_SWRST_WIDTH 1 433 434 435/* 436 * FR_AZ_IOM_IND_ADR_REG(32bit): 437 * IO-mapped indirect access address register 438 */ 439#define FR_AZ_IOM_IND_ADR_REG_OFST 0x00000000 440/* falcona0,falconb0,sienaa0=net_func_bar0 */ 441 442#define FRF_AZ_IOM_AUTO_ADR_INC_EN_LBN 24 443#define FRF_AZ_IOM_AUTO_ADR_INC_EN_WIDTH 1 444#define FRF_AZ_IOM_IND_ADR_LBN 0 445#define FRF_AZ_IOM_IND_ADR_WIDTH 24 446 447 448/* 449 * FR_AZ_IOM_IND_DAT_REG(32bit): 450 * IO-mapped indirect access data register 451 */ 452#define FR_AZ_IOM_IND_DAT_REG_OFST 0x00000004 453/* falcona0,falconb0,sienaa0=net_func_bar0 */ 454 455#define FRF_AZ_IOM_IND_DAT_LBN 0 456#define FRF_AZ_IOM_IND_DAT_WIDTH 32 457 458 459/* 460 * FR_AZ_ADR_REGION_REG(128bit): 461 * Address region register 462 */ 463#define FR_AZ_ADR_REGION_REG_OFST 0x00000000 464/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 465 466#define FRF_AZ_ADR_REGION3_LBN 96 467#define FRF_AZ_ADR_REGION3_WIDTH 18 468#define FRF_AZ_ADR_REGION2_LBN 64 469#define FRF_AZ_ADR_REGION2_WIDTH 18 470#define FRF_AZ_ADR_REGION1_LBN 32 471#define FRF_AZ_ADR_REGION1_WIDTH 18 472#define FRF_AZ_ADR_REGION0_LBN 0 473#define FRF_AZ_ADR_REGION0_WIDTH 18 474 475 476/* 477 * FR_AZ_INT_EN_REG_KER(128bit): 478 * Kernel driver Interrupt enable register 479 */ 480#define FR_AZ_INT_EN_REG_KER_OFST 0x00000010 481/* falcona0,falconb0,sienaa0=net_func_bar2 */ 482 483#define FRF_AZ_KER_INT_LEVE_SEL_LBN 8 484#define FRF_AZ_KER_INT_LEVE_SEL_WIDTH 6 485#define FRF_AZ_KER_INT_CHAR_LBN 4 486#define FRF_AZ_KER_INT_CHAR_WIDTH 1 487#define FRF_AZ_KER_INT_KER_LBN 3 488#define FRF_AZ_KER_INT_KER_WIDTH 1 489#define FRF_AZ_DRV_INT_EN_KER_LBN 0 490#define FRF_AZ_DRV_INT_EN_KER_WIDTH 1 491 492 493/* 494 * FR_AZ_INT_EN_REG_CHAR(128bit): 495 * Char Driver interrupt enable register 496 */ 497#define FR_AZ_INT_EN_REG_CHAR_OFST 0x00000020 498/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 499 500#define FRF_AZ_CHAR_INT_LEVE_SEL_LBN 8 501#define FRF_AZ_CHAR_INT_LEVE_SEL_WIDTH 6 502#define FRF_AZ_CHAR_INT_CHAR_LBN 4 503#define FRF_AZ_CHAR_INT_CHAR_WIDTH 1 504#define FRF_AZ_CHAR_INT_KER_LBN 3 505#define FRF_AZ_CHAR_INT_KER_WIDTH 1 506#define FRF_AZ_DRV_INT_EN_CHAR_LBN 0 507#define FRF_AZ_DRV_INT_EN_CHAR_WIDTH 1 508 509 510/* 511 * FR_AZ_INT_ADR_REG_KER(128bit): 512 * Interrupt host address for Kernel driver 513 */ 514#define FR_AZ_INT_ADR_REG_KER_OFST 0x00000030 515/* falcona0,falconb0,sienaa0=net_func_bar2 */ 516 517#define FRF_AZ_NORM_INT_VEC_DIS_KER_LBN 64 518#define FRF_AZ_NORM_INT_VEC_DIS_KER_WIDTH 1 519#define FRF_AZ_INT_ADR_KER_LBN 0 520#define FRF_AZ_INT_ADR_KER_WIDTH 64 521#define FRF_AZ_INT_ADR_KER_DW0_LBN 0 522#define FRF_AZ_INT_ADR_KER_DW0_WIDTH 32 523#define FRF_AZ_INT_ADR_KER_DW1_LBN 32 524#define FRF_AZ_INT_ADR_KER_DW1_WIDTH 32 525 526 527/* 528 * FR_AZ_INT_ADR_REG_CHAR(128bit): 529 * Interrupt host address for Char driver 530 */ 531#define FR_AZ_INT_ADR_REG_CHAR_OFST 0x00000040 532/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 533 534#define FRF_AZ_NORM_INT_VEC_DIS_CHAR_LBN 64 535#define FRF_AZ_NORM_INT_VEC_DIS_CHAR_WIDTH 1 536#define FRF_AZ_INT_ADR_CHAR_LBN 0 537#define FRF_AZ_INT_ADR_CHAR_WIDTH 64 538#define FRF_AZ_INT_ADR_CHAR_DW0_LBN 0 539#define FRF_AZ_INT_ADR_CHAR_DW0_WIDTH 32 540#define FRF_AZ_INT_ADR_CHAR_DW1_LBN 32 541#define FRF_AZ_INT_ADR_CHAR_DW1_WIDTH 32 542 543 544/* 545 * FR_AA_INT_ACK_KER(32bit): 546 * Kernel interrupt acknowledge register 547 */ 548#define FR_AA_INT_ACK_KER_OFST 0x00000050 549/* falcona0=net_func_bar2 */ 550 551#define FRF_AA_INT_ACK_KER_FIELD_LBN 0 552#define FRF_AA_INT_ACK_KER_FIELD_WIDTH 32 553 554 555/* 556 * FR_BZ_INT_ISR0_REG(128bit): 557 * Function 0 Interrupt Acknowlege Status register 558 */ 559#define FR_BZ_INT_ISR0_REG_OFST 0x00000090 560/* falconb0,sienaa0=net_func_bar2 */ 561 562#define FRF_BZ_INT_ISR_REG_LBN 0 563#define FRF_BZ_INT_ISR_REG_WIDTH 64 564#define FRF_BZ_INT_ISR_REG_DW0_LBN 0 565#define FRF_BZ_INT_ISR_REG_DW0_WIDTH 32 566#define FRF_BZ_INT_ISR_REG_DW1_LBN 32 567#define FRF_BZ_INT_ISR_REG_DW1_WIDTH 32 568 569 570/* 571 * FR_AB_EE_SPI_HCMD_REG(128bit): 572 * SPI host command register 573 */ 574#define FR_AB_EE_SPI_HCMD_REG_OFST 0x00000100 575/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 576 577#define FRF_AB_EE_SPI_HCMD_CMD_EN_LBN 31 578#define FRF_AB_EE_SPI_HCMD_CMD_EN_WIDTH 1 579#define FRF_AB_EE_WR_TIMER_ACTIVE_LBN 28 580#define FRF_AB_EE_WR_TIMER_ACTIVE_WIDTH 1 581#define FRF_AB_EE_SPI_HCMD_SF_SEL_LBN 24 582#define FRF_AB_EE_SPI_HCMD_SF_SEL_WIDTH 1 583#define FRF_AB_EE_SPI_HCMD_DABCNT_LBN 16 584#define FRF_AB_EE_SPI_HCMD_DABCNT_WIDTH 5 585#define FRF_AB_EE_SPI_HCMD_READ_LBN 15 586#define FRF_AB_EE_SPI_HCMD_READ_WIDTH 1 587#define FRF_AB_EE_SPI_HCMD_DUBCNT_LBN 12 588#define FRF_AB_EE_SPI_HCMD_DUBCNT_WIDTH 2 589#define FRF_AB_EE_SPI_HCMD_ADBCNT_LBN 8 590#define FRF_AB_EE_SPI_HCMD_ADBCNT_WIDTH 2 591#define FRF_AB_EE_SPI_HCMD_ENC_LBN 0 592#define FRF_AB_EE_SPI_HCMD_ENC_WIDTH 8 593 594 595/* 596 * FR_CZ_USR_EV_CFG(32bit): 597 * User Level Event Configuration register 598 */ 599#define FR_CZ_USR_EV_CFG_OFST 0x00000100 600/* sienaa0=net_func_bar2 */ 601 602#define FRF_CZ_USREV_DIS_LBN 16 603#define FRF_CZ_USREV_DIS_WIDTH 1 604#define FRF_CZ_DFLT_EVQ_LBN 0 605#define FRF_CZ_DFLT_EVQ_WIDTH 10 606 607 608/* 609 * FR_AB_EE_SPI_HADR_REG(128bit): 610 * SPI host address register 611 */ 612#define FR_AB_EE_SPI_HADR_REG_OFST 0x00000110 613/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 614 615#define FRF_AB_EE_SPI_HADR_DUBYTE_LBN 24 616#define FRF_AB_EE_SPI_HADR_DUBYTE_WIDTH 8 617#define FRF_AB_EE_SPI_HADR_ADR_LBN 0 618#define FRF_AB_EE_SPI_HADR_ADR_WIDTH 24 619 620 621/* 622 * FR_AB_EE_SPI_HDATA_REG(128bit): 623 * SPI host data register 624 */ 625#define FR_AB_EE_SPI_HDATA_REG_OFST 0x00000120 626/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 627 628#define FRF_AB_EE_SPI_HDATA3_LBN 96 629#define FRF_AB_EE_SPI_HDATA3_WIDTH 32 630#define FRF_AB_EE_SPI_HDATA2_LBN 64 631#define FRF_AB_EE_SPI_HDATA2_WIDTH 32 632#define FRF_AB_EE_SPI_HDATA1_LBN 32 633#define FRF_AB_EE_SPI_HDATA1_WIDTH 32 634#define FRF_AB_EE_SPI_HDATA0_LBN 0 635#define FRF_AB_EE_SPI_HDATA0_WIDTH 32 636 637 638/* 639 * FR_AB_EE_BASE_PAGE_REG(128bit): 640 * Expansion ROM base mirror register 641 */ 642#define FR_AB_EE_BASE_PAGE_REG_OFST 0x00000130 643/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 644 645#define FRF_AB_EE_EXPROM_MASK_LBN 16 646#define FRF_AB_EE_EXPROM_MASK_WIDTH 13 647#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_LBN 0 648#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_WIDTH 13 649 650 651/* 652 * FR_AB_EE_VPD_SW_CNTL_REG(128bit): 653 * VPD access SW control register 654 */ 655#define FR_AB_EE_VPD_SW_CNTL_REG_OFST 0x00000150 656/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 657 658#define FRF_AB_EE_VPD_CYCLE_PENDING_LBN 31 659#define FRF_AB_EE_VPD_CYCLE_PENDING_WIDTH 1 660#define FRF_AB_EE_VPD_CYC_WRITE_LBN 28 661#define FRF_AB_EE_VPD_CYC_WRITE_WIDTH 1 662#define FRF_AB_EE_VPD_CYC_ADR_LBN 0 663#define FRF_AB_EE_VPD_CYC_ADR_WIDTH 15 664 665 666/* 667 * FR_AB_EE_VPD_SW_DATA_REG(128bit): 668 * VPD access SW data register 669 */ 670#define FR_AB_EE_VPD_SW_DATA_REG_OFST 0x00000160 671/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 672 673#define FRF_AB_EE_VPD_CYC_DAT_LBN 0 674#define FRF_AB_EE_VPD_CYC_DAT_WIDTH 32 675 676 677/* 678 * FR_BB_PCIE_CORE_INDIRECT_REG(64bit): 679 * Indirect Access to PCIE Core registers 680 */ 681#define FR_BB_PCIE_CORE_INDIRECT_REG_OFST 0x000001f0 682/* falconb0=net_func_bar2 */ 683 684#define FRF_BB_PCIE_CORE_TARGET_DATA_LBN 32 685#define FRF_BB_PCIE_CORE_TARGET_DATA_WIDTH 32 686#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_LBN 15 687#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_WIDTH 1 688#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_LBN 0 689#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_WIDTH 12 690 691 692/* 693 * FR_AB_GPIO_CTL_REG(128bit): 694 * GPIO control register 695 */ 696#define FR_AB_GPIO_CTL_REG_OFST 0x00000210 697/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 698 699#define FRF_AB_GPIO15_OEN_LBN 63 700#define FRF_AB_GPIO15_OEN_WIDTH 1 701#define FRF_AB_GPIO14_OEN_LBN 62 702#define FRF_AB_GPIO14_OEN_WIDTH 1 703#define FRF_AB_GPIO13_OEN_LBN 61 704#define FRF_AB_GPIO13_OEN_WIDTH 1 705#define FRF_AB_GPIO12_OEN_LBN 60 706#define FRF_AB_GPIO12_OEN_WIDTH 1 707#define FRF_AB_GPIO11_OEN_LBN 59 708#define FRF_AB_GPIO11_OEN_WIDTH 1 709#define FRF_AB_GPIO10_OEN_LBN 58 710#define FRF_AB_GPIO10_OEN_WIDTH 1 711#define FRF_AB_GPIO9_OEN_LBN 57 712#define FRF_AB_GPIO9_OEN_WIDTH 1 713#define FRF_AB_GPIO8_OEN_LBN 56 714#define FRF_AB_GPIO8_OEN_WIDTH 1 715#define FRF_AB_GPIO15_OUT_LBN 55 716#define FRF_AB_GPIO15_OUT_WIDTH 1 717#define FRF_AB_GPIO14_OUT_LBN 54 718#define FRF_AB_GPIO14_OUT_WIDTH 1 719#define FRF_AB_GPIO13_OUT_LBN 53 720#define FRF_AB_GPIO13_OUT_WIDTH 1 721#define FRF_AB_GPIO12_OUT_LBN 52 722#define FRF_AB_GPIO12_OUT_WIDTH 1 723#define FRF_AB_GPIO11_OUT_LBN 51 724#define FRF_AB_GPIO11_OUT_WIDTH 1 725#define FRF_AB_GPIO10_OUT_LBN 50 726#define FRF_AB_GPIO10_OUT_WIDTH 1 727#define FRF_AB_GPIO9_OUT_LBN 49 728#define FRF_AB_GPIO9_OUT_WIDTH 1 729#define FRF_AB_GPIO8_OUT_LBN 48 730#define FRF_AB_GPIO8_OUT_WIDTH 1 731#define FRF_AB_GPIO15_IN_LBN 47 732#define FRF_AB_GPIO15_IN_WIDTH 1 733#define FRF_AB_GPIO14_IN_LBN 46 734#define FRF_AB_GPIO14_IN_WIDTH 1 735#define FRF_AB_GPIO13_IN_LBN 45 736#define FRF_AB_GPIO13_IN_WIDTH 1 737#define FRF_AB_GPIO12_IN_LBN 44 738#define FRF_AB_GPIO12_IN_WIDTH 1 739#define FRF_AB_GPIO11_IN_LBN 43 740#define FRF_AB_GPIO11_IN_WIDTH 1 741#define FRF_AB_GPIO10_IN_LBN 42 742#define FRF_AB_GPIO10_IN_WIDTH 1 743#define FRF_AB_GPIO9_IN_LBN 41 744#define FRF_AB_GPIO9_IN_WIDTH 1 745#define FRF_AB_GPIO8_IN_LBN 40 746#define FRF_AB_GPIO8_IN_WIDTH 1 747#define FRF_AB_GPIO15_PWRUP_VALUE_LBN 39 748#define FRF_AB_GPIO15_PWRUP_VALUE_WIDTH 1 749#define FRF_AB_GPIO14_PWRUP_VALUE_LBN 38 750#define FRF_AB_GPIO14_PWRUP_VALUE_WIDTH 1 751#define FRF_AB_GPIO13_PWRUP_VALUE_LBN 37 752#define FRF_AB_GPIO13_PWRUP_VALUE_WIDTH 1 753#define FRF_AB_GPIO12_PWRUP_VALUE_LBN 36 754#define FRF_AB_GPIO12_PWRUP_VALUE_WIDTH 1 755#define FRF_AB_GPIO11_PWRUP_VALUE_LBN 35 756#define FRF_AB_GPIO11_PWRUP_VALUE_WIDTH 1 757#define FRF_AB_GPIO10_PWRUP_VALUE_LBN 34 758#define FRF_AB_GPIO10_PWRUP_VALUE_WIDTH 1 759#define FRF_AB_GPIO9_PWRUP_VALUE_LBN 33 760#define FRF_AB_GPIO9_PWRUP_VALUE_WIDTH 1 761#define FRF_AB_GPIO8_PWRUP_VALUE_LBN 32 762#define FRF_AB_GPIO8_PWRUP_VALUE_WIDTH 1 763#define FRF_BB_CLK156_OUT_EN_LBN 31 764#define FRF_BB_CLK156_OUT_EN_WIDTH 1 765#define FRF_BB_USE_NIC_CLK_LBN 30 766#define FRF_BB_USE_NIC_CLK_WIDTH 1 767#define FRF_AB_GPIO5_OEN_LBN 29 768#define FRF_AB_GPIO5_OEN_WIDTH 1 769#define FRF_AB_GPIO4_OEN_LBN 28 770#define FRF_AB_GPIO4_OEN_WIDTH 1 771#define FRF_AB_GPIO3_OEN_LBN 27 772#define FRF_AB_GPIO3_OEN_WIDTH 1 773#define FRF_AB_GPIO2_OEN_LBN 26 774#define FRF_AB_GPIO2_OEN_WIDTH 1 775#define FRF_AB_GPIO1_OEN_LBN 25 776#define FRF_AB_GPIO1_OEN_WIDTH 1 777#define FRF_AB_GPIO0_OEN_LBN 24 778#define FRF_AB_GPIO0_OEN_WIDTH 1 779#define FRF_AB_GPIO5_OUT_LBN 21 780#define FRF_AB_GPIO5_OUT_WIDTH 1 781#define FRF_AB_GPIO4_OUT_LBN 20 782#define FRF_AB_GPIO4_OUT_WIDTH 1 783#define FRF_AB_GPIO3_OUT_LBN 19 784#define FRF_AB_GPIO3_OUT_WIDTH 1 785#define FRF_AB_GPIO2_OUT_LBN 18 786#define FRF_AB_GPIO2_OUT_WIDTH 1 787#define FRF_AB_GPIO1_OUT_LBN 17 788#define FRF_AB_GPIO1_OUT_WIDTH 1 789#define FRF_AB_GPIO0_OUT_LBN 16 790#define FRF_AB_GPIO0_OUT_WIDTH 1 791#define FRF_AB_GPIO5_IN_LBN 13 792#define FRF_AB_GPIO5_IN_WIDTH 1 793#define FRF_AB_GPIO4_IN_LBN 12 794#define FRF_AB_GPIO4_IN_WIDTH 1 795#define FRF_AB_GPIO3_IN_LBN 11 796#define FRF_AB_GPIO3_IN_WIDTH 1 797#define FRF_AB_GPIO2_IN_LBN 10 798#define FRF_AB_GPIO2_IN_WIDTH 1 799#define FRF_AB_GPIO1_IN_LBN 9 800#define FRF_AB_GPIO1_IN_WIDTH 1 801#define FRF_AB_GPIO0_IN_LBN 8 802#define FRF_AB_GPIO0_IN_WIDTH 1 803#define FRF_AB_GPIO5_PWRUP_VALUE_LBN 5 804#define FRF_AB_GPIO5_PWRUP_VALUE_WIDTH 1 805#define FRF_AB_GPIO4_PWRUP_VALUE_LBN 4 806#define FRF_AB_GPIO4_PWRUP_VALUE_WIDTH 1 807#define FRF_AB_GPIO3_PWRUP_VALUE_LBN 3 808#define FRF_AB_GPIO3_PWRUP_VALUE_WIDTH 1 809#define FRF_AB_GPIO2_PWRUP_VALUE_LBN 2 810#define FRF_AB_GPIO2_PWRUP_VALUE_WIDTH 1 811#define FRF_AB_GPIO1_PWRUP_VALUE_LBN 1 812#define FRF_AB_GPIO1_PWRUP_VALUE_WIDTH 1 813#define FRF_AB_GPIO0_PWRUP_VALUE_LBN 0 814#define FRF_AB_GPIO0_PWRUP_VALUE_WIDTH 1 815 816 817/* 818 * FR_AZ_FATAL_INTR_REG_KER(128bit): 819 * Fatal interrupt register for Kernel 820 */ 821#define FR_AZ_FATAL_INTR_REG_KER_OFST 0x00000230 822/* falcona0,falconb0,sienaa0=net_func_bar2 */ 823 824#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_LBN 44 825#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_WIDTH 1 826#define FRF_AB_PCI_BUSERR_INT_KER_EN_LBN 43 827#define FRF_AB_PCI_BUSERR_INT_KER_EN_WIDTH 1 828#define FRF_CZ_MBU_PERR_INT_KER_EN_LBN 43 829#define FRF_CZ_MBU_PERR_INT_KER_EN_WIDTH 1 830#define FRF_AZ_SRAM_OOB_INT_KER_EN_LBN 42 831#define FRF_AZ_SRAM_OOB_INT_KER_EN_WIDTH 1 832#define FRF_AZ_BUFID_OOB_INT_KER_EN_LBN 41 833#define FRF_AZ_BUFID_OOB_INT_KER_EN_WIDTH 1 834#define FRF_AZ_MEM_PERR_INT_KER_EN_LBN 40 835#define FRF_AZ_MEM_PERR_INT_KER_EN_WIDTH 1 836#define FRF_AZ_RBUF_OWN_INT_KER_EN_LBN 39 837#define FRF_AZ_RBUF_OWN_INT_KER_EN_WIDTH 1 838#define FRF_AZ_TBUF_OWN_INT_KER_EN_LBN 38 839#define FRF_AZ_TBUF_OWN_INT_KER_EN_WIDTH 1 840#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_LBN 37 841#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_WIDTH 1 842#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_LBN 36 843#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_WIDTH 1 844#define FRF_AZ_EVQ_OWN_INT_KER_EN_LBN 35 845#define FRF_AZ_EVQ_OWN_INT_KER_EN_WIDTH 1 846#define FRF_AZ_EVF_OFLO_INT_KER_EN_LBN 34 847#define FRF_AZ_EVF_OFLO_INT_KER_EN_WIDTH 1 848#define FRF_AZ_ILL_ADR_INT_KER_EN_LBN 33 849#define FRF_AZ_ILL_ADR_INT_KER_EN_WIDTH 1 850#define FRF_AZ_SRM_PERR_INT_KER_EN_LBN 32 851#define FRF_AZ_SRM_PERR_INT_KER_EN_WIDTH 1 852#define FRF_CZ_SRAM_PERR_INT_P_KER_LBN 12 853#define FRF_CZ_SRAM_PERR_INT_P_KER_WIDTH 1 854#define FRF_AB_PCI_BUSERR_INT_KER_LBN 11 855#define FRF_AB_PCI_BUSERR_INT_KER_WIDTH 1 856#define FRF_CZ_MBU_PERR_INT_KER_LBN 11 857#define FRF_CZ_MBU_PERR_INT_KER_WIDTH 1 858#define FRF_AZ_SRAM_OOB_INT_KER_LBN 10 859#define FRF_AZ_SRAM_OOB_INT_KER_WIDTH 1 860#define FRF_AZ_BUFID_DC_OOB_INT_KER_LBN 9 861#define FRF_AZ_BUFID_DC_OOB_INT_KER_WIDTH 1 862#define FRF_AZ_MEM_PERR_INT_KER_LBN 8 863#define FRF_AZ_MEM_PERR_INT_KER_WIDTH 1 864#define FRF_AZ_RBUF_OWN_INT_KER_LBN 7 865#define FRF_AZ_RBUF_OWN_INT_KER_WIDTH 1 866#define FRF_AZ_TBUF_OWN_INT_KER_LBN 6 867#define FRF_AZ_TBUF_OWN_INT_KER_WIDTH 1 868#define FRF_AZ_RDESCQ_OWN_INT_KER_LBN 5 869#define FRF_AZ_RDESCQ_OWN_INT_KER_WIDTH 1 870#define FRF_AZ_TDESCQ_OWN_INT_KER_LBN 4 871#define FRF_AZ_TDESCQ_OWN_INT_KER_WIDTH 1 872#define FRF_AZ_EVQ_OWN_INT_KER_LBN 3 873#define FRF_AZ_EVQ_OWN_INT_KER_WIDTH 1 874#define FRF_AZ_EVF_OFLO_INT_KER_LBN 2 875#define FRF_AZ_EVF_OFLO_INT_KER_WIDTH 1 876#define FRF_AZ_ILL_ADR_INT_KER_LBN 1 877#define FRF_AZ_ILL_ADR_INT_KER_WIDTH 1 878#define FRF_AZ_SRM_PERR_INT_KER_LBN 0 879#define FRF_AZ_SRM_PERR_INT_KER_WIDTH 1 880 881 882/* 883 * FR_AZ_FATAL_INTR_REG_CHAR(128bit): 884 * Fatal interrupt register for Char 885 */ 886#define FR_AZ_FATAL_INTR_REG_CHAR_OFST 0x00000240 887/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 888 889#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_LBN 44 890#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_WIDTH 1 891#define FRF_AB_PCI_BUSERR_INT_CHAR_EN_LBN 43 892#define FRF_AB_PCI_BUSERR_INT_CHAR_EN_WIDTH 1 893#define FRF_CZ_MBU_PERR_INT_CHAR_EN_LBN 43 894#define FRF_CZ_MBU_PERR_INT_CHAR_EN_WIDTH 1 895#define FRF_AZ_SRAM_OOB_INT_CHAR_EN_LBN 42 896#define FRF_AZ_SRAM_OOB_INT_CHAR_EN_WIDTH 1 897#define FRF_AZ_BUFID_OOB_INT_CHAR_EN_LBN 41 898#define FRF_AZ_BUFID_OOB_INT_CHAR_EN_WIDTH 1 899#define FRF_AZ_MEM_PERR_INT_CHAR_EN_LBN 40 900#define FRF_AZ_MEM_PERR_INT_CHAR_EN_WIDTH 1 901#define FRF_AZ_RBUF_OWN_INT_CHAR_EN_LBN 39 902#define FRF_AZ_RBUF_OWN_INT_CHAR_EN_WIDTH 1 903#define FRF_AZ_TBUF_OWN_INT_CHAR_EN_LBN 38 904#define FRF_AZ_TBUF_OWN_INT_CHAR_EN_WIDTH 1 905#define FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_LBN 37 906#define FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_WIDTH 1 907#define FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_LBN 36 908#define FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_WIDTH 1 909#define FRF_AZ_EVQ_OWN_INT_CHAR_EN_LBN 35 910#define FRF_AZ_EVQ_OWN_INT_CHAR_EN_WIDTH 1 911#define FRF_AZ_EVF_OFLO_INT_CHAR_EN_LBN 34 912#define FRF_AZ_EVF_OFLO_INT_CHAR_EN_WIDTH 1 913#define FRF_AZ_ILL_ADR_INT_CHAR_EN_LBN 33 914#define FRF_AZ_ILL_ADR_INT_CHAR_EN_WIDTH 1 915#define FRF_AZ_SRM_PERR_INT_CHAR_EN_LBN 32 916#define FRF_AZ_SRM_PERR_INT_CHAR_EN_WIDTH 1 917#define FRF_CZ_SRAM_PERR_INT_P_CHAR_LBN 12 918#define FRF_CZ_SRAM_PERR_INT_P_CHAR_WIDTH 1 919#define FRF_AB_PCI_BUSERR_INT_CHAR_LBN 11 920#define FRF_AB_PCI_BUSERR_INT_CHAR_WIDTH 1 921#define FRF_CZ_MBU_PERR_INT_CHAR_LBN 11 922#define FRF_CZ_MBU_PERR_INT_CHAR_WIDTH 1 923#define FRF_AZ_SRAM_OOB_INT_CHAR_LBN 10 924#define FRF_AZ_SRAM_OOB_INT_CHAR_WIDTH 1 925#define FRF_AZ_BUFID_DC_OOB_INT_CHAR_LBN 9 926#define FRF_AZ_BUFID_DC_OOB_INT_CHAR_WIDTH 1 927#define FRF_AZ_MEM_PERR_INT_CHAR_LBN 8 928#define FRF_AZ_MEM_PERR_INT_CHAR_WIDTH 1 929#define FRF_AZ_RBUF_OWN_INT_CHAR_LBN 7 930#define FRF_AZ_RBUF_OWN_INT_CHAR_WIDTH 1 931#define FRF_AZ_TBUF_OWN_INT_CHAR_LBN 6 932#define FRF_AZ_TBUF_OWN_INT_CHAR_WIDTH 1 933#define FRF_AZ_RDESCQ_OWN_INT_CHAR_LBN 5 934#define FRF_AZ_RDESCQ_OWN_INT_CHAR_WIDTH 1 935#define FRF_AZ_TDESCQ_OWN_INT_CHAR_LBN 4 936#define FRF_AZ_TDESCQ_OWN_INT_CHAR_WIDTH 1 937#define FRF_AZ_EVQ_OWN_INT_CHAR_LBN 3 938#define FRF_AZ_EVQ_OWN_INT_CHAR_WIDTH 1 939#define FRF_AZ_EVF_OFLO_INT_CHAR_LBN 2 940#define FRF_AZ_EVF_OFLO_INT_CHAR_WIDTH 1 941#define FRF_AZ_ILL_ADR_INT_CHAR_LBN 1 942#define FRF_AZ_ILL_ADR_INT_CHAR_WIDTH 1 943#define FRF_AZ_SRM_PERR_INT_CHAR_LBN 0 944#define FRF_AZ_SRM_PERR_INT_CHAR_WIDTH 1 945 946 947/* 948 * FR_AZ_DP_CTRL_REG(128bit): 949 * Datapath control register 950 */ 951#define FR_AZ_DP_CTRL_REG_OFST 0x00000250 952/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 953 954#define FRF_AZ_FLS_EVQ_ID_LBN 0 955#define FRF_AZ_FLS_EVQ_ID_WIDTH 12 956 957 958/* 959 * FR_AZ_MEM_STAT_REG(128bit): 960 * Memory status register 961 */ 962#define FR_AZ_MEM_STAT_REG_OFST 0x00000260 963/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 964 965#define FRF_AB_MEM_PERR_VEC_LBN 53 966#define FRF_AB_MEM_PERR_VEC_WIDTH 40 967#define FRF_AB_MEM_PERR_VEC_DW0_LBN 53 968#define FRF_AB_MEM_PERR_VEC_DW0_WIDTH 32 969#define FRF_AB_MEM_PERR_VEC_DW1_LBN 85 970#define FRF_AB_MEM_PERR_VEC_DW1_WIDTH 6 971#define FRF_AB_MBIST_CORR_LBN 38 972#define FRF_AB_MBIST_CORR_WIDTH 15 973#define FRF_AB_MBIST_ERR_LBN 0 974#define FRF_AB_MBIST_ERR_WIDTH 40 975#define FRF_AB_MBIST_ERR_DW0_LBN 0 976#define FRF_AB_MBIST_ERR_DW0_WIDTH 32 977#define FRF_AB_MBIST_ERR_DW1_LBN 32 978#define FRF_AB_MBIST_ERR_DW1_WIDTH 6 979#define FRF_CZ_MEM_PERR_VEC_LBN 0 980#define FRF_CZ_MEM_PERR_VEC_WIDTH 35 981#define FRF_CZ_MEM_PERR_VEC_DW0_LBN 0 982#define FRF_CZ_MEM_PERR_VEC_DW0_WIDTH 32 983#define FRF_CZ_MEM_PERR_VEC_DW1_LBN 32 984#define FRF_CZ_MEM_PERR_VEC_DW1_WIDTH 3 985 986 987/* 988 * FR_PORT0_CS_DEBUG_REG(128bit): 989 * Debug register 990 */ 991 992#define FR_AZ_CS_DEBUG_REG_OFST 0x00000270 993/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 994 995#define FRF_AB_GLB_DEBUG2_SEL_LBN 50 996#define FRF_AB_GLB_DEBUG2_SEL_WIDTH 3 997#define FRF_AB_DEBUG_BLK_SEL2_LBN 47 998#define FRF_AB_DEBUG_BLK_SEL2_WIDTH 3 999#define FRF_AB_DEBUG_BLK_SEL1_LBN 44 1000#define FRF_AB_DEBUG_BLK_SEL1_WIDTH 3 1001#define FRF_AB_DEBUG_BLK_SEL0_LBN 41 1002#define FRF_AB_DEBUG_BLK_SEL0_WIDTH 3 1003#define FRF_CZ_CS_PORT_NUM_LBN 40 1004#define FRF_CZ_CS_PORT_NUM_WIDTH 2 1005#define FRF_AB_MISC_DEBUG_ADDR_LBN 36 1006#define FRF_AB_MISC_DEBUG_ADDR_WIDTH 5 1007#define FRF_CZ_CS_RESERVED_LBN 36 1008#define FRF_CZ_CS_RESERVED_WIDTH 4 1009#define FRF_AB_SERDES_DEBUG_ADDR_LBN 31 1010#define FRF_AB_SERDES_DEBUG_ADDR_WIDTH 5 1011#define FRF_CZ_CS_PORT_FPE_DW0_LBN 1 1012#define FRF_CZ_CS_PORT_FPE_DW0_WIDTH 32 1013#define FRF_CZ_CS_PORT_FPE_DW1_LBN 33 1014#define FRF_CZ_CS_PORT_FPE_DW1_WIDTH 3 1015#define FRF_CZ_CS_PORT_FPE_LBN 1 1016#define FRF_CZ_CS_PORT_FPE_WIDTH 35 1017#define FRF_AB_EM_DEBUG_ADDR_LBN 26 1018#define FRF_AB_EM_DEBUG_ADDR_WIDTH 5 1019#define FRF_AB_SR_DEBUG_ADDR_LBN 21 1020#define FRF_AB_SR_DEBUG_ADDR_WIDTH 5 1021#define FRF_AB_EV_DEBUG_ADDR_LBN 16 1022#define FRF_AB_EV_DEBUG_ADDR_WIDTH 5 1023#define FRF_AB_RX_DEBUG_ADDR_LBN 11 1024#define FRF_AB_RX_DEBUG_ADDR_WIDTH 5 1025#define FRF_AB_TX_DEBUG_ADDR_LBN 6 1026#define FRF_AB_TX_DEBUG_ADDR_WIDTH 5 1027#define FRF_AB_CS_BIU_DEBUG_ADDR_LBN 1 1028#define FRF_AB_CS_BIU_DEBUG_ADDR_WIDTH 5 1029#define FRF_AZ_CS_DEBUG_EN_LBN 0 1030#define FRF_AZ_CS_DEBUG_EN_WIDTH 1 1031 1032 1033/* 1034 * FR_AZ_DRIVER_REG(128bit): 1035 * Driver scratch register [0-7] 1036 */ 1037#define FR_AZ_DRIVER_REG_OFST 0x00000280 1038/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1039#define FR_AZ_DRIVER_REG_STEP 16 1040#define FR_AZ_DRIVER_REG_ROWS 8 1041 1042#define FRF_AZ_DRIVER_DW0_LBN 0 1043#define FRF_AZ_DRIVER_DW0_WIDTH 32 1044 1045 1046/* 1047 * FR_AZ_ALTERA_BUILD_REG(128bit): 1048 * Altera build register 1049 */ 1050#define FR_AZ_ALTERA_BUILD_REG_OFST 0x00000300 1051/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1052 1053#define FRF_AZ_ALTERA_BUILD_VER_LBN 0 1054#define FRF_AZ_ALTERA_BUILD_VER_WIDTH 32 1055 1056 1057/* 1058 * FR_AZ_CSR_SPARE_REG(128bit): 1059 * Spare register 1060 */ 1061#define FR_AZ_CSR_SPARE_REG_OFST 0x00000310 1062/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1063 1064#define FRF_AZ_MEM_PERR_EN_TX_DATA_LBN 72 1065#define FRF_AZ_MEM_PERR_EN_TX_DATA_WIDTH 2 1066#define FRF_AZ_MEM_PERR_EN_LBN 64 1067#define FRF_AZ_MEM_PERR_EN_WIDTH 38 1068#define FRF_AZ_MEM_PERR_EN_DW0_LBN 64 1069#define FRF_AZ_MEM_PERR_EN_DW0_WIDTH 32 1070#define FRF_AZ_MEM_PERR_EN_DW1_LBN 96 1071#define FRF_AZ_MEM_PERR_EN_DW1_WIDTH 6 1072#define FRF_AZ_CSR_SPARE_BITS_LBN 0 1073#define FRF_AZ_CSR_SPARE_BITS_WIDTH 32 1074 1075 1076/* 1077 * FR_BZ_DEBUG_DATA_OUT_REG(128bit): 1078 * Live Debug and Debug 2 out ports 1079 */ 1080#define FR_BZ_DEBUG_DATA_OUT_REG_OFST 0x00000350 1081/* falconb0,sienaa0=net_func_bar2 */ 1082 1083#define FRF_BZ_DEBUG2_PORT_LBN 25 1084#define FRF_BZ_DEBUG2_PORT_WIDTH 15 1085#define FRF_BZ_DEBUG1_PORT_LBN 0 1086#define FRF_BZ_DEBUG1_PORT_WIDTH 25 1087 1088 1089/* 1090 * FR_BZ_EVQ_RPTR_REGP0(32bit): 1091 * Event queue read pointer register 1092 */ 1093#define FR_BZ_EVQ_RPTR_REGP0_OFST 0x00000400 1094/* falconb0,sienaa0=net_func_bar2 */ 1095#define FR_BZ_EVQ_RPTR_REGP0_STEP 8192 1096#define FR_BZ_EVQ_RPTR_REGP0_ROWS 1024 1097/* 1098 * FR_AA_EVQ_RPTR_REG_KER(32bit): 1099 * Event queue read pointer register 1100 */ 1101#define FR_AA_EVQ_RPTR_REG_KER_OFST 0x00011b00 1102/* falcona0=net_func_bar2 */ 1103#define FR_AA_EVQ_RPTR_REG_KER_STEP 4 1104#define FR_AA_EVQ_RPTR_REG_KER_ROWS 4 1105/* 1106 * FR_AZ_EVQ_RPTR_REG(32bit): 1107 * Event queue read pointer register 1108 */ 1109#define FR_AZ_EVQ_RPTR_REG_OFST 0x00fa0000 1110/* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1111#define FR_AZ_EVQ_RPTR_REG_STEP 16 1112#define FR_AB_EVQ_RPTR_REG_ROWS 4096 1113#define FR_CZ_EVQ_RPTR_REG_ROWS 1024 1114/* 1115 * FR_BB_EVQ_RPTR_REGP123(32bit): 1116 * Event queue read pointer register 1117 */ 1118#define FR_BB_EVQ_RPTR_REGP123_OFST 0x01000400 1119/* falconb0=net_func_bar2 */ 1120#define FR_BB_EVQ_RPTR_REGP123_STEP 8192 1121#define FR_BB_EVQ_RPTR_REGP123_ROWS 3072 1122 1123#define FRF_AZ_EVQ_RPTR_VLD_LBN 15 1124#define FRF_AZ_EVQ_RPTR_VLD_WIDTH 1 1125#define FRF_AZ_EVQ_RPTR_LBN 0 1126#define FRF_AZ_EVQ_RPTR_WIDTH 15 1127 1128 1129/* 1130 * FR_BZ_TIMER_COMMAND_REGP0(128bit): 1131 * Timer Command Registers 1132 */ 1133#define FR_BZ_TIMER_COMMAND_REGP0_OFST 0x00000420 1134/* falconb0,sienaa0=net_func_bar2 */ 1135#define FR_BZ_TIMER_COMMAND_REGP0_STEP 8192 1136#define FR_BZ_TIMER_COMMAND_REGP0_ROWS 1024 1137/* 1138 * FR_AA_TIMER_COMMAND_REG_KER(128bit): 1139 * Timer Command Registers 1140 */ 1141#define FR_AA_TIMER_COMMAND_REG_KER_OFST 0x00000420 1142/* falcona0=net_func_bar2 */ 1143#define FR_AA_TIMER_COMMAND_REG_KER_STEP 8192 1144#define FR_AA_TIMER_COMMAND_REG_KER_ROWS 4 1145/* 1146 * FR_AB_TIMER_COMMAND_REGP123(128bit): 1147 * Timer Command Registers 1148 */ 1149#define FR_AB_TIMER_COMMAND_REGP123_OFST 0x01000420 1150/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1151#define FR_AB_TIMER_COMMAND_REGP123_STEP 8192 1152#define FR_AB_TIMER_COMMAND_REGP123_ROWS 3072 1153/* 1154 * FR_AA_TIMER_COMMAND_REGP0(128bit): 1155 * Timer Command Registers 1156 */ 1157#define FR_AA_TIMER_COMMAND_REGP0_OFST 0x00008420 1158/* falcona0=char_func_bar0 */ 1159#define FR_AA_TIMER_COMMAND_REGP0_STEP 8192 1160#define FR_AA_TIMER_COMMAND_REGP0_ROWS 1020 1161 1162#define FRF_CZ_TC_TIMER_MODE_LBN 14 1163#define FRF_CZ_TC_TIMER_MODE_WIDTH 2 1164#define FRF_AB_TC_TIMER_MODE_LBN 12 1165#define FRF_AB_TC_TIMER_MODE_WIDTH 2 1166#define FRF_CZ_TC_TIMER_VAL_LBN 0 1167#define FRF_CZ_TC_TIMER_VAL_WIDTH 14 1168#define FRF_AB_TC_TIMER_VAL_LBN 0 1169#define FRF_AB_TC_TIMER_VAL_WIDTH 12 1170 1171 1172/* 1173 * FR_AZ_DRV_EV_REG(128bit): 1174 * Driver generated event register 1175 */ 1176#define FR_AZ_DRV_EV_REG_OFST 0x00000440 1177/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1178 1179#define FRF_AZ_DRV_EV_QID_LBN 64 1180#define FRF_AZ_DRV_EV_QID_WIDTH 12 1181#define FRF_AZ_DRV_EV_DATA_LBN 0 1182#define FRF_AZ_DRV_EV_DATA_WIDTH 64 1183#define FRF_AZ_DRV_EV_DATA_DW0_LBN 0 1184#define FRF_AZ_DRV_EV_DATA_DW0_WIDTH 32 1185#define FRF_AZ_DRV_EV_DATA_DW1_LBN 32 1186#define FRF_AZ_DRV_EV_DATA_DW1_WIDTH 32 1187 1188 1189/* 1190 * FR_AZ_EVQ_CTL_REG(128bit): 1191 * Event queue control register 1192 */ 1193#define FR_AZ_EVQ_CTL_REG_OFST 0x00000450 1194/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1195 1196#define FRF_CZ_RX_EVQ_WAKEUP_MASK_LBN 15 1197#define FRF_CZ_RX_EVQ_WAKEUP_MASK_WIDTH 10 1198#define FRF_BB_RX_EVQ_WAKEUP_MASK_LBN 15 1199#define FRF_BB_RX_EVQ_WAKEUP_MASK_WIDTH 6 1200#define FRF_AZ_EVQ_OWNERR_CTL_LBN 14 1201#define FRF_AZ_EVQ_OWNERR_CTL_WIDTH 1 1202#define FRF_AZ_EVQ_FIFO_AF_TH_LBN 7 1203#define FRF_AZ_EVQ_FIFO_AF_TH_WIDTH 7 1204#define FRF_AZ_EVQ_FIFO_NOTAF_TH_LBN 0 1205#define FRF_AZ_EVQ_FIFO_NOTAF_TH_WIDTH 7 1206 1207 1208/* 1209 * FR_AZ_EVQ_CNT1_REG(128bit): 1210 * Event counter 1 register 1211 */ 1212#define FR_AZ_EVQ_CNT1_REG_OFST 0x00000460 1213/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1214 1215#define FRF_AZ_EVQ_CNT_PRE_FIFO_LBN 120 1216#define FRF_AZ_EVQ_CNT_PRE_FIFO_WIDTH 7 1217#define FRF_AZ_EVQ_CNT_TOBIU_LBN 100 1218#define FRF_AZ_EVQ_CNT_TOBIU_WIDTH 20 1219#define FRF_AZ_EVQ_TX_REQ_CNT_LBN 80 1220#define FRF_AZ_EVQ_TX_REQ_CNT_WIDTH 20 1221#define FRF_AZ_EVQ_RX_REQ_CNT_LBN 60 1222#define FRF_AZ_EVQ_RX_REQ_CNT_WIDTH 20 1223#define FRF_AZ_EVQ_EM_REQ_CNT_LBN 40 1224#define FRF_AZ_EVQ_EM_REQ_CNT_WIDTH 20 1225#define FRF_AZ_EVQ_CSR_REQ_CNT_LBN 20 1226#define FRF_AZ_EVQ_CSR_REQ_CNT_WIDTH 20 1227#define FRF_AZ_EVQ_ERR_REQ_CNT_LBN 0 1228#define FRF_AZ_EVQ_ERR_REQ_CNT_WIDTH 20 1229 1230 1231/* 1232 * FR_AZ_EVQ_CNT2_REG(128bit): 1233 * Event counter 2 register 1234 */ 1235#define FR_AZ_EVQ_CNT2_REG_OFST 0x00000470 1236/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1237 1238#define FRF_AZ_EVQ_UPD_REQ_CNT_LBN 104 1239#define FRF_AZ_EVQ_UPD_REQ_CNT_WIDTH 20 1240#define FRF_AZ_EVQ_CLR_REQ_CNT_LBN 84 1241#define FRF_AZ_EVQ_CLR_REQ_CNT_WIDTH 20 1242#define FRF_AZ_EVQ_RDY_CNT_LBN 80 1243#define FRF_AZ_EVQ_RDY_CNT_WIDTH 4 1244#define FRF_AZ_EVQ_WU_REQ_CNT_LBN 60 1245#define FRF_AZ_EVQ_WU_REQ_CNT_WIDTH 20 1246#define FRF_AZ_EVQ_WET_REQ_CNT_LBN 40 1247#define FRF_AZ_EVQ_WET_REQ_CNT_WIDTH 20 1248#define FRF_AZ_EVQ_INIT_REQ_CNT_LBN 20 1249#define FRF_AZ_EVQ_INIT_REQ_CNT_WIDTH 20 1250#define FRF_AZ_EVQ_TM_REQ_CNT_LBN 0 1251#define FRF_AZ_EVQ_TM_REQ_CNT_WIDTH 20 1252 1253 1254/* 1255 * FR_CZ_USR_EV_REG(32bit): 1256 * Event mailbox register 1257 */ 1258#define FR_CZ_USR_EV_REG_OFST 0x00000540 1259/* sienaa0=net_func_bar2 */ 1260#define FR_CZ_USR_EV_REG_STEP 8192 1261#define FR_CZ_USR_EV_REG_ROWS 1024 1262 1263#define FRF_CZ_USR_EV_DATA_LBN 0 1264#define FRF_CZ_USR_EV_DATA_WIDTH 32 1265 1266 1267/* 1268 * FR_AZ_BUF_TBL_CFG_REG(128bit): 1269 * Buffer table configuration register 1270 */ 1271#define FR_AZ_BUF_TBL_CFG_REG_OFST 0x00000600 1272/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1273 1274#define FRF_AZ_BUF_TBL_MODE_LBN 3 1275#define FRF_AZ_BUF_TBL_MODE_WIDTH 1 1276 1277 1278/* 1279 * FR_AZ_SRM_RX_DC_CFG_REG(128bit): 1280 * SRAM receive descriptor cache configuration register 1281 */ 1282#define FR_AZ_SRM_RX_DC_CFG_REG_OFST 0x00000610 1283/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1284 1285#define FRF_AZ_SRM_CLK_TMP_EN_LBN 21 1286#define FRF_AZ_SRM_CLK_TMP_EN_WIDTH 1 1287#define FRF_AZ_SRM_RX_DC_BASE_ADR_LBN 0 1288#define FRF_AZ_SRM_RX_DC_BASE_ADR_WIDTH 21 1289 1290 1291/* 1292 * FR_AZ_SRM_TX_DC_CFG_REG(128bit): 1293 * SRAM transmit descriptor cache configuration register 1294 */ 1295#define FR_AZ_SRM_TX_DC_CFG_REG_OFST 0x00000620 1296/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1297 1298#define FRF_AZ_SRM_TX_DC_BASE_ADR_LBN 0 1299#define FRF_AZ_SRM_TX_DC_BASE_ADR_WIDTH 21 1300 1301 1302/* 1303 * FR_AZ_SRM_CFG_REG(128bit): 1304 * SRAM configuration register 1305 */ 1306#define FR_AZ_SRM_CFG_REG_SF_OFST 0x00000380 1307/* falcona0,falconb0=eeprom_flash */ 1308/* 1309 * FR_AZ_SRM_CFG_REG(128bit): 1310 * SRAM configuration register 1311 */ 1312#define FR_AZ_SRM_CFG_REG_OFST 0x00000630 1313/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1314 1315#define FRF_AZ_SRM_OOB_ADR_INTEN_LBN 5 1316#define FRF_AZ_SRM_OOB_ADR_INTEN_WIDTH 1 1317#define FRF_AZ_SRM_OOB_BUF_INTEN_LBN 4 1318#define FRF_AZ_SRM_OOB_BUF_INTEN_WIDTH 1 1319#define FRF_AZ_SRM_INIT_EN_LBN 3 1320#define FRF_AZ_SRM_INIT_EN_WIDTH 1 1321#define FRF_AZ_SRM_NUM_BANK_LBN 2 1322#define FRF_AZ_SRM_NUM_BANK_WIDTH 1 1323#define FRF_AZ_SRM_BANK_SIZE_LBN 0 1324#define FRF_AZ_SRM_BANK_SIZE_WIDTH 2 1325 1326 1327/* 1328 * FR_AZ_BUF_TBL_UPD_REG(128bit): 1329 * Buffer table update register 1330 */ 1331#define FR_AZ_BUF_TBL_UPD_REG_OFST 0x00000650 1332/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1333 1334#define FRF_AZ_BUF_UPD_CMD_LBN 63 1335#define FRF_AZ_BUF_UPD_CMD_WIDTH 1 1336#define FRF_AZ_BUF_CLR_CMD_LBN 62 1337#define FRF_AZ_BUF_CLR_CMD_WIDTH 1 1338#define FRF_AZ_BUF_CLR_END_ID_LBN 32 1339#define FRF_AZ_BUF_CLR_END_ID_WIDTH 20 1340#define FRF_AZ_BUF_CLR_START_ID_LBN 0 1341#define FRF_AZ_BUF_CLR_START_ID_WIDTH 20 1342 1343 1344/* 1345 * FR_AZ_SRM_UPD_EVQ_REG(128bit): 1346 * Buffer table update register 1347 */ 1348#define FR_AZ_SRM_UPD_EVQ_REG_OFST 0x00000660 1349/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1350 1351#define FRF_AZ_SRM_UPD_EVQ_ID_LBN 0 1352#define FRF_AZ_SRM_UPD_EVQ_ID_WIDTH 12 1353 1354 1355/* 1356 * FR_AZ_SRAM_PARITY_REG(128bit): 1357 * SRAM parity register. 1358 */ 1359#define FR_AZ_SRAM_PARITY_REG_OFST 0x00000670 1360/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1361 1362#define FRF_CZ_BYPASS_ECC_LBN 3 1363#define FRF_CZ_BYPASS_ECC_WIDTH 1 1364#define FRF_CZ_SEC_INT_LBN 2 1365#define FRF_CZ_SEC_INT_WIDTH 1 1366#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_LBN 1 1367#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_WIDTH 1 1368#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_LBN 0 1369#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_WIDTH 1 1370#define FRF_AB_FORCE_SRAM_PERR_LBN 0 1371#define FRF_AB_FORCE_SRAM_PERR_WIDTH 1 1372 1373 1374/* 1375 * FR_AZ_RX_CFG_REG(128bit): 1376 * Receive configuration register 1377 */ 1378#define FR_AZ_RX_CFG_REG_OFST 0x00000800 1379/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1380 1381#define FRF_CZ_RX_HDR_SPLIT_EN_LBN 71 1382#define FRF_CZ_RX_HDR_SPLIT_EN_WIDTH 1 1383#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_LBN 62 1384#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_WIDTH 9 1385#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_LBN 53 1386#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_WIDTH 9 1387#define FRF_CZ_RX_PRE_RFF_IPG_LBN 49 1388#define FRF_CZ_RX_PRE_RFF_IPG_WIDTH 4 1389#define FRF_BZ_RX_TCP_SUP_LBN 48 1390#define FRF_BZ_RX_TCP_SUP_WIDTH 1 1391#define FRF_BZ_RX_INGR_EN_LBN 47 1392#define FRF_BZ_RX_INGR_EN_WIDTH 1 1393#define FRF_BZ_RX_IP_HASH_LBN 46 1394#define FRF_BZ_RX_IP_HASH_WIDTH 1 1395#define FRF_BZ_RX_HASH_ALG_LBN 45 1396#define FRF_BZ_RX_HASH_ALG_WIDTH 1 1397#define FRF_BZ_RX_HASH_INSRT_HDR_LBN 44 1398#define FRF_BZ_RX_HASH_INSRT_HDR_WIDTH 1 1399#define FRF_BZ_RX_DESC_PUSH_EN_LBN 43 1400#define FRF_BZ_RX_DESC_PUSH_EN_WIDTH 1 1401#define FRF_BZ_RX_RDW_PATCH_EN_LBN 42 1402#define FRF_BZ_RX_RDW_PATCH_EN_WIDTH 1 1403#define FRF_BB_RX_PCI_BURST_SIZE_LBN 39 1404#define FRF_BB_RX_PCI_BURST_SIZE_WIDTH 3 1405#define FRF_BZ_RX_OWNERR_CTL_LBN 38 1406#define FRF_BZ_RX_OWNERR_CTL_WIDTH 1 1407#define FRF_BZ_RX_XON_TX_TH_LBN 33 1408#define FRF_BZ_RX_XON_TX_TH_WIDTH 5 1409#define FRF_AA_RX_DESC_PUSH_EN_LBN 35 1410#define FRF_AA_RX_DESC_PUSH_EN_WIDTH 1 1411#define FRF_AA_RX_RDW_PATCH_EN_LBN 34 1412#define FRF_AA_RX_RDW_PATCH_EN_WIDTH 1 1413#define FRF_AA_RX_PCI_BURST_SIZE_LBN 31 1414#define FRF_AA_RX_PCI_BURST_SIZE_WIDTH 3 1415#define FRF_BZ_RX_XOFF_TX_TH_LBN 28 1416#define FRF_BZ_RX_XOFF_TX_TH_WIDTH 5 1417#define FRF_AA_RX_OWNERR_CTL_LBN 30 1418#define FRF_AA_RX_OWNERR_CTL_WIDTH 1 1419#define FRF_AA_RX_XON_TX_TH_LBN 25 1420#define FRF_AA_RX_XON_TX_TH_WIDTH 5 1421#define FRF_BZ_RX_USR_BUF_SIZE_LBN 19 1422#define FRF_BZ_RX_USR_BUF_SIZE_WIDTH 9 1423#define FRF_AA_RX_XOFF_TX_TH_LBN 20 1424#define FRF_AA_RX_XOFF_TX_TH_WIDTH 5 1425#define FRF_AA_RX_USR_BUF_SIZE_LBN 11 1426#define FRF_AA_RX_USR_BUF_SIZE_WIDTH 9 1427#define FRF_BZ_RX_XON_MAC_TH_LBN 10 1428#define FRF_BZ_RX_XON_MAC_TH_WIDTH 9 1429#define FRF_AA_RX_XON_MAC_TH_LBN 6 1430#define FRF_AA_RX_XON_MAC_TH_WIDTH 5 1431#define FRF_BZ_RX_XOFF_MAC_TH_LBN 1 1432#define FRF_BZ_RX_XOFF_MAC_TH_WIDTH 9 1433#define FRF_AA_RX_XOFF_MAC_TH_LBN 1 1434#define FRF_AA_RX_XOFF_MAC_TH_WIDTH 5 1435#define FRF_AZ_RX_XOFF_MAC_EN_LBN 0 1436#define FRF_AZ_RX_XOFF_MAC_EN_WIDTH 1 1437 1438 1439/* 1440 * FR_AZ_RX_FILTER_CTL_REG(128bit): 1441 * Receive filter control registers 1442 */ 1443#define FR_AZ_RX_FILTER_CTL_REG_OFST 0x00000810 1444/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1445 1446#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_LBN 94 1447#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_WIDTH 8 1448#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_LBN 86 1449#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_WIDTH 8 1450#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_LBN 85 1451#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_WIDTH 1 1452#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_LBN 69 1453#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_WIDTH 16 1454#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_LBN 57 1455#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_WIDTH 12 1456#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_LBN 56 1457#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_WIDTH 1 1458#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_LBN 55 1459#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_WIDTH 1 1460#define FRF_CZ_UNICAST_NOMATCH_Q_ID_LBN 43 1461#define FRF_CZ_UNICAST_NOMATCH_Q_ID_WIDTH 12 1462#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_LBN 42 1463#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_WIDTH 1 1464#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_LBN 41 1465#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_WIDTH 1 1466#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_LBN 40 1467#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_WIDTH 1 1468#define FRF_AZ_UDP_FULL_SRCH_LIMIT_LBN 32 1469#define FRF_AZ_UDP_FULL_SRCH_LIMIT_WIDTH 8 1470#define FRF_AZ_NUM_KER_LBN 24 1471#define FRF_AZ_NUM_KER_WIDTH 2 1472#define FRF_AZ_UDP_WILD_SRCH_LIMIT_LBN 16 1473#define FRF_AZ_UDP_WILD_SRCH_LIMIT_WIDTH 8 1474#define FRF_AZ_TCP_WILD_SRCH_LIMIT_LBN 8 1475#define FRF_AZ_TCP_WILD_SRCH_LIMIT_WIDTH 8 1476#define FRF_AZ_TCP_FULL_SRCH_LIMIT_LBN 0 1477#define FRF_AZ_TCP_FULL_SRCH_LIMIT_WIDTH 8 1478 1479 1480/* 1481 * FR_AZ_RX_FLUSH_DESCQ_REG(128bit): 1482 * Receive flush descriptor queue register 1483 */ 1484#define FR_AZ_RX_FLUSH_DESCQ_REG_OFST 0x00000820 1485/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1486 1487#define FRF_AZ_RX_FLUSH_DESCQ_CMD_LBN 24 1488#define FRF_AZ_RX_FLUSH_DESCQ_CMD_WIDTH 1 1489#define FRF_AZ_RX_FLUSH_DESCQ_LBN 0 1490#define FRF_AZ_RX_FLUSH_DESCQ_WIDTH 12 1491 1492 1493/* 1494 * FR_BZ_RX_DESC_UPD_REGP0(128bit): 1495 * Receive descriptor update register. 1496 */ 1497#define FR_BZ_RX_DESC_UPD_REGP0_OFST 0x00000830 1498/* falconb0,sienaa0=net_func_bar2 */ 1499#define FR_BZ_RX_DESC_UPD_REGP0_STEP 8192 1500#define FR_BZ_RX_DESC_UPD_REGP0_ROWS 1024 1501/* 1502 * FR_AA_RX_DESC_UPD_REG_KER(128bit): 1503 * Receive descriptor update register. 1504 */ 1505#define FR_AA_RX_DESC_UPD_REG_KER_OFST 0x00000830 1506/* falcona0=net_func_bar2 */ 1507#define FR_AA_RX_DESC_UPD_REG_KER_STEP 8192 1508#define FR_AA_RX_DESC_UPD_REG_KER_ROWS 4 1509/* 1510 * FR_AB_RX_DESC_UPD_REGP123(128bit): 1511 * Receive descriptor update register. 1512 */ 1513#define FR_AB_RX_DESC_UPD_REGP123_OFST 0x01000830 1514/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1515#define FR_AB_RX_DESC_UPD_REGP123_STEP 8192 1516#define FR_AB_RX_DESC_UPD_REGP123_ROWS 3072 1517/* 1518 * FR_AA_RX_DESC_UPD_REGP0(128bit): 1519 * Receive descriptor update register. 1520 */ 1521#define FR_AA_RX_DESC_UPD_REGP0_OFST 0x00008830 1522/* falcona0=char_func_bar0 */ 1523#define FR_AA_RX_DESC_UPD_REGP0_STEP 8192 1524#define FR_AA_RX_DESC_UPD_REGP0_ROWS 1020 1525 1526#define FRF_AZ_RX_DESC_WPTR_LBN 96 1527#define FRF_AZ_RX_DESC_WPTR_WIDTH 12 1528#define FRF_AZ_RX_DESC_PUSH_CMD_LBN 95 1529#define FRF_AZ_RX_DESC_PUSH_CMD_WIDTH 1 1530#define FRF_AZ_RX_DESC_LBN 0 1531#define FRF_AZ_RX_DESC_WIDTH 64 1532#define FRF_AZ_RX_DESC_DW0_LBN 0 1533#define FRF_AZ_RX_DESC_DW0_WIDTH 32 1534#define FRF_AZ_RX_DESC_DW1_LBN 32 1535#define FRF_AZ_RX_DESC_DW1_WIDTH 32 1536 1537 1538/* 1539 * FR_AZ_RX_DC_CFG_REG(128bit): 1540 * Receive descriptor cache configuration register 1541 */ 1542#define FR_AZ_RX_DC_CFG_REG_OFST 0x00000840 1543/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1544 1545#define FRF_AZ_RX_MAX_PF_LBN 2 1546#define FRF_AZ_RX_MAX_PF_WIDTH 2 1547#define FRF_AZ_RX_DC_SIZE_LBN 0 1548#define FRF_AZ_RX_DC_SIZE_WIDTH 2 1549#define FFE_AZ_RX_DC_SIZE_64 3 1550#define FFE_AZ_RX_DC_SIZE_32 2 1551#define FFE_AZ_RX_DC_SIZE_16 1 1552#define FFE_AZ_RX_DC_SIZE_8 0 1553 1554 1555/* 1556 * FR_AZ_RX_DC_PF_WM_REG(128bit): 1557 * Receive descriptor cache pre-fetch watermark register 1558 */ 1559#define FR_AZ_RX_DC_PF_WM_REG_OFST 0x00000850 1560/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1561 1562#define FRF_AZ_RX_DC_PF_HWM_LBN 6 1563#define FRF_AZ_RX_DC_PF_HWM_WIDTH 6 1564#define FRF_AZ_RX_DC_PF_LWM_LBN 0 1565#define FRF_AZ_RX_DC_PF_LWM_WIDTH 6 1566 1567 1568/* 1569 * FR_BZ_RX_RSS_TKEY_REG(128bit): 1570 * RSS Toeplitz hash key 1571 */ 1572#define FR_BZ_RX_RSS_TKEY_REG_OFST 0x00000860 1573/* falconb0,sienaa0=net_func_bar2 */ 1574 1575#define FRF_BZ_RX_RSS_TKEY_LBN 96 1576#define FRF_BZ_RX_RSS_TKEY_WIDTH 32 1577#define FRF_BZ_RX_RSS_TKEY_DW3_LBN 96 1578#define FRF_BZ_RX_RSS_TKEY_DW3_WIDTH 32 1579#define FRF_BZ_RX_RSS_TKEY_DW2_LBN 64 1580#define FRF_BZ_RX_RSS_TKEY_DW2_WIDTH 32 1581#define FRF_BZ_RX_RSS_TKEY_DW1_LBN 32 1582#define FRF_BZ_RX_RSS_TKEY_DW1_WIDTH 32 1583#define FRF_BZ_RX_RSS_TKEY_DW0_LBN 0 1584#define FRF_BZ_RX_RSS_TKEY_DW0_WIDTH 32 1585 1586 1587/* 1588 * FR_AZ_RX_NODESC_DROP_REG(128bit): 1589 * Receive dropped packet counter register 1590 */ 1591#define FR_AZ_RX_NODESC_DROP_REG_OFST 0x00000880 1592/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1593 1594#define FRF_AZ_RX_NODESC_DROP_CNT_LBN 0 1595#define FRF_AZ_RX_NODESC_DROP_CNT_WIDTH 16 1596 1597 1598/* 1599 * FR_AZ_RX_SELF_RST_REG(128bit): 1600 * Receive self reset register 1601 */ 1602#define FR_AZ_RX_SELF_RST_REG_OFST 0x00000890 1603/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1604 1605#define FRF_AZ_RX_ISCSI_DIS_LBN 17 1606#define FRF_AZ_RX_ISCSI_DIS_WIDTH 1 1607#define FRF_AB_RX_SW_RST_REG_LBN 16 1608#define FRF_AB_RX_SW_RST_REG_WIDTH 1 1609#define FRF_AB_RX_SELF_RST_EN_LBN 8 1610#define FRF_AB_RX_SELF_RST_EN_WIDTH 1 1611#define FRF_AZ_RX_MAX_PF_LAT_LBN 4 1612#define FRF_AZ_RX_MAX_PF_LAT_WIDTH 4 1613#define FRF_AZ_RX_MAX_LU_LAT_LBN 0 1614#define FRF_AZ_RX_MAX_LU_LAT_WIDTH 4 1615 1616 1617/* 1618 * FR_AZ_RX_DEBUG_REG(128bit): 1619 * undocumented register 1620 */ 1621#define FR_AZ_RX_DEBUG_REG_OFST 0x000008a0 1622/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1623 1624#define FRF_AZ_RX_DEBUG_LBN 0 1625#define FRF_AZ_RX_DEBUG_WIDTH 64 1626#define FRF_AZ_RX_DEBUG_DW0_LBN 0 1627#define FRF_AZ_RX_DEBUG_DW0_WIDTH 32 1628#define FRF_AZ_RX_DEBUG_DW1_LBN 32 1629#define FRF_AZ_RX_DEBUG_DW1_WIDTH 32 1630 1631 1632/* 1633 * FR_AZ_RX_PUSH_DROP_REG(128bit): 1634 * Receive descriptor push dropped counter register 1635 */ 1636#define FR_AZ_RX_PUSH_DROP_REG_OFST 0x000008b0 1637/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1638 1639#define FRF_AZ_RX_PUSH_DROP_CNT_LBN 0 1640#define FRF_AZ_RX_PUSH_DROP_CNT_WIDTH 32 1641 1642 1643/* 1644 * FR_CZ_RX_RSS_IPV6_REG1(128bit): 1645 * IPv6 RSS Toeplitz hash key low bytes 1646 */ 1647#define FR_CZ_RX_RSS_IPV6_REG1_OFST 0x000008d0 1648/* sienaa0=net_func_bar2 */ 1649 1650#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN 0 1651#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH 128 1652#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_LBN 0 1653#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_WIDTH 32 1654#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_LBN 32 1655#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_WIDTH 32 1656#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_LBN 64 1657#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_WIDTH 32 1658#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_LBN 96 1659#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_WIDTH 32 1660 1661 1662/* 1663 * FR_CZ_RX_RSS_IPV6_REG2(128bit): 1664 * IPv6 RSS Toeplitz hash key middle bytes 1665 */ 1666#define FR_CZ_RX_RSS_IPV6_REG2_OFST 0x000008e0 1667/* sienaa0=net_func_bar2 */ 1668 1669#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN 0 1670#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH 128 1671#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_LBN 0 1672#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_WIDTH 32 1673#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_LBN 32 1674#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_WIDTH 32 1675#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_LBN 64 1676#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_WIDTH 32 1677#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_LBN 96 1678#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_WIDTH 32 1679 1680 1681/* 1682 * FR_CZ_RX_RSS_IPV6_REG3(128bit): 1683 * IPv6 RSS Toeplitz hash key upper bytes and IPv6 RSS settings 1684 */ 1685#define FR_CZ_RX_RSS_IPV6_REG3_OFST 0x000008f0 1686/* sienaa0=net_func_bar2 */ 1687 1688#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_LBN 66 1689#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_WIDTH 1 1690#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_LBN 65 1691#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_WIDTH 1 1692#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_LBN 64 1693#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_WIDTH 1 1694#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN 0 1695#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH 64 1696#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_LBN 0 1697#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_WIDTH 32 1698#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_LBN 32 1699#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_WIDTH 32 1700 1701 1702/* 1703 * FR_AZ_TX_FLUSH_DESCQ_REG(128bit): 1704 * Transmit flush descriptor queue register 1705 */ 1706#define FR_AZ_TX_FLUSH_DESCQ_REG_OFST 0x00000a00 1707/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1708 1709#define FRF_AZ_TX_FLUSH_DESCQ_CMD_LBN 12 1710#define FRF_AZ_TX_FLUSH_DESCQ_CMD_WIDTH 1 1711#define FRF_AZ_TX_FLUSH_DESCQ_LBN 0 1712#define FRF_AZ_TX_FLUSH_DESCQ_WIDTH 12 1713 1714 1715/* 1716 * FR_BZ_TX_DESC_UPD_REGP0(128bit): 1717 * Transmit descriptor update register. 1718 */ 1719#define FR_BZ_TX_DESC_UPD_REGP0_OFST 0x00000a10 1720/* falconb0,sienaa0=net_func_bar2 */ 1721#define FR_BZ_TX_DESC_UPD_REGP0_STEP 8192 1722#define FR_BZ_TX_DESC_UPD_REGP0_ROWS 1024 1723/* 1724 * FR_AA_TX_DESC_UPD_REG_KER(128bit): 1725 * Transmit descriptor update register. 1726 */ 1727#define FR_AA_TX_DESC_UPD_REG_KER_OFST 0x00000a10 1728/* falcona0=net_func_bar2 */ 1729#define FR_AA_TX_DESC_UPD_REG_KER_STEP 8192 1730#define FR_AA_TX_DESC_UPD_REG_KER_ROWS 8 1731/* 1732 * FR_AB_TX_DESC_UPD_REGP123(128bit): 1733 * Transmit descriptor update register. 1734 */ 1735#define FR_AB_TX_DESC_UPD_REGP123_OFST 0x01000a10 1736/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1737#define FR_AB_TX_DESC_UPD_REGP123_STEP 8192 1738#define FR_AB_TX_DESC_UPD_REGP123_ROWS 3072 1739/* 1740 * FR_AA_TX_DESC_UPD_REGP0(128bit): 1741 * Transmit descriptor update register. 1742 */ 1743#define FR_AA_TX_DESC_UPD_REGP0_OFST 0x00008a10 1744/* falcona0=char_func_bar0 */ 1745#define FR_AA_TX_DESC_UPD_REGP0_STEP 8192 1746#define FR_AA_TX_DESC_UPD_REGP0_ROWS 1020 1747 1748#define FRF_AZ_TX_DESC_WPTR_LBN 96 1749#define FRF_AZ_TX_DESC_WPTR_WIDTH 12 1750#define FRF_AZ_TX_DESC_PUSH_CMD_LBN 95 1751#define FRF_AZ_TX_DESC_PUSH_CMD_WIDTH 1 1752#define FRF_AZ_TX_DESC_LBN 0 1753#define FRF_AZ_TX_DESC_WIDTH 95 1754#define FRF_AZ_TX_DESC_DW0_LBN 0 1755#define FRF_AZ_TX_DESC_DW0_WIDTH 32 1756#define FRF_AZ_TX_DESC_DW1_LBN 32 1757#define FRF_AZ_TX_DESC_DW1_WIDTH 32 1758#define FRF_AZ_TX_DESC_DW2_LBN 64 1759#define FRF_AZ_TX_DESC_DW2_WIDTH 31 1760 1761 1762/* 1763 * FR_AZ_TX_DC_CFG_REG(128bit): 1764 * Transmit descriptor cache configuration register 1765 */ 1766#define FR_AZ_TX_DC_CFG_REG_OFST 0x00000a20 1767/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1768 1769#define FRF_AZ_TX_DC_SIZE_LBN 0 1770#define FRF_AZ_TX_DC_SIZE_WIDTH 2 1771#define FFE_AZ_TX_DC_SIZE_32 2 1772#define FFE_AZ_TX_DC_SIZE_16 1 1773#define FFE_AZ_TX_DC_SIZE_8 0 1774 1775 1776/* 1777 * FR_AA_TX_CHKSM_CFG_REG(128bit): 1778 * Transmit checksum configuration register 1779 */ 1780#define FR_AA_TX_CHKSM_CFG_REG_OFST 0x00000a30 1781/* falcona0=net_func_bar2,falcona0=char_func_bar0 */ 1782 1783#define FRF_AA_TX_Q_CHKSM_DIS_96_127_LBN 96 1784#define FRF_AA_TX_Q_CHKSM_DIS_96_127_WIDTH 32 1785#define FRF_AA_TX_Q_CHKSM_DIS_64_95_LBN 64 1786#define FRF_AA_TX_Q_CHKSM_DIS_64_95_WIDTH 32 1787#define FRF_AA_TX_Q_CHKSM_DIS_32_63_LBN 32 1788#define FRF_AA_TX_Q_CHKSM_DIS_32_63_WIDTH 32 1789#define FRF_AA_TX_Q_CHKSM_DIS_0_31_LBN 0 1790#define FRF_AA_TX_Q_CHKSM_DIS_0_31_WIDTH 32 1791 1792 1793/* 1794 * FR_AZ_TX_CFG_REG(128bit): 1795 * Transmit configuration register 1796 */ 1797#define FR_AZ_TX_CFG_REG_OFST 0x00000a50 1798/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1799 1800#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_LBN 114 1801#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_WIDTH 8 1802#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_LBN 113 1803#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_WIDTH 1 1804#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_LBN 105 1805#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1806#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_LBN 97 1807#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1808#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_LBN 89 1809#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1810#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_LBN 81 1811#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1812#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_LBN 73 1813#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1814#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_LBN 65 1815#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1816#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_LBN 64 1817#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_WIDTH 1 1818#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_LBN 48 1819#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_WIDTH 16 1820#define FRF_CZ_TX_FILTER_EN_BIT_LBN 47 1821#define FRF_CZ_TX_FILTER_EN_BIT_WIDTH 1 1822#define FRF_AZ_TX_IP_ID_P0_OFS_LBN 16 1823#define FRF_AZ_TX_IP_ID_P0_OFS_WIDTH 15 1824#define FRF_AZ_TX_NO_EOP_DISC_EN_LBN 5 1825#define FRF_AZ_TX_NO_EOP_DISC_EN_WIDTH 1 1826#define FRF_AZ_TX_P1_PRI_EN_LBN 4 1827#define FRF_AZ_TX_P1_PRI_EN_WIDTH 1 1828#define FRF_AZ_TX_OWNERR_CTL_LBN 2 1829#define FRF_AZ_TX_OWNERR_CTL_WIDTH 1 1830#define FRF_AA_TX_NON_IP_DROP_DIS_LBN 1 1831#define FRF_AA_TX_NON_IP_DROP_DIS_WIDTH 1 1832#define FRF_AZ_TX_IP_ID_REP_EN_LBN 0 1833#define FRF_AZ_TX_IP_ID_REP_EN_WIDTH 1 1834 1835 1836/* 1837 * FR_AZ_TX_PUSH_DROP_REG(128bit): 1838 * Transmit push dropped register 1839 */ 1840#define FR_AZ_TX_PUSH_DROP_REG_OFST 0x00000a60 1841/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1842 1843#define FRF_AZ_TX_PUSH_DROP_CNT_LBN 0 1844#define FRF_AZ_TX_PUSH_DROP_CNT_WIDTH 32 1845 1846 1847/* 1848 * FR_AZ_TX_RESERVED_REG(128bit): 1849 * Transmit configuration register 1850 */ 1851#define FR_AZ_TX_RESERVED_REG_OFST 0x00000a80 1852/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1853 1854#define FRF_AZ_TX_EVT_CNT_LBN 121 1855#define FRF_AZ_TX_EVT_CNT_WIDTH 7 1856#define FRF_AZ_TX_PREF_AGE_CNT_LBN 119 1857#define FRF_AZ_TX_PREF_AGE_CNT_WIDTH 2 1858#define FRF_AZ_TX_RD_COMP_TMR_LBN 96 1859#define FRF_AZ_TX_RD_COMP_TMR_WIDTH 23 1860#define FRF_AZ_TX_PUSH_EN_LBN 89 1861#define FRF_AZ_TX_PUSH_EN_WIDTH 1 1862#define FRF_AZ_TX_PUSH_CHK_DIS_LBN 88 1863#define FRF_AZ_TX_PUSH_CHK_DIS_WIDTH 1 1864#define FRF_AZ_TX_D_FF_FULL_P0_LBN 85 1865#define FRF_AZ_TX_D_FF_FULL_P0_WIDTH 1 1866#define FRF_AZ_TX_DMAR_ST_P0_LBN 81 1867#define FRF_AZ_TX_DMAR_ST_P0_WIDTH 1 1868#define FRF_AZ_TX_DMAQ_ST_LBN 78 1869#define FRF_AZ_TX_DMAQ_ST_WIDTH 1 1870#define FRF_AZ_TX_RX_SPACER_LBN 64 1871#define FRF_AZ_TX_RX_SPACER_WIDTH 8 1872#define FRF_AZ_TX_DROP_ABORT_EN_LBN 60 1873#define FRF_AZ_TX_DROP_ABORT_EN_WIDTH 1 1874#define FRF_AZ_TX_SOFT_EVT_EN_LBN 59 1875#define FRF_AZ_TX_SOFT_EVT_EN_WIDTH 1 1876#define FRF_AZ_TX_PS_EVT_DIS_LBN 58 1877#define FRF_AZ_TX_PS_EVT_DIS_WIDTH 1 1878#define FRF_AZ_TX_RX_SPACER_EN_LBN 57 1879#define FRF_AZ_TX_RX_SPACER_EN_WIDTH 1 1880#define FRF_AZ_TX_XP_TIMER_LBN 52 1881#define FRF_AZ_TX_XP_TIMER_WIDTH 5 1882#define FRF_AZ_TX_PREF_SPACER_LBN 44 1883#define FRF_AZ_TX_PREF_SPACER_WIDTH 8 1884#define FRF_AZ_TX_PREF_WD_TMR_LBN 22 1885#define FRF_AZ_TX_PREF_WD_TMR_WIDTH 22 1886#define FRF_AZ_TX_ONLY1TAG_LBN 21 1887#define FRF_AZ_TX_ONLY1TAG_WIDTH 1 1888#define FRF_AZ_TX_PREF_THRESHOLD_LBN 19 1889#define FRF_AZ_TX_PREF_THRESHOLD_WIDTH 2 1890#define FRF_AZ_TX_ONE_PKT_PER_Q_LBN 18 1891#define FRF_AZ_TX_ONE_PKT_PER_Q_WIDTH 1 1892#define FRF_AZ_TX_DIS_NON_IP_EV_LBN 17 1893#define FRF_AZ_TX_DIS_NON_IP_EV_WIDTH 1 1894#define FRF_AA_TX_DMA_FF_THR_LBN 16 1895#define FRF_AA_TX_DMA_FF_THR_WIDTH 1 1896#define FRF_AZ_TX_DMA_SPACER_LBN 8 1897#define FRF_AZ_TX_DMA_SPACER_WIDTH 8 1898#define FRF_AA_TX_TCP_DIS_LBN 7 1899#define FRF_AA_TX_TCP_DIS_WIDTH 1 1900#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_LBN 7 1901#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_WIDTH 1 1902#define FRF_AA_TX_IP_DIS_LBN 6 1903#define FRF_AA_TX_IP_DIS_WIDTH 1 1904#define FRF_AZ_TX_MAX_CPL_LBN 2 1905#define FRF_AZ_TX_MAX_CPL_WIDTH 2 1906#define FFE_AZ_TX_MAX_CPL_16 3 1907#define FFE_AZ_TX_MAX_CPL_8 2 1908#define FFE_AZ_TX_MAX_CPL_4 1 1909#define FFE_AZ_TX_MAX_CPL_NOLIMIT 0 1910#define FRF_AZ_TX_MAX_PREF_LBN 0 1911#define FRF_AZ_TX_MAX_PREF_WIDTH 2 1912#define FFE_AZ_TX_MAX_PREF_32 3 1913#define FFE_AZ_TX_MAX_PREF_16 2 1914#define FFE_AZ_TX_MAX_PREF_8 1 1915#define FFE_AZ_TX_MAX_PREF_OFF 0 1916 1917 1918/* 1919 * FR_BZ_TX_PACE_REG(128bit): 1920 * Transmit pace control register 1921 */ 1922#define FR_BZ_TX_PACE_REG_OFST 0x00000a90 1923/* falconb0,sienaa0=net_func_bar2 */ 1924/* 1925 * FR_AA_TX_PACE_REG(128bit): 1926 * Transmit pace control register 1927 */ 1928#define FR_AA_TX_PACE_REG_OFST 0x00f80000 1929/* falcona0=char_func_bar0 */ 1930 1931#define FRF_AZ_TX_PACE_SB_NOT_AF_LBN 19 1932#define FRF_AZ_TX_PACE_SB_NOT_AF_WIDTH 10 1933#define FRF_AZ_TX_PACE_SB_AF_LBN 9 1934#define FRF_AZ_TX_PACE_SB_AF_WIDTH 10 1935#define FRF_AZ_TX_PACE_FB_BASE_LBN 5 1936#define FRF_AZ_TX_PACE_FB_BASE_WIDTH 4 1937#define FRF_AZ_TX_PACE_BIN_TH_LBN 0 1938#define FRF_AZ_TX_PACE_BIN_TH_WIDTH 5 1939 1940 1941/* 1942 * FR_AZ_TX_PACE_DROP_QID_REG(128bit): 1943 * PACE Drop QID Counter 1944 */ 1945#define FR_AZ_TX_PACE_DROP_QID_REG_OFST 0x00000aa0 1946/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1947 1948#define FRF_AZ_TX_PACE_QID_DRP_CNT_LBN 0 1949#define FRF_AZ_TX_PACE_QID_DRP_CNT_WIDTH 16 1950 1951 1952/* 1953 * FR_AB_TX_VLAN_REG(128bit): 1954 * Transmit VLAN tag register 1955 */ 1956#define FR_AB_TX_VLAN_REG_OFST 0x00000ae0 1957/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1958 1959#define FRF_AB_TX_VLAN_EN_LBN 127 1960#define FRF_AB_TX_VLAN_EN_WIDTH 1 1961#define FRF_AB_TX_VLAN7_PORT1_EN_LBN 125 1962#define FRF_AB_TX_VLAN7_PORT1_EN_WIDTH 1 1963#define FRF_AB_TX_VLAN7_PORT0_EN_LBN 124 1964#define FRF_AB_TX_VLAN7_PORT0_EN_WIDTH 1 1965#define FRF_AB_TX_VLAN7_LBN 112 1966#define FRF_AB_TX_VLAN7_WIDTH 12 1967#define FRF_AB_TX_VLAN6_PORT1_EN_LBN 109 1968#define FRF_AB_TX_VLAN6_PORT1_EN_WIDTH 1 1969#define FRF_AB_TX_VLAN6_PORT0_EN_LBN 108 1970#define FRF_AB_TX_VLAN6_PORT0_EN_WIDTH 1 1971#define FRF_AB_TX_VLAN6_LBN 96 1972#define FRF_AB_TX_VLAN6_WIDTH 12 1973#define FRF_AB_TX_VLAN5_PORT1_EN_LBN 93 1974#define FRF_AB_TX_VLAN5_PORT1_EN_WIDTH 1 1975#define FRF_AB_TX_VLAN5_PORT0_EN_LBN 92 1976#define FRF_AB_TX_VLAN5_PORT0_EN_WIDTH 1 1977#define FRF_AB_TX_VLAN5_LBN 80 1978#define FRF_AB_TX_VLAN5_WIDTH 12 1979#define FRF_AB_TX_VLAN4_PORT1_EN_LBN 77 1980#define FRF_AB_TX_VLAN4_PORT1_EN_WIDTH 1 1981#define FRF_AB_TX_VLAN4_PORT0_EN_LBN 76 1982#define FRF_AB_TX_VLAN4_PORT0_EN_WIDTH 1 1983#define FRF_AB_TX_VLAN4_LBN 64 1984#define FRF_AB_TX_VLAN4_WIDTH 12 1985#define FRF_AB_TX_VLAN3_PORT1_EN_LBN 61 1986#define FRF_AB_TX_VLAN3_PORT1_EN_WIDTH 1 1987#define FRF_AB_TX_VLAN3_PORT0_EN_LBN 60 1988#define FRF_AB_TX_VLAN3_PORT0_EN_WIDTH 1 1989#define FRF_AB_TX_VLAN3_LBN 48 1990#define FRF_AB_TX_VLAN3_WIDTH 12 1991#define FRF_AB_TX_VLAN2_PORT1_EN_LBN 45 1992#define FRF_AB_TX_VLAN2_PORT1_EN_WIDTH 1 1993#define FRF_AB_TX_VLAN2_PORT0_EN_LBN 44 1994#define FRF_AB_TX_VLAN2_PORT0_EN_WIDTH 1 1995#define FRF_AB_TX_VLAN2_LBN 32 1996#define FRF_AB_TX_VLAN2_WIDTH 12 1997#define FRF_AB_TX_VLAN1_PORT1_EN_LBN 29 1998#define FRF_AB_TX_VLAN1_PORT1_EN_WIDTH 1 1999#define FRF_AB_TX_VLAN1_PORT0_EN_LBN 28 2000#define FRF_AB_TX_VLAN1_PORT0_EN_WIDTH 1 2001#define FRF_AB_TX_VLAN1_LBN 16 2002#define FRF_AB_TX_VLAN1_WIDTH 12 2003#define FRF_AB_TX_VLAN0_PORT1_EN_LBN 13 2004#define FRF_AB_TX_VLAN0_PORT1_EN_WIDTH 1 2005#define FRF_AB_TX_VLAN0_PORT0_EN_LBN 12 2006#define FRF_AB_TX_VLAN0_PORT0_EN_WIDTH 1 2007#define FRF_AB_TX_VLAN0_LBN 0 2008#define FRF_AB_TX_VLAN0_WIDTH 12 2009 2010 2011/* 2012 * FR_AZ_TX_IPFIL_PORTEN_REG(128bit): 2013 * Transmit filter control register 2014 */ 2015#define FR_AZ_TX_IPFIL_PORTEN_REG_OFST 0x00000af0 2016/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 2017 2018#define FRF_AZ_TX_MADR0_FIL_EN_LBN 64 2019#define FRF_AZ_TX_MADR0_FIL_EN_WIDTH 1 2020#define FRF_AB_TX_IPFIL31_PORT_EN_LBN 62 2021#define FRF_AB_TX_IPFIL31_PORT_EN_WIDTH 1 2022#define FRF_AB_TX_IPFIL30_PORT_EN_LBN 60 2023#define FRF_AB_TX_IPFIL30_PORT_EN_WIDTH 1 2024#define FRF_AB_TX_IPFIL29_PORT_EN_LBN 58 2025#define FRF_AB_TX_IPFIL29_PORT_EN_WIDTH 1 2026#define FRF_AB_TX_IPFIL28_PORT_EN_LBN 56 2027#define FRF_AB_TX_IPFIL28_PORT_EN_WIDTH 1 2028#define FRF_AB_TX_IPFIL27_PORT_EN_LBN 54 2029#define FRF_AB_TX_IPFIL27_PORT_EN_WIDTH 1 2030#define FRF_AB_TX_IPFIL26_PORT_EN_LBN 52 2031#define FRF_AB_TX_IPFIL26_PORT_EN_WIDTH 1 2032#define FRF_AB_TX_IPFIL25_PORT_EN_LBN 50 2033#define FRF_AB_TX_IPFIL25_PORT_EN_WIDTH 1 2034#define FRF_AB_TX_IPFIL24_PORT_EN_LBN 48 2035#define FRF_AB_TX_IPFIL24_PORT_EN_WIDTH 1 2036#define FRF_AB_TX_IPFIL23_PORT_EN_LBN 46 2037#define FRF_AB_TX_IPFIL23_PORT_EN_WIDTH 1 2038#define FRF_AB_TX_IPFIL22_PORT_EN_LBN 44 2039#define FRF_AB_TX_IPFIL22_PORT_EN_WIDTH 1 2040#define FRF_AB_TX_IPFIL21_PORT_EN_LBN 42 2041#define FRF_AB_TX_IPFIL21_PORT_EN_WIDTH 1 2042#define FRF_AB_TX_IPFIL20_PORT_EN_LBN 40 2043#define FRF_AB_TX_IPFIL20_PORT_EN_WIDTH 1 2044#define FRF_AB_TX_IPFIL19_PORT_EN_LBN 38 2045#define FRF_AB_TX_IPFIL19_PORT_EN_WIDTH 1 2046#define FRF_AB_TX_IPFIL18_PORT_EN_LBN 36 2047#define FRF_AB_TX_IPFIL18_PORT_EN_WIDTH 1 2048#define FRF_AB_TX_IPFIL17_PORT_EN_LBN 34 2049#define FRF_AB_TX_IPFIL17_PORT_EN_WIDTH 1 2050#define FRF_AB_TX_IPFIL16_PORT_EN_LBN 32 2051#define FRF_AB_TX_IPFIL16_PORT_EN_WIDTH 1 2052#define FRF_AB_TX_IPFIL15_PORT_EN_LBN 30 2053#define FRF_AB_TX_IPFIL15_PORT_EN_WIDTH 1 2054#define FRF_AB_TX_IPFIL14_PORT_EN_LBN 28 2055#define FRF_AB_TX_IPFIL14_PORT_EN_WIDTH 1 2056#define FRF_AB_TX_IPFIL13_PORT_EN_LBN 26 2057#define FRF_AB_TX_IPFIL13_PORT_EN_WIDTH 1 2058#define FRF_AB_TX_IPFIL12_PORT_EN_LBN 24 2059#define FRF_AB_TX_IPFIL12_PORT_EN_WIDTH 1 2060#define FRF_AB_TX_IPFIL11_PORT_EN_LBN 22 2061#define FRF_AB_TX_IPFIL11_PORT_EN_WIDTH 1 2062#define FRF_AB_TX_IPFIL10_PORT_EN_LBN 20 2063#define FRF_AB_TX_IPFIL10_PORT_EN_WIDTH 1 2064#define FRF_AB_TX_IPFIL9_PORT_EN_LBN 18 2065#define FRF_AB_TX_IPFIL9_PORT_EN_WIDTH 1 2066#define FRF_AB_TX_IPFIL8_PORT_EN_LBN 16 2067#define FRF_AB_TX_IPFIL8_PORT_EN_WIDTH 1 2068#define FRF_AB_TX_IPFIL7_PORT_EN_LBN 14 2069#define FRF_AB_TX_IPFIL7_PORT_EN_WIDTH 1 2070#define FRF_AB_TX_IPFIL6_PORT_EN_LBN 12 2071#define FRF_AB_TX_IPFIL6_PORT_EN_WIDTH 1 2072#define FRF_AB_TX_IPFIL5_PORT_EN_LBN 10 2073#define FRF_AB_TX_IPFIL5_PORT_EN_WIDTH 1 2074#define FRF_AB_TX_IPFIL4_PORT_EN_LBN 8 2075#define FRF_AB_TX_IPFIL4_PORT_EN_WIDTH 1 2076#define FRF_AB_TX_IPFIL3_PORT_EN_LBN 6 2077#define FRF_AB_TX_IPFIL3_PORT_EN_WIDTH 1 2078#define FRF_AB_TX_IPFIL2_PORT_EN_LBN 4 2079#define FRF_AB_TX_IPFIL2_PORT_EN_WIDTH 1 2080#define FRF_AB_TX_IPFIL1_PORT_EN_LBN 2 2081#define FRF_AB_TX_IPFIL1_PORT_EN_WIDTH 1 2082#define FRF_AB_TX_IPFIL0_PORT_EN_LBN 0 2083#define FRF_AB_TX_IPFIL0_PORT_EN_WIDTH 1 2084 2085 2086/* 2087 * FR_AB_TX_IPFIL_TBL(128bit): 2088 * Transmit IP source address filter table 2089 */ 2090#define FR_AB_TX_IPFIL_TBL_OFST 0x00000b00 2091/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2092#define FR_AB_TX_IPFIL_TBL_STEP 16 2093#define FR_AB_TX_IPFIL_TBL_ROWS 16 2094 2095#define FRF_AB_TX_IPFIL_MASK_1_LBN 96 2096#define FRF_AB_TX_IPFIL_MASK_1_WIDTH 32 2097#define FRF_AB_TX_IP_SRC_ADR_1_LBN 64 2098#define FRF_AB_TX_IP_SRC_ADR_1_WIDTH 32 2099#define FRF_AB_TX_IPFIL_MASK_0_LBN 32 2100#define FRF_AB_TX_IPFIL_MASK_0_WIDTH 32 2101#define FRF_AB_TX_IP_SRC_ADR_0_LBN 0 2102#define FRF_AB_TX_IP_SRC_ADR_0_WIDTH 32 2103 2104 2105/* 2106 * FR_AB_MD_TXD_REG(128bit): 2107 * PHY management transmit data register 2108 */ 2109#define FR_AB_MD_TXD_REG_OFST 0x00000c00 2110/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2111 2112#define FRF_AB_MD_TXD_LBN 0 2113#define FRF_AB_MD_TXD_WIDTH 16 2114 2115 2116/* 2117 * FR_AB_MD_RXD_REG(128bit): 2118 * PHY management receive data register 2119 */ 2120#define FR_AB_MD_RXD_REG_OFST 0x00000c10 2121/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2122 2123#define FRF_AB_MD_RXD_LBN 0 2124#define FRF_AB_MD_RXD_WIDTH 16 2125 2126 2127/* 2128 * FR_AB_MD_CS_REG(128bit): 2129 * PHY management configuration & status register 2130 */ 2131#define FR_AB_MD_CS_REG_OFST 0x00000c20 2132/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2133 2134#define FRF_AB_MD_RD_EN_LBN 15 2135#define FRF_AB_MD_RD_EN_WIDTH 1 2136#define FRF_AB_MD_WR_EN_LBN 14 2137#define FRF_AB_MD_WR_EN_WIDTH 1 2138#define FRF_AB_MD_ADDR_CMD_LBN 13 2139#define FRF_AB_MD_ADDR_CMD_WIDTH 1 2140#define FRF_AB_MD_PT_LBN 7 2141#define FRF_AB_MD_PT_WIDTH 3 2142#define FRF_AB_MD_PL_LBN 6 2143#define FRF_AB_MD_PL_WIDTH 1 2144#define FRF_AB_MD_INT_CLR_LBN 5 2145#define FRF_AB_MD_INT_CLR_WIDTH 1 2146#define FRF_AB_MD_GC_LBN 4 2147#define FRF_AB_MD_GC_WIDTH 1 2148#define FRF_AB_MD_PRSP_LBN 3 2149#define FRF_AB_MD_PRSP_WIDTH 1 2150#define FRF_AB_MD_RIC_LBN 2 2151#define FRF_AB_MD_RIC_WIDTH 1 2152#define FRF_AB_MD_RDC_LBN 1 2153#define FRF_AB_MD_RDC_WIDTH 1 2154#define FRF_AB_MD_WRC_LBN 0 2155#define FRF_AB_MD_WRC_WIDTH 1 2156 2157 2158/* 2159 * FR_AB_MD_PHY_ADR_REG(128bit): 2160 * PHY management PHY address register 2161 */ 2162#define FR_AB_MD_PHY_ADR_REG_OFST 0x00000c30 2163/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2164 2165#define FRF_AB_MD_PHY_ADR_LBN 0 2166#define FRF_AB_MD_PHY_ADR_WIDTH 16 2167 2168 2169/* 2170 * FR_AB_MD_ID_REG(128bit): 2171 * PHY management ID register 2172 */ 2173#define FR_AB_MD_ID_REG_OFST 0x00000c40 2174/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2175 2176#define FRF_AB_MD_PRT_ADR_LBN 11 2177#define FRF_AB_MD_PRT_ADR_WIDTH 5 2178#define FRF_AB_MD_DEV_ADR_LBN 6 2179#define FRF_AB_MD_DEV_ADR_WIDTH 5 2180 2181 2182/* 2183 * FR_AB_MD_STAT_REG(128bit): 2184 * PHY management status & mask register 2185 */ 2186#define FR_AB_MD_STAT_REG_OFST 0x00000c50 2187/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2188 2189#define FRF_AB_MD_PINT_LBN 4 2190#define FRF_AB_MD_PINT_WIDTH 1 2191#define FRF_AB_MD_DONE_LBN 3 2192#define FRF_AB_MD_DONE_WIDTH 1 2193#define FRF_AB_MD_BSERR_LBN 2 2194#define FRF_AB_MD_BSERR_WIDTH 1 2195#define FRF_AB_MD_LNFL_LBN 1 2196#define FRF_AB_MD_LNFL_WIDTH 1 2197#define FRF_AB_MD_BSY_LBN 0 2198#define FRF_AB_MD_BSY_WIDTH 1 2199 2200 2201/* 2202 * FR_AB_MAC_STAT_DMA_REG(128bit): 2203 * Port MAC statistical counter DMA register 2204 */ 2205#define FR_AB_MAC_STAT_DMA_REG_OFST 0x00000c60 2206/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2207 2208#define FRF_AB_MAC_STAT_DMA_CMD_LBN 48 2209#define FRF_AB_MAC_STAT_DMA_CMD_WIDTH 1 2210#define FRF_AB_MAC_STAT_DMA_ADR_LBN 0 2211#define FRF_AB_MAC_STAT_DMA_ADR_WIDTH 48 2212#define FRF_AB_MAC_STAT_DMA_ADR_DW0_LBN 0 2213#define FRF_AB_MAC_STAT_DMA_ADR_DW0_WIDTH 32 2214#define FRF_AB_MAC_STAT_DMA_ADR_DW1_LBN 32 2215#define FRF_AB_MAC_STAT_DMA_ADR_DW1_WIDTH 16 2216 2217 2218/* 2219 * FR_AB_MAC_CTRL_REG(128bit): 2220 * Port MAC control register 2221 */ 2222#define FR_AB_MAC_CTRL_REG_OFST 0x00000c80 2223/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2224 2225#define FRF_AB_MAC_XOFF_VAL_LBN 16 2226#define FRF_AB_MAC_XOFF_VAL_WIDTH 16 2227#define FRF_BB_TXFIFO_DRAIN_EN_LBN 7 2228#define FRF_BB_TXFIFO_DRAIN_EN_WIDTH 1 2229#define FRF_AB_MAC_XG_DISTXCRC_LBN 5 2230#define FRF_AB_MAC_XG_DISTXCRC_WIDTH 1 2231#define FRF_AB_MAC_BCAD_ACPT_LBN 4 2232#define FRF_AB_MAC_BCAD_ACPT_WIDTH 1 2233#define FRF_AB_MAC_UC_PROM_LBN 3 2234#define FRF_AB_MAC_UC_PROM_WIDTH 1 2235#define FRF_AB_MAC_LINK_STATUS_LBN 2 2236#define FRF_AB_MAC_LINK_STATUS_WIDTH 1 2237#define FRF_AB_MAC_SPEED_LBN 0 2238#define FRF_AB_MAC_SPEED_WIDTH 2 2239#define FRF_AB_MAC_SPEED_10M 0 2240#define FRF_AB_MAC_SPEED_100M 1 2241#define FRF_AB_MAC_SPEED_1G 2 2242#define FRF_AB_MAC_SPEED_10G 3 2243 2244/* 2245 * FR_BB_GEN_MODE_REG(128bit): 2246 * General Purpose mode register (external interrupt mask) 2247 */ 2248#define FR_BB_GEN_MODE_REG_OFST 0x00000c90 2249/* falconb0=net_func_bar2 */ 2250 2251#define FRF_BB_XFP_PHY_INT_POL_SEL_LBN 3 2252#define FRF_BB_XFP_PHY_INT_POL_SEL_WIDTH 1 2253#define FRF_BB_XG_PHY_INT_POL_SEL_LBN 2 2254#define FRF_BB_XG_PHY_INT_POL_SEL_WIDTH 1 2255#define FRF_BB_XFP_PHY_INT_MASK_LBN 1 2256#define FRF_BB_XFP_PHY_INT_MASK_WIDTH 1 2257#define FRF_BB_XG_PHY_INT_MASK_LBN 0 2258#define FRF_BB_XG_PHY_INT_MASK_WIDTH 1 2259 2260 2261/* 2262 * FR_AB_MAC_MC_HASH_REG0(128bit): 2263 * Multicast address hash table 2264 */ 2265#define FR_AB_MAC_MC_HASH0_REG_OFST 0x00000ca0 2266/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2267 2268#define FRF_AB_MAC_MCAST_HASH0_LBN 0 2269#define FRF_AB_MAC_MCAST_HASH0_WIDTH 128 2270#define FRF_AB_MAC_MCAST_HASH0_DW0_LBN 0 2271#define FRF_AB_MAC_MCAST_HASH0_DW0_WIDTH 32 2272#define FRF_AB_MAC_MCAST_HASH0_DW1_LBN 32 2273#define FRF_AB_MAC_MCAST_HASH0_DW1_WIDTH 32 2274#define FRF_AB_MAC_MCAST_HASH0_DW2_LBN 64 2275#define FRF_AB_MAC_MCAST_HASH0_DW2_WIDTH 32 2276#define FRF_AB_MAC_MCAST_HASH0_DW3_LBN 96 2277#define FRF_AB_MAC_MCAST_HASH0_DW3_WIDTH 32 2278 2279 2280/* 2281 * FR_AB_MAC_MC_HASH_REG1(128bit): 2282 * Multicast address hash table 2283 */ 2284#define FR_AB_MAC_MC_HASH1_REG_OFST 0x00000cb0 2285/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2286 2287#define FRF_AB_MAC_MCAST_HASH1_LBN 0 2288#define FRF_AB_MAC_MCAST_HASH1_WIDTH 128 2289#define FRF_AB_MAC_MCAST_HASH1_DW0_LBN 0 2290#define FRF_AB_MAC_MCAST_HASH1_DW0_WIDTH 32 2291#define FRF_AB_MAC_MCAST_HASH1_DW1_LBN 32 2292#define FRF_AB_MAC_MCAST_HASH1_DW1_WIDTH 32 2293#define FRF_AB_MAC_MCAST_HASH1_DW2_LBN 64 2294#define FRF_AB_MAC_MCAST_HASH1_DW2_WIDTH 32 2295#define FRF_AB_MAC_MCAST_HASH1_DW3_LBN 96 2296#define FRF_AB_MAC_MCAST_HASH1_DW3_WIDTH 32 2297 2298 2299/* 2300 * FR_AB_GM_CFG1_REG(32bit): 2301 * GMAC configuration register 1 2302 */ 2303#define FR_AB_GM_CFG1_REG_OFST 0x00000e00 2304/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2305 2306#define FRF_AB_GM_SW_RST_LBN 31 2307#define FRF_AB_GM_SW_RST_WIDTH 1 2308#define FRF_AB_GM_SIM_RST_LBN 30 2309#define FRF_AB_GM_SIM_RST_WIDTH 1 2310#define FRF_AB_GM_RST_RX_MAC_CTL_LBN 19 2311#define FRF_AB_GM_RST_RX_MAC_CTL_WIDTH 1 2312#define FRF_AB_GM_RST_TX_MAC_CTL_LBN 18 2313#define FRF_AB_GM_RST_TX_MAC_CTL_WIDTH 1 2314#define FRF_AB_GM_RST_RX_FUNC_LBN 17 2315#define FRF_AB_GM_RST_RX_FUNC_WIDTH 1 2316#define FRF_AB_GM_RST_TX_FUNC_LBN 16 2317#define FRF_AB_GM_RST_TX_FUNC_WIDTH 1 2318#define FRF_AB_GM_LOOP_LBN 8 2319#define FRF_AB_GM_LOOP_WIDTH 1 2320#define FRF_AB_GM_RX_FC_EN_LBN 5 2321#define FRF_AB_GM_RX_FC_EN_WIDTH 1 2322#define FRF_AB_GM_TX_FC_EN_LBN 4 2323#define FRF_AB_GM_TX_FC_EN_WIDTH 1 2324#define FRF_AB_GM_SYNC_RXEN_LBN 3 2325#define FRF_AB_GM_SYNC_RXEN_WIDTH 1 2326#define FRF_AB_GM_RX_EN_LBN 2 2327#define FRF_AB_GM_RX_EN_WIDTH 1 2328#define FRF_AB_GM_SYNC_TXEN_LBN 1 2329#define FRF_AB_GM_SYNC_TXEN_WIDTH 1 2330#define FRF_AB_GM_TX_EN_LBN 0 2331#define FRF_AB_GM_TX_EN_WIDTH 1 2332 2333 2334/* 2335 * FR_AB_GM_CFG2_REG(32bit): 2336 * GMAC configuration register 2 2337 */ 2338#define FR_AB_GM_CFG2_REG_OFST 0x00000e10 2339/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2340 2341#define FRF_AB_GM_PAMBL_LEN_LBN 12 2342#define FRF_AB_GM_PAMBL_LEN_WIDTH 4 2343#define FRF_AB_GM_IF_MODE_LBN 8 2344#define FRF_AB_GM_IF_MODE_WIDTH 2 2345#define FRF_AB_GM_IF_MODE_BYTE_MODE 2 2346#define FRF_AB_GM_IF_MODE_NIBBLE_MODE 1 2347#define FRF_AB_GM_HUGE_FRM_EN_LBN 5 2348#define FRF_AB_GM_HUGE_FRM_EN_WIDTH 1 2349#define FRF_AB_GM_LEN_CHK_LBN 4 2350#define FRF_AB_GM_LEN_CHK_WIDTH 1 2351#define FRF_AB_GM_PAD_CRC_EN_LBN 2 2352#define FRF_AB_GM_PAD_CRC_EN_WIDTH 1 2353#define FRF_AB_GM_CRC_EN_LBN 1 2354#define FRF_AB_GM_CRC_EN_WIDTH 1 2355#define FRF_AB_GM_FD_LBN 0 2356#define FRF_AB_GM_FD_WIDTH 1 2357 2358 2359/* 2360 * FR_AB_GM_IPG_REG(32bit): 2361 * GMAC IPG register 2362 */ 2363#define FR_AB_GM_IPG_REG_OFST 0x00000e20 2364/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2365 2366#define FRF_AB_GM_NONB2B_IPG1_LBN 24 2367#define FRF_AB_GM_NONB2B_IPG1_WIDTH 7 2368#define FRF_AB_GM_NONB2B_IPG2_LBN 16 2369#define FRF_AB_GM_NONB2B_IPG2_WIDTH 7 2370#define FRF_AB_GM_MIN_IPG_ENF_LBN 8 2371#define FRF_AB_GM_MIN_IPG_ENF_WIDTH 8 2372#define FRF_AB_GM_B2B_IPG_LBN 0 2373#define FRF_AB_GM_B2B_IPG_WIDTH 7 2374 2375 2376/* 2377 * FR_AB_GM_HD_REG(32bit): 2378 * GMAC half duplex register 2379 */ 2380#define FR_AB_GM_HD_REG_OFST 0x00000e30 2381/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2382 2383#define FRF_AB_GM_ALT_BOFF_VAL_LBN 20 2384#define FRF_AB_GM_ALT_BOFF_VAL_WIDTH 4 2385#define FRF_AB_GM_ALT_BOFF_EN_LBN 19 2386#define FRF_AB_GM_ALT_BOFF_EN_WIDTH 1 2387#define FRF_AB_GM_BP_NO_BOFF_LBN 18 2388#define FRF_AB_GM_BP_NO_BOFF_WIDTH 1 2389#define FRF_AB_GM_DIS_BOFF_LBN 17 2390#define FRF_AB_GM_DIS_BOFF_WIDTH 1 2391#define FRF_AB_GM_EXDEF_TX_EN_LBN 16 2392#define FRF_AB_GM_EXDEF_TX_EN_WIDTH 1 2393#define FRF_AB_GM_RTRY_LIMIT_LBN 12 2394#define FRF_AB_GM_RTRY_LIMIT_WIDTH 4 2395#define FRF_AB_GM_COL_WIN_LBN 0 2396#define FRF_AB_GM_COL_WIN_WIDTH 10 2397 2398 2399/* 2400 * FR_AB_GM_MAX_FLEN_REG(32bit): 2401 * GMAC maximum frame length register 2402 */ 2403#define FR_AB_GM_MAX_FLEN_REG_OFST 0x00000e40 2404/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2405 2406#define FRF_AB_GM_MAX_FLEN_LBN 0 2407#define FRF_AB_GM_MAX_FLEN_WIDTH 16 2408 2409 2410/* 2411 * FR_AB_GM_TEST_REG(32bit): 2412 * GMAC test register 2413 */ 2414#define FR_AB_GM_TEST_REG_OFST 0x00000e70 2415/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2416 2417#define FRF_AB_GM_MAX_BOFF_LBN 3 2418#define FRF_AB_GM_MAX_BOFF_WIDTH 1 2419#define FRF_AB_GM_REG_TX_FLOW_EN_LBN 2 2420#define FRF_AB_GM_REG_TX_FLOW_EN_WIDTH 1 2421#define FRF_AB_GM_TEST_PAUSE_LBN 1 2422#define FRF_AB_GM_TEST_PAUSE_WIDTH 1 2423#define FRF_AB_GM_SHORT_SLOT_LBN 0 2424#define FRF_AB_GM_SHORT_SLOT_WIDTH 1 2425 2426 2427/* 2428 * FR_AB_GM_ADR1_REG(32bit): 2429 * GMAC station address register 1 2430 */ 2431#define FR_AB_GM_ADR1_REG_OFST 0x00000f00 2432/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2433 2434#define FRF_AB_GM_ADR_B0_LBN 24 2435#define FRF_AB_GM_ADR_B0_WIDTH 8 2436#define FRF_AB_GM_ADR_B1_LBN 16 2437#define FRF_AB_GM_ADR_B1_WIDTH 8 2438#define FRF_AB_GM_ADR_B2_LBN 8 2439#define FRF_AB_GM_ADR_B2_WIDTH 8 2440#define FRF_AB_GM_ADR_B3_LBN 0 2441#define FRF_AB_GM_ADR_B3_WIDTH 8 2442 2443 2444/* 2445 * FR_AB_GM_ADR2_REG(32bit): 2446 * GMAC station address register 2 2447 */ 2448#define FR_AB_GM_ADR2_REG_OFST 0x00000f10 2449/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2450 2451#define FRF_AB_GM_ADR_B4_LBN 24 2452#define FRF_AB_GM_ADR_B4_WIDTH 8 2453#define FRF_AB_GM_ADR_B5_LBN 16 2454#define FRF_AB_GM_ADR_B5_WIDTH 8 2455 2456 2457/* 2458 * FR_AB_GMF_CFG0_REG(32bit): 2459 * GMAC FIFO configuration register 0 2460 */ 2461#define FR_AB_GMF_CFG0_REG_OFST 0x00000f20 2462/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2463 2464#define FRF_AB_GMF_FTFENRPLY_LBN 20 2465#define FRF_AB_GMF_FTFENRPLY_WIDTH 1 2466#define FRF_AB_GMF_STFENRPLY_LBN 19 2467#define FRF_AB_GMF_STFENRPLY_WIDTH 1 2468#define FRF_AB_GMF_FRFENRPLY_LBN 18 2469#define FRF_AB_GMF_FRFENRPLY_WIDTH 1 2470#define FRF_AB_GMF_SRFENRPLY_LBN 17 2471#define FRF_AB_GMF_SRFENRPLY_WIDTH 1 2472#define FRF_AB_GMF_WTMENRPLY_LBN 16 2473#define FRF_AB_GMF_WTMENRPLY_WIDTH 1 2474#define FRF_AB_GMF_FTFENREQ_LBN 12 2475#define FRF_AB_GMF_FTFENREQ_WIDTH 1 2476#define FRF_AB_GMF_STFENREQ_LBN 11 2477#define FRF_AB_GMF_STFENREQ_WIDTH 1 2478#define FRF_AB_GMF_FRFENREQ_LBN 10 2479#define FRF_AB_GMF_FRFENREQ_WIDTH 1 2480#define FRF_AB_GMF_SRFENREQ_LBN 9 2481#define FRF_AB_GMF_SRFENREQ_WIDTH 1 2482#define FRF_AB_GMF_WTMENREQ_LBN 8 2483#define FRF_AB_GMF_WTMENREQ_WIDTH 1 2484#define FRF_AB_GMF_HSTRSTFT_LBN 4 2485#define FRF_AB_GMF_HSTRSTFT_WIDTH 1 2486#define FRF_AB_GMF_HSTRSTST_LBN 3 2487#define FRF_AB_GMF_HSTRSTST_WIDTH 1 2488#define FRF_AB_GMF_HSTRSTFR_LBN 2 2489#define FRF_AB_GMF_HSTRSTFR_WIDTH 1 2490#define FRF_AB_GMF_HSTRSTSR_LBN 1 2491#define FRF_AB_GMF_HSTRSTSR_WIDTH 1 2492#define FRF_AB_GMF_HSTRSTWT_LBN 0 2493#define FRF_AB_GMF_HSTRSTWT_WIDTH 1 2494 2495 2496/* 2497 * FR_AB_GMF_CFG1_REG(32bit): 2498 * GMAC FIFO configuration register 1 2499 */ 2500#define FR_AB_GMF_CFG1_REG_OFST 0x00000f30 2501/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2502 2503#define FRF_AB_GMF_CFGFRTH_LBN 16 2504#define FRF_AB_GMF_CFGFRTH_WIDTH 5 2505#define FRF_AB_GMF_CFGXOFFRTX_LBN 0 2506#define FRF_AB_GMF_CFGXOFFRTX_WIDTH 16 2507 2508 2509/* 2510 * FR_AB_GMF_CFG2_REG(32bit): 2511 * GMAC FIFO configuration register 2 2512 */ 2513#define FR_AB_GMF_CFG2_REG_OFST 0x00000f40 2514/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2515 2516#define FRF_AB_GMF_CFGHWM_LBN 16 2517#define FRF_AB_GMF_CFGHWM_WIDTH 6 2518#define FRF_AB_GMF_CFGLWM_LBN 0 2519#define FRF_AB_GMF_CFGLWM_WIDTH 6 2520 2521 2522/* 2523 * FR_AB_GMF_CFG3_REG(32bit): 2524 * GMAC FIFO configuration register 3 2525 */ 2526#define FR_AB_GMF_CFG3_REG_OFST 0x00000f50 2527/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2528 2529#define FRF_AB_GMF_CFGHWMFT_LBN 16 2530#define FRF_AB_GMF_CFGHWMFT_WIDTH 6 2531#define FRF_AB_GMF_CFGFTTH_LBN 0 2532#define FRF_AB_GMF_CFGFTTH_WIDTH 6 2533 2534 2535/* 2536 * FR_AB_GMF_CFG4_REG(32bit): 2537 * GMAC FIFO configuration register 4 2538 */ 2539#define FR_AB_GMF_CFG4_REG_OFST 0x00000f60 2540/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2541 2542#define FRF_AB_GMF_HSTFLTRFRM_LBN 0 2543#define FRF_AB_GMF_HSTFLTRFRM_WIDTH 18 2544 2545 2546/* 2547 * FR_AB_GMF_CFG5_REG(32bit): 2548 * GMAC FIFO configuration register 5 2549 */ 2550#define FR_AB_GMF_CFG5_REG_OFST 0x00000f70 2551/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2552 2553#define FRF_AB_GMF_CFGHDPLX_LBN 22 2554#define FRF_AB_GMF_CFGHDPLX_WIDTH 1 2555#define FRF_AB_GMF_SRFULL_LBN 21 2556#define FRF_AB_GMF_SRFULL_WIDTH 1 2557#define FRF_AB_GMF_HSTSRFULLCLR_LBN 20 2558#define FRF_AB_GMF_HSTSRFULLCLR_WIDTH 1 2559#define FRF_AB_GMF_CFGBYTMODE_LBN 19 2560#define FRF_AB_GMF_CFGBYTMODE_WIDTH 1 2561#define FRF_AB_GMF_HSTDRPLT64_LBN 18 2562#define FRF_AB_GMF_HSTDRPLT64_WIDTH 1 2563#define FRF_AB_GMF_HSTFLTRFRMDC_LBN 0 2564#define FRF_AB_GMF_HSTFLTRFRMDC_WIDTH 18 2565 2566 2567/* 2568 * FR_BB_TX_SRC_MAC_TBL(128bit): 2569 * Transmit IP source address filter table 2570 */ 2571#define FR_BB_TX_SRC_MAC_TBL_OFST 0x00001000 2572/* falconb0=net_func_bar2 */ 2573#define FR_BB_TX_SRC_MAC_TBL_STEP 16 2574#define FR_BB_TX_SRC_MAC_TBL_ROWS 16 2575 2576#define FRF_BB_TX_SRC_MAC_ADR_1_LBN 64 2577#define FRF_BB_TX_SRC_MAC_ADR_1_WIDTH 48 2578#define FRF_BB_TX_SRC_MAC_ADR_1_DW0_LBN 64 2579#define FRF_BB_TX_SRC_MAC_ADR_1_DW0_WIDTH 32 2580#define FRF_BB_TX_SRC_MAC_ADR_1_DW1_LBN 96 2581#define FRF_BB_TX_SRC_MAC_ADR_1_DW1_WIDTH 16 2582#define FRF_BB_TX_SRC_MAC_ADR_0_LBN 0 2583#define FRF_BB_TX_SRC_MAC_ADR_0_WIDTH 48 2584#define FRF_BB_TX_SRC_MAC_ADR_0_DW0_LBN 0 2585#define FRF_BB_TX_SRC_MAC_ADR_0_DW0_WIDTH 32 2586#define FRF_BB_TX_SRC_MAC_ADR_0_DW1_LBN 32 2587#define FRF_BB_TX_SRC_MAC_ADR_0_DW1_WIDTH 16 2588 2589 2590/* 2591 * FR_BB_TX_SRC_MAC_CTL_REG(128bit): 2592 * Transmit MAC source address filter control 2593 */ 2594#define FR_BB_TX_SRC_MAC_CTL_REG_OFST 0x00001100 2595/* falconb0=net_func_bar2 */ 2596 2597#define FRF_BB_TX_SRC_DROP_CTR_LBN 16 2598#define FRF_BB_TX_SRC_DROP_CTR_WIDTH 16 2599#define FRF_BB_TX_SRC_FLTR_EN_LBN 15 2600#define FRF_BB_TX_SRC_FLTR_EN_WIDTH 1 2601#define FRF_BB_TX_DROP_CTR_CLR_LBN 12 2602#define FRF_BB_TX_DROP_CTR_CLR_WIDTH 1 2603#define FRF_BB_TX_MAC_QID_SEL_LBN 0 2604#define FRF_BB_TX_MAC_QID_SEL_WIDTH 3 2605 2606 2607/* 2608 * FR_AB_XM_ADR_LO_REG(128bit): 2609 * XGMAC address register low 2610 */ 2611#define FR_AB_XM_ADR_LO_REG_OFST 0x00001200 2612/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2613 2614#define FRF_AB_XM_ADR_LO_LBN 0 2615#define FRF_AB_XM_ADR_LO_WIDTH 32 2616 2617 2618/* 2619 * FR_AB_XM_ADR_HI_REG(128bit): 2620 * XGMAC address register high 2621 */ 2622#define FR_AB_XM_ADR_HI_REG_OFST 0x00001210 2623/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2624 2625#define FRF_AB_XM_ADR_HI_LBN 0 2626#define FRF_AB_XM_ADR_HI_WIDTH 16 2627 2628 2629/* 2630 * FR_AB_XM_GLB_CFG_REG(128bit): 2631 * XGMAC global configuration 2632 */ 2633#define FR_AB_XM_GLB_CFG_REG_OFST 0x00001220 2634/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2635 2636#define FRF_AB_XM_RMTFLT_GEN_LBN 17 2637#define FRF_AB_XM_RMTFLT_GEN_WIDTH 1 2638#define FRF_AB_XM_DEBUG_MODE_LBN 16 2639#define FRF_AB_XM_DEBUG_MODE_WIDTH 1 2640#define FRF_AB_XM_RX_STAT_EN_LBN 11 2641#define FRF_AB_XM_RX_STAT_EN_WIDTH 1 2642#define FRF_AB_XM_TX_STAT_EN_LBN 10 2643#define FRF_AB_XM_TX_STAT_EN_WIDTH 1 2644#define FRF_AB_XM_RX_JUMBO_MODE_LBN 6 2645#define FRF_AB_XM_RX_JUMBO_MODE_WIDTH 1 2646#define FRF_AB_XM_WAN_MODE_LBN 5 2647#define FRF_AB_XM_WAN_MODE_WIDTH 1 2648#define FRF_AB_XM_INTCLR_MODE_LBN 3 2649#define FRF_AB_XM_INTCLR_MODE_WIDTH 1 2650#define FRF_AB_XM_CORE_RST_LBN 0 2651#define FRF_AB_XM_CORE_RST_WIDTH 1 2652 2653 2654/* 2655 * FR_AB_XM_TX_CFG_REG(128bit): 2656 * XGMAC transmit configuration 2657 */ 2658#define FR_AB_XM_TX_CFG_REG_OFST 0x00001230 2659/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2660 2661#define FRF_AB_XM_TX_PROG_LBN 24 2662#define FRF_AB_XM_TX_PROG_WIDTH 1 2663#define FRF_AB_XM_IPG_LBN 16 2664#define FRF_AB_XM_IPG_WIDTH 4 2665#define FRF_AB_XM_FCNTL_LBN 10 2666#define FRF_AB_XM_FCNTL_WIDTH 1 2667#define FRF_AB_XM_TXCRC_LBN 8 2668#define FRF_AB_XM_TXCRC_WIDTH 1 2669#define FRF_AB_XM_EDRC_LBN 6 2670#define FRF_AB_XM_EDRC_WIDTH 1 2671#define FRF_AB_XM_AUTO_PAD_LBN 5 2672#define FRF_AB_XM_AUTO_PAD_WIDTH 1 2673#define FRF_AB_XM_TX_PRMBL_LBN 2 2674#define FRF_AB_XM_TX_PRMBL_WIDTH 1 2675#define FRF_AB_XM_TXEN_LBN 1 2676#define FRF_AB_XM_TXEN_WIDTH 1 2677#define FRF_AB_XM_TX_RST_LBN 0 2678#define FRF_AB_XM_TX_RST_WIDTH 1 2679 2680 2681/* 2682 * FR_AB_XM_RX_CFG_REG(128bit): 2683 * XGMAC receive configuration 2684 */ 2685#define FR_AB_XM_RX_CFG_REG_OFST 0x00001240 2686/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2687 2688#define FRF_AB_XM_PASS_LENERR_LBN 26 2689#define FRF_AB_XM_PASS_LENERR_WIDTH 1 2690#define FRF_AB_XM_PASS_CRC_ERR_LBN 25 2691#define FRF_AB_XM_PASS_CRC_ERR_WIDTH 1 2692#define FRF_AB_XM_PASS_PRMBLE_ERR_LBN 24 2693#define FRF_AB_XM_PASS_PRMBLE_ERR_WIDTH 1 2694#define FRF_AB_XM_REJ_BCAST_LBN 20 2695#define FRF_AB_XM_REJ_BCAST_WIDTH 1 2696#define FRF_AB_XM_ACPT_ALL_MCAST_LBN 11 2697#define FRF_AB_XM_ACPT_ALL_MCAST_WIDTH 1 2698#define FRF_AB_XM_ACPT_ALL_UCAST_LBN 9 2699#define FRF_AB_XM_ACPT_ALL_UCAST_WIDTH 1 2700#define FRF_AB_XM_AUTO_DEPAD_LBN 8 2701#define FRF_AB_XM_AUTO_DEPAD_WIDTH 1 2702#define FRF_AB_XM_RXCRC_LBN 3 2703#define FRF_AB_XM_RXCRC_WIDTH 1 2704#define FRF_AB_XM_RX_PRMBL_LBN 2 2705#define FRF_AB_XM_RX_PRMBL_WIDTH 1 2706#define FRF_AB_XM_RXEN_LBN 1 2707#define FRF_AB_XM_RXEN_WIDTH 1 2708#define FRF_AB_XM_RX_RST_LBN 0 2709#define FRF_AB_XM_RX_RST_WIDTH 1 2710 2711 2712/* 2713 * FR_AB_XM_MGT_INT_MASK(128bit): 2714 * documentation to be written for sum_XM_MGT_INT_MASK 2715 */ 2716#define FR_AB_XM_MGT_INT_MASK_OFST 0x00001250 2717/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2718 2719#define FRF_AB_XM_MSK_STA_INTR_LBN 16 2720#define FRF_AB_XM_MSK_STA_INTR_WIDTH 1 2721#define FRF_AB_XM_MSK_STAT_CNTR_HF_LBN 9 2722#define FRF_AB_XM_MSK_STAT_CNTR_HF_WIDTH 1 2723#define FRF_AB_XM_MSK_STAT_CNTR_OF_LBN 8 2724#define FRF_AB_XM_MSK_STAT_CNTR_OF_WIDTH 1 2725#define FRF_AB_XM_MSK_PRMBLE_ERR_LBN 2 2726#define FRF_AB_XM_MSK_PRMBLE_ERR_WIDTH 1 2727#define FRF_AB_XM_MSK_RMTFLT_LBN 1 2728#define FRF_AB_XM_MSK_RMTFLT_WIDTH 1 2729#define FRF_AB_XM_MSK_LCLFLT_LBN 0 2730#define FRF_AB_XM_MSK_LCLFLT_WIDTH 1 2731 2732 2733/* 2734 * FR_AB_XM_FC_REG(128bit): 2735 * XGMAC flow control register 2736 */ 2737#define FR_AB_XM_FC_REG_OFST 0x00001270 2738/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2739 2740#define FRF_AB_XM_PAUSE_TIME_LBN 16 2741#define FRF_AB_XM_PAUSE_TIME_WIDTH 16 2742#define FRF_AB_XM_RX_MAC_STAT_LBN 11 2743#define FRF_AB_XM_RX_MAC_STAT_WIDTH 1 2744#define FRF_AB_XM_TX_MAC_STAT_LBN 10 2745#define FRF_AB_XM_TX_MAC_STAT_WIDTH 1 2746#define FRF_AB_XM_MCNTL_PASS_LBN 8 2747#define FRF_AB_XM_MCNTL_PASS_WIDTH 2 2748#define FRF_AB_XM_REJ_CNTL_UCAST_LBN 6 2749#define FRF_AB_XM_REJ_CNTL_UCAST_WIDTH 1 2750#define FRF_AB_XM_REJ_CNTL_MCAST_LBN 5 2751#define FRF_AB_XM_REJ_CNTL_MCAST_WIDTH 1 2752#define FRF_AB_XM_ZPAUSE_LBN 2 2753#define FRF_AB_XM_ZPAUSE_WIDTH 1 2754#define FRF_AB_XM_XMIT_PAUSE_LBN 1 2755#define FRF_AB_XM_XMIT_PAUSE_WIDTH 1 2756#define FRF_AB_XM_DIS_FCNTL_LBN 0 2757#define FRF_AB_XM_DIS_FCNTL_WIDTH 1 2758 2759 2760/* 2761 * FR_AB_XM_PAUSE_TIME_REG(128bit): 2762 * XGMAC pause time register 2763 */ 2764#define FR_AB_XM_PAUSE_TIME_REG_OFST 0x00001290 2765/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2766 2767#define FRF_AB_XM_TX_PAUSE_CNT_LBN 16 2768#define FRF_AB_XM_TX_PAUSE_CNT_WIDTH 16 2769#define FRF_AB_XM_RX_PAUSE_CNT_LBN 0 2770#define FRF_AB_XM_RX_PAUSE_CNT_WIDTH 16 2771 2772 2773/* 2774 * FR_AB_XM_TX_PARAM_REG(128bit): 2775 * XGMAC transmit parameter register 2776 */ 2777#define FR_AB_XM_TX_PARAM_REG_OFST 0x000012d0 2778/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2779 2780#define FRF_AB_XM_TX_JUMBO_MODE_LBN 31 2781#define FRF_AB_XM_TX_JUMBO_MODE_WIDTH 1 2782#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_LBN 19 2783#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH 11 2784#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN 16 2785#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH 3 2786#define FRF_AB_XM_PAD_CHAR_LBN 0 2787#define FRF_AB_XM_PAD_CHAR_WIDTH 8 2788 2789 2790/* 2791 * FR_AB_XM_RX_PARAM_REG(128bit): 2792 * XGMAC receive parameter register 2793 */ 2794#define FR_AB_XM_RX_PARAM_REG_OFST 0x000012e0 2795/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2796 2797#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_LBN 3 2798#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH 11 2799#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN 0 2800#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH 3 2801 2802 2803/* 2804 * FR_AB_XM_MGT_INT_MSK_REG(128bit): 2805 * XGMAC management interrupt mask register 2806 */ 2807#define FR_AB_XM_MGT_INT_REG_OFST 0x000012f0 2808/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2809 2810#define FRF_AB_XM_STAT_CNTR_OF_LBN 9 2811#define FRF_AB_XM_STAT_CNTR_OF_WIDTH 1 2812#define FRF_AB_XM_STAT_CNTR_HF_LBN 8 2813#define FRF_AB_XM_STAT_CNTR_HF_WIDTH 1 2814#define FRF_AB_XM_PRMBLE_ERR_LBN 2 2815#define FRF_AB_XM_PRMBLE_ERR_WIDTH 1 2816#define FRF_AB_XM_RMTFLT_LBN 1 2817#define FRF_AB_XM_RMTFLT_WIDTH 1 2818#define FRF_AB_XM_LCLFLT_LBN 0 2819#define FRF_AB_XM_LCLFLT_WIDTH 1 2820 2821 2822/* 2823 * FR_AB_XX_PWR_RST_REG(128bit): 2824 * XGXS/XAUI powerdown/reset register 2825 */ 2826#define FR_AB_XX_PWR_RST_REG_OFST 0x00001300 2827/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2828 2829#define FRF_AB_XX_PWRDND_SIG_LBN 31 2830#define FRF_AB_XX_PWRDND_SIG_WIDTH 1 2831#define FRF_AB_XX_PWRDNC_SIG_LBN 30 2832#define FRF_AB_XX_PWRDNC_SIG_WIDTH 1 2833#define FRF_AB_XX_PWRDNB_SIG_LBN 29 2834#define FRF_AB_XX_PWRDNB_SIG_WIDTH 1 2835#define FRF_AB_XX_PWRDNA_SIG_LBN 28 2836#define FRF_AB_XX_PWRDNA_SIG_WIDTH 1 2837#define FRF_AB_XX_SIM_MODE_LBN 27 2838#define FRF_AB_XX_SIM_MODE_WIDTH 1 2839#define FRF_AB_XX_RSTPLLCD_SIG_LBN 25 2840#define FRF_AB_XX_RSTPLLCD_SIG_WIDTH 1 2841#define FRF_AB_XX_RSTPLLAB_SIG_LBN 24 2842#define FRF_AB_XX_RSTPLLAB_SIG_WIDTH 1 2843#define FRF_AB_XX_RESETD_SIG_LBN 23 2844#define FRF_AB_XX_RESETD_SIG_WIDTH 1 2845#define FRF_AB_XX_RESETC_SIG_LBN 22 2846#define FRF_AB_XX_RESETC_SIG_WIDTH 1 2847#define FRF_AB_XX_RESETB_SIG_LBN 21 2848#define FRF_AB_XX_RESETB_SIG_WIDTH 1 2849#define FRF_AB_XX_RESETA_SIG_LBN 20 2850#define FRF_AB_XX_RESETA_SIG_WIDTH 1 2851#define FRF_AB_XX_RSTXGXSRX_SIG_LBN 18 2852#define FRF_AB_XX_RSTXGXSRX_SIG_WIDTH 1 2853#define FRF_AB_XX_RSTXGXSTX_SIG_LBN 17 2854#define FRF_AB_XX_RSTXGXSTX_SIG_WIDTH 1 2855#define FRF_AB_XX_SD_RST_ACT_LBN 16 2856#define FRF_AB_XX_SD_RST_ACT_WIDTH 1 2857#define FRF_AB_XX_PWRDND_EN_LBN 15 2858#define FRF_AB_XX_PWRDND_EN_WIDTH 1 2859#define FRF_AB_XX_PWRDNC_EN_LBN 14 2860#define FRF_AB_XX_PWRDNC_EN_WIDTH 1 2861#define FRF_AB_XX_PWRDNB_EN_LBN 13 2862#define FRF_AB_XX_PWRDNB_EN_WIDTH 1 2863#define FRF_AB_XX_PWRDNA_EN_LBN 12 2864#define FRF_AB_XX_PWRDNA_EN_WIDTH 1 2865#define FRF_AB_XX_RSTPLLCD_EN_LBN 9 2866#define FRF_AB_XX_RSTPLLCD_EN_WIDTH 1 2867#define FRF_AB_XX_RSTPLLAB_EN_LBN 8 2868#define FRF_AB_XX_RSTPLLAB_EN_WIDTH 1 2869#define FRF_AB_XX_RESETD_EN_LBN 7 2870#define FRF_AB_XX_RESETD_EN_WIDTH 1 2871#define FRF_AB_XX_RESETC_EN_LBN 6 2872#define FRF_AB_XX_RESETC_EN_WIDTH 1 2873#define FRF_AB_XX_RESETB_EN_LBN 5 2874#define FRF_AB_XX_RESETB_EN_WIDTH 1 2875#define FRF_AB_XX_RESETA_EN_LBN 4 2876#define FRF_AB_XX_RESETA_EN_WIDTH 1 2877#define FRF_AB_XX_RSTXGXSRX_EN_LBN 2 2878#define FRF_AB_XX_RSTXGXSRX_EN_WIDTH 1 2879#define FRF_AB_XX_RSTXGXSTX_EN_LBN 1 2880#define FRF_AB_XX_RSTXGXSTX_EN_WIDTH 1 2881#define FRF_AB_XX_RST_XX_EN_LBN 0 2882#define FRF_AB_XX_RST_XX_EN_WIDTH 1 2883 2884 2885/* 2886 * FR_AB_XX_SD_CTL_REG(128bit): 2887 * XGXS/XAUI powerdown/reset control register 2888 */ 2889#define FR_AB_XX_SD_CTL_REG_OFST 0x00001310 2890/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2891 2892#define FRF_AB_XX_TERMADJ1_LBN 17 2893#define FRF_AB_XX_TERMADJ1_WIDTH 1 2894#define FRF_AB_XX_TERMADJ0_LBN 16 2895#define FRF_AB_XX_TERMADJ0_WIDTH 1 2896#define FRF_AB_XX_HIDRVD_LBN 15 2897#define FRF_AB_XX_HIDRVD_WIDTH 1 2898#define FRF_AB_XX_LODRVD_LBN 14 2899#define FRF_AB_XX_LODRVD_WIDTH 1 2900#define FRF_AB_XX_HIDRVC_LBN 13 2901#define FRF_AB_XX_HIDRVC_WIDTH 1 2902#define FRF_AB_XX_LODRVC_LBN 12 2903#define FRF_AB_XX_LODRVC_WIDTH 1 2904#define FRF_AB_XX_HIDRVB_LBN 11 2905#define FRF_AB_XX_HIDRVB_WIDTH 1 2906#define FRF_AB_XX_LODRVB_LBN 10 2907#define FRF_AB_XX_LODRVB_WIDTH 1 2908#define FRF_AB_XX_HIDRVA_LBN 9 2909#define FRF_AB_XX_HIDRVA_WIDTH 1 2910#define FRF_AB_XX_LODRVA_LBN 8 2911#define FRF_AB_XX_LODRVA_WIDTH 1 2912#define FRF_AB_XX_LPBKD_LBN 3 2913#define FRF_AB_XX_LPBKD_WIDTH 1 2914#define FRF_AB_XX_LPBKC_LBN 2 2915#define FRF_AB_XX_LPBKC_WIDTH 1 2916#define FRF_AB_XX_LPBKB_LBN 1 2917#define FRF_AB_XX_LPBKB_WIDTH 1 2918#define FRF_AB_XX_LPBKA_LBN 0 2919#define FRF_AB_XX_LPBKA_WIDTH 1 2920 2921 2922/* 2923 * FR_AB_XX_TXDRV_CTL_REG(128bit): 2924 * XAUI SerDes transmit drive control register 2925 */ 2926#define FR_AB_XX_TXDRV_CTL_REG_OFST 0x00001320 2927/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2928 2929#define FRF_AB_XX_DEQD_LBN 28 2930#define FRF_AB_XX_DEQD_WIDTH 4 2931#define FRF_AB_XX_DEQC_LBN 24 2932#define FRF_AB_XX_DEQC_WIDTH 4 2933#define FRF_AB_XX_DEQB_LBN 20 2934#define FRF_AB_XX_DEQB_WIDTH 4 2935#define FRF_AB_XX_DEQA_LBN 16 2936#define FRF_AB_XX_DEQA_WIDTH 4 2937#define FRF_AB_XX_DTXD_LBN 12 2938#define FRF_AB_XX_DTXD_WIDTH 4 2939#define FRF_AB_XX_DTXC_LBN 8 2940#define FRF_AB_XX_DTXC_WIDTH 4 2941#define FRF_AB_XX_DTXB_LBN 4 2942#define FRF_AB_XX_DTXB_WIDTH 4 2943#define FRF_AB_XX_DTXA_LBN 0 2944#define FRF_AB_XX_DTXA_WIDTH 4 2945 2946 2947/* 2948 * FR_AB_XX_PRBS_CTL_REG(128bit): 2949 * documentation to be written for sum_XX_PRBS_CTL_REG 2950 */ 2951#define FR_AB_XX_PRBS_CTL_REG_OFST 0x00001330 2952/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2953 2954#define FRF_AB_XX_CH3_RX_PRBS_SEL_LBN 30 2955#define FRF_AB_XX_CH3_RX_PRBS_SEL_WIDTH 2 2956#define FRF_AB_XX_CH3_RX_PRBS_INV_LBN 29 2957#define FRF_AB_XX_CH3_RX_PRBS_INV_WIDTH 1 2958#define FRF_AB_XX_CH3_RX_PRBS_CHKEN_LBN 28 2959#define FRF_AB_XX_CH3_RX_PRBS_CHKEN_WIDTH 1 2960#define FRF_AB_XX_CH2_RX_PRBS_SEL_LBN 26 2961#define FRF_AB_XX_CH2_RX_PRBS_SEL_WIDTH 2 2962#define FRF_AB_XX_CH2_RX_PRBS_INV_LBN 25 2963#define FRF_AB_XX_CH2_RX_PRBS_INV_WIDTH 1 2964#define FRF_AB_XX_CH2_RX_PRBS_CHKEN_LBN 24 2965#define FRF_AB_XX_CH2_RX_PRBS_CHKEN_WIDTH 1 2966#define FRF_AB_XX_CH1_RX_PRBS_SEL_LBN 22 2967#define FRF_AB_XX_CH1_RX_PRBS_SEL_WIDTH 2 2968#define FRF_AB_XX_CH1_RX_PRBS_INV_LBN 21 2969#define FRF_AB_XX_CH1_RX_PRBS_INV_WIDTH 1 2970#define FRF_AB_XX_CH1_RX_PRBS_CHKEN_LBN 20 2971#define FRF_AB_XX_CH1_RX_PRBS_CHKEN_WIDTH 1 2972#define FRF_AB_XX_CH0_RX_PRBS_SEL_LBN 18 2973#define FRF_AB_XX_CH0_RX_PRBS_SEL_WIDTH 2 2974#define FRF_AB_XX_CH0_RX_PRBS_INV_LBN 17 2975#define FRF_AB_XX_CH0_RX_PRBS_INV_WIDTH 1 2976#define FRF_AB_XX_CH0_RX_PRBS_CHKEN_LBN 16 2977#define FRF_AB_XX_CH0_RX_PRBS_CHKEN_WIDTH 1 2978#define FRF_AB_XX_CH3_TX_PRBS_SEL_LBN 14 2979#define FRF_AB_XX_CH3_TX_PRBS_SEL_WIDTH 2 2980#define FRF_AB_XX_CH3_TX_PRBS_INV_LBN 13 2981#define FRF_AB_XX_CH3_TX_PRBS_INV_WIDTH 1 2982#define FRF_AB_XX_CH3_TX_PRBS_CHKEN_LBN 12 2983#define FRF_AB_XX_CH3_TX_PRBS_CHKEN_WIDTH 1 2984#define FRF_AB_XX_CH2_TX_PRBS_SEL_LBN 10 2985#define FRF_AB_XX_CH2_TX_PRBS_SEL_WIDTH 2 2986#define FRF_AB_XX_CH2_TX_PRBS_INV_LBN 9 2987#define FRF_AB_XX_CH2_TX_PRBS_INV_WIDTH 1 2988#define FRF_AB_XX_CH2_TX_PRBS_CHKEN_LBN 8 2989#define FRF_AB_XX_CH2_TX_PRBS_CHKEN_WIDTH 1 2990#define FRF_AB_XX_CH1_TX_PRBS_SEL_LBN 6 2991#define FRF_AB_XX_CH1_TX_PRBS_SEL_WIDTH 2 2992#define FRF_AB_XX_CH1_TX_PRBS_INV_LBN 5 2993#define FRF_AB_XX_CH1_TX_PRBS_INV_WIDTH 1 2994#define FRF_AB_XX_CH1_TX_PRBS_CHKEN_LBN 4 2995#define FRF_AB_XX_CH1_TX_PRBS_CHKEN_WIDTH 1 2996#define FRF_AB_XX_CH0_TX_PRBS_SEL_LBN 2 2997#define FRF_AB_XX_CH0_TX_PRBS_SEL_WIDTH 2 2998#define FRF_AB_XX_CH0_TX_PRBS_INV_LBN 1 2999#define FRF_AB_XX_CH0_TX_PRBS_INV_WIDTH 1 3000#define FRF_AB_XX_CH0_TX_PRBS_CHKEN_LBN 0 3001#define FRF_AB_XX_CH0_TX_PRBS_CHKEN_WIDTH 1 3002 3003 3004/* 3005 * FR_AB_XX_PRBS_CHK_REG(128bit): 3006 * documentation to be written for sum_XX_PRBS_CHK_REG 3007 */ 3008#define FR_AB_XX_PRBS_CHK_REG_OFST 0x00001340 3009/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3010 3011#define FRF_AB_XX_REV_LB_EN_LBN 16 3012#define FRF_AB_XX_REV_LB_EN_WIDTH 1 3013#define FRF_AB_XX_CH3_DEG_DET_LBN 15 3014#define FRF_AB_XX_CH3_DEG_DET_WIDTH 1 3015#define FRF_AB_XX_CH3_LFSR_LOCK_IND_LBN 14 3016#define FRF_AB_XX_CH3_LFSR_LOCK_IND_WIDTH 1 3017#define FRF_AB_XX_CH3_PRBS_FRUN_LBN 13 3018#define FRF_AB_XX_CH3_PRBS_FRUN_WIDTH 1 3019#define FRF_AB_XX_CH3_ERR_CHK_LBN 12 3020#define FRF_AB_XX_CH3_ERR_CHK_WIDTH 1 3021#define FRF_AB_XX_CH2_DEG_DET_LBN 11 3022#define FRF_AB_XX_CH2_DEG_DET_WIDTH 1 3023#define FRF_AB_XX_CH2_LFSR_LOCK_IND_LBN 10 3024#define FRF_AB_XX_CH2_LFSR_LOCK_IND_WIDTH 1 3025#define FRF_AB_XX_CH2_PRBS_FRUN_LBN 9 3026#define FRF_AB_XX_CH2_PRBS_FRUN_WIDTH 1 3027#define FRF_AB_XX_CH2_ERR_CHK_LBN 8 3028#define FRF_AB_XX_CH2_ERR_CHK_WIDTH 1 3029#define FRF_AB_XX_CH1_DEG_DET_LBN 7 3030#define FRF_AB_XX_CH1_DEG_DET_WIDTH 1 3031#define FRF_AB_XX_CH1_LFSR_LOCK_IND_LBN 6 3032#define FRF_AB_XX_CH1_LFSR_LOCK_IND_WIDTH 1 3033#define FRF_AB_XX_CH1_PRBS_FRUN_LBN 5 3034#define FRF_AB_XX_CH1_PRBS_FRUN_WIDTH 1 3035#define FRF_AB_XX_CH1_ERR_CHK_LBN 4 3036#define FRF_AB_XX_CH1_ERR_CHK_WIDTH 1 3037#define FRF_AB_XX_CH0_DEG_DET_LBN 3 3038#define FRF_AB_XX_CH0_DEG_DET_WIDTH 1 3039#define FRF_AB_XX_CH0_LFSR_LOCK_IND_LBN 2 3040#define FRF_AB_XX_CH0_LFSR_LOCK_IND_WIDTH 1 3041#define FRF_AB_XX_CH0_PRBS_FRUN_LBN 1 3042#define FRF_AB_XX_CH0_PRBS_FRUN_WIDTH 1 3043#define FRF_AB_XX_CH0_ERR_CHK_LBN 0 3044#define FRF_AB_XX_CH0_ERR_CHK_WIDTH 1 3045 3046 3047/* 3048 * FR_AB_XX_PRBS_ERR_REG(128bit): 3049 * documentation to be written for sum_XX_PRBS_ERR_REG 3050 */ 3051#define FR_AB_XX_PRBS_ERR_REG_OFST 0x00001350 3052/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3053 3054#define FRF_AB_XX_CH3_PRBS_ERR_CNT_LBN 24 3055#define FRF_AB_XX_CH3_PRBS_ERR_CNT_WIDTH 8 3056#define FRF_AB_XX_CH2_PRBS_ERR_CNT_LBN 16 3057#define FRF_AB_XX_CH2_PRBS_ERR_CNT_WIDTH 8 3058#define FRF_AB_XX_CH1_PRBS_ERR_CNT_LBN 8 3059#define FRF_AB_XX_CH1_PRBS_ERR_CNT_WIDTH 8 3060#define FRF_AB_XX_CH0_PRBS_ERR_CNT_LBN 0 3061#define FRF_AB_XX_CH0_PRBS_ERR_CNT_WIDTH 8 3062 3063 3064/* 3065 * FR_AB_XX_CORE_STAT_REG(128bit): 3066 * XAUI XGXS core status register 3067 */ 3068#define FR_AB_XX_CORE_STAT_REG_OFST 0x00001360 3069/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3070 3071#define FRF_AB_XX_FORCE_SIG3_LBN 31 3072#define FRF_AB_XX_FORCE_SIG3_WIDTH 1 3073#define FRF_AB_XX_FORCE_SIG3_VAL_LBN 30 3074#define FRF_AB_XX_FORCE_SIG3_VAL_WIDTH 1 3075#define FRF_AB_XX_FORCE_SIG2_LBN 29 3076#define FRF_AB_XX_FORCE_SIG2_WIDTH 1 3077#define FRF_AB_XX_FORCE_SIG2_VAL_LBN 28 3078#define FRF_AB_XX_FORCE_SIG2_VAL_WIDTH 1 3079#define FRF_AB_XX_FORCE_SIG1_LBN 27 3080#define FRF_AB_XX_FORCE_SIG1_WIDTH 1 3081#define FRF_AB_XX_FORCE_SIG1_VAL_LBN 26 3082#define FRF_AB_XX_FORCE_SIG1_VAL_WIDTH 1 3083#define FRF_AB_XX_FORCE_SIG0_LBN 25 3084#define FRF_AB_XX_FORCE_SIG0_WIDTH 1 3085#define FRF_AB_XX_FORCE_SIG0_VAL_LBN 24 3086#define FRF_AB_XX_FORCE_SIG0_VAL_WIDTH 1 3087#define FRF_AB_XX_XGXS_LB_EN_LBN 23 3088#define FRF_AB_XX_XGXS_LB_EN_WIDTH 1 3089#define FRF_AB_XX_XGMII_LB_EN_LBN 22 3090#define FRF_AB_XX_XGMII_LB_EN_WIDTH 1 3091#define FRF_AB_XX_MATCH_FAULT_LBN 21 3092#define FRF_AB_XX_MATCH_FAULT_WIDTH 1 3093#define FRF_AB_XX_ALIGN_DONE_LBN 20 3094#define FRF_AB_XX_ALIGN_DONE_WIDTH 1 3095#define FRF_AB_XX_SYNC_STAT3_LBN 19 3096#define FRF_AB_XX_SYNC_STAT3_WIDTH 1 3097#define FRF_AB_XX_SYNC_STAT2_LBN 18 3098#define FRF_AB_XX_SYNC_STAT2_WIDTH 1 3099#define FRF_AB_XX_SYNC_STAT1_LBN 17 3100#define FRF_AB_XX_SYNC_STAT1_WIDTH 1 3101#define FRF_AB_XX_SYNC_STAT0_LBN 16 3102#define FRF_AB_XX_SYNC_STAT0_WIDTH 1 3103#define FRF_AB_XX_COMMA_DET_CH3_LBN 15 3104#define FRF_AB_XX_COMMA_DET_CH3_WIDTH 1 3105#define FRF_AB_XX_COMMA_DET_CH2_LBN 14 3106#define FRF_AB_XX_COMMA_DET_CH2_WIDTH 1 3107#define FRF_AB_XX_COMMA_DET_CH1_LBN 13 3108#define FRF_AB_XX_COMMA_DET_CH1_WIDTH 1 3109#define FRF_AB_XX_COMMA_DET_CH0_LBN 12 3110#define FRF_AB_XX_COMMA_DET_CH0_WIDTH 1 3111#define FRF_AB_XX_CGRP_ALIGN_CH3_LBN 11 3112#define FRF_AB_XX_CGRP_ALIGN_CH3_WIDTH 1 3113#define FRF_AB_XX_CGRP_ALIGN_CH2_LBN 10 3114#define FRF_AB_XX_CGRP_ALIGN_CH2_WIDTH 1 3115#define FRF_AB_XX_CGRP_ALIGN_CH1_LBN 9 3116#define FRF_AB_XX_CGRP_ALIGN_CH1_WIDTH 1 3117#define FRF_AB_XX_CGRP_ALIGN_CH0_LBN 8 3118#define FRF_AB_XX_CGRP_ALIGN_CH0_WIDTH 1 3119#define FRF_AB_XX_CHAR_ERR_CH3_LBN 7 3120#define FRF_AB_XX_CHAR_ERR_CH3_WIDTH 1 3121#define FRF_AB_XX_CHAR_ERR_CH2_LBN 6 3122#define FRF_AB_XX_CHAR_ERR_CH2_WIDTH 1 3123#define FRF_AB_XX_CHAR_ERR_CH1_LBN 5 3124#define FRF_AB_XX_CHAR_ERR_CH1_WIDTH 1 3125#define FRF_AB_XX_CHAR_ERR_CH0_LBN 4 3126#define FRF_AB_XX_CHAR_ERR_CH0_WIDTH 1 3127#define FRF_AB_XX_DISPERR_CH3_LBN 3 3128#define FRF_AB_XX_DISPERR_CH3_WIDTH 1 3129#define FRF_AB_XX_DISPERR_CH2_LBN 2 3130#define FRF_AB_XX_DISPERR_CH2_WIDTH 1 3131#define FRF_AB_XX_DISPERR_CH1_LBN 1 3132#define FRF_AB_XX_DISPERR_CH1_WIDTH 1 3133#define FRF_AB_XX_DISPERR_CH0_LBN 0 3134#define FRF_AB_XX_DISPERR_CH0_WIDTH 1 3135 3136 3137/* 3138 * FR_AA_RX_DESC_PTR_TBL_KER(128bit): 3139 * Receive descriptor pointer table 3140 */ 3141#define FR_AA_RX_DESC_PTR_TBL_KER_OFST 0x00011800 3142/* falcona0=net_func_bar2 */ 3143#define FR_AA_RX_DESC_PTR_TBL_KER_STEP 16 3144#define FR_AA_RX_DESC_PTR_TBL_KER_ROWS 4 3145/* 3146 * FR_AZ_RX_DESC_PTR_TBL(128bit): 3147 * Receive descriptor pointer table 3148 */ 3149#define FR_AZ_RX_DESC_PTR_TBL_OFST 0x00f40000 3150/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3151#define FR_AZ_RX_DESC_PTR_TBL_STEP 16 3152#define FR_CZ_RX_DESC_PTR_TBL_ROWS 1024 3153#define FR_AB_RX_DESC_PTR_TBL_ROWS 4096 3154 3155#define FRF_CZ_RX_HDR_SPLIT_LBN 90 3156#define FRF_CZ_RX_HDR_SPLIT_WIDTH 1 3157#define FRF_AZ_RX_RESET_LBN 89 3158#define FRF_AZ_RX_RESET_WIDTH 1 3159#define FRF_AZ_RX_ISCSI_DDIG_EN_LBN 88 3160#define FRF_AZ_RX_ISCSI_DDIG_EN_WIDTH 1 3161#define FRF_AZ_RX_ISCSI_HDIG_EN_LBN 87 3162#define FRF_AZ_RX_ISCSI_HDIG_EN_WIDTH 1 3163#define FRF_AZ_RX_DESC_PREF_ACT_LBN 86 3164#define FRF_AZ_RX_DESC_PREF_ACT_WIDTH 1 3165#define FRF_AZ_RX_DC_HW_RPTR_LBN 80 3166#define FRF_AZ_RX_DC_HW_RPTR_WIDTH 6 3167#define FRF_AZ_RX_DESCQ_HW_RPTR_LBN 68 3168#define FRF_AZ_RX_DESCQ_HW_RPTR_WIDTH 12 3169#define FRF_AZ_RX_DESCQ_SW_WPTR_LBN 56 3170#define FRF_AZ_RX_DESCQ_SW_WPTR_WIDTH 12 3171#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_LBN 36 3172#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_WIDTH 20 3173#define FRF_AZ_RX_DESCQ_EVQ_ID_LBN 24 3174#define FRF_AZ_RX_DESCQ_EVQ_ID_WIDTH 12 3175#define FRF_AZ_RX_DESCQ_OWNER_ID_LBN 10 3176#define FRF_AZ_RX_DESCQ_OWNER_ID_WIDTH 14 3177#define FRF_AZ_RX_DESCQ_LABEL_LBN 5 3178#define FRF_AZ_RX_DESCQ_LABEL_WIDTH 5 3179#define FRF_AZ_RX_DESCQ_SIZE_LBN 3 3180#define FRF_AZ_RX_DESCQ_SIZE_WIDTH 2 3181#define FFE_AZ_RX_DESCQ_SIZE_4K 3 3182#define FFE_AZ_RX_DESCQ_SIZE_2K 2 3183#define FFE_AZ_RX_DESCQ_SIZE_1K 1 3184#define FFE_AZ_RX_DESCQ_SIZE_512 0 3185#define FRF_AZ_RX_DESCQ_TYPE_LBN 2 3186#define FRF_AZ_RX_DESCQ_TYPE_WIDTH 1 3187#define FRF_AZ_RX_DESCQ_JUMBO_LBN 1 3188#define FRF_AZ_RX_DESCQ_JUMBO_WIDTH 1 3189#define FRF_AZ_RX_DESCQ_EN_LBN 0 3190#define FRF_AZ_RX_DESCQ_EN_WIDTH 1 3191 3192 3193/* 3194 * FR_AA_TX_DESC_PTR_TBL_KER(128bit): 3195 * Transmit descriptor pointer 3196 */ 3197#define FR_AA_TX_DESC_PTR_TBL_KER_OFST 0x00011900 3198/* falcona0=net_func_bar2 */ 3199#define FR_AA_TX_DESC_PTR_TBL_KER_STEP 16 3200#define FR_AA_TX_DESC_PTR_TBL_KER_ROWS 8 3201/* 3202 * FR_AZ_TX_DESC_PTR_TBL(128bit): 3203 * Transmit descriptor pointer 3204 */ 3205#define FR_AZ_TX_DESC_PTR_TBL_OFST 0x00f50000 3206/* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 3207#define FR_AZ_TX_DESC_PTR_TBL_STEP 16 3208#define FR_AB_TX_DESC_PTR_TBL_ROWS 4096 3209#define FR_CZ_TX_DESC_PTR_TBL_ROWS 1024 3210 3211#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_LBN 94 3212#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_WIDTH 2 3213#define FRF_CZ_TX_DPT_ETH_FILT_EN_LBN 93 3214#define FRF_CZ_TX_DPT_ETH_FILT_EN_WIDTH 1 3215#define FRF_CZ_TX_DPT_IP_FILT_EN_LBN 92 3216#define FRF_CZ_TX_DPT_IP_FILT_EN_WIDTH 1 3217#define FRF_BZ_TX_NON_IP_DROP_DIS_LBN 91 3218#define FRF_BZ_TX_NON_IP_DROP_DIS_WIDTH 1 3219#define FRF_BZ_TX_IP_CHKSM_DIS_LBN 90 3220#define FRF_BZ_TX_IP_CHKSM_DIS_WIDTH 1 3221#define FRF_BZ_TX_TCP_CHKSM_DIS_LBN 89 3222#define FRF_BZ_TX_TCP_CHKSM_DIS_WIDTH 1 3223#define FRF_AZ_TX_DESCQ_EN_LBN 88 3224#define FRF_AZ_TX_DESCQ_EN_WIDTH 1 3225#define FRF_AZ_TX_ISCSI_DDIG_EN_LBN 87 3226#define FRF_AZ_TX_ISCSI_DDIG_EN_WIDTH 1 3227#define FRF_AZ_TX_ISCSI_HDIG_EN_LBN 86 3228#define FRF_AZ_TX_ISCSI_HDIG_EN_WIDTH 1 3229#define FRF_AZ_TX_DC_HW_RPTR_LBN 80 3230#define FRF_AZ_TX_DC_HW_RPTR_WIDTH 6 3231#define FRF_AZ_TX_DESCQ_HW_RPTR_LBN 68 3232#define FRF_AZ_TX_DESCQ_HW_RPTR_WIDTH 12 3233#define FRF_AZ_TX_DESCQ_SW_WPTR_LBN 56 3234#define FRF_AZ_TX_DESCQ_SW_WPTR_WIDTH 12 3235#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_LBN 36 3236#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_WIDTH 20 3237#define FRF_AZ_TX_DESCQ_EVQ_ID_LBN 24 3238#define FRF_AZ_TX_DESCQ_EVQ_ID_WIDTH 12 3239#define FRF_AZ_TX_DESCQ_OWNER_ID_LBN 10 3240#define FRF_AZ_TX_DESCQ_OWNER_ID_WIDTH 14 3241#define FRF_AZ_TX_DESCQ_LABEL_LBN 5 3242#define FRF_AZ_TX_DESCQ_LABEL_WIDTH 5 3243#define FRF_AZ_TX_DESCQ_SIZE_LBN 3 3244#define FRF_AZ_TX_DESCQ_SIZE_WIDTH 2 3245#define FFE_AZ_TX_DESCQ_SIZE_4K 3 3246#define FFE_AZ_TX_DESCQ_SIZE_2K 2 3247#define FFE_AZ_TX_DESCQ_SIZE_1K 1 3248#define FFE_AZ_TX_DESCQ_SIZE_512 0 3249#define FRF_AZ_TX_DESCQ_TYPE_LBN 1 3250#define FRF_AZ_TX_DESCQ_TYPE_WIDTH 2 3251#define FRF_AZ_TX_DESCQ_FLUSH_LBN 0 3252#define FRF_AZ_TX_DESCQ_FLUSH_WIDTH 1 3253 3254 3255/* 3256 * FR_AA_EVQ_PTR_TBL_KER(128bit): 3257 * Event queue pointer table 3258 */ 3259#define FR_AA_EVQ_PTR_TBL_KER_OFST 0x00011a00 3260/* falcona0=net_func_bar2 */ 3261#define FR_AA_EVQ_PTR_TBL_KER_STEP 16 3262#define FR_AA_EVQ_PTR_TBL_KER_ROWS 4 3263/* 3264 * FR_AZ_EVQ_PTR_TBL(128bit): 3265 * Event queue pointer table 3266 */ 3267#define FR_AZ_EVQ_PTR_TBL_OFST 0x00f60000 3268/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3269#define FR_AZ_EVQ_PTR_TBL_STEP 16 3270#define FR_CZ_EVQ_PTR_TBL_ROWS 1024 3271#define FR_AB_EVQ_PTR_TBL_ROWS 4096 3272 3273#define FRF_BZ_EVQ_RPTR_IGN_LBN 40 3274#define FRF_BZ_EVQ_RPTR_IGN_WIDTH 1 3275#define FRF_AZ_EVQ_WKUP_OR_INT_EN_LBN 39 3276#define FRF_AZ_EVQ_WKUP_OR_INT_EN_WIDTH 1 3277#define FRF_AZ_EVQ_NXT_WPTR_LBN 24 3278#define FRF_AZ_EVQ_NXT_WPTR_WIDTH 15 3279#define FRF_AZ_EVQ_EN_LBN 23 3280#define FRF_AZ_EVQ_EN_WIDTH 1 3281#define FRF_AZ_EVQ_SIZE_LBN 20 3282#define FRF_AZ_EVQ_SIZE_WIDTH 3 3283#define FFE_AZ_EVQ_SIZE_32K 6 3284#define FFE_AZ_EVQ_SIZE_16K 5 3285#define FFE_AZ_EVQ_SIZE_8K 4 3286#define FFE_AZ_EVQ_SIZE_4K 3 3287#define FFE_AZ_EVQ_SIZE_2K 2 3288#define FFE_AZ_EVQ_SIZE_1K 1 3289#define FFE_AZ_EVQ_SIZE_512 0 3290#define FRF_AZ_EVQ_BUF_BASE_ID_LBN 0 3291#define FRF_AZ_EVQ_BUF_BASE_ID_WIDTH 20 3292 3293 3294/* 3295 * FR_AA_BUF_HALF_TBL_KER(64bit): 3296 * Buffer table in half buffer table mode direct access by driver 3297 */ 3298#define FR_AA_BUF_HALF_TBL_KER_OFST 0x00018000 3299/* falcona0=net_func_bar2 */ 3300#define FR_AA_BUF_HALF_TBL_KER_STEP 8 3301#define FR_AA_BUF_HALF_TBL_KER_ROWS 4096 3302/* 3303 * FR_AZ_BUF_HALF_TBL(64bit): 3304 * Buffer table in half buffer table mode direct access by driver 3305 */ 3306#define FR_AZ_BUF_HALF_TBL_OFST 0x00800000 3307/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3308#define FR_AZ_BUF_HALF_TBL_STEP 8 3309#define FR_CZ_BUF_HALF_TBL_ROWS 147456 3310#define FR_AB_BUF_HALF_TBL_ROWS 524288 3311 3312#define FRF_AZ_BUF_ADR_HBUF_ODD_LBN 44 3313#define FRF_AZ_BUF_ADR_HBUF_ODD_WIDTH 20 3314#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN 32 3315#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_WIDTH 12 3316#define FRF_AZ_BUF_ADR_HBUF_EVEN_LBN 12 3317#define FRF_AZ_BUF_ADR_HBUF_EVEN_WIDTH 20 3318#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN 0 3319#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH 12 3320 3321 3322/* 3323 * FR_AA_BUF_FULL_TBL_KER(64bit): 3324 * Buffer table in full buffer table mode direct access by driver 3325 */ 3326#define FR_AA_BUF_FULL_TBL_KER_OFST 0x00018000 3327/* falcona0=net_func_bar2 */ 3328#define FR_AA_BUF_FULL_TBL_KER_STEP 8 3329#define FR_AA_BUF_FULL_TBL_KER_ROWS 4096 3330/* 3331 * FR_AZ_BUF_FULL_TBL(64bit): 3332 * Buffer table in full buffer table mode direct access by driver 3333 */ 3334#define FR_AZ_BUF_FULL_TBL_OFST 0x00800000 3335/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3336#define FR_AZ_BUF_FULL_TBL_STEP 8 3337 3338#define FR_CZ_BUF_FULL_TBL_ROWS 147456 3339#define FR_AB_BUF_FULL_TBL_ROWS 917504 3340 3341#define FRF_AZ_BUF_FULL_UNUSED_LBN 51 3342#define FRF_AZ_BUF_FULL_UNUSED_WIDTH 13 3343#define FRF_AZ_IP_DAT_BUF_SIZE_LBN 50 3344#define FRF_AZ_IP_DAT_BUF_SIZE_WIDTH 1 3345#define FRF_AZ_BUF_ADR_REGION_LBN 48 3346#define FRF_AZ_BUF_ADR_REGION_WIDTH 2 3347#define FFE_AZ_BUF_ADR_REGN3 3 3348#define FFE_AZ_BUF_ADR_REGN2 2 3349#define FFE_AZ_BUF_ADR_REGN1 1 3350#define FFE_AZ_BUF_ADR_REGN0 0 3351#define FRF_AZ_BUF_ADR_FBUF_LBN 14 3352#define FRF_AZ_BUF_ADR_FBUF_WIDTH 34 3353#define FRF_AZ_BUF_ADR_FBUF_DW0_LBN 14 3354#define FRF_AZ_BUF_ADR_FBUF_DW0_WIDTH 32 3355#define FRF_AZ_BUF_ADR_FBUF_DW1_LBN 46 3356#define FRF_AZ_BUF_ADR_FBUF_DW1_WIDTH 2 3357#define FRF_AZ_BUF_OWNER_ID_FBUF_LBN 0 3358#define FRF_AZ_BUF_OWNER_ID_FBUF_WIDTH 14 3359 3360 3361/* 3362 * FR_AZ_RX_FILTER_TBL0(128bit): 3363 * TCP/IPv4 Receive filter table 3364 */ 3365#define FR_AZ_RX_FILTER_TBL0_OFST 0x00f00000 3366/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 3367#define FR_AZ_RX_FILTER_TBL0_STEP 32 3368#define FR_AZ_RX_FILTER_TBL0_ROWS 8192 3369/* 3370 * FR_AB_RX_FILTER_TBL1(128bit): 3371 * TCP/IPv4 Receive filter table 3372 */ 3373#define FR_AB_RX_FILTER_TBL1_OFST 0x00f00010 3374/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3375#define FR_AB_RX_FILTER_TBL1_STEP 32 3376#define FR_AB_RX_FILTER_TBL1_ROWS 8192 3377 3378#define FRF_BZ_RSS_EN_LBN 110 3379#define FRF_BZ_RSS_EN_WIDTH 1 3380#define FRF_BZ_SCATTER_EN_LBN 109 3381#define FRF_BZ_SCATTER_EN_WIDTH 1 3382#define FRF_AZ_TCP_UDP_LBN 108 3383#define FRF_AZ_TCP_UDP_WIDTH 1 3384#define FRF_AZ_RXQ_ID_LBN 96 3385#define FRF_AZ_RXQ_ID_WIDTH 12 3386#define FRF_AZ_DEST_IP_LBN 64 3387#define FRF_AZ_DEST_IP_WIDTH 32 3388#define FRF_AZ_DEST_PORT_TCP_LBN 48 3389#define FRF_AZ_DEST_PORT_TCP_WIDTH 16 3390#define FRF_AZ_SRC_IP_LBN 16 3391#define FRF_AZ_SRC_IP_WIDTH 32 3392#define FRF_AZ_SRC_TCP_DEST_UDP_LBN 0 3393#define FRF_AZ_SRC_TCP_DEST_UDP_WIDTH 16 3394 3395 3396/* 3397 * FR_CZ_RX_MAC_FILTER_TBL0(128bit): 3398 * Receive Ethernet filter table 3399 */ 3400#define FR_CZ_RX_MAC_FILTER_TBL0_OFST 0x00f00010 3401/* sienaa0=net_func_bar2 */ 3402#define FR_CZ_RX_MAC_FILTER_TBL0_STEP 32 3403#define FR_CZ_RX_MAC_FILTER_TBL0_ROWS 512 3404 3405#define FRF_CZ_RMFT_RSS_EN_LBN 75 3406#define FRF_CZ_RMFT_RSS_EN_WIDTH 1 3407#define FRF_CZ_RMFT_SCATTER_EN_LBN 74 3408#define FRF_CZ_RMFT_SCATTER_EN_WIDTH 1 3409#define FRF_CZ_RMFT_IP_OVERRIDE_LBN 73 3410#define FRF_CZ_RMFT_IP_OVERRIDE_WIDTH 1 3411#define FRF_CZ_RMFT_RXQ_ID_LBN 61 3412#define FRF_CZ_RMFT_RXQ_ID_WIDTH 12 3413#define FRF_CZ_RMFT_WILDCARD_MATCH_LBN 60 3414#define FRF_CZ_RMFT_WILDCARD_MATCH_WIDTH 1 3415#define FRF_CZ_RMFT_DEST_MAC_LBN 12 3416#define FRF_CZ_RMFT_DEST_MAC_WIDTH 48 3417#define FRF_CZ_RMFT_DEST_MAC_DW0_LBN 12 3418#define FRF_CZ_RMFT_DEST_MAC_DW0_WIDTH 32 3419#define FRF_CZ_RMFT_DEST_MAC_DW1_LBN 44 3420#define FRF_CZ_RMFT_DEST_MAC_DW1_WIDTH 16 3421#define FRF_CZ_RMFT_VLAN_ID_LBN 0 3422#define FRF_CZ_RMFT_VLAN_ID_WIDTH 12 3423 3424 3425/* 3426 * FR_AZ_TIMER_TBL(128bit): 3427 * Timer table 3428 */ 3429#define FR_AZ_TIMER_TBL_OFST 0x00f70000 3430/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3431#define FR_AZ_TIMER_TBL_STEP 16 3432#define FR_CZ_TIMER_TBL_ROWS 1024 3433#define FR_AB_TIMER_TBL_ROWS 4096 3434 3435#define FRF_CZ_TIMER_Q_EN_LBN 33 3436#define FRF_CZ_TIMER_Q_EN_WIDTH 1 3437#define FRF_CZ_INT_ARMD_LBN 32 3438#define FRF_CZ_INT_ARMD_WIDTH 1 3439#define FRF_CZ_INT_PEND_LBN 31 3440#define FRF_CZ_INT_PEND_WIDTH 1 3441#define FRF_CZ_HOST_NOTIFY_MODE_LBN 30 3442#define FRF_CZ_HOST_NOTIFY_MODE_WIDTH 1 3443#define FRF_CZ_RELOAD_TIMER_VAL_LBN 16 3444#define FRF_CZ_RELOAD_TIMER_VAL_WIDTH 14 3445#define FRF_CZ_TIMER_MODE_LBN 14 3446#define FRF_CZ_TIMER_MODE_WIDTH 2 3447#define FFE_CZ_TIMER_MODE_INT_HLDOFF 3 3448#define FFE_CZ_TIMER_MODE_TRIG_START 2 3449#define FFE_CZ_TIMER_MODE_IMMED_START 1 3450#define FFE_CZ_TIMER_MODE_DIS 0 3451#define FRF_AB_TIMER_MODE_LBN 12 3452#define FRF_AB_TIMER_MODE_WIDTH 2 3453#define FFE_AB_TIMER_MODE_INT_HLDOFF 2 3454#define FFE_AB_TIMER_MODE_TRIG_START 2 3455#define FFE_AB_TIMER_MODE_IMMED_START 1 3456#define FFE_AB_TIMER_MODE_DIS 0 3457#define FRF_CZ_TIMER_VAL_LBN 0 3458#define FRF_CZ_TIMER_VAL_WIDTH 14 3459#define FRF_AB_TIMER_VAL_LBN 0 3460#define FRF_AB_TIMER_VAL_WIDTH 12 3461 3462 3463/* 3464 * FR_BZ_TX_PACE_TBL(128bit): 3465 * Transmit pacing table 3466 */ 3467#define FR_BZ_TX_PACE_TBL_OFST 0x00f80000 3468/* sienaa0=net_func_bar2,falconb0=net_func_bar2 */ 3469#define FR_AZ_TX_PACE_TBL_STEP 16 3470#define FR_CZ_TX_PACE_TBL_ROWS 1024 3471#define FR_BB_TX_PACE_TBL_ROWS 4096 3472/* 3473 * FR_AA_TX_PACE_TBL(128bit): 3474 * Transmit pacing table 3475 */ 3476#define FR_AA_TX_PACE_TBL_OFST 0x00f80040 3477/* falcona0=char_func_bar0 */ 3478/* FR_AZ_TX_PACE_TBL_STEP 16 */ 3479#define FR_AA_TX_PACE_TBL_ROWS 4092 3480 3481#define FRF_AZ_TX_PACE_LBN 0 3482#define FRF_AZ_TX_PACE_WIDTH 5 3483 3484 3485/* 3486 * FR_BZ_RX_INDIRECTION_TBL(7bit): 3487 * RX Indirection Table 3488 */ 3489#define FR_BZ_RX_INDIRECTION_TBL_OFST 0x00fb0000 3490/* falconb0,sienaa0=net_func_bar2 */ 3491#define FR_BZ_RX_INDIRECTION_TBL_STEP 16 3492#define FR_BZ_RX_INDIRECTION_TBL_ROWS 128 3493 3494#define FRF_BZ_IT_QUEUE_LBN 0 3495#define FRF_BZ_IT_QUEUE_WIDTH 6 3496 3497 3498/* 3499 * FR_CZ_TX_FILTER_TBL0(128bit): 3500 * TCP/IPv4 Transmit filter table 3501 */ 3502#define FR_CZ_TX_FILTER_TBL0_OFST 0x00fc0000 3503/* sienaa0=net_func_bar2 */ 3504#define FR_CZ_TX_FILTER_TBL0_STEP 16 3505#define FR_CZ_TX_FILTER_TBL0_ROWS 8192 3506 3507#define FRF_CZ_TIFT_TCP_UDP_LBN 108 3508#define FRF_CZ_TIFT_TCP_UDP_WIDTH 1 3509#define FRF_CZ_TIFT_TXQ_ID_LBN 96 3510#define FRF_CZ_TIFT_TXQ_ID_WIDTH 12 3511#define FRF_CZ_TIFT_DEST_IP_LBN 64 3512#define FRF_CZ_TIFT_DEST_IP_WIDTH 32 3513#define FRF_CZ_TIFT_DEST_PORT_TCP_LBN 48 3514#define FRF_CZ_TIFT_DEST_PORT_TCP_WIDTH 16 3515#define FRF_CZ_TIFT_SRC_IP_LBN 16 3516#define FRF_CZ_TIFT_SRC_IP_WIDTH 32 3517#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_LBN 0 3518#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_WIDTH 16 3519 3520 3521/* 3522 * FR_CZ_TX_MAC_FILTER_TBL0(128bit): 3523 * Transmit Ethernet filter table 3524 */ 3525#define FR_CZ_TX_MAC_FILTER_TBL0_OFST 0x00fe0000 3526/* sienaa0=net_func_bar2 */ 3527#define FR_CZ_TX_MAC_FILTER_TBL0_STEP 16 3528#define FR_CZ_TX_MAC_FILTER_TBL0_ROWS 512 3529 3530#define FRF_CZ_TMFT_TXQ_ID_LBN 61 3531#define FRF_CZ_TMFT_TXQ_ID_WIDTH 12 3532#define FRF_CZ_TMFT_WILDCARD_MATCH_LBN 60 3533#define FRF_CZ_TMFT_WILDCARD_MATCH_WIDTH 1 3534#define FRF_CZ_TMFT_SRC_MAC_LBN 12 3535#define FRF_CZ_TMFT_SRC_MAC_WIDTH 48 3536#define FRF_CZ_TMFT_SRC_MAC_DW0_LBN 12 3537#define FRF_CZ_TMFT_SRC_MAC_DW0_WIDTH 32 3538#define FRF_CZ_TMFT_SRC_MAC_DW1_LBN 44 3539#define FRF_CZ_TMFT_SRC_MAC_DW1_WIDTH 16 3540#define FRF_CZ_TMFT_VLAN_ID_LBN 0 3541#define FRF_CZ_TMFT_VLAN_ID_WIDTH 12 3542 3543 3544/* 3545 * FR_CZ_MC_TREG_SMEM(32bit): 3546 * MC Shared Memory 3547 */ 3548#define FR_CZ_MC_TREG_SMEM_OFST 0x00ff0000 3549/* sienaa0=net_func_bar2 */ 3550#define FR_CZ_MC_TREG_SMEM_STEP 4 3551#define FR_CZ_MC_TREG_SMEM_ROWS 512 3552 3553#define FRF_CZ_MC_TREG_SMEM_ROW_LBN 0 3554#define FRF_CZ_MC_TREG_SMEM_ROW_WIDTH 32 3555 3556 3557/* 3558 * FR_BB_MSIX_VECTOR_TABLE(128bit): 3559 * MSIX Vector Table 3560 */ 3561#define FR_BB_MSIX_VECTOR_TABLE_OFST 0x00ff0000 3562/* falconb0=net_func_bar2 */ 3563#define FR_BZ_MSIX_VECTOR_TABLE_STEP 16 3564#define FR_BB_MSIX_VECTOR_TABLE_ROWS 64 3565/* 3566 * FR_CZ_MSIX_VECTOR_TABLE(128bit): 3567 * MSIX Vector Table 3568 */ 3569#define FR_CZ_MSIX_VECTOR_TABLE_OFST 0x00000000 3570/* sienaa0=pci_f0_bar4 */ 3571/* FR_BZ_MSIX_VECTOR_TABLE_STEP 16 */ 3572#define FR_CZ_MSIX_VECTOR_TABLE_ROWS 1024 3573 3574#define FRF_BZ_MSIX_VECTOR_RESERVED_LBN 97 3575#define FRF_BZ_MSIX_VECTOR_RESERVED_WIDTH 31 3576#define FRF_BZ_MSIX_VECTOR_MASK_LBN 96 3577#define FRF_BZ_MSIX_VECTOR_MASK_WIDTH 1 3578#define FRF_BZ_MSIX_MESSAGE_DATA_LBN 64 3579#define FRF_BZ_MSIX_MESSAGE_DATA_WIDTH 32 3580#define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_LBN 32 3581#define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_WIDTH 32 3582#define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_LBN 0 3583#define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_WIDTH 32 3584 3585 3586/* 3587 * FR_BB_MSIX_PBA_TABLE(32bit): 3588 * MSIX Pending Bit Array 3589 */ 3590#define FR_BB_MSIX_PBA_TABLE_OFST 0x00ff2000 3591/* falconb0=net_func_bar2 */ 3592#define FR_BZ_MSIX_PBA_TABLE_STEP 4 3593#define FR_BB_MSIX_PBA_TABLE_ROWS 2 3594/* 3595 * FR_CZ_MSIX_PBA_TABLE(32bit): 3596 * MSIX Pending Bit Array 3597 */ 3598#define FR_CZ_MSIX_PBA_TABLE_OFST 0x00008000 3599/* sienaa0=pci_f0_bar4 */ 3600/* FR_BZ_MSIX_PBA_TABLE_STEP 4 */ 3601#define FR_CZ_MSIX_PBA_TABLE_ROWS 32 3602 3603#define FRF_BZ_MSIX_PBA_PEND_DWORD_LBN 0 3604#define FRF_BZ_MSIX_PBA_PEND_DWORD_WIDTH 32 3605 3606 3607/* 3608 * FR_AZ_SRM_DBG_REG(64bit): 3609 * SRAM debug access 3610 */ 3611#define FR_AZ_SRM_DBG_REG_OFST 0x03000000 3612/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3613#define FR_AZ_SRM_DBG_REG_STEP 8 3614 3615#define FR_CZ_SRM_DBG_REG_ROWS 262144 3616#define FR_AB_SRM_DBG_REG_ROWS 2097152 3617 3618#define FRF_AZ_SRM_DBG_LBN 0 3619#define FRF_AZ_SRM_DBG_WIDTH 64 3620#define FRF_AZ_SRM_DBG_DW0_LBN 0 3621#define FRF_AZ_SRM_DBG_DW0_WIDTH 32 3622#define FRF_AZ_SRM_DBG_DW1_LBN 32 3623#define FRF_AZ_SRM_DBG_DW1_WIDTH 32 3624 3625 3626/* 3627 * FR_AA_INT_ACK_CHAR(32bit): 3628 * CHAR interrupt acknowledge register 3629 */ 3630#define FR_AA_INT_ACK_CHAR_OFST 0x00000060 3631/* falcona0=char_func_bar0 */ 3632 3633#define FRF_AA_INT_ACK_CHAR_FIELD_LBN 0 3634#define FRF_AA_INT_ACK_CHAR_FIELD_WIDTH 32 3635 3636 3637/* FS_DRIVER_EV */ 3638#define FSF_AZ_DRIVER_EV_SUBCODE_LBN 56 3639#define FSF_AZ_DRIVER_EV_SUBCODE_WIDTH 4 3640#define FSE_AZ_TX_DSC_ERROR_EV 15 3641#define FSE_AZ_RX_DSC_ERROR_EV 14 3642#define FSE_AZ_RX_RECOVER_EV 11 3643#define FSE_AZ_TIMER_EV 10 3644#define FSE_AZ_TX_PKT_NON_TCP_UDP 9 3645#define FSE_AZ_WAKE_UP_EV 6 3646#define FSE_AZ_SRM_UPD_DONE_EV 5 3647#define FSE_AZ_EVQ_NOT_EN_EV 3 3648#define FSE_AZ_EVQ_INIT_DONE_EV 2 3649#define FSE_AZ_RX_DESCQ_FLS_DONE_EV 1 3650#define FSE_AZ_TX_DESCQ_FLS_DONE_EV 0 3651#define FSF_AZ_DRIVER_EV_SUBDATA_LBN 0 3652#define FSF_AZ_DRIVER_EV_SUBDATA_WIDTH 14 3653 3654 3655/* FS_EVENT_ENTRY */ 3656#define FSF_AZ_EV_CODE_LBN 60 3657#define FSF_AZ_EV_CODE_WIDTH 4 3658#define FSE_AZ_EV_CODE_USER_EV 8 3659#define FSE_AZ_EV_CODE_DRV_GEN_EV 7 3660#define FSE_AZ_EV_CODE_GLOBAL_EV 6 3661#define FSE_AZ_EV_CODE_DRIVER_EV 5 3662#define FSE_AZ_EV_CODE_TX_EV 2 3663#define FSE_AZ_EV_CODE_RX_EV 0 3664#define FSF_AZ_EV_DATA_LBN 0 3665#define FSF_AZ_EV_DATA_WIDTH 60 3666#define FSF_AZ_EV_DATA_DW0_LBN 0 3667#define FSF_AZ_EV_DATA_DW0_WIDTH 32 3668#define FSF_AZ_EV_DATA_DW1_LBN 32 3669#define FSF_AZ_EV_DATA_DW1_WIDTH 28 3670 3671 3672/* FS_GLOBAL_EV */ 3673#define FSF_AA_GLB_EV_RX_RECOVERY_LBN 12 3674#define FSF_AA_GLB_EV_RX_RECOVERY_WIDTH 1 3675#define FSF_BZ_GLB_EV_XG_MNT_INTR_LBN 11 3676#define FSF_BZ_GLB_EV_XG_MNT_INTR_WIDTH 1 3677#define FSF_AZ_GLB_EV_XFP_PHY0_INTR_LBN 10 3678#define FSF_AZ_GLB_EV_XFP_PHY0_INTR_WIDTH 1 3679#define FSF_AZ_GLB_EV_XG_PHY0_INTR_LBN 9 3680#define FSF_AZ_GLB_EV_XG_PHY0_INTR_WIDTH 1 3681#define FSF_AZ_GLB_EV_G_PHY0_INTR_LBN 7 3682#define FSF_AZ_GLB_EV_G_PHY0_INTR_WIDTH 1 3683 3684 3685/* FS_RX_EV */ 3686#define FSF_CZ_RX_EV_PKT_NOT_PARSED_LBN 58 3687#define FSF_CZ_RX_EV_PKT_NOT_PARSED_WIDTH 1 3688#define FSF_CZ_RX_EV_IPV6_PKT_LBN 57 3689#define FSF_CZ_RX_EV_IPV6_PKT_WIDTH 1 3690#define FSF_AZ_RX_EV_PKT_OK_LBN 56 3691#define FSF_AZ_RX_EV_PKT_OK_WIDTH 1 3692#define FSF_AZ_RX_EV_PAUSE_FRM_ERR_LBN 55 3693#define FSF_AZ_RX_EV_PAUSE_FRM_ERR_WIDTH 1 3694#define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_LBN 54 3695#define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_WIDTH 1 3696#define FSF_AZ_RX_EV_IP_FRAG_ERR_LBN 53 3697#define FSF_AZ_RX_EV_IP_FRAG_ERR_WIDTH 1 3698#define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_LBN 52 3699#define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 1 3700#define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_LBN 51 3701#define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 1 3702#define FSF_AZ_RX_EV_ETH_CRC_ERR_LBN 50 3703#define FSF_AZ_RX_EV_ETH_CRC_ERR_WIDTH 1 3704#define FSF_AZ_RX_EV_FRM_TRUNC_LBN 49 3705#define FSF_AZ_RX_EV_FRM_TRUNC_WIDTH 1 3706#define FSF_AZ_RX_EV_TOBE_DISC_LBN 47 3707#define FSF_AZ_RX_EV_TOBE_DISC_WIDTH 1 3708#define FSF_AZ_RX_EV_PKT_TYPE_LBN 44 3709#define FSF_AZ_RX_EV_PKT_TYPE_WIDTH 3 3710#define FSE_AZ_RX_EV_PKT_TYPE_VLAN_JUMBO 5 3711#define FSE_AZ_RX_EV_PKT_TYPE_VLAN_LLC 4 3712#define FSE_AZ_RX_EV_PKT_TYPE_VLAN 3 3713#define FSE_AZ_RX_EV_PKT_TYPE_JUMBO 2 3714#define FSE_AZ_RX_EV_PKT_TYPE_LLC 1 3715#define FSE_AZ_RX_EV_PKT_TYPE_ETH 0 3716#define FSF_AZ_RX_EV_HDR_TYPE_LBN 42 3717#define FSF_AZ_RX_EV_HDR_TYPE_WIDTH 2 3718#define FSE_AZ_RX_EV_HDR_TYPE_OTHER 3 3719#define FSE_AZ_RX_EV_HDR_TYPE_IPV4_OTHER 2 3720#define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER 2 3721#define FSE_AZ_RX_EV_HDR_TYPE_IPV4_UDP 1 3722#define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP 1 3723#define FSE_AZ_RX_EV_HDR_TYPE_IPV4_TCP 0 3724#define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP 0 3725#define FSF_AZ_RX_EV_DESC_Q_EMPTY_LBN 41 3726#define FSF_AZ_RX_EV_DESC_Q_EMPTY_WIDTH 1 3727#define FSF_AZ_RX_EV_MCAST_HASH_MATCH_LBN 40 3728#define FSF_AZ_RX_EV_MCAST_HASH_MATCH_WIDTH 1 3729#define FSF_AZ_RX_EV_MCAST_PKT_LBN 39 3730#define FSF_AZ_RX_EV_MCAST_PKT_WIDTH 1 3731#define FSF_AA_RX_EV_RECOVERY_FLAG_LBN 37 3732#define FSF_AA_RX_EV_RECOVERY_FLAG_WIDTH 1 3733#define FSF_AZ_RX_EV_Q_LABEL_LBN 32 3734#define FSF_AZ_RX_EV_Q_LABEL_WIDTH 5 3735#define FSF_AZ_RX_EV_JUMBO_CONT_LBN 31 3736#define FSF_AZ_RX_EV_JUMBO_CONT_WIDTH 1 3737#define FSF_AZ_RX_EV_PORT_LBN 30 3738#define FSF_AZ_RX_EV_PORT_WIDTH 1 3739#define FSF_AZ_RX_EV_BYTE_CNT_LBN 16 3740#define FSF_AZ_RX_EV_BYTE_CNT_WIDTH 14 3741#define FSF_AZ_RX_EV_SOP_LBN 15 3742#define FSF_AZ_RX_EV_SOP_WIDTH 1 3743#define FSF_AZ_RX_EV_ISCSI_PKT_OK_LBN 14 3744#define FSF_AZ_RX_EV_ISCSI_PKT_OK_WIDTH 1 3745#define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_LBN 13 3746#define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_WIDTH 1 3747#define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_LBN 12 3748#define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_WIDTH 1 3749#define FSF_AZ_RX_EV_DESC_PTR_LBN 0 3750#define FSF_AZ_RX_EV_DESC_PTR_WIDTH 12 3751 3752 3753/* FS_RX_KER_DESC */ 3754#define FSF_AZ_RX_KER_BUF_SIZE_LBN 48 3755#define FSF_AZ_RX_KER_BUF_SIZE_WIDTH 14 3756#define FSF_AZ_RX_KER_BUF_REGION_LBN 46 3757#define FSF_AZ_RX_KER_BUF_REGION_WIDTH 2 3758#define FSF_AZ_RX_KER_BUF_ADDR_LBN 0 3759#define FSF_AZ_RX_KER_BUF_ADDR_WIDTH 46 3760#define FSF_AZ_RX_KER_BUF_ADDR_DW0_LBN 0 3761#define FSF_AZ_RX_KER_BUF_ADDR_DW0_WIDTH 32 3762#define FSF_AZ_RX_KER_BUF_ADDR_DW1_LBN 32 3763#define FSF_AZ_RX_KER_BUF_ADDR_DW1_WIDTH 14 3764 3765 3766/* FS_RX_USER_DESC */ 3767#define FSF_AZ_RX_USER_2BYTE_OFFSET_LBN 20 3768#define FSF_AZ_RX_USER_2BYTE_OFFSET_WIDTH 12 3769#define FSF_AZ_RX_USER_BUF_ID_LBN 0 3770#define FSF_AZ_RX_USER_BUF_ID_WIDTH 20 3771 3772 3773/* FS_TX_EV */ 3774#define FSF_AZ_TX_EV_PKT_ERR_LBN 38 3775#define FSF_AZ_TX_EV_PKT_ERR_WIDTH 1 3776#define FSF_AZ_TX_EV_PKT_TOO_BIG_LBN 37 3777#define FSF_AZ_TX_EV_PKT_TOO_BIG_WIDTH 1 3778#define FSF_AZ_TX_EV_Q_LABEL_LBN 32 3779#define FSF_AZ_TX_EV_Q_LABEL_WIDTH 5 3780#define FSF_AZ_TX_EV_PORT_LBN 16 3781#define FSF_AZ_TX_EV_PORT_WIDTH 1 3782#define FSF_AZ_TX_EV_WQ_FF_FULL_LBN 15 3783#define FSF_AZ_TX_EV_WQ_FF_FULL_WIDTH 1 3784#define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_LBN 14 3785#define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_WIDTH 1 3786#define FSF_AZ_TX_EV_COMP_LBN 12 3787#define FSF_AZ_TX_EV_COMP_WIDTH 1 3788#define FSF_AZ_TX_EV_DESC_PTR_LBN 0 3789#define FSF_AZ_TX_EV_DESC_PTR_WIDTH 12 3790 3791 3792/* FS_TX_KER_DESC */ 3793#define FSF_AZ_TX_KER_CONT_LBN 62 3794#define FSF_AZ_TX_KER_CONT_WIDTH 1 3795#define FSF_AZ_TX_KER_BYTE_COUNT_LBN 48 3796#define FSF_AZ_TX_KER_BYTE_COUNT_WIDTH 14 3797#define FSF_AZ_TX_KER_BUF_REGION_LBN 46 3798#define FSF_AZ_TX_KER_BUF_REGION_WIDTH 2 3799#define FSF_AZ_TX_KER_BUF_ADDR_LBN 0 3800#define FSF_AZ_TX_KER_BUF_ADDR_WIDTH 46 3801#define FSF_AZ_TX_KER_BUF_ADDR_DW0_LBN 0 3802#define FSF_AZ_TX_KER_BUF_ADDR_DW0_WIDTH 32 3803#define FSF_AZ_TX_KER_BUF_ADDR_DW1_LBN 32 3804#define FSF_AZ_TX_KER_BUF_ADDR_DW1_WIDTH 14 3805 3806 3807/* FS_TX_USER_DESC */ 3808#define FSF_AZ_TX_USER_SW_EV_EN_LBN 48 3809#define FSF_AZ_TX_USER_SW_EV_EN_WIDTH 1 3810#define FSF_AZ_TX_USER_CONT_LBN 46 3811#define FSF_AZ_TX_USER_CONT_WIDTH 1 3812#define FSF_AZ_TX_USER_BYTE_CNT_LBN 33 3813#define FSF_AZ_TX_USER_BYTE_CNT_WIDTH 13 3814#define FSF_AZ_TX_USER_BUF_ID_LBN 13 3815#define FSF_AZ_TX_USER_BUF_ID_WIDTH 20 3816#define FSF_AZ_TX_USER_BYTE_OFS_LBN 0 3817#define FSF_AZ_TX_USER_BYTE_OFS_WIDTH 13 3818 3819 3820/* FS_USER_EV */ 3821#define FSF_CZ_USER_QID_LBN 32 3822#define FSF_CZ_USER_QID_WIDTH 10 3823#define FSF_CZ_USER_EV_REG_VALUE_LBN 0 3824#define FSF_CZ_USER_EV_REG_VALUE_WIDTH 32 3825 3826 3827/* FS_NET_IVEC */ 3828#define FSF_AZ_NET_IVEC_FATAL_INT_LBN 64 3829#define FSF_AZ_NET_IVEC_FATAL_INT_WIDTH 1 3830#define FSF_AZ_NET_IVEC_INT_Q_LBN 40 3831#define FSF_AZ_NET_IVEC_INT_Q_WIDTH 4 3832#define FSF_AZ_NET_IVEC_INT_FLAG_LBN 32 3833#define FSF_AZ_NET_IVEC_INT_FLAG_WIDTH 1 3834#define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_LBN 1 3835#define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_WIDTH 1 3836#define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_LBN 0 3837#define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_WIDTH 1 3838 3839 3840/* DRIVER_EV */ 3841/* Sub-fields of an RX flush completion event */ 3842#define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_LBN 12 3843#define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_WIDTH 1 3844#define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_LBN 0 3845#define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_WIDTH 12 3846 3847 3848 3849/************************************************************************** 3850 * 3851 * Falcon non-volatile configuration 3852 * 3853 ************************************************************************** 3854 */ 3855 3856 3857#define FR_AZ_TX_PACE_TBL_OFST FR_BZ_TX_PACE_TBL_OFST 3858 3859 3860#ifdef __cplusplus 3861} 3862#endif 3863 3864 3865 3866 3867#endif /* _SYS_EFX_REGS_H */ 3868