efx_regs.h revision 227569
1/*- 2 * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26#ifndef _SYS_EFX_REGS_H 27#define _SYS_EFX_REGS_H 28 29 30#ifdef __cplusplus 31extern "C" { 32#endif 33 34 35/* 36 * FR_AB_EE_VPD_CFG0_REG_SF(128bit): 37 * SPI/VPD configuration register 0 38 */ 39#define FR_AB_EE_VPD_CFG0_REG_SF_OFST 0x00000300 40/* falcona0,falconb0=eeprom_flash */ 41/* 42 * FR_AB_EE_VPD_CFG0_REG(128bit): 43 * SPI/VPD configuration register 0 44 */ 45#define FR_AB_EE_VPD_CFG0_REG_OFST 0x00000140 46/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 47 48#define FRF_AB_EE_SF_FASTRD_EN_LBN 127 49#define FRF_AB_EE_SF_FASTRD_EN_WIDTH 1 50#define FRF_AB_EE_SF_CLOCK_DIV_LBN 120 51#define FRF_AB_EE_SF_CLOCK_DIV_WIDTH 7 52#define FRF_AB_EE_VPD_WIP_POLL_LBN 119 53#define FRF_AB_EE_VPD_WIP_POLL_WIDTH 1 54#define FRF_AB_EE_EE_CLOCK_DIV_LBN 112 55#define FRF_AB_EE_EE_CLOCK_DIV_WIDTH 7 56#define FRF_AB_EE_EE_WR_TMR_VALUE_LBN 96 57#define FRF_AB_EE_EE_WR_TMR_VALUE_WIDTH 16 58#define FRF_AB_EE_VPDW_LENGTH_LBN 80 59#define FRF_AB_EE_VPDW_LENGTH_WIDTH 15 60#define FRF_AB_EE_VPDW_BASE_LBN 64 61#define FRF_AB_EE_VPDW_BASE_WIDTH 15 62#define FRF_AB_EE_VPD_WR_CMD_EN_LBN 56 63#define FRF_AB_EE_VPD_WR_CMD_EN_WIDTH 8 64#define FRF_AB_EE_VPD_BASE_LBN 32 65#define FRF_AB_EE_VPD_BASE_WIDTH 24 66#define FRF_AB_EE_VPD_LENGTH_LBN 16 67#define FRF_AB_EE_VPD_LENGTH_WIDTH 15 68#define FRF_AB_EE_VPD_AD_SIZE_LBN 8 69#define FRF_AB_EE_VPD_AD_SIZE_WIDTH 5 70#define FRF_AB_EE_VPD_ACCESS_ON_LBN 5 71#define FRF_AB_EE_VPD_ACCESS_ON_WIDTH 1 72#define FRF_AB_EE_VPD_ACCESS_BLOCK_LBN 4 73#define FRF_AB_EE_VPD_ACCESS_BLOCK_WIDTH 1 74#define FRF_AB_EE_VPD_DEV_SF_SEL_LBN 2 75#define FRF_AB_EE_VPD_DEV_SF_SEL_WIDTH 1 76#define FRF_AB_EE_VPD_EN_AD9_MODE_LBN 1 77#define FRF_AB_EE_VPD_EN_AD9_MODE_WIDTH 1 78#define FRF_AB_EE_VPD_EN_LBN 0 79#define FRF_AB_EE_VPD_EN_WIDTH 1 80 81 82/* 83 * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit): 84 * PCIE SerDes control register 0 to 3 85 */ 86#define FR_AB_PCIE_SD_CTL0123_REG_SF_OFST 0x00000320 87/* falcona0,falconb0=eeprom_flash */ 88/* 89 * FR_AB_PCIE_SD_CTL0123_REG(128bit): 90 * PCIE SerDes control register 0 to 3 91 */ 92#define FR_AB_PCIE_SD_CTL0123_REG_OFST 0x00000320 93/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 94 95#define FRF_AB_PCIE_TESTSIG_H_LBN 96 96#define FRF_AB_PCIE_TESTSIG_H_WIDTH 19 97#define FRF_AB_PCIE_TESTSIG_L_LBN 64 98#define FRF_AB_PCIE_TESTSIG_L_WIDTH 19 99#define FRF_AB_PCIE_OFFSET_LBN 56 100#define FRF_AB_PCIE_OFFSET_WIDTH 8 101#define FRF_AB_PCIE_OFFSETEN_H_LBN 55 102#define FRF_AB_PCIE_OFFSETEN_H_WIDTH 1 103#define FRF_AB_PCIE_OFFSETEN_L_LBN 54 104#define FRF_AB_PCIE_OFFSETEN_L_WIDTH 1 105#define FRF_AB_PCIE_HIVMODE_H_LBN 53 106#define FRF_AB_PCIE_HIVMODE_H_WIDTH 1 107#define FRF_AB_PCIE_HIVMODE_L_LBN 52 108#define FRF_AB_PCIE_HIVMODE_L_WIDTH 1 109#define FRF_AB_PCIE_PARRESET_H_LBN 51 110#define FRF_AB_PCIE_PARRESET_H_WIDTH 1 111#define FRF_AB_PCIE_PARRESET_L_LBN 50 112#define FRF_AB_PCIE_PARRESET_L_WIDTH 1 113#define FRF_AB_PCIE_LPBKWDRV_H_LBN 49 114#define FRF_AB_PCIE_LPBKWDRV_H_WIDTH 1 115#define FRF_AB_PCIE_LPBKWDRV_L_LBN 48 116#define FRF_AB_PCIE_LPBKWDRV_L_WIDTH 1 117#define FRF_AB_PCIE_LPBK_LBN 40 118#define FRF_AB_PCIE_LPBK_WIDTH 8 119#define FRF_AB_PCIE_PARLPBK_LBN 32 120#define FRF_AB_PCIE_PARLPBK_WIDTH 8 121#define FRF_AB_PCIE_RXTERMADJ_H_LBN 30 122#define FRF_AB_PCIE_RXTERMADJ_H_WIDTH 2 123#define FRF_AB_PCIE_RXTERMADJ_L_LBN 28 124#define FRF_AB_PCIE_RXTERMADJ_L_WIDTH 2 125#define FFE_AB_PCIE_RXTERMADJ_MIN15PCNT 3 126#define FFE_AB_PCIE_RXTERMADJ_PL10PCNT 2 127#define FFE_AB_PCIE_RXTERMADJ_MIN17PCNT 1 128#define FFE_AB_PCIE_RXTERMADJ_NOMNL 0 129#define FRF_AB_PCIE_TXTERMADJ_H_LBN 26 130#define FRF_AB_PCIE_TXTERMADJ_H_WIDTH 2 131#define FRF_AB_PCIE_TXTERMADJ_L_LBN 24 132#define FRF_AB_PCIE_TXTERMADJ_L_WIDTH 2 133#define FFE_AB_PCIE_TXTERMADJ_MIN15PCNT 3 134#define FFE_AB_PCIE_TXTERMADJ_PL10PCNT 2 135#define FFE_AB_PCIE_TXTERMADJ_MIN17PCNT 1 136#define FFE_AB_PCIE_TXTERMADJ_NOMNL 0 137#define FRF_AB_PCIE_RXEQCTL_H_LBN 18 138#define FRF_AB_PCIE_RXEQCTL_H_WIDTH 2 139#define FRF_AB_PCIE_RXEQCTL_L_LBN 16 140#define FRF_AB_PCIE_RXEQCTL_L_WIDTH 2 141#define FFE_AB_PCIE_RXEQCTL_OFF_ALT 3 142#define FFE_AB_PCIE_RXEQCTL_OFF 2 143#define FFE_AB_PCIE_RXEQCTL_MIN 1 144#define FFE_AB_PCIE_RXEQCTL_MAX 0 145#define FRF_AB_PCIE_HIDRV_LBN 8 146#define FRF_AB_PCIE_HIDRV_WIDTH 8 147#define FRF_AB_PCIE_LODRV_LBN 0 148#define FRF_AB_PCIE_LODRV_WIDTH 8 149 150 151/* 152 * FR_AB_PCIE_SD_CTL45_REG_SF(128bit): 153 * PCIE SerDes control register 4 and 5 154 */ 155#define FR_AB_PCIE_SD_CTL45_REG_SF_OFST 0x00000330 156/* falcona0,falconb0=eeprom_flash */ 157/* 158 * FR_AB_PCIE_SD_CTL45_REG(128bit): 159 * PCIE SerDes control register 4 and 5 160 */ 161#define FR_AB_PCIE_SD_CTL45_REG_OFST 0x00000330 162/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 163 164#define FRF_AB_PCIE_DTX7_LBN 60 165#define FRF_AB_PCIE_DTX7_WIDTH 4 166#define FRF_AB_PCIE_DTX6_LBN 56 167#define FRF_AB_PCIE_DTX6_WIDTH 4 168#define FRF_AB_PCIE_DTX5_LBN 52 169#define FRF_AB_PCIE_DTX5_WIDTH 4 170#define FRF_AB_PCIE_DTX4_LBN 48 171#define FRF_AB_PCIE_DTX4_WIDTH 4 172#define FRF_AB_PCIE_DTX3_LBN 44 173#define FRF_AB_PCIE_DTX3_WIDTH 4 174#define FRF_AB_PCIE_DTX2_LBN 40 175#define FRF_AB_PCIE_DTX2_WIDTH 4 176#define FRF_AB_PCIE_DTX1_LBN 36 177#define FRF_AB_PCIE_DTX1_WIDTH 4 178#define FRF_AB_PCIE_DTX0_LBN 32 179#define FRF_AB_PCIE_DTX0_WIDTH 4 180#define FRF_AB_PCIE_DEQ7_LBN 28 181#define FRF_AB_PCIE_DEQ7_WIDTH 4 182#define FRF_AB_PCIE_DEQ6_LBN 24 183#define FRF_AB_PCIE_DEQ6_WIDTH 4 184#define FRF_AB_PCIE_DEQ5_LBN 20 185#define FRF_AB_PCIE_DEQ5_WIDTH 4 186#define FRF_AB_PCIE_DEQ4_LBN 16 187#define FRF_AB_PCIE_DEQ4_WIDTH 4 188#define FRF_AB_PCIE_DEQ3_LBN 12 189#define FRF_AB_PCIE_DEQ3_WIDTH 4 190#define FRF_AB_PCIE_DEQ2_LBN 8 191#define FRF_AB_PCIE_DEQ2_WIDTH 4 192#define FRF_AB_PCIE_DEQ1_LBN 4 193#define FRF_AB_PCIE_DEQ1_WIDTH 4 194#define FRF_AB_PCIE_DEQ0_LBN 0 195#define FRF_AB_PCIE_DEQ0_WIDTH 4 196 197 198/* 199 * FR_AB_PCIE_PCS_CTL_STAT_REG_SF(128bit): 200 * PCIE PCS control and status register 201 */ 202#define FR_AB_PCIE_PCS_CTL_STAT_REG_SF_OFST 0x00000340 203/* falcona0,falconb0=eeprom_flash */ 204/* 205 * FR_AB_PCIE_PCS_CTL_STAT_REG(128bit): 206 * PCIE PCS control and status register 207 */ 208#define FR_AB_PCIE_PCS_CTL_STAT_REG_OFST 0x00000340 209/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 210 211#define FRF_AB_PCIE_PRBSERRCOUNT0_H_LBN 52 212#define FRF_AB_PCIE_PRBSERRCOUNT0_H_WIDTH 4 213#define FRF_AB_PCIE_PRBSERRCOUNT0_L_LBN 48 214#define FRF_AB_PCIE_PRBSERRCOUNT0_L_WIDTH 4 215#define FRF_AB_PCIE_PRBSERR_LBN 40 216#define FRF_AB_PCIE_PRBSERR_WIDTH 8 217#define FRF_AB_PCIE_PRBSERRH0_LBN 32 218#define FRF_AB_PCIE_PRBSERRH0_WIDTH 8 219#define FRF_AB_PCIE_FASTINIT_H_LBN 15 220#define FRF_AB_PCIE_FASTINIT_H_WIDTH 1 221#define FRF_AB_PCIE_FASTINIT_L_LBN 14 222#define FRF_AB_PCIE_FASTINIT_L_WIDTH 1 223#define FRF_AB_PCIE_CTCDISABLE_H_LBN 13 224#define FRF_AB_PCIE_CTCDISABLE_H_WIDTH 1 225#define FRF_AB_PCIE_CTCDISABLE_L_LBN 12 226#define FRF_AB_PCIE_CTCDISABLE_L_WIDTH 1 227#define FRF_AB_PCIE_PRBSSYNC_H_LBN 11 228#define FRF_AB_PCIE_PRBSSYNC_H_WIDTH 1 229#define FRF_AB_PCIE_PRBSSYNC_L_LBN 10 230#define FRF_AB_PCIE_PRBSSYNC_L_WIDTH 1 231#define FRF_AB_PCIE_PRBSERRACK_H_LBN 9 232#define FRF_AB_PCIE_PRBSERRACK_H_WIDTH 1 233#define FRF_AB_PCIE_PRBSERRACK_L_LBN 8 234#define FRF_AB_PCIE_PRBSERRACK_L_WIDTH 1 235#define FRF_AB_PCIE_PRBSSEL_LBN 0 236#define FRF_AB_PCIE_PRBSSEL_WIDTH 8 237 238 239/* 240 * FR_AB_HW_INIT_REG_SF(128bit): 241 * Hardware initialization register 242 */ 243#define FR_AB_HW_INIT_REG_SF_OFST 0x00000350 244/* falcona0,falconb0=eeprom_flash */ 245/* 246 * FR_AZ_HW_INIT_REG(128bit): 247 * Hardware initialization register 248 */ 249#define FR_AZ_HW_INIT_REG_OFST 0x000000c0 250/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 251 252#define FRF_BB_BDMRD_CPLF_FULL_LBN 124 253#define FRF_BB_BDMRD_CPLF_FULL_WIDTH 1 254#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_LBN 121 255#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_WIDTH 3 256#define FRF_CZ_TX_MRG_TAGS_LBN 120 257#define FRF_CZ_TX_MRG_TAGS_WIDTH 1 258#define FRF_AZ_TRGT_MASK_ALL_LBN 100 259#define FRF_AZ_TRGT_MASK_ALL_WIDTH 1 260#define FRF_AZ_DOORBELL_DROP_LBN 92 261#define FRF_AZ_DOORBELL_DROP_WIDTH 8 262#define FRF_AB_TX_RREQ_MASK_EN_LBN 76 263#define FRF_AB_TX_RREQ_MASK_EN_WIDTH 1 264#define FRF_AB_PE_EIDLE_DIS_LBN 75 265#define FRF_AB_PE_EIDLE_DIS_WIDTH 1 266#define FRF_AZ_FC_BLOCKING_EN_LBN 45 267#define FRF_AZ_FC_BLOCKING_EN_WIDTH 1 268#define FRF_AZ_B2B_REQ_EN_LBN 44 269#define FRF_AZ_B2B_REQ_EN_WIDTH 1 270#define FRF_AZ_POST_WR_MASK_LBN 40 271#define FRF_AZ_POST_WR_MASK_WIDTH 4 272#define FRF_AZ_TLP_TC_LBN 34 273#define FRF_AZ_TLP_TC_WIDTH 3 274#define FRF_AZ_TLP_ATTR_LBN 32 275#define FRF_AZ_TLP_ATTR_WIDTH 2 276#define FRF_AB_INTB_VEC_LBN 24 277#define FRF_AB_INTB_VEC_WIDTH 5 278#define FRF_AB_INTA_VEC_LBN 16 279#define FRF_AB_INTA_VEC_WIDTH 5 280#define FRF_AZ_WD_TIMER_LBN 8 281#define FRF_AZ_WD_TIMER_WIDTH 8 282#define FRF_AZ_US_DISABLE_LBN 5 283#define FRF_AZ_US_DISABLE_WIDTH 1 284#define FRF_AZ_TLP_EP_LBN 4 285#define FRF_AZ_TLP_EP_WIDTH 1 286#define FRF_AZ_ATTR_SEL_LBN 3 287#define FRF_AZ_ATTR_SEL_WIDTH 1 288#define FRF_AZ_TD_SEL_LBN 1 289#define FRF_AZ_TD_SEL_WIDTH 1 290#define FRF_AZ_TLP_TD_LBN 0 291#define FRF_AZ_TLP_TD_WIDTH 1 292 293 294/* 295 * FR_AB_NIC_STAT_REG_SF(128bit): 296 * NIC status register 297 */ 298#define FR_AB_NIC_STAT_REG_SF_OFST 0x00000360 299/* falcona0,falconb0=eeprom_flash */ 300/* 301 * FR_AB_NIC_STAT_REG(128bit): 302 * NIC status register 303 */ 304#define FR_AB_NIC_STAT_REG_OFST 0x00000200 305/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 306 307#define FRF_BB_AER_DIS_LBN 34 308#define FRF_BB_AER_DIS_WIDTH 1 309#define FRF_BB_EE_STRAP_EN_LBN 31 310#define FRF_BB_EE_STRAP_EN_WIDTH 1 311#define FRF_BB_EE_STRAP_LBN 24 312#define FRF_BB_EE_STRAP_WIDTH 4 313#define FRF_BB_REVISION_ID_LBN 17 314#define FRF_BB_REVISION_ID_WIDTH 7 315#define FRF_AB_ONCHIP_SRAM_LBN 16 316#define FRF_AB_ONCHIP_SRAM_WIDTH 1 317#define FRF_AB_SF_PRST_LBN 9 318#define FRF_AB_SF_PRST_WIDTH 1 319#define FRF_AB_EE_PRST_LBN 8 320#define FRF_AB_EE_PRST_WIDTH 1 321#define FRF_AB_ATE_MODE_LBN 3 322#define FRF_AB_ATE_MODE_WIDTH 1 323#define FRF_AB_STRAP_PINS_LBN 0 324#define FRF_AB_STRAP_PINS_WIDTH 3 325 326 327/* 328 * FR_AB_GLB_CTL_REG_SF(128bit): 329 * Global control register 330 */ 331#define FR_AB_GLB_CTL_REG_SF_OFST 0x00000370 332/* falcona0,falconb0=eeprom_flash */ 333/* 334 * FR_AB_GLB_CTL_REG(128bit): 335 * Global control register 336 */ 337#define FR_AB_GLB_CTL_REG_OFST 0x00000220 338/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 339 340#define FRF_AB_EXT_PHY_RST_CTL_LBN 63 341#define FRF_AB_EXT_PHY_RST_CTL_WIDTH 1 342#define FRF_AB_XAUI_SD_RST_CTL_LBN 62 343#define FRF_AB_XAUI_SD_RST_CTL_WIDTH 1 344#define FRF_AB_PCIE_SD_RST_CTL_LBN 61 345#define FRF_AB_PCIE_SD_RST_CTL_WIDTH 1 346#define FRF_AA_PCIX_RST_CTL_LBN 60 347#define FRF_AA_PCIX_RST_CTL_WIDTH 1 348#define FRF_BB_BIU_RST_CTL_LBN 60 349#define FRF_BB_BIU_RST_CTL_WIDTH 1 350#define FRF_AB_PCIE_STKY_RST_CTL_LBN 59 351#define FRF_AB_PCIE_STKY_RST_CTL_WIDTH 1 352#define FRF_AB_PCIE_NSTKY_RST_CTL_LBN 58 353#define FRF_AB_PCIE_NSTKY_RST_CTL_WIDTH 1 354#define FRF_AB_PCIE_CORE_RST_CTL_LBN 57 355#define FRF_AB_PCIE_CORE_RST_CTL_WIDTH 1 356#define FRF_AB_XGRX_RST_CTL_LBN 56 357#define FRF_AB_XGRX_RST_CTL_WIDTH 1 358#define FRF_AB_XGTX_RST_CTL_LBN 55 359#define FRF_AB_XGTX_RST_CTL_WIDTH 1 360#define FRF_AB_EM_RST_CTL_LBN 54 361#define FRF_AB_EM_RST_CTL_WIDTH 1 362#define FRF_AB_EV_RST_CTL_LBN 53 363#define FRF_AB_EV_RST_CTL_WIDTH 1 364#define FRF_AB_SR_RST_CTL_LBN 52 365#define FRF_AB_SR_RST_CTL_WIDTH 1 366#define FRF_AB_RX_RST_CTL_LBN 51 367#define FRF_AB_RX_RST_CTL_WIDTH 1 368#define FRF_AB_TX_RST_CTL_LBN 50 369#define FRF_AB_TX_RST_CTL_WIDTH 1 370#define FRF_AB_EE_RST_CTL_LBN 49 371#define FRF_AB_EE_RST_CTL_WIDTH 1 372#define FRF_AB_CS_RST_CTL_LBN 48 373#define FRF_AB_CS_RST_CTL_WIDTH 1 374#define FRF_AB_HOT_RST_CTL_LBN 40 375#define FRF_AB_HOT_RST_CTL_WIDTH 2 376#define FRF_AB_RST_EXT_PHY_LBN 31 377#define FRF_AB_RST_EXT_PHY_WIDTH 1 378#define FRF_AB_RST_XAUI_SD_LBN 30 379#define FRF_AB_RST_XAUI_SD_WIDTH 1 380#define FRF_AB_RST_PCIE_SD_LBN 29 381#define FRF_AB_RST_PCIE_SD_WIDTH 1 382#define FRF_AA_RST_PCIX_LBN 28 383#define FRF_AA_RST_PCIX_WIDTH 1 384#define FRF_BB_RST_BIU_LBN 28 385#define FRF_BB_RST_BIU_WIDTH 1 386#define FRF_AB_RST_PCIE_STKY_LBN 27 387#define FRF_AB_RST_PCIE_STKY_WIDTH 1 388#define FRF_AB_RST_PCIE_NSTKY_LBN 26 389#define FRF_AB_RST_PCIE_NSTKY_WIDTH 1 390#define FRF_AB_RST_PCIE_CORE_LBN 25 391#define FRF_AB_RST_PCIE_CORE_WIDTH 1 392#define FRF_AB_RST_XGRX_LBN 24 393#define FRF_AB_RST_XGRX_WIDTH 1 394#define FRF_AB_RST_XGTX_LBN 23 395#define FRF_AB_RST_XGTX_WIDTH 1 396#define FRF_AB_RST_EM_LBN 22 397#define FRF_AB_RST_EM_WIDTH 1 398#define FRF_AB_RST_EV_LBN 21 399#define FRF_AB_RST_EV_WIDTH 1 400#define FRF_AB_RST_SR_LBN 20 401#define FRF_AB_RST_SR_WIDTH 1 402#define FRF_AB_RST_RX_LBN 19 403#define FRF_AB_RST_RX_WIDTH 1 404#define FRF_AB_RST_TX_LBN 18 405#define FRF_AB_RST_TX_WIDTH 1 406#define FRF_AB_RST_SF_LBN 17 407#define FRF_AB_RST_SF_WIDTH 1 408#define FRF_AB_RST_CS_LBN 16 409#define FRF_AB_RST_CS_WIDTH 1 410#define FRF_AB_INT_RST_DUR_LBN 4 411#define FRF_AB_INT_RST_DUR_WIDTH 3 412#define FRF_AB_EXT_PHY_RST_DUR_LBN 1 413#define FRF_AB_EXT_PHY_RST_DUR_WIDTH 3 414#define FFE_AB_EXT_PHY_RST_DUR_10240US 7 415#define FFE_AB_EXT_PHY_RST_DUR_5120US 6 416#define FFE_AB_EXT_PHY_RST_DUR_2560US 5 417#define FFE_AB_EXT_PHY_RST_DUR_1280US 4 418#define FFE_AB_EXT_PHY_RST_DUR_640US 3 419#define FFE_AB_EXT_PHY_RST_DUR_320US 2 420#define FFE_AB_EXT_PHY_RST_DUR_160US 1 421#define FFE_AB_EXT_PHY_RST_DUR_80US 0 422#define FRF_AB_SWRST_LBN 0 423#define FRF_AB_SWRST_WIDTH 1 424 425 426/* 427 * FR_AZ_IOM_IND_ADR_REG(32bit): 428 * IO-mapped indirect access address register 429 */ 430#define FR_AZ_IOM_IND_ADR_REG_OFST 0x00000000 431/* falcona0,falconb0,sienaa0=net_func_bar0 */ 432 433#define FRF_AZ_IOM_AUTO_ADR_INC_EN_LBN 24 434#define FRF_AZ_IOM_AUTO_ADR_INC_EN_WIDTH 1 435#define FRF_AZ_IOM_IND_ADR_LBN 0 436#define FRF_AZ_IOM_IND_ADR_WIDTH 24 437 438 439/* 440 * FR_AZ_IOM_IND_DAT_REG(32bit): 441 * IO-mapped indirect access data register 442 */ 443#define FR_AZ_IOM_IND_DAT_REG_OFST 0x00000004 444/* falcona0,falconb0,sienaa0=net_func_bar0 */ 445 446#define FRF_AZ_IOM_IND_DAT_LBN 0 447#define FRF_AZ_IOM_IND_DAT_WIDTH 32 448 449 450/* 451 * FR_AZ_ADR_REGION_REG(128bit): 452 * Address region register 453 */ 454#define FR_AZ_ADR_REGION_REG_OFST 0x00000000 455/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 456 457#define FRF_AZ_ADR_REGION3_LBN 96 458#define FRF_AZ_ADR_REGION3_WIDTH 18 459#define FRF_AZ_ADR_REGION2_LBN 64 460#define FRF_AZ_ADR_REGION2_WIDTH 18 461#define FRF_AZ_ADR_REGION1_LBN 32 462#define FRF_AZ_ADR_REGION1_WIDTH 18 463#define FRF_AZ_ADR_REGION0_LBN 0 464#define FRF_AZ_ADR_REGION0_WIDTH 18 465 466 467/* 468 * FR_AZ_INT_EN_REG_KER(128bit): 469 * Kernel driver Interrupt enable register 470 */ 471#define FR_AZ_INT_EN_REG_KER_OFST 0x00000010 472/* falcona0,falconb0,sienaa0=net_func_bar2 */ 473 474#define FRF_AZ_KER_INT_LEVE_SEL_LBN 8 475#define FRF_AZ_KER_INT_LEVE_SEL_WIDTH 6 476#define FRF_AZ_KER_INT_CHAR_LBN 4 477#define FRF_AZ_KER_INT_CHAR_WIDTH 1 478#define FRF_AZ_KER_INT_KER_LBN 3 479#define FRF_AZ_KER_INT_KER_WIDTH 1 480#define FRF_AZ_DRV_INT_EN_KER_LBN 0 481#define FRF_AZ_DRV_INT_EN_KER_WIDTH 1 482 483 484/* 485 * FR_AZ_INT_EN_REG_CHAR(128bit): 486 * Char Driver interrupt enable register 487 */ 488#define FR_AZ_INT_EN_REG_CHAR_OFST 0x00000020 489/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 490 491#define FRF_AZ_CHAR_INT_LEVE_SEL_LBN 8 492#define FRF_AZ_CHAR_INT_LEVE_SEL_WIDTH 6 493#define FRF_AZ_CHAR_INT_CHAR_LBN 4 494#define FRF_AZ_CHAR_INT_CHAR_WIDTH 1 495#define FRF_AZ_CHAR_INT_KER_LBN 3 496#define FRF_AZ_CHAR_INT_KER_WIDTH 1 497#define FRF_AZ_DRV_INT_EN_CHAR_LBN 0 498#define FRF_AZ_DRV_INT_EN_CHAR_WIDTH 1 499 500 501/* 502 * FR_AZ_INT_ADR_REG_KER(128bit): 503 * Interrupt host address for Kernel driver 504 */ 505#define FR_AZ_INT_ADR_REG_KER_OFST 0x00000030 506/* falcona0,falconb0,sienaa0=net_func_bar2 */ 507 508#define FRF_AZ_NORM_INT_VEC_DIS_KER_LBN 64 509#define FRF_AZ_NORM_INT_VEC_DIS_KER_WIDTH 1 510#define FRF_AZ_INT_ADR_KER_LBN 0 511#define FRF_AZ_INT_ADR_KER_WIDTH 64 512#define FRF_AZ_INT_ADR_KER_DW0_LBN 0 513#define FRF_AZ_INT_ADR_KER_DW0_WIDTH 32 514#define FRF_AZ_INT_ADR_KER_DW1_LBN 32 515#define FRF_AZ_INT_ADR_KER_DW1_WIDTH 32 516 517 518/* 519 * FR_AZ_INT_ADR_REG_CHAR(128bit): 520 * Interrupt host address for Char driver 521 */ 522#define FR_AZ_INT_ADR_REG_CHAR_OFST 0x00000040 523/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 524 525#define FRF_AZ_NORM_INT_VEC_DIS_CHAR_LBN 64 526#define FRF_AZ_NORM_INT_VEC_DIS_CHAR_WIDTH 1 527#define FRF_AZ_INT_ADR_CHAR_LBN 0 528#define FRF_AZ_INT_ADR_CHAR_WIDTH 64 529#define FRF_AZ_INT_ADR_CHAR_DW0_LBN 0 530#define FRF_AZ_INT_ADR_CHAR_DW0_WIDTH 32 531#define FRF_AZ_INT_ADR_CHAR_DW1_LBN 32 532#define FRF_AZ_INT_ADR_CHAR_DW1_WIDTH 32 533 534 535/* 536 * FR_AA_INT_ACK_KER(32bit): 537 * Kernel interrupt acknowledge register 538 */ 539#define FR_AA_INT_ACK_KER_OFST 0x00000050 540/* falcona0=net_func_bar2 */ 541 542#define FRF_AA_INT_ACK_KER_FIELD_LBN 0 543#define FRF_AA_INT_ACK_KER_FIELD_WIDTH 32 544 545 546/* 547 * FR_BZ_INT_ISR0_REG(128bit): 548 * Function 0 Interrupt Acknowlege Status register 549 */ 550#define FR_BZ_INT_ISR0_REG_OFST 0x00000090 551/* falconb0,sienaa0=net_func_bar2 */ 552 553#define FRF_BZ_INT_ISR_REG_LBN 0 554#define FRF_BZ_INT_ISR_REG_WIDTH 64 555#define FRF_BZ_INT_ISR_REG_DW0_LBN 0 556#define FRF_BZ_INT_ISR_REG_DW0_WIDTH 32 557#define FRF_BZ_INT_ISR_REG_DW1_LBN 32 558#define FRF_BZ_INT_ISR_REG_DW1_WIDTH 32 559 560 561/* 562 * FR_AB_EE_SPI_HCMD_REG(128bit): 563 * SPI host command register 564 */ 565#define FR_AB_EE_SPI_HCMD_REG_OFST 0x00000100 566/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 567 568#define FRF_AB_EE_SPI_HCMD_CMD_EN_LBN 31 569#define FRF_AB_EE_SPI_HCMD_CMD_EN_WIDTH 1 570#define FRF_AB_EE_WR_TIMER_ACTIVE_LBN 28 571#define FRF_AB_EE_WR_TIMER_ACTIVE_WIDTH 1 572#define FRF_AB_EE_SPI_HCMD_SF_SEL_LBN 24 573#define FRF_AB_EE_SPI_HCMD_SF_SEL_WIDTH 1 574#define FRF_AB_EE_SPI_HCMD_DABCNT_LBN 16 575#define FRF_AB_EE_SPI_HCMD_DABCNT_WIDTH 5 576#define FRF_AB_EE_SPI_HCMD_READ_LBN 15 577#define FRF_AB_EE_SPI_HCMD_READ_WIDTH 1 578#define FRF_AB_EE_SPI_HCMD_DUBCNT_LBN 12 579#define FRF_AB_EE_SPI_HCMD_DUBCNT_WIDTH 2 580#define FRF_AB_EE_SPI_HCMD_ADBCNT_LBN 8 581#define FRF_AB_EE_SPI_HCMD_ADBCNT_WIDTH 2 582#define FRF_AB_EE_SPI_HCMD_ENC_LBN 0 583#define FRF_AB_EE_SPI_HCMD_ENC_WIDTH 8 584 585 586/* 587 * FR_CZ_USR_EV_CFG(32bit): 588 * User Level Event Configuration register 589 */ 590#define FR_CZ_USR_EV_CFG_OFST 0x00000100 591/* sienaa0=net_func_bar2 */ 592 593#define FRF_CZ_USREV_DIS_LBN 16 594#define FRF_CZ_USREV_DIS_WIDTH 1 595#define FRF_CZ_DFLT_EVQ_LBN 0 596#define FRF_CZ_DFLT_EVQ_WIDTH 10 597 598 599/* 600 * FR_AB_EE_SPI_HADR_REG(128bit): 601 * SPI host address register 602 */ 603#define FR_AB_EE_SPI_HADR_REG_OFST 0x00000110 604/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 605 606#define FRF_AB_EE_SPI_HADR_DUBYTE_LBN 24 607#define FRF_AB_EE_SPI_HADR_DUBYTE_WIDTH 8 608#define FRF_AB_EE_SPI_HADR_ADR_LBN 0 609#define FRF_AB_EE_SPI_HADR_ADR_WIDTH 24 610 611 612/* 613 * FR_AB_EE_SPI_HDATA_REG(128bit): 614 * SPI host data register 615 */ 616#define FR_AB_EE_SPI_HDATA_REG_OFST 0x00000120 617/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 618 619#define FRF_AB_EE_SPI_HDATA3_LBN 96 620#define FRF_AB_EE_SPI_HDATA3_WIDTH 32 621#define FRF_AB_EE_SPI_HDATA2_LBN 64 622#define FRF_AB_EE_SPI_HDATA2_WIDTH 32 623#define FRF_AB_EE_SPI_HDATA1_LBN 32 624#define FRF_AB_EE_SPI_HDATA1_WIDTH 32 625#define FRF_AB_EE_SPI_HDATA0_LBN 0 626#define FRF_AB_EE_SPI_HDATA0_WIDTH 32 627 628 629/* 630 * FR_AB_EE_BASE_PAGE_REG(128bit): 631 * Expansion ROM base mirror register 632 */ 633#define FR_AB_EE_BASE_PAGE_REG_OFST 0x00000130 634/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 635 636#define FRF_AB_EE_EXPROM_MASK_LBN 16 637#define FRF_AB_EE_EXPROM_MASK_WIDTH 13 638#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_LBN 0 639#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_WIDTH 13 640 641 642/* 643 * FR_AB_EE_VPD_SW_CNTL_REG(128bit): 644 * VPD access SW control register 645 */ 646#define FR_AB_EE_VPD_SW_CNTL_REG_OFST 0x00000150 647/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 648 649#define FRF_AB_EE_VPD_CYCLE_PENDING_LBN 31 650#define FRF_AB_EE_VPD_CYCLE_PENDING_WIDTH 1 651#define FRF_AB_EE_VPD_CYC_WRITE_LBN 28 652#define FRF_AB_EE_VPD_CYC_WRITE_WIDTH 1 653#define FRF_AB_EE_VPD_CYC_ADR_LBN 0 654#define FRF_AB_EE_VPD_CYC_ADR_WIDTH 15 655 656 657/* 658 * FR_AB_EE_VPD_SW_DATA_REG(128bit): 659 * VPD access SW data register 660 */ 661#define FR_AB_EE_VPD_SW_DATA_REG_OFST 0x00000160 662/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 663 664#define FRF_AB_EE_VPD_CYC_DAT_LBN 0 665#define FRF_AB_EE_VPD_CYC_DAT_WIDTH 32 666 667 668/* 669 * FR_BB_PCIE_CORE_INDIRECT_REG(64bit): 670 * Indirect Access to PCIE Core registers 671 */ 672#define FR_BB_PCIE_CORE_INDIRECT_REG_OFST 0x000001f0 673/* falconb0=net_func_bar2 */ 674 675#define FRF_BB_PCIE_CORE_TARGET_DATA_LBN 32 676#define FRF_BB_PCIE_CORE_TARGET_DATA_WIDTH 32 677#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_LBN 15 678#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_WIDTH 1 679#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_LBN 0 680#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_WIDTH 12 681 682 683/* 684 * FR_AB_GPIO_CTL_REG(128bit): 685 * GPIO control register 686 */ 687#define FR_AB_GPIO_CTL_REG_OFST 0x00000210 688/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 689 690#define FRF_AB_GPIO15_OEN_LBN 63 691#define FRF_AB_GPIO15_OEN_WIDTH 1 692#define FRF_AB_GPIO14_OEN_LBN 62 693#define FRF_AB_GPIO14_OEN_WIDTH 1 694#define FRF_AB_GPIO13_OEN_LBN 61 695#define FRF_AB_GPIO13_OEN_WIDTH 1 696#define FRF_AB_GPIO12_OEN_LBN 60 697#define FRF_AB_GPIO12_OEN_WIDTH 1 698#define FRF_AB_GPIO11_OEN_LBN 59 699#define FRF_AB_GPIO11_OEN_WIDTH 1 700#define FRF_AB_GPIO10_OEN_LBN 58 701#define FRF_AB_GPIO10_OEN_WIDTH 1 702#define FRF_AB_GPIO9_OEN_LBN 57 703#define FRF_AB_GPIO9_OEN_WIDTH 1 704#define FRF_AB_GPIO8_OEN_LBN 56 705#define FRF_AB_GPIO8_OEN_WIDTH 1 706#define FRF_AB_GPIO15_OUT_LBN 55 707#define FRF_AB_GPIO15_OUT_WIDTH 1 708#define FRF_AB_GPIO14_OUT_LBN 54 709#define FRF_AB_GPIO14_OUT_WIDTH 1 710#define FRF_AB_GPIO13_OUT_LBN 53 711#define FRF_AB_GPIO13_OUT_WIDTH 1 712#define FRF_AB_GPIO12_OUT_LBN 52 713#define FRF_AB_GPIO12_OUT_WIDTH 1 714#define FRF_AB_GPIO11_OUT_LBN 51 715#define FRF_AB_GPIO11_OUT_WIDTH 1 716#define FRF_AB_GPIO10_OUT_LBN 50 717#define FRF_AB_GPIO10_OUT_WIDTH 1 718#define FRF_AB_GPIO9_OUT_LBN 49 719#define FRF_AB_GPIO9_OUT_WIDTH 1 720#define FRF_AB_GPIO8_OUT_LBN 48 721#define FRF_AB_GPIO8_OUT_WIDTH 1 722#define FRF_AB_GPIO15_IN_LBN 47 723#define FRF_AB_GPIO15_IN_WIDTH 1 724#define FRF_AB_GPIO14_IN_LBN 46 725#define FRF_AB_GPIO14_IN_WIDTH 1 726#define FRF_AB_GPIO13_IN_LBN 45 727#define FRF_AB_GPIO13_IN_WIDTH 1 728#define FRF_AB_GPIO12_IN_LBN 44 729#define FRF_AB_GPIO12_IN_WIDTH 1 730#define FRF_AB_GPIO11_IN_LBN 43 731#define FRF_AB_GPIO11_IN_WIDTH 1 732#define FRF_AB_GPIO10_IN_LBN 42 733#define FRF_AB_GPIO10_IN_WIDTH 1 734#define FRF_AB_GPIO9_IN_LBN 41 735#define FRF_AB_GPIO9_IN_WIDTH 1 736#define FRF_AB_GPIO8_IN_LBN 40 737#define FRF_AB_GPIO8_IN_WIDTH 1 738#define FRF_AB_GPIO15_PWRUP_VALUE_LBN 39 739#define FRF_AB_GPIO15_PWRUP_VALUE_WIDTH 1 740#define FRF_AB_GPIO14_PWRUP_VALUE_LBN 38 741#define FRF_AB_GPIO14_PWRUP_VALUE_WIDTH 1 742#define FRF_AB_GPIO13_PWRUP_VALUE_LBN 37 743#define FRF_AB_GPIO13_PWRUP_VALUE_WIDTH 1 744#define FRF_AB_GPIO12_PWRUP_VALUE_LBN 36 745#define FRF_AB_GPIO12_PWRUP_VALUE_WIDTH 1 746#define FRF_AB_GPIO11_PWRUP_VALUE_LBN 35 747#define FRF_AB_GPIO11_PWRUP_VALUE_WIDTH 1 748#define FRF_AB_GPIO10_PWRUP_VALUE_LBN 34 749#define FRF_AB_GPIO10_PWRUP_VALUE_WIDTH 1 750#define FRF_AB_GPIO9_PWRUP_VALUE_LBN 33 751#define FRF_AB_GPIO9_PWRUP_VALUE_WIDTH 1 752#define FRF_AB_GPIO8_PWRUP_VALUE_LBN 32 753#define FRF_AB_GPIO8_PWRUP_VALUE_WIDTH 1 754#define FRF_BB_CLK156_OUT_EN_LBN 31 755#define FRF_BB_CLK156_OUT_EN_WIDTH 1 756#define FRF_BB_USE_NIC_CLK_LBN 30 757#define FRF_BB_USE_NIC_CLK_WIDTH 1 758#define FRF_AB_GPIO5_OEN_LBN 29 759#define FRF_AB_GPIO5_OEN_WIDTH 1 760#define FRF_AB_GPIO4_OEN_LBN 28 761#define FRF_AB_GPIO4_OEN_WIDTH 1 762#define FRF_AB_GPIO3_OEN_LBN 27 763#define FRF_AB_GPIO3_OEN_WIDTH 1 764#define FRF_AB_GPIO2_OEN_LBN 26 765#define FRF_AB_GPIO2_OEN_WIDTH 1 766#define FRF_AB_GPIO1_OEN_LBN 25 767#define FRF_AB_GPIO1_OEN_WIDTH 1 768#define FRF_AB_GPIO0_OEN_LBN 24 769#define FRF_AB_GPIO0_OEN_WIDTH 1 770#define FRF_AB_GPIO5_OUT_LBN 21 771#define FRF_AB_GPIO5_OUT_WIDTH 1 772#define FRF_AB_GPIO4_OUT_LBN 20 773#define FRF_AB_GPIO4_OUT_WIDTH 1 774#define FRF_AB_GPIO3_OUT_LBN 19 775#define FRF_AB_GPIO3_OUT_WIDTH 1 776#define FRF_AB_GPIO2_OUT_LBN 18 777#define FRF_AB_GPIO2_OUT_WIDTH 1 778#define FRF_AB_GPIO1_OUT_LBN 17 779#define FRF_AB_GPIO1_OUT_WIDTH 1 780#define FRF_AB_GPIO0_OUT_LBN 16 781#define FRF_AB_GPIO0_OUT_WIDTH 1 782#define FRF_AB_GPIO5_IN_LBN 13 783#define FRF_AB_GPIO5_IN_WIDTH 1 784#define FRF_AB_GPIO4_IN_LBN 12 785#define FRF_AB_GPIO4_IN_WIDTH 1 786#define FRF_AB_GPIO3_IN_LBN 11 787#define FRF_AB_GPIO3_IN_WIDTH 1 788#define FRF_AB_GPIO2_IN_LBN 10 789#define FRF_AB_GPIO2_IN_WIDTH 1 790#define FRF_AB_GPIO1_IN_LBN 9 791#define FRF_AB_GPIO1_IN_WIDTH 1 792#define FRF_AB_GPIO0_IN_LBN 8 793#define FRF_AB_GPIO0_IN_WIDTH 1 794#define FRF_AB_GPIO5_PWRUP_VALUE_LBN 5 795#define FRF_AB_GPIO5_PWRUP_VALUE_WIDTH 1 796#define FRF_AB_GPIO4_PWRUP_VALUE_LBN 4 797#define FRF_AB_GPIO4_PWRUP_VALUE_WIDTH 1 798#define FRF_AB_GPIO3_PWRUP_VALUE_LBN 3 799#define FRF_AB_GPIO3_PWRUP_VALUE_WIDTH 1 800#define FRF_AB_GPIO2_PWRUP_VALUE_LBN 2 801#define FRF_AB_GPIO2_PWRUP_VALUE_WIDTH 1 802#define FRF_AB_GPIO1_PWRUP_VALUE_LBN 1 803#define FRF_AB_GPIO1_PWRUP_VALUE_WIDTH 1 804#define FRF_AB_GPIO0_PWRUP_VALUE_LBN 0 805#define FRF_AB_GPIO0_PWRUP_VALUE_WIDTH 1 806 807 808/* 809 * FR_AZ_FATAL_INTR_REG_KER(128bit): 810 * Fatal interrupt register for Kernel 811 */ 812#define FR_AZ_FATAL_INTR_REG_KER_OFST 0x00000230 813/* falcona0,falconb0,sienaa0=net_func_bar2 */ 814 815#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_LBN 44 816#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_WIDTH 1 817#define FRF_AB_PCI_BUSERR_INT_KER_EN_LBN 43 818#define FRF_AB_PCI_BUSERR_INT_KER_EN_WIDTH 1 819#define FRF_CZ_MBU_PERR_INT_KER_EN_LBN 43 820#define FRF_CZ_MBU_PERR_INT_KER_EN_WIDTH 1 821#define FRF_AZ_SRAM_OOB_INT_KER_EN_LBN 42 822#define FRF_AZ_SRAM_OOB_INT_KER_EN_WIDTH 1 823#define FRF_AZ_BUFID_OOB_INT_KER_EN_LBN 41 824#define FRF_AZ_BUFID_OOB_INT_KER_EN_WIDTH 1 825#define FRF_AZ_MEM_PERR_INT_KER_EN_LBN 40 826#define FRF_AZ_MEM_PERR_INT_KER_EN_WIDTH 1 827#define FRF_AZ_RBUF_OWN_INT_KER_EN_LBN 39 828#define FRF_AZ_RBUF_OWN_INT_KER_EN_WIDTH 1 829#define FRF_AZ_TBUF_OWN_INT_KER_EN_LBN 38 830#define FRF_AZ_TBUF_OWN_INT_KER_EN_WIDTH 1 831#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_LBN 37 832#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_WIDTH 1 833#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_LBN 36 834#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_WIDTH 1 835#define FRF_AZ_EVQ_OWN_INT_KER_EN_LBN 35 836#define FRF_AZ_EVQ_OWN_INT_KER_EN_WIDTH 1 837#define FRF_AZ_EVF_OFLO_INT_KER_EN_LBN 34 838#define FRF_AZ_EVF_OFLO_INT_KER_EN_WIDTH 1 839#define FRF_AZ_ILL_ADR_INT_KER_EN_LBN 33 840#define FRF_AZ_ILL_ADR_INT_KER_EN_WIDTH 1 841#define FRF_AZ_SRM_PERR_INT_KER_EN_LBN 32 842#define FRF_AZ_SRM_PERR_INT_KER_EN_WIDTH 1 843#define FRF_CZ_SRAM_PERR_INT_P_KER_LBN 12 844#define FRF_CZ_SRAM_PERR_INT_P_KER_WIDTH 1 845#define FRF_AB_PCI_BUSERR_INT_KER_LBN 11 846#define FRF_AB_PCI_BUSERR_INT_KER_WIDTH 1 847#define FRF_CZ_MBU_PERR_INT_KER_LBN 11 848#define FRF_CZ_MBU_PERR_INT_KER_WIDTH 1 849#define FRF_AZ_SRAM_OOB_INT_KER_LBN 10 850#define FRF_AZ_SRAM_OOB_INT_KER_WIDTH 1 851#define FRF_AZ_BUFID_DC_OOB_INT_KER_LBN 9 852#define FRF_AZ_BUFID_DC_OOB_INT_KER_WIDTH 1 853#define FRF_AZ_MEM_PERR_INT_KER_LBN 8 854#define FRF_AZ_MEM_PERR_INT_KER_WIDTH 1 855#define FRF_AZ_RBUF_OWN_INT_KER_LBN 7 856#define FRF_AZ_RBUF_OWN_INT_KER_WIDTH 1 857#define FRF_AZ_TBUF_OWN_INT_KER_LBN 6 858#define FRF_AZ_TBUF_OWN_INT_KER_WIDTH 1 859#define FRF_AZ_RDESCQ_OWN_INT_KER_LBN 5 860#define FRF_AZ_RDESCQ_OWN_INT_KER_WIDTH 1 861#define FRF_AZ_TDESCQ_OWN_INT_KER_LBN 4 862#define FRF_AZ_TDESCQ_OWN_INT_KER_WIDTH 1 863#define FRF_AZ_EVQ_OWN_INT_KER_LBN 3 864#define FRF_AZ_EVQ_OWN_INT_KER_WIDTH 1 865#define FRF_AZ_EVF_OFLO_INT_KER_LBN 2 866#define FRF_AZ_EVF_OFLO_INT_KER_WIDTH 1 867#define FRF_AZ_ILL_ADR_INT_KER_LBN 1 868#define FRF_AZ_ILL_ADR_INT_KER_WIDTH 1 869#define FRF_AZ_SRM_PERR_INT_KER_LBN 0 870#define FRF_AZ_SRM_PERR_INT_KER_WIDTH 1 871 872 873/* 874 * FR_AZ_FATAL_INTR_REG_CHAR(128bit): 875 * Fatal interrupt register for Char 876 */ 877#define FR_AZ_FATAL_INTR_REG_CHAR_OFST 0x00000240 878/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 879 880#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_LBN 44 881#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_WIDTH 1 882#define FRF_AB_PCI_BUSERR_INT_CHAR_EN_LBN 43 883#define FRF_AB_PCI_BUSERR_INT_CHAR_EN_WIDTH 1 884#define FRF_CZ_MBU_PERR_INT_CHAR_EN_LBN 43 885#define FRF_CZ_MBU_PERR_INT_CHAR_EN_WIDTH 1 886#define FRF_AZ_SRAM_OOB_INT_CHAR_EN_LBN 42 887#define FRF_AZ_SRAM_OOB_INT_CHAR_EN_WIDTH 1 888#define FRF_AZ_BUFID_OOB_INT_CHAR_EN_LBN 41 889#define FRF_AZ_BUFID_OOB_INT_CHAR_EN_WIDTH 1 890#define FRF_AZ_MEM_PERR_INT_CHAR_EN_LBN 40 891#define FRF_AZ_MEM_PERR_INT_CHAR_EN_WIDTH 1 892#define FRF_AZ_RBUF_OWN_INT_CHAR_EN_LBN 39 893#define FRF_AZ_RBUF_OWN_INT_CHAR_EN_WIDTH 1 894#define FRF_AZ_TBUF_OWN_INT_CHAR_EN_LBN 38 895#define FRF_AZ_TBUF_OWN_INT_CHAR_EN_WIDTH 1 896#define FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_LBN 37 897#define FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_WIDTH 1 898#define FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_LBN 36 899#define FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_WIDTH 1 900#define FRF_AZ_EVQ_OWN_INT_CHAR_EN_LBN 35 901#define FRF_AZ_EVQ_OWN_INT_CHAR_EN_WIDTH 1 902#define FRF_AZ_EVF_OFLO_INT_CHAR_EN_LBN 34 903#define FRF_AZ_EVF_OFLO_INT_CHAR_EN_WIDTH 1 904#define FRF_AZ_ILL_ADR_INT_CHAR_EN_LBN 33 905#define FRF_AZ_ILL_ADR_INT_CHAR_EN_WIDTH 1 906#define FRF_AZ_SRM_PERR_INT_CHAR_EN_LBN 32 907#define FRF_AZ_SRM_PERR_INT_CHAR_EN_WIDTH 1 908#define FRF_CZ_SRAM_PERR_INT_P_CHAR_LBN 12 909#define FRF_CZ_SRAM_PERR_INT_P_CHAR_WIDTH 1 910#define FRF_AB_PCI_BUSERR_INT_CHAR_LBN 11 911#define FRF_AB_PCI_BUSERR_INT_CHAR_WIDTH 1 912#define FRF_CZ_MBU_PERR_INT_CHAR_LBN 11 913#define FRF_CZ_MBU_PERR_INT_CHAR_WIDTH 1 914#define FRF_AZ_SRAM_OOB_INT_CHAR_LBN 10 915#define FRF_AZ_SRAM_OOB_INT_CHAR_WIDTH 1 916#define FRF_AZ_BUFID_DC_OOB_INT_CHAR_LBN 9 917#define FRF_AZ_BUFID_DC_OOB_INT_CHAR_WIDTH 1 918#define FRF_AZ_MEM_PERR_INT_CHAR_LBN 8 919#define FRF_AZ_MEM_PERR_INT_CHAR_WIDTH 1 920#define FRF_AZ_RBUF_OWN_INT_CHAR_LBN 7 921#define FRF_AZ_RBUF_OWN_INT_CHAR_WIDTH 1 922#define FRF_AZ_TBUF_OWN_INT_CHAR_LBN 6 923#define FRF_AZ_TBUF_OWN_INT_CHAR_WIDTH 1 924#define FRF_AZ_RDESCQ_OWN_INT_CHAR_LBN 5 925#define FRF_AZ_RDESCQ_OWN_INT_CHAR_WIDTH 1 926#define FRF_AZ_TDESCQ_OWN_INT_CHAR_LBN 4 927#define FRF_AZ_TDESCQ_OWN_INT_CHAR_WIDTH 1 928#define FRF_AZ_EVQ_OWN_INT_CHAR_LBN 3 929#define FRF_AZ_EVQ_OWN_INT_CHAR_WIDTH 1 930#define FRF_AZ_EVF_OFLO_INT_CHAR_LBN 2 931#define FRF_AZ_EVF_OFLO_INT_CHAR_WIDTH 1 932#define FRF_AZ_ILL_ADR_INT_CHAR_LBN 1 933#define FRF_AZ_ILL_ADR_INT_CHAR_WIDTH 1 934#define FRF_AZ_SRM_PERR_INT_CHAR_LBN 0 935#define FRF_AZ_SRM_PERR_INT_CHAR_WIDTH 1 936 937 938/* 939 * FR_AZ_DP_CTRL_REG(128bit): 940 * Datapath control register 941 */ 942#define FR_AZ_DP_CTRL_REG_OFST 0x00000250 943/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 944 945#define FRF_AZ_FLS_EVQ_ID_LBN 0 946#define FRF_AZ_FLS_EVQ_ID_WIDTH 12 947 948 949/* 950 * FR_AZ_MEM_STAT_REG(128bit): 951 * Memory status register 952 */ 953#define FR_AZ_MEM_STAT_REG_OFST 0x00000260 954/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 955 956#define FRF_AB_MEM_PERR_VEC_LBN 53 957#define FRF_AB_MEM_PERR_VEC_WIDTH 40 958#define FRF_AB_MEM_PERR_VEC_DW0_LBN 53 959#define FRF_AB_MEM_PERR_VEC_DW0_WIDTH 32 960#define FRF_AB_MEM_PERR_VEC_DW1_LBN 85 961#define FRF_AB_MEM_PERR_VEC_DW1_WIDTH 6 962#define FRF_AB_MBIST_CORR_LBN 38 963#define FRF_AB_MBIST_CORR_WIDTH 15 964#define FRF_AB_MBIST_ERR_LBN 0 965#define FRF_AB_MBIST_ERR_WIDTH 40 966#define FRF_AB_MBIST_ERR_DW0_LBN 0 967#define FRF_AB_MBIST_ERR_DW0_WIDTH 32 968#define FRF_AB_MBIST_ERR_DW1_LBN 32 969#define FRF_AB_MBIST_ERR_DW1_WIDTH 6 970#define FRF_CZ_MEM_PERR_VEC_LBN 0 971#define FRF_CZ_MEM_PERR_VEC_WIDTH 35 972#define FRF_CZ_MEM_PERR_VEC_DW0_LBN 0 973#define FRF_CZ_MEM_PERR_VEC_DW0_WIDTH 32 974#define FRF_CZ_MEM_PERR_VEC_DW1_LBN 32 975#define FRF_CZ_MEM_PERR_VEC_DW1_WIDTH 3 976 977 978/* 979 * FR_PORT0_CS_DEBUG_REG(128bit): 980 * Debug register 981 */ 982 983#define FR_AZ_CS_DEBUG_REG_OFST 0x00000270 984/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 985 986#define FRF_AB_GLB_DEBUG2_SEL_LBN 50 987#define FRF_AB_GLB_DEBUG2_SEL_WIDTH 3 988#define FRF_AB_DEBUG_BLK_SEL2_LBN 47 989#define FRF_AB_DEBUG_BLK_SEL2_WIDTH 3 990#define FRF_AB_DEBUG_BLK_SEL1_LBN 44 991#define FRF_AB_DEBUG_BLK_SEL1_WIDTH 3 992#define FRF_AB_DEBUG_BLK_SEL0_LBN 41 993#define FRF_AB_DEBUG_BLK_SEL0_WIDTH 3 994#define FRF_CZ_CS_PORT_NUM_LBN 40 995#define FRF_CZ_CS_PORT_NUM_WIDTH 2 996#define FRF_AB_MISC_DEBUG_ADDR_LBN 36 997#define FRF_AB_MISC_DEBUG_ADDR_WIDTH 5 998#define FRF_CZ_CS_RESERVED_LBN 36 999#define FRF_CZ_CS_RESERVED_WIDTH 4 1000#define FRF_AB_SERDES_DEBUG_ADDR_LBN 31 1001#define FRF_AB_SERDES_DEBUG_ADDR_WIDTH 5 1002#define FRF_CZ_CS_PORT_FPE_DW0_LBN 1 1003#define FRF_CZ_CS_PORT_FPE_DW0_WIDTH 32 1004#define FRF_CZ_CS_PORT_FPE_DW1_LBN 33 1005#define FRF_CZ_CS_PORT_FPE_DW1_WIDTH 3 1006#define FRF_CZ_CS_PORT_FPE_LBN 1 1007#define FRF_CZ_CS_PORT_FPE_WIDTH 35 1008#define FRF_AB_EM_DEBUG_ADDR_LBN 26 1009#define FRF_AB_EM_DEBUG_ADDR_WIDTH 5 1010#define FRF_AB_SR_DEBUG_ADDR_LBN 21 1011#define FRF_AB_SR_DEBUG_ADDR_WIDTH 5 1012#define FRF_AB_EV_DEBUG_ADDR_LBN 16 1013#define FRF_AB_EV_DEBUG_ADDR_WIDTH 5 1014#define FRF_AB_RX_DEBUG_ADDR_LBN 11 1015#define FRF_AB_RX_DEBUG_ADDR_WIDTH 5 1016#define FRF_AB_TX_DEBUG_ADDR_LBN 6 1017#define FRF_AB_TX_DEBUG_ADDR_WIDTH 5 1018#define FRF_AB_CS_BIU_DEBUG_ADDR_LBN 1 1019#define FRF_AB_CS_BIU_DEBUG_ADDR_WIDTH 5 1020#define FRF_AZ_CS_DEBUG_EN_LBN 0 1021#define FRF_AZ_CS_DEBUG_EN_WIDTH 1 1022 1023 1024/* 1025 * FR_AZ_DRIVER_REG(128bit): 1026 * Driver scratch register [0-7] 1027 */ 1028#define FR_AZ_DRIVER_REG_OFST 0x00000280 1029/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1030#define FR_AZ_DRIVER_REG_STEP 16 1031#define FR_AZ_DRIVER_REG_ROWS 8 1032 1033#define FRF_AZ_DRIVER_DW0_LBN 0 1034#define FRF_AZ_DRIVER_DW0_WIDTH 32 1035 1036 1037/* 1038 * FR_AZ_ALTERA_BUILD_REG(128bit): 1039 * Altera build register 1040 */ 1041#define FR_AZ_ALTERA_BUILD_REG_OFST 0x00000300 1042/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1043 1044#define FRF_AZ_ALTERA_BUILD_VER_LBN 0 1045#define FRF_AZ_ALTERA_BUILD_VER_WIDTH 32 1046 1047 1048/* 1049 * FR_AZ_CSR_SPARE_REG(128bit): 1050 * Spare register 1051 */ 1052#define FR_AZ_CSR_SPARE_REG_OFST 0x00000310 1053/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1054 1055#define FRF_AZ_MEM_PERR_EN_TX_DATA_LBN 72 1056#define FRF_AZ_MEM_PERR_EN_TX_DATA_WIDTH 2 1057#define FRF_AZ_MEM_PERR_EN_LBN 64 1058#define FRF_AZ_MEM_PERR_EN_WIDTH 38 1059#define FRF_AZ_MEM_PERR_EN_DW0_LBN 64 1060#define FRF_AZ_MEM_PERR_EN_DW0_WIDTH 32 1061#define FRF_AZ_MEM_PERR_EN_DW1_LBN 96 1062#define FRF_AZ_MEM_PERR_EN_DW1_WIDTH 6 1063#define FRF_AZ_CSR_SPARE_BITS_LBN 0 1064#define FRF_AZ_CSR_SPARE_BITS_WIDTH 32 1065 1066 1067/* 1068 * FR_BZ_DEBUG_DATA_OUT_REG(128bit): 1069 * Live Debug and Debug 2 out ports 1070 */ 1071#define FR_BZ_DEBUG_DATA_OUT_REG_OFST 0x00000350 1072/* falconb0,sienaa0=net_func_bar2 */ 1073 1074#define FRF_BZ_DEBUG2_PORT_LBN 25 1075#define FRF_BZ_DEBUG2_PORT_WIDTH 15 1076#define FRF_BZ_DEBUG1_PORT_LBN 0 1077#define FRF_BZ_DEBUG1_PORT_WIDTH 25 1078 1079 1080/* 1081 * FR_BZ_EVQ_RPTR_REGP0(32bit): 1082 * Event queue read pointer register 1083 */ 1084#define FR_BZ_EVQ_RPTR_REGP0_OFST 0x00000400 1085/* falconb0,sienaa0=net_func_bar2 */ 1086#define FR_BZ_EVQ_RPTR_REGP0_STEP 8192 1087#define FR_BZ_EVQ_RPTR_REGP0_ROWS 1024 1088/* 1089 * FR_AA_EVQ_RPTR_REG_KER(32bit): 1090 * Event queue read pointer register 1091 */ 1092#define FR_AA_EVQ_RPTR_REG_KER_OFST 0x00011b00 1093/* falcona0=net_func_bar2 */ 1094#define FR_AA_EVQ_RPTR_REG_KER_STEP 4 1095#define FR_AA_EVQ_RPTR_REG_KER_ROWS 4 1096/* 1097 * FR_AZ_EVQ_RPTR_REG(32bit): 1098 * Event queue read pointer register 1099 */ 1100#define FR_AZ_EVQ_RPTR_REG_OFST 0x00fa0000 1101/* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1102#define FR_AZ_EVQ_RPTR_REG_STEP 16 1103#define FR_AB_EVQ_RPTR_REG_ROWS 4096 1104#define FR_CZ_EVQ_RPTR_REG_ROWS 1024 1105/* 1106 * FR_BB_EVQ_RPTR_REGP123(32bit): 1107 * Event queue read pointer register 1108 */ 1109#define FR_BB_EVQ_RPTR_REGP123_OFST 0x01000400 1110/* falconb0=net_func_bar2 */ 1111#define FR_BB_EVQ_RPTR_REGP123_STEP 8192 1112#define FR_BB_EVQ_RPTR_REGP123_ROWS 3072 1113 1114#define FRF_AZ_EVQ_RPTR_VLD_LBN 15 1115#define FRF_AZ_EVQ_RPTR_VLD_WIDTH 1 1116#define FRF_AZ_EVQ_RPTR_LBN 0 1117#define FRF_AZ_EVQ_RPTR_WIDTH 15 1118 1119 1120/* 1121 * FR_BZ_TIMER_COMMAND_REGP0(128bit): 1122 * Timer Command Registers 1123 */ 1124#define FR_BZ_TIMER_COMMAND_REGP0_OFST 0x00000420 1125/* falconb0,sienaa0=net_func_bar2 */ 1126#define FR_BZ_TIMER_COMMAND_REGP0_STEP 8192 1127#define FR_BZ_TIMER_COMMAND_REGP0_ROWS 1024 1128/* 1129 * FR_AA_TIMER_COMMAND_REG_KER(128bit): 1130 * Timer Command Registers 1131 */ 1132#define FR_AA_TIMER_COMMAND_REG_KER_OFST 0x00000420 1133/* falcona0=net_func_bar2 */ 1134#define FR_AA_TIMER_COMMAND_REG_KER_STEP 8192 1135#define FR_AA_TIMER_COMMAND_REG_KER_ROWS 4 1136/* 1137 * FR_AB_TIMER_COMMAND_REGP123(128bit): 1138 * Timer Command Registers 1139 */ 1140#define FR_AB_TIMER_COMMAND_REGP123_OFST 0x01000420 1141/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1142#define FR_AB_TIMER_COMMAND_REGP123_STEP 8192 1143#define FR_AB_TIMER_COMMAND_REGP123_ROWS 3072 1144/* 1145 * FR_AA_TIMER_COMMAND_REGP0(128bit): 1146 * Timer Command Registers 1147 */ 1148#define FR_AA_TIMER_COMMAND_REGP0_OFST 0x00008420 1149/* falcona0=char_func_bar0 */ 1150#define FR_AA_TIMER_COMMAND_REGP0_STEP 8192 1151#define FR_AA_TIMER_COMMAND_REGP0_ROWS 1020 1152 1153#define FRF_CZ_TC_TIMER_MODE_LBN 14 1154#define FRF_CZ_TC_TIMER_MODE_WIDTH 2 1155#define FRF_AB_TC_TIMER_MODE_LBN 12 1156#define FRF_AB_TC_TIMER_MODE_WIDTH 2 1157#define FRF_CZ_TC_TIMER_VAL_LBN 0 1158#define FRF_CZ_TC_TIMER_VAL_WIDTH 14 1159#define FRF_AB_TC_TIMER_VAL_LBN 0 1160#define FRF_AB_TC_TIMER_VAL_WIDTH 12 1161 1162 1163/* 1164 * FR_AZ_DRV_EV_REG(128bit): 1165 * Driver generated event register 1166 */ 1167#define FR_AZ_DRV_EV_REG_OFST 0x00000440 1168/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1169 1170#define FRF_AZ_DRV_EV_QID_LBN 64 1171#define FRF_AZ_DRV_EV_QID_WIDTH 12 1172#define FRF_AZ_DRV_EV_DATA_LBN 0 1173#define FRF_AZ_DRV_EV_DATA_WIDTH 64 1174#define FRF_AZ_DRV_EV_DATA_DW0_LBN 0 1175#define FRF_AZ_DRV_EV_DATA_DW0_WIDTH 32 1176#define FRF_AZ_DRV_EV_DATA_DW1_LBN 32 1177#define FRF_AZ_DRV_EV_DATA_DW1_WIDTH 32 1178 1179 1180/* 1181 * FR_AZ_EVQ_CTL_REG(128bit): 1182 * Event queue control register 1183 */ 1184#define FR_AZ_EVQ_CTL_REG_OFST 0x00000450 1185/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1186 1187#define FRF_CZ_RX_EVQ_WAKEUP_MASK_LBN 15 1188#define FRF_CZ_RX_EVQ_WAKEUP_MASK_WIDTH 10 1189#define FRF_BB_RX_EVQ_WAKEUP_MASK_LBN 15 1190#define FRF_BB_RX_EVQ_WAKEUP_MASK_WIDTH 6 1191#define FRF_AZ_EVQ_OWNERR_CTL_LBN 14 1192#define FRF_AZ_EVQ_OWNERR_CTL_WIDTH 1 1193#define FRF_AZ_EVQ_FIFO_AF_TH_LBN 7 1194#define FRF_AZ_EVQ_FIFO_AF_TH_WIDTH 7 1195#define FRF_AZ_EVQ_FIFO_NOTAF_TH_LBN 0 1196#define FRF_AZ_EVQ_FIFO_NOTAF_TH_WIDTH 7 1197 1198 1199/* 1200 * FR_AZ_EVQ_CNT1_REG(128bit): 1201 * Event counter 1 register 1202 */ 1203#define FR_AZ_EVQ_CNT1_REG_OFST 0x00000460 1204/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1205 1206#define FRF_AZ_EVQ_CNT_PRE_FIFO_LBN 120 1207#define FRF_AZ_EVQ_CNT_PRE_FIFO_WIDTH 7 1208#define FRF_AZ_EVQ_CNT_TOBIU_LBN 100 1209#define FRF_AZ_EVQ_CNT_TOBIU_WIDTH 20 1210#define FRF_AZ_EVQ_TX_REQ_CNT_LBN 80 1211#define FRF_AZ_EVQ_TX_REQ_CNT_WIDTH 20 1212#define FRF_AZ_EVQ_RX_REQ_CNT_LBN 60 1213#define FRF_AZ_EVQ_RX_REQ_CNT_WIDTH 20 1214#define FRF_AZ_EVQ_EM_REQ_CNT_LBN 40 1215#define FRF_AZ_EVQ_EM_REQ_CNT_WIDTH 20 1216#define FRF_AZ_EVQ_CSR_REQ_CNT_LBN 20 1217#define FRF_AZ_EVQ_CSR_REQ_CNT_WIDTH 20 1218#define FRF_AZ_EVQ_ERR_REQ_CNT_LBN 0 1219#define FRF_AZ_EVQ_ERR_REQ_CNT_WIDTH 20 1220 1221 1222/* 1223 * FR_AZ_EVQ_CNT2_REG(128bit): 1224 * Event counter 2 register 1225 */ 1226#define FR_AZ_EVQ_CNT2_REG_OFST 0x00000470 1227/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1228 1229#define FRF_AZ_EVQ_UPD_REQ_CNT_LBN 104 1230#define FRF_AZ_EVQ_UPD_REQ_CNT_WIDTH 20 1231#define FRF_AZ_EVQ_CLR_REQ_CNT_LBN 84 1232#define FRF_AZ_EVQ_CLR_REQ_CNT_WIDTH 20 1233#define FRF_AZ_EVQ_RDY_CNT_LBN 80 1234#define FRF_AZ_EVQ_RDY_CNT_WIDTH 4 1235#define FRF_AZ_EVQ_WU_REQ_CNT_LBN 60 1236#define FRF_AZ_EVQ_WU_REQ_CNT_WIDTH 20 1237#define FRF_AZ_EVQ_WET_REQ_CNT_LBN 40 1238#define FRF_AZ_EVQ_WET_REQ_CNT_WIDTH 20 1239#define FRF_AZ_EVQ_INIT_REQ_CNT_LBN 20 1240#define FRF_AZ_EVQ_INIT_REQ_CNT_WIDTH 20 1241#define FRF_AZ_EVQ_TM_REQ_CNT_LBN 0 1242#define FRF_AZ_EVQ_TM_REQ_CNT_WIDTH 20 1243 1244 1245/* 1246 * FR_CZ_USR_EV_REG(32bit): 1247 * Event mailbox register 1248 */ 1249#define FR_CZ_USR_EV_REG_OFST 0x00000540 1250/* sienaa0=net_func_bar2 */ 1251#define FR_CZ_USR_EV_REG_STEP 8192 1252#define FR_CZ_USR_EV_REG_ROWS 1024 1253 1254#define FRF_CZ_USR_EV_DATA_LBN 0 1255#define FRF_CZ_USR_EV_DATA_WIDTH 32 1256 1257 1258/* 1259 * FR_AZ_BUF_TBL_CFG_REG(128bit): 1260 * Buffer table configuration register 1261 */ 1262#define FR_AZ_BUF_TBL_CFG_REG_OFST 0x00000600 1263/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1264 1265#define FRF_AZ_BUF_TBL_MODE_LBN 3 1266#define FRF_AZ_BUF_TBL_MODE_WIDTH 1 1267 1268 1269/* 1270 * FR_AZ_SRM_RX_DC_CFG_REG(128bit): 1271 * SRAM receive descriptor cache configuration register 1272 */ 1273#define FR_AZ_SRM_RX_DC_CFG_REG_OFST 0x00000610 1274/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1275 1276#define FRF_AZ_SRM_CLK_TMP_EN_LBN 21 1277#define FRF_AZ_SRM_CLK_TMP_EN_WIDTH 1 1278#define FRF_AZ_SRM_RX_DC_BASE_ADR_LBN 0 1279#define FRF_AZ_SRM_RX_DC_BASE_ADR_WIDTH 21 1280 1281 1282/* 1283 * FR_AZ_SRM_TX_DC_CFG_REG(128bit): 1284 * SRAM transmit descriptor cache configuration register 1285 */ 1286#define FR_AZ_SRM_TX_DC_CFG_REG_OFST 0x00000620 1287/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1288 1289#define FRF_AZ_SRM_TX_DC_BASE_ADR_LBN 0 1290#define FRF_AZ_SRM_TX_DC_BASE_ADR_WIDTH 21 1291 1292 1293/* 1294 * FR_AZ_SRM_CFG_REG(128bit): 1295 * SRAM configuration register 1296 */ 1297#define FR_AZ_SRM_CFG_REG_SF_OFST 0x00000380 1298/* falcona0,falconb0=eeprom_flash */ 1299/* 1300 * FR_AZ_SRM_CFG_REG(128bit): 1301 * SRAM configuration register 1302 */ 1303#define FR_AZ_SRM_CFG_REG_OFST 0x00000630 1304/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1305 1306#define FRF_AZ_SRM_OOB_ADR_INTEN_LBN 5 1307#define FRF_AZ_SRM_OOB_ADR_INTEN_WIDTH 1 1308#define FRF_AZ_SRM_OOB_BUF_INTEN_LBN 4 1309#define FRF_AZ_SRM_OOB_BUF_INTEN_WIDTH 1 1310#define FRF_AZ_SRM_INIT_EN_LBN 3 1311#define FRF_AZ_SRM_INIT_EN_WIDTH 1 1312#define FRF_AZ_SRM_NUM_BANK_LBN 2 1313#define FRF_AZ_SRM_NUM_BANK_WIDTH 1 1314#define FRF_AZ_SRM_BANK_SIZE_LBN 0 1315#define FRF_AZ_SRM_BANK_SIZE_WIDTH 2 1316 1317 1318/* 1319 * FR_AZ_BUF_TBL_UPD_REG(128bit): 1320 * Buffer table update register 1321 */ 1322#define FR_AZ_BUF_TBL_UPD_REG_OFST 0x00000650 1323/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1324 1325#define FRF_AZ_BUF_UPD_CMD_LBN 63 1326#define FRF_AZ_BUF_UPD_CMD_WIDTH 1 1327#define FRF_AZ_BUF_CLR_CMD_LBN 62 1328#define FRF_AZ_BUF_CLR_CMD_WIDTH 1 1329#define FRF_AZ_BUF_CLR_END_ID_LBN 32 1330#define FRF_AZ_BUF_CLR_END_ID_WIDTH 20 1331#define FRF_AZ_BUF_CLR_START_ID_LBN 0 1332#define FRF_AZ_BUF_CLR_START_ID_WIDTH 20 1333 1334 1335/* 1336 * FR_AZ_SRM_UPD_EVQ_REG(128bit): 1337 * Buffer table update register 1338 */ 1339#define FR_AZ_SRM_UPD_EVQ_REG_OFST 0x00000660 1340/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1341 1342#define FRF_AZ_SRM_UPD_EVQ_ID_LBN 0 1343#define FRF_AZ_SRM_UPD_EVQ_ID_WIDTH 12 1344 1345 1346/* 1347 * FR_AZ_SRAM_PARITY_REG(128bit): 1348 * SRAM parity register. 1349 */ 1350#define FR_AZ_SRAM_PARITY_REG_OFST 0x00000670 1351/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1352 1353#define FRF_CZ_BYPASS_ECC_LBN 3 1354#define FRF_CZ_BYPASS_ECC_WIDTH 1 1355#define FRF_CZ_SEC_INT_LBN 2 1356#define FRF_CZ_SEC_INT_WIDTH 1 1357#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_LBN 1 1358#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_WIDTH 1 1359#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_LBN 0 1360#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_WIDTH 1 1361#define FRF_AB_FORCE_SRAM_PERR_LBN 0 1362#define FRF_AB_FORCE_SRAM_PERR_WIDTH 1 1363 1364 1365/* 1366 * FR_AZ_RX_CFG_REG(128bit): 1367 * Receive configuration register 1368 */ 1369#define FR_AZ_RX_CFG_REG_OFST 0x00000800 1370/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1371 1372#define FRF_CZ_RX_HDR_SPLIT_EN_LBN 71 1373#define FRF_CZ_RX_HDR_SPLIT_EN_WIDTH 1 1374#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_LBN 62 1375#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_WIDTH 9 1376#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_LBN 53 1377#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_WIDTH 9 1378#define FRF_CZ_RX_PRE_RFF_IPG_LBN 49 1379#define FRF_CZ_RX_PRE_RFF_IPG_WIDTH 4 1380#define FRF_BZ_RX_TCP_SUP_LBN 48 1381#define FRF_BZ_RX_TCP_SUP_WIDTH 1 1382#define FRF_BZ_RX_INGR_EN_LBN 47 1383#define FRF_BZ_RX_INGR_EN_WIDTH 1 1384#define FRF_BZ_RX_IP_HASH_LBN 46 1385#define FRF_BZ_RX_IP_HASH_WIDTH 1 1386#define FRF_BZ_RX_HASH_ALG_LBN 45 1387#define FRF_BZ_RX_HASH_ALG_WIDTH 1 1388#define FRF_BZ_RX_HASH_INSRT_HDR_LBN 44 1389#define FRF_BZ_RX_HASH_INSRT_HDR_WIDTH 1 1390#define FRF_BZ_RX_DESC_PUSH_EN_LBN 43 1391#define FRF_BZ_RX_DESC_PUSH_EN_WIDTH 1 1392#define FRF_BZ_RX_RDW_PATCH_EN_LBN 42 1393#define FRF_BZ_RX_RDW_PATCH_EN_WIDTH 1 1394#define FRF_BB_RX_PCI_BURST_SIZE_LBN 39 1395#define FRF_BB_RX_PCI_BURST_SIZE_WIDTH 3 1396#define FRF_BZ_RX_OWNERR_CTL_LBN 38 1397#define FRF_BZ_RX_OWNERR_CTL_WIDTH 1 1398#define FRF_BZ_RX_XON_TX_TH_LBN 33 1399#define FRF_BZ_RX_XON_TX_TH_WIDTH 5 1400#define FRF_AA_RX_DESC_PUSH_EN_LBN 35 1401#define FRF_AA_RX_DESC_PUSH_EN_WIDTH 1 1402#define FRF_AA_RX_RDW_PATCH_EN_LBN 34 1403#define FRF_AA_RX_RDW_PATCH_EN_WIDTH 1 1404#define FRF_AA_RX_PCI_BURST_SIZE_LBN 31 1405#define FRF_AA_RX_PCI_BURST_SIZE_WIDTH 3 1406#define FRF_BZ_RX_XOFF_TX_TH_LBN 28 1407#define FRF_BZ_RX_XOFF_TX_TH_WIDTH 5 1408#define FRF_AA_RX_OWNERR_CTL_LBN 30 1409#define FRF_AA_RX_OWNERR_CTL_WIDTH 1 1410#define FRF_AA_RX_XON_TX_TH_LBN 25 1411#define FRF_AA_RX_XON_TX_TH_WIDTH 5 1412#define FRF_BZ_RX_USR_BUF_SIZE_LBN 19 1413#define FRF_BZ_RX_USR_BUF_SIZE_WIDTH 9 1414#define FRF_AA_RX_XOFF_TX_TH_LBN 20 1415#define FRF_AA_RX_XOFF_TX_TH_WIDTH 5 1416#define FRF_AA_RX_USR_BUF_SIZE_LBN 11 1417#define FRF_AA_RX_USR_BUF_SIZE_WIDTH 9 1418#define FRF_BZ_RX_XON_MAC_TH_LBN 10 1419#define FRF_BZ_RX_XON_MAC_TH_WIDTH 9 1420#define FRF_AA_RX_XON_MAC_TH_LBN 6 1421#define FRF_AA_RX_XON_MAC_TH_WIDTH 5 1422#define FRF_BZ_RX_XOFF_MAC_TH_LBN 1 1423#define FRF_BZ_RX_XOFF_MAC_TH_WIDTH 9 1424#define FRF_AA_RX_XOFF_MAC_TH_LBN 1 1425#define FRF_AA_RX_XOFF_MAC_TH_WIDTH 5 1426#define FRF_AZ_RX_XOFF_MAC_EN_LBN 0 1427#define FRF_AZ_RX_XOFF_MAC_EN_WIDTH 1 1428 1429 1430/* 1431 * FR_AZ_RX_FILTER_CTL_REG(128bit): 1432 * Receive filter control registers 1433 */ 1434#define FR_AZ_RX_FILTER_CTL_REG_OFST 0x00000810 1435/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1436 1437#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_LBN 94 1438#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_WIDTH 8 1439#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_LBN 86 1440#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_WIDTH 8 1441#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_LBN 85 1442#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_WIDTH 1 1443#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_LBN 69 1444#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_WIDTH 16 1445#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_LBN 57 1446#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_WIDTH 12 1447#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_LBN 56 1448#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_WIDTH 1 1449#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_LBN 55 1450#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_WIDTH 1 1451#define FRF_CZ_UNICAST_NOMATCH_Q_ID_LBN 43 1452#define FRF_CZ_UNICAST_NOMATCH_Q_ID_WIDTH 12 1453#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_LBN 42 1454#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_WIDTH 1 1455#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_LBN 41 1456#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_WIDTH 1 1457#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_LBN 40 1458#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_WIDTH 1 1459#define FRF_AZ_UDP_FULL_SRCH_LIMIT_LBN 32 1460#define FRF_AZ_UDP_FULL_SRCH_LIMIT_WIDTH 8 1461#define FRF_AZ_NUM_KER_LBN 24 1462#define FRF_AZ_NUM_KER_WIDTH 2 1463#define FRF_AZ_UDP_WILD_SRCH_LIMIT_LBN 16 1464#define FRF_AZ_UDP_WILD_SRCH_LIMIT_WIDTH 8 1465#define FRF_AZ_TCP_WILD_SRCH_LIMIT_LBN 8 1466#define FRF_AZ_TCP_WILD_SRCH_LIMIT_WIDTH 8 1467#define FRF_AZ_TCP_FULL_SRCH_LIMIT_LBN 0 1468#define FRF_AZ_TCP_FULL_SRCH_LIMIT_WIDTH 8 1469 1470 1471/* 1472 * FR_AZ_RX_FLUSH_DESCQ_REG(128bit): 1473 * Receive flush descriptor queue register 1474 */ 1475#define FR_AZ_RX_FLUSH_DESCQ_REG_OFST 0x00000820 1476/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1477 1478#define FRF_AZ_RX_FLUSH_DESCQ_CMD_LBN 24 1479#define FRF_AZ_RX_FLUSH_DESCQ_CMD_WIDTH 1 1480#define FRF_AZ_RX_FLUSH_DESCQ_LBN 0 1481#define FRF_AZ_RX_FLUSH_DESCQ_WIDTH 12 1482 1483 1484/* 1485 * FR_BZ_RX_DESC_UPD_REGP0(128bit): 1486 * Receive descriptor update register. 1487 */ 1488#define FR_BZ_RX_DESC_UPD_REGP0_OFST 0x00000830 1489/* falconb0,sienaa0=net_func_bar2 */ 1490#define FR_BZ_RX_DESC_UPD_REGP0_STEP 8192 1491#define FR_BZ_RX_DESC_UPD_REGP0_ROWS 1024 1492/* 1493 * FR_AA_RX_DESC_UPD_REG_KER(128bit): 1494 * Receive descriptor update register. 1495 */ 1496#define FR_AA_RX_DESC_UPD_REG_KER_OFST 0x00000830 1497/* falcona0=net_func_bar2 */ 1498#define FR_AA_RX_DESC_UPD_REG_KER_STEP 8192 1499#define FR_AA_RX_DESC_UPD_REG_KER_ROWS 4 1500/* 1501 * FR_AB_RX_DESC_UPD_REGP123(128bit): 1502 * Receive descriptor update register. 1503 */ 1504#define FR_AB_RX_DESC_UPD_REGP123_OFST 0x01000830 1505/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1506#define FR_AB_RX_DESC_UPD_REGP123_STEP 8192 1507#define FR_AB_RX_DESC_UPD_REGP123_ROWS 3072 1508/* 1509 * FR_AA_RX_DESC_UPD_REGP0(128bit): 1510 * Receive descriptor update register. 1511 */ 1512#define FR_AA_RX_DESC_UPD_REGP0_OFST 0x00008830 1513/* falcona0=char_func_bar0 */ 1514#define FR_AA_RX_DESC_UPD_REGP0_STEP 8192 1515#define FR_AA_RX_DESC_UPD_REGP0_ROWS 1020 1516 1517#define FRF_AZ_RX_DESC_WPTR_LBN 96 1518#define FRF_AZ_RX_DESC_WPTR_WIDTH 12 1519#define FRF_AZ_RX_DESC_PUSH_CMD_LBN 95 1520#define FRF_AZ_RX_DESC_PUSH_CMD_WIDTH 1 1521#define FRF_AZ_RX_DESC_LBN 0 1522#define FRF_AZ_RX_DESC_WIDTH 64 1523#define FRF_AZ_RX_DESC_DW0_LBN 0 1524#define FRF_AZ_RX_DESC_DW0_WIDTH 32 1525#define FRF_AZ_RX_DESC_DW1_LBN 32 1526#define FRF_AZ_RX_DESC_DW1_WIDTH 32 1527 1528 1529/* 1530 * FR_AZ_RX_DC_CFG_REG(128bit): 1531 * Receive descriptor cache configuration register 1532 */ 1533#define FR_AZ_RX_DC_CFG_REG_OFST 0x00000840 1534/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1535 1536#define FRF_AZ_RX_MAX_PF_LBN 2 1537#define FRF_AZ_RX_MAX_PF_WIDTH 2 1538#define FRF_AZ_RX_DC_SIZE_LBN 0 1539#define FRF_AZ_RX_DC_SIZE_WIDTH 2 1540#define FFE_AZ_RX_DC_SIZE_64 3 1541#define FFE_AZ_RX_DC_SIZE_32 2 1542#define FFE_AZ_RX_DC_SIZE_16 1 1543#define FFE_AZ_RX_DC_SIZE_8 0 1544 1545 1546/* 1547 * FR_AZ_RX_DC_PF_WM_REG(128bit): 1548 * Receive descriptor cache pre-fetch watermark register 1549 */ 1550#define FR_AZ_RX_DC_PF_WM_REG_OFST 0x00000850 1551/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1552 1553#define FRF_AZ_RX_DC_PF_HWM_LBN 6 1554#define FRF_AZ_RX_DC_PF_HWM_WIDTH 6 1555#define FRF_AZ_RX_DC_PF_LWM_LBN 0 1556#define FRF_AZ_RX_DC_PF_LWM_WIDTH 6 1557 1558 1559/* 1560 * FR_BZ_RX_RSS_TKEY_REG(128bit): 1561 * RSS Toeplitz hash key 1562 */ 1563#define FR_BZ_RX_RSS_TKEY_REG_OFST 0x00000860 1564/* falconb0,sienaa0=net_func_bar2 */ 1565 1566#define FRF_BZ_RX_RSS_TKEY_LBN 96 1567#define FRF_BZ_RX_RSS_TKEY_WIDTH 32 1568#define FRF_BZ_RX_RSS_TKEY_DW3_LBN 96 1569#define FRF_BZ_RX_RSS_TKEY_DW3_WIDTH 32 1570#define FRF_BZ_RX_RSS_TKEY_DW2_LBN 64 1571#define FRF_BZ_RX_RSS_TKEY_DW2_WIDTH 32 1572#define FRF_BZ_RX_RSS_TKEY_DW1_LBN 32 1573#define FRF_BZ_RX_RSS_TKEY_DW1_WIDTH 32 1574#define FRF_BZ_RX_RSS_TKEY_DW0_LBN 0 1575#define FRF_BZ_RX_RSS_TKEY_DW0_WIDTH 32 1576 1577 1578/* 1579 * FR_AZ_RX_NODESC_DROP_REG(128bit): 1580 * Receive dropped packet counter register 1581 */ 1582#define FR_AZ_RX_NODESC_DROP_REG_OFST 0x00000880 1583/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1584 1585#define FRF_AZ_RX_NODESC_DROP_CNT_LBN 0 1586#define FRF_AZ_RX_NODESC_DROP_CNT_WIDTH 16 1587 1588 1589/* 1590 * FR_AZ_RX_SELF_RST_REG(128bit): 1591 * Receive self reset register 1592 */ 1593#define FR_AZ_RX_SELF_RST_REG_OFST 0x00000890 1594/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1595 1596#define FRF_AZ_RX_ISCSI_DIS_LBN 17 1597#define FRF_AZ_RX_ISCSI_DIS_WIDTH 1 1598#define FRF_AB_RX_SW_RST_REG_LBN 16 1599#define FRF_AB_RX_SW_RST_REG_WIDTH 1 1600#define FRF_AB_RX_SELF_RST_EN_LBN 8 1601#define FRF_AB_RX_SELF_RST_EN_WIDTH 1 1602#define FRF_AZ_RX_MAX_PF_LAT_LBN 4 1603#define FRF_AZ_RX_MAX_PF_LAT_WIDTH 4 1604#define FRF_AZ_RX_MAX_LU_LAT_LBN 0 1605#define FRF_AZ_RX_MAX_LU_LAT_WIDTH 4 1606 1607 1608/* 1609 * FR_AZ_RX_DEBUG_REG(128bit): 1610 * undocumented register 1611 */ 1612#define FR_AZ_RX_DEBUG_REG_OFST 0x000008a0 1613/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1614 1615#define FRF_AZ_RX_DEBUG_LBN 0 1616#define FRF_AZ_RX_DEBUG_WIDTH 64 1617#define FRF_AZ_RX_DEBUG_DW0_LBN 0 1618#define FRF_AZ_RX_DEBUG_DW0_WIDTH 32 1619#define FRF_AZ_RX_DEBUG_DW1_LBN 32 1620#define FRF_AZ_RX_DEBUG_DW1_WIDTH 32 1621 1622 1623/* 1624 * FR_AZ_RX_PUSH_DROP_REG(128bit): 1625 * Receive descriptor push dropped counter register 1626 */ 1627#define FR_AZ_RX_PUSH_DROP_REG_OFST 0x000008b0 1628/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1629 1630#define FRF_AZ_RX_PUSH_DROP_CNT_LBN 0 1631#define FRF_AZ_RX_PUSH_DROP_CNT_WIDTH 32 1632 1633 1634/* 1635 * FR_CZ_RX_RSS_IPV6_REG1(128bit): 1636 * IPv6 RSS Toeplitz hash key low bytes 1637 */ 1638#define FR_CZ_RX_RSS_IPV6_REG1_OFST 0x000008d0 1639/* sienaa0=net_func_bar2 */ 1640 1641#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN 0 1642#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH 128 1643#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_LBN 0 1644#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_WIDTH 32 1645#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_LBN 32 1646#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_WIDTH 32 1647#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_LBN 64 1648#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_WIDTH 32 1649#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_LBN 96 1650#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_WIDTH 32 1651 1652 1653/* 1654 * FR_CZ_RX_RSS_IPV6_REG2(128bit): 1655 * IPv6 RSS Toeplitz hash key middle bytes 1656 */ 1657#define FR_CZ_RX_RSS_IPV6_REG2_OFST 0x000008e0 1658/* sienaa0=net_func_bar2 */ 1659 1660#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN 0 1661#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH 128 1662#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_LBN 0 1663#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_WIDTH 32 1664#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_LBN 32 1665#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_WIDTH 32 1666#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_LBN 64 1667#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_WIDTH 32 1668#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_LBN 96 1669#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_WIDTH 32 1670 1671 1672/* 1673 * FR_CZ_RX_RSS_IPV6_REG3(128bit): 1674 * IPv6 RSS Toeplitz hash key upper bytes and IPv6 RSS settings 1675 */ 1676#define FR_CZ_RX_RSS_IPV6_REG3_OFST 0x000008f0 1677/* sienaa0=net_func_bar2 */ 1678 1679#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_LBN 66 1680#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_WIDTH 1 1681#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_LBN 65 1682#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_WIDTH 1 1683#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_LBN 64 1684#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_WIDTH 1 1685#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN 0 1686#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH 64 1687#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_LBN 0 1688#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_WIDTH 32 1689#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_LBN 32 1690#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_WIDTH 32 1691 1692 1693/* 1694 * FR_AZ_TX_FLUSH_DESCQ_REG(128bit): 1695 * Transmit flush descriptor queue register 1696 */ 1697#define FR_AZ_TX_FLUSH_DESCQ_REG_OFST 0x00000a00 1698/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1699 1700#define FRF_AZ_TX_FLUSH_DESCQ_CMD_LBN 12 1701#define FRF_AZ_TX_FLUSH_DESCQ_CMD_WIDTH 1 1702#define FRF_AZ_TX_FLUSH_DESCQ_LBN 0 1703#define FRF_AZ_TX_FLUSH_DESCQ_WIDTH 12 1704 1705 1706/* 1707 * FR_BZ_TX_DESC_UPD_REGP0(128bit): 1708 * Transmit descriptor update register. 1709 */ 1710#define FR_BZ_TX_DESC_UPD_REGP0_OFST 0x00000a10 1711/* falconb0,sienaa0=net_func_bar2 */ 1712#define FR_BZ_TX_DESC_UPD_REGP0_STEP 8192 1713#define FR_BZ_TX_DESC_UPD_REGP0_ROWS 1024 1714/* 1715 * FR_AA_TX_DESC_UPD_REG_KER(128bit): 1716 * Transmit descriptor update register. 1717 */ 1718#define FR_AA_TX_DESC_UPD_REG_KER_OFST 0x00000a10 1719/* falcona0=net_func_bar2 */ 1720#define FR_AA_TX_DESC_UPD_REG_KER_STEP 8192 1721#define FR_AA_TX_DESC_UPD_REG_KER_ROWS 8 1722/* 1723 * FR_AB_TX_DESC_UPD_REGP123(128bit): 1724 * Transmit descriptor update register. 1725 */ 1726#define FR_AB_TX_DESC_UPD_REGP123_OFST 0x01000a10 1727/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1728#define FR_AB_TX_DESC_UPD_REGP123_STEP 8192 1729#define FR_AB_TX_DESC_UPD_REGP123_ROWS 3072 1730/* 1731 * FR_AA_TX_DESC_UPD_REGP0(128bit): 1732 * Transmit descriptor update register. 1733 */ 1734#define FR_AA_TX_DESC_UPD_REGP0_OFST 0x00008a10 1735/* falcona0=char_func_bar0 */ 1736#define FR_AA_TX_DESC_UPD_REGP0_STEP 8192 1737#define FR_AA_TX_DESC_UPD_REGP0_ROWS 1020 1738 1739#define FRF_AZ_TX_DESC_WPTR_LBN 96 1740#define FRF_AZ_TX_DESC_WPTR_WIDTH 12 1741#define FRF_AZ_TX_DESC_PUSH_CMD_LBN 95 1742#define FRF_AZ_TX_DESC_PUSH_CMD_WIDTH 1 1743#define FRF_AZ_TX_DESC_LBN 0 1744#define FRF_AZ_TX_DESC_WIDTH 95 1745#define FRF_AZ_TX_DESC_DW0_LBN 0 1746#define FRF_AZ_TX_DESC_DW0_WIDTH 32 1747#define FRF_AZ_TX_DESC_DW1_LBN 32 1748#define FRF_AZ_TX_DESC_DW1_WIDTH 32 1749#define FRF_AZ_TX_DESC_DW2_LBN 64 1750#define FRF_AZ_TX_DESC_DW2_WIDTH 31 1751 1752 1753/* 1754 * FR_AZ_TX_DC_CFG_REG(128bit): 1755 * Transmit descriptor cache configuration register 1756 */ 1757#define FR_AZ_TX_DC_CFG_REG_OFST 0x00000a20 1758/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1759 1760#define FRF_AZ_TX_DC_SIZE_LBN 0 1761#define FRF_AZ_TX_DC_SIZE_WIDTH 2 1762#define FFE_AZ_TX_DC_SIZE_32 2 1763#define FFE_AZ_TX_DC_SIZE_16 1 1764#define FFE_AZ_TX_DC_SIZE_8 0 1765 1766 1767/* 1768 * FR_AA_TX_CHKSM_CFG_REG(128bit): 1769 * Transmit checksum configuration register 1770 */ 1771#define FR_AA_TX_CHKSM_CFG_REG_OFST 0x00000a30 1772/* falcona0=net_func_bar2,falcona0=char_func_bar0 */ 1773 1774#define FRF_AA_TX_Q_CHKSM_DIS_96_127_LBN 96 1775#define FRF_AA_TX_Q_CHKSM_DIS_96_127_WIDTH 32 1776#define FRF_AA_TX_Q_CHKSM_DIS_64_95_LBN 64 1777#define FRF_AA_TX_Q_CHKSM_DIS_64_95_WIDTH 32 1778#define FRF_AA_TX_Q_CHKSM_DIS_32_63_LBN 32 1779#define FRF_AA_TX_Q_CHKSM_DIS_32_63_WIDTH 32 1780#define FRF_AA_TX_Q_CHKSM_DIS_0_31_LBN 0 1781#define FRF_AA_TX_Q_CHKSM_DIS_0_31_WIDTH 32 1782 1783 1784/* 1785 * FR_AZ_TX_CFG_REG(128bit): 1786 * Transmit configuration register 1787 */ 1788#define FR_AZ_TX_CFG_REG_OFST 0x00000a50 1789/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1790 1791#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_LBN 114 1792#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_WIDTH 8 1793#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_LBN 113 1794#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_WIDTH 1 1795#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_LBN 105 1796#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1797#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_LBN 97 1798#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1799#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_LBN 89 1800#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1801#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_LBN 81 1802#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1803#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_LBN 73 1804#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1805#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_LBN 65 1806#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1807#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_LBN 64 1808#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_WIDTH 1 1809#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_LBN 48 1810#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_WIDTH 16 1811#define FRF_CZ_TX_FILTER_EN_BIT_LBN 47 1812#define FRF_CZ_TX_FILTER_EN_BIT_WIDTH 1 1813#define FRF_AZ_TX_IP_ID_P0_OFS_LBN 16 1814#define FRF_AZ_TX_IP_ID_P0_OFS_WIDTH 15 1815#define FRF_AZ_TX_NO_EOP_DISC_EN_LBN 5 1816#define FRF_AZ_TX_NO_EOP_DISC_EN_WIDTH 1 1817#define FRF_AZ_TX_P1_PRI_EN_LBN 4 1818#define FRF_AZ_TX_P1_PRI_EN_WIDTH 1 1819#define FRF_AZ_TX_OWNERR_CTL_LBN 2 1820#define FRF_AZ_TX_OWNERR_CTL_WIDTH 1 1821#define FRF_AA_TX_NON_IP_DROP_DIS_LBN 1 1822#define FRF_AA_TX_NON_IP_DROP_DIS_WIDTH 1 1823#define FRF_AZ_TX_IP_ID_REP_EN_LBN 0 1824#define FRF_AZ_TX_IP_ID_REP_EN_WIDTH 1 1825 1826 1827/* 1828 * FR_AZ_TX_PUSH_DROP_REG(128bit): 1829 * Transmit push dropped register 1830 */ 1831#define FR_AZ_TX_PUSH_DROP_REG_OFST 0x00000a60 1832/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1833 1834#define FRF_AZ_TX_PUSH_DROP_CNT_LBN 0 1835#define FRF_AZ_TX_PUSH_DROP_CNT_WIDTH 32 1836 1837 1838/* 1839 * FR_AZ_TX_RESERVED_REG(128bit): 1840 * Transmit configuration register 1841 */ 1842#define FR_AZ_TX_RESERVED_REG_OFST 0x00000a80 1843/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1844 1845#define FRF_AZ_TX_EVT_CNT_LBN 121 1846#define FRF_AZ_TX_EVT_CNT_WIDTH 7 1847#define FRF_AZ_TX_PREF_AGE_CNT_LBN 119 1848#define FRF_AZ_TX_PREF_AGE_CNT_WIDTH 2 1849#define FRF_AZ_TX_RD_COMP_TMR_LBN 96 1850#define FRF_AZ_TX_RD_COMP_TMR_WIDTH 23 1851#define FRF_AZ_TX_PUSH_EN_LBN 89 1852#define FRF_AZ_TX_PUSH_EN_WIDTH 1 1853#define FRF_AZ_TX_PUSH_CHK_DIS_LBN 88 1854#define FRF_AZ_TX_PUSH_CHK_DIS_WIDTH 1 1855#define FRF_AZ_TX_D_FF_FULL_P0_LBN 85 1856#define FRF_AZ_TX_D_FF_FULL_P0_WIDTH 1 1857#define FRF_AZ_TX_DMAR_ST_P0_LBN 81 1858#define FRF_AZ_TX_DMAR_ST_P0_WIDTH 1 1859#define FRF_AZ_TX_DMAQ_ST_LBN 78 1860#define FRF_AZ_TX_DMAQ_ST_WIDTH 1 1861#define FRF_AZ_TX_RX_SPACER_LBN 64 1862#define FRF_AZ_TX_RX_SPACER_WIDTH 8 1863#define FRF_AZ_TX_DROP_ABORT_EN_LBN 60 1864#define FRF_AZ_TX_DROP_ABORT_EN_WIDTH 1 1865#define FRF_AZ_TX_SOFT_EVT_EN_LBN 59 1866#define FRF_AZ_TX_SOFT_EVT_EN_WIDTH 1 1867#define FRF_AZ_TX_PS_EVT_DIS_LBN 58 1868#define FRF_AZ_TX_PS_EVT_DIS_WIDTH 1 1869#define FRF_AZ_TX_RX_SPACER_EN_LBN 57 1870#define FRF_AZ_TX_RX_SPACER_EN_WIDTH 1 1871#define FRF_AZ_TX_XP_TIMER_LBN 52 1872#define FRF_AZ_TX_XP_TIMER_WIDTH 5 1873#define FRF_AZ_TX_PREF_SPACER_LBN 44 1874#define FRF_AZ_TX_PREF_SPACER_WIDTH 8 1875#define FRF_AZ_TX_PREF_WD_TMR_LBN 22 1876#define FRF_AZ_TX_PREF_WD_TMR_WIDTH 22 1877#define FRF_AZ_TX_ONLY1TAG_LBN 21 1878#define FRF_AZ_TX_ONLY1TAG_WIDTH 1 1879#define FRF_AZ_TX_PREF_THRESHOLD_LBN 19 1880#define FRF_AZ_TX_PREF_THRESHOLD_WIDTH 2 1881#define FRF_AZ_TX_ONE_PKT_PER_Q_LBN 18 1882#define FRF_AZ_TX_ONE_PKT_PER_Q_WIDTH 1 1883#define FRF_AZ_TX_DIS_NON_IP_EV_LBN 17 1884#define FRF_AZ_TX_DIS_NON_IP_EV_WIDTH 1 1885#define FRF_AA_TX_DMA_FF_THR_LBN 16 1886#define FRF_AA_TX_DMA_FF_THR_WIDTH 1 1887#define FRF_AZ_TX_DMA_SPACER_LBN 8 1888#define FRF_AZ_TX_DMA_SPACER_WIDTH 8 1889#define FRF_AA_TX_TCP_DIS_LBN 7 1890#define FRF_AA_TX_TCP_DIS_WIDTH 1 1891#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_LBN 7 1892#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_WIDTH 1 1893#define FRF_AA_TX_IP_DIS_LBN 6 1894#define FRF_AA_TX_IP_DIS_WIDTH 1 1895#define FRF_AZ_TX_MAX_CPL_LBN 2 1896#define FRF_AZ_TX_MAX_CPL_WIDTH 2 1897#define FFE_AZ_TX_MAX_CPL_16 3 1898#define FFE_AZ_TX_MAX_CPL_8 2 1899#define FFE_AZ_TX_MAX_CPL_4 1 1900#define FFE_AZ_TX_MAX_CPL_NOLIMIT 0 1901#define FRF_AZ_TX_MAX_PREF_LBN 0 1902#define FRF_AZ_TX_MAX_PREF_WIDTH 2 1903#define FFE_AZ_TX_MAX_PREF_32 3 1904#define FFE_AZ_TX_MAX_PREF_16 2 1905#define FFE_AZ_TX_MAX_PREF_8 1 1906#define FFE_AZ_TX_MAX_PREF_OFF 0 1907 1908 1909/* 1910 * FR_BZ_TX_PACE_REG(128bit): 1911 * Transmit pace control register 1912 */ 1913#define FR_BZ_TX_PACE_REG_OFST 0x00000a90 1914/* falconb0,sienaa0=net_func_bar2 */ 1915/* 1916 * FR_AA_TX_PACE_REG(128bit): 1917 * Transmit pace control register 1918 */ 1919#define FR_AA_TX_PACE_REG_OFST 0x00f80000 1920/* falcona0=char_func_bar0 */ 1921 1922#define FRF_AZ_TX_PACE_SB_NOT_AF_LBN 19 1923#define FRF_AZ_TX_PACE_SB_NOT_AF_WIDTH 10 1924#define FRF_AZ_TX_PACE_SB_AF_LBN 9 1925#define FRF_AZ_TX_PACE_SB_AF_WIDTH 10 1926#define FRF_AZ_TX_PACE_FB_BASE_LBN 5 1927#define FRF_AZ_TX_PACE_FB_BASE_WIDTH 4 1928#define FRF_AZ_TX_PACE_BIN_TH_LBN 0 1929#define FRF_AZ_TX_PACE_BIN_TH_WIDTH 5 1930 1931 1932/* 1933 * FR_AZ_TX_PACE_DROP_QID_REG(128bit): 1934 * PACE Drop QID Counter 1935 */ 1936#define FR_AZ_TX_PACE_DROP_QID_REG_OFST 0x00000aa0 1937/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1938 1939#define FRF_AZ_TX_PACE_QID_DRP_CNT_LBN 0 1940#define FRF_AZ_TX_PACE_QID_DRP_CNT_WIDTH 16 1941 1942 1943/* 1944 * FR_AB_TX_VLAN_REG(128bit): 1945 * Transmit VLAN tag register 1946 */ 1947#define FR_AB_TX_VLAN_REG_OFST 0x00000ae0 1948/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1949 1950#define FRF_AB_TX_VLAN_EN_LBN 127 1951#define FRF_AB_TX_VLAN_EN_WIDTH 1 1952#define FRF_AB_TX_VLAN7_PORT1_EN_LBN 125 1953#define FRF_AB_TX_VLAN7_PORT1_EN_WIDTH 1 1954#define FRF_AB_TX_VLAN7_PORT0_EN_LBN 124 1955#define FRF_AB_TX_VLAN7_PORT0_EN_WIDTH 1 1956#define FRF_AB_TX_VLAN7_LBN 112 1957#define FRF_AB_TX_VLAN7_WIDTH 12 1958#define FRF_AB_TX_VLAN6_PORT1_EN_LBN 109 1959#define FRF_AB_TX_VLAN6_PORT1_EN_WIDTH 1 1960#define FRF_AB_TX_VLAN6_PORT0_EN_LBN 108 1961#define FRF_AB_TX_VLAN6_PORT0_EN_WIDTH 1 1962#define FRF_AB_TX_VLAN6_LBN 96 1963#define FRF_AB_TX_VLAN6_WIDTH 12 1964#define FRF_AB_TX_VLAN5_PORT1_EN_LBN 93 1965#define FRF_AB_TX_VLAN5_PORT1_EN_WIDTH 1 1966#define FRF_AB_TX_VLAN5_PORT0_EN_LBN 92 1967#define FRF_AB_TX_VLAN5_PORT0_EN_WIDTH 1 1968#define FRF_AB_TX_VLAN5_LBN 80 1969#define FRF_AB_TX_VLAN5_WIDTH 12 1970#define FRF_AB_TX_VLAN4_PORT1_EN_LBN 77 1971#define FRF_AB_TX_VLAN4_PORT1_EN_WIDTH 1 1972#define FRF_AB_TX_VLAN4_PORT0_EN_LBN 76 1973#define FRF_AB_TX_VLAN4_PORT0_EN_WIDTH 1 1974#define FRF_AB_TX_VLAN4_LBN 64 1975#define FRF_AB_TX_VLAN4_WIDTH 12 1976#define FRF_AB_TX_VLAN3_PORT1_EN_LBN 61 1977#define FRF_AB_TX_VLAN3_PORT1_EN_WIDTH 1 1978#define FRF_AB_TX_VLAN3_PORT0_EN_LBN 60 1979#define FRF_AB_TX_VLAN3_PORT0_EN_WIDTH 1 1980#define FRF_AB_TX_VLAN3_LBN 48 1981#define FRF_AB_TX_VLAN3_WIDTH 12 1982#define FRF_AB_TX_VLAN2_PORT1_EN_LBN 45 1983#define FRF_AB_TX_VLAN2_PORT1_EN_WIDTH 1 1984#define FRF_AB_TX_VLAN2_PORT0_EN_LBN 44 1985#define FRF_AB_TX_VLAN2_PORT0_EN_WIDTH 1 1986#define FRF_AB_TX_VLAN2_LBN 32 1987#define FRF_AB_TX_VLAN2_WIDTH 12 1988#define FRF_AB_TX_VLAN1_PORT1_EN_LBN 29 1989#define FRF_AB_TX_VLAN1_PORT1_EN_WIDTH 1 1990#define FRF_AB_TX_VLAN1_PORT0_EN_LBN 28 1991#define FRF_AB_TX_VLAN1_PORT0_EN_WIDTH 1 1992#define FRF_AB_TX_VLAN1_LBN 16 1993#define FRF_AB_TX_VLAN1_WIDTH 12 1994#define FRF_AB_TX_VLAN0_PORT1_EN_LBN 13 1995#define FRF_AB_TX_VLAN0_PORT1_EN_WIDTH 1 1996#define FRF_AB_TX_VLAN0_PORT0_EN_LBN 12 1997#define FRF_AB_TX_VLAN0_PORT0_EN_WIDTH 1 1998#define FRF_AB_TX_VLAN0_LBN 0 1999#define FRF_AB_TX_VLAN0_WIDTH 12 2000 2001 2002/* 2003 * FR_AZ_TX_IPFIL_PORTEN_REG(128bit): 2004 * Transmit filter control register 2005 */ 2006#define FR_AZ_TX_IPFIL_PORTEN_REG_OFST 0x00000af0 2007/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 2008 2009#define FRF_AZ_TX_MADR0_FIL_EN_LBN 64 2010#define FRF_AZ_TX_MADR0_FIL_EN_WIDTH 1 2011#define FRF_AB_TX_IPFIL31_PORT_EN_LBN 62 2012#define FRF_AB_TX_IPFIL31_PORT_EN_WIDTH 1 2013#define FRF_AB_TX_IPFIL30_PORT_EN_LBN 60 2014#define FRF_AB_TX_IPFIL30_PORT_EN_WIDTH 1 2015#define FRF_AB_TX_IPFIL29_PORT_EN_LBN 58 2016#define FRF_AB_TX_IPFIL29_PORT_EN_WIDTH 1 2017#define FRF_AB_TX_IPFIL28_PORT_EN_LBN 56 2018#define FRF_AB_TX_IPFIL28_PORT_EN_WIDTH 1 2019#define FRF_AB_TX_IPFIL27_PORT_EN_LBN 54 2020#define FRF_AB_TX_IPFIL27_PORT_EN_WIDTH 1 2021#define FRF_AB_TX_IPFIL26_PORT_EN_LBN 52 2022#define FRF_AB_TX_IPFIL26_PORT_EN_WIDTH 1 2023#define FRF_AB_TX_IPFIL25_PORT_EN_LBN 50 2024#define FRF_AB_TX_IPFIL25_PORT_EN_WIDTH 1 2025#define FRF_AB_TX_IPFIL24_PORT_EN_LBN 48 2026#define FRF_AB_TX_IPFIL24_PORT_EN_WIDTH 1 2027#define FRF_AB_TX_IPFIL23_PORT_EN_LBN 46 2028#define FRF_AB_TX_IPFIL23_PORT_EN_WIDTH 1 2029#define FRF_AB_TX_IPFIL22_PORT_EN_LBN 44 2030#define FRF_AB_TX_IPFIL22_PORT_EN_WIDTH 1 2031#define FRF_AB_TX_IPFIL21_PORT_EN_LBN 42 2032#define FRF_AB_TX_IPFIL21_PORT_EN_WIDTH 1 2033#define FRF_AB_TX_IPFIL20_PORT_EN_LBN 40 2034#define FRF_AB_TX_IPFIL20_PORT_EN_WIDTH 1 2035#define FRF_AB_TX_IPFIL19_PORT_EN_LBN 38 2036#define FRF_AB_TX_IPFIL19_PORT_EN_WIDTH 1 2037#define FRF_AB_TX_IPFIL18_PORT_EN_LBN 36 2038#define FRF_AB_TX_IPFIL18_PORT_EN_WIDTH 1 2039#define FRF_AB_TX_IPFIL17_PORT_EN_LBN 34 2040#define FRF_AB_TX_IPFIL17_PORT_EN_WIDTH 1 2041#define FRF_AB_TX_IPFIL16_PORT_EN_LBN 32 2042#define FRF_AB_TX_IPFIL16_PORT_EN_WIDTH 1 2043#define FRF_AB_TX_IPFIL15_PORT_EN_LBN 30 2044#define FRF_AB_TX_IPFIL15_PORT_EN_WIDTH 1 2045#define FRF_AB_TX_IPFIL14_PORT_EN_LBN 28 2046#define FRF_AB_TX_IPFIL14_PORT_EN_WIDTH 1 2047#define FRF_AB_TX_IPFIL13_PORT_EN_LBN 26 2048#define FRF_AB_TX_IPFIL13_PORT_EN_WIDTH 1 2049#define FRF_AB_TX_IPFIL12_PORT_EN_LBN 24 2050#define FRF_AB_TX_IPFIL12_PORT_EN_WIDTH 1 2051#define FRF_AB_TX_IPFIL11_PORT_EN_LBN 22 2052#define FRF_AB_TX_IPFIL11_PORT_EN_WIDTH 1 2053#define FRF_AB_TX_IPFIL10_PORT_EN_LBN 20 2054#define FRF_AB_TX_IPFIL10_PORT_EN_WIDTH 1 2055#define FRF_AB_TX_IPFIL9_PORT_EN_LBN 18 2056#define FRF_AB_TX_IPFIL9_PORT_EN_WIDTH 1 2057#define FRF_AB_TX_IPFIL8_PORT_EN_LBN 16 2058#define FRF_AB_TX_IPFIL8_PORT_EN_WIDTH 1 2059#define FRF_AB_TX_IPFIL7_PORT_EN_LBN 14 2060#define FRF_AB_TX_IPFIL7_PORT_EN_WIDTH 1 2061#define FRF_AB_TX_IPFIL6_PORT_EN_LBN 12 2062#define FRF_AB_TX_IPFIL6_PORT_EN_WIDTH 1 2063#define FRF_AB_TX_IPFIL5_PORT_EN_LBN 10 2064#define FRF_AB_TX_IPFIL5_PORT_EN_WIDTH 1 2065#define FRF_AB_TX_IPFIL4_PORT_EN_LBN 8 2066#define FRF_AB_TX_IPFIL4_PORT_EN_WIDTH 1 2067#define FRF_AB_TX_IPFIL3_PORT_EN_LBN 6 2068#define FRF_AB_TX_IPFIL3_PORT_EN_WIDTH 1 2069#define FRF_AB_TX_IPFIL2_PORT_EN_LBN 4 2070#define FRF_AB_TX_IPFIL2_PORT_EN_WIDTH 1 2071#define FRF_AB_TX_IPFIL1_PORT_EN_LBN 2 2072#define FRF_AB_TX_IPFIL1_PORT_EN_WIDTH 1 2073#define FRF_AB_TX_IPFIL0_PORT_EN_LBN 0 2074#define FRF_AB_TX_IPFIL0_PORT_EN_WIDTH 1 2075 2076 2077/* 2078 * FR_AB_TX_IPFIL_TBL(128bit): 2079 * Transmit IP source address filter table 2080 */ 2081#define FR_AB_TX_IPFIL_TBL_OFST 0x00000b00 2082/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2083#define FR_AB_TX_IPFIL_TBL_STEP 16 2084#define FR_AB_TX_IPFIL_TBL_ROWS 16 2085 2086#define FRF_AB_TX_IPFIL_MASK_1_LBN 96 2087#define FRF_AB_TX_IPFIL_MASK_1_WIDTH 32 2088#define FRF_AB_TX_IP_SRC_ADR_1_LBN 64 2089#define FRF_AB_TX_IP_SRC_ADR_1_WIDTH 32 2090#define FRF_AB_TX_IPFIL_MASK_0_LBN 32 2091#define FRF_AB_TX_IPFIL_MASK_0_WIDTH 32 2092#define FRF_AB_TX_IP_SRC_ADR_0_LBN 0 2093#define FRF_AB_TX_IP_SRC_ADR_0_WIDTH 32 2094 2095 2096/* 2097 * FR_AB_MD_TXD_REG(128bit): 2098 * PHY management transmit data register 2099 */ 2100#define FR_AB_MD_TXD_REG_OFST 0x00000c00 2101/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2102 2103#define FRF_AB_MD_TXD_LBN 0 2104#define FRF_AB_MD_TXD_WIDTH 16 2105 2106 2107/* 2108 * FR_AB_MD_RXD_REG(128bit): 2109 * PHY management receive data register 2110 */ 2111#define FR_AB_MD_RXD_REG_OFST 0x00000c10 2112/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2113 2114#define FRF_AB_MD_RXD_LBN 0 2115#define FRF_AB_MD_RXD_WIDTH 16 2116 2117 2118/* 2119 * FR_AB_MD_CS_REG(128bit): 2120 * PHY management configuration & status register 2121 */ 2122#define FR_AB_MD_CS_REG_OFST 0x00000c20 2123/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2124 2125#define FRF_AB_MD_RD_EN_LBN 15 2126#define FRF_AB_MD_RD_EN_WIDTH 1 2127#define FRF_AB_MD_WR_EN_LBN 14 2128#define FRF_AB_MD_WR_EN_WIDTH 1 2129#define FRF_AB_MD_ADDR_CMD_LBN 13 2130#define FRF_AB_MD_ADDR_CMD_WIDTH 1 2131#define FRF_AB_MD_PT_LBN 7 2132#define FRF_AB_MD_PT_WIDTH 3 2133#define FRF_AB_MD_PL_LBN 6 2134#define FRF_AB_MD_PL_WIDTH 1 2135#define FRF_AB_MD_INT_CLR_LBN 5 2136#define FRF_AB_MD_INT_CLR_WIDTH 1 2137#define FRF_AB_MD_GC_LBN 4 2138#define FRF_AB_MD_GC_WIDTH 1 2139#define FRF_AB_MD_PRSP_LBN 3 2140#define FRF_AB_MD_PRSP_WIDTH 1 2141#define FRF_AB_MD_RIC_LBN 2 2142#define FRF_AB_MD_RIC_WIDTH 1 2143#define FRF_AB_MD_RDC_LBN 1 2144#define FRF_AB_MD_RDC_WIDTH 1 2145#define FRF_AB_MD_WRC_LBN 0 2146#define FRF_AB_MD_WRC_WIDTH 1 2147 2148 2149/* 2150 * FR_AB_MD_PHY_ADR_REG(128bit): 2151 * PHY management PHY address register 2152 */ 2153#define FR_AB_MD_PHY_ADR_REG_OFST 0x00000c30 2154/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2155 2156#define FRF_AB_MD_PHY_ADR_LBN 0 2157#define FRF_AB_MD_PHY_ADR_WIDTH 16 2158 2159 2160/* 2161 * FR_AB_MD_ID_REG(128bit): 2162 * PHY management ID register 2163 */ 2164#define FR_AB_MD_ID_REG_OFST 0x00000c40 2165/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2166 2167#define FRF_AB_MD_PRT_ADR_LBN 11 2168#define FRF_AB_MD_PRT_ADR_WIDTH 5 2169#define FRF_AB_MD_DEV_ADR_LBN 6 2170#define FRF_AB_MD_DEV_ADR_WIDTH 5 2171 2172 2173/* 2174 * FR_AB_MD_STAT_REG(128bit): 2175 * PHY management status & mask register 2176 */ 2177#define FR_AB_MD_STAT_REG_OFST 0x00000c50 2178/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2179 2180#define FRF_AB_MD_PINT_LBN 4 2181#define FRF_AB_MD_PINT_WIDTH 1 2182#define FRF_AB_MD_DONE_LBN 3 2183#define FRF_AB_MD_DONE_WIDTH 1 2184#define FRF_AB_MD_BSERR_LBN 2 2185#define FRF_AB_MD_BSERR_WIDTH 1 2186#define FRF_AB_MD_LNFL_LBN 1 2187#define FRF_AB_MD_LNFL_WIDTH 1 2188#define FRF_AB_MD_BSY_LBN 0 2189#define FRF_AB_MD_BSY_WIDTH 1 2190 2191 2192/* 2193 * FR_AB_MAC_STAT_DMA_REG(128bit): 2194 * Port MAC statistical counter DMA register 2195 */ 2196#define FR_AB_MAC_STAT_DMA_REG_OFST 0x00000c60 2197/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2198 2199#define FRF_AB_MAC_STAT_DMA_CMD_LBN 48 2200#define FRF_AB_MAC_STAT_DMA_CMD_WIDTH 1 2201#define FRF_AB_MAC_STAT_DMA_ADR_LBN 0 2202#define FRF_AB_MAC_STAT_DMA_ADR_WIDTH 48 2203#define FRF_AB_MAC_STAT_DMA_ADR_DW0_LBN 0 2204#define FRF_AB_MAC_STAT_DMA_ADR_DW0_WIDTH 32 2205#define FRF_AB_MAC_STAT_DMA_ADR_DW1_LBN 32 2206#define FRF_AB_MAC_STAT_DMA_ADR_DW1_WIDTH 16 2207 2208 2209/* 2210 * FR_AB_MAC_CTRL_REG(128bit): 2211 * Port MAC control register 2212 */ 2213#define FR_AB_MAC_CTRL_REG_OFST 0x00000c80 2214/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2215 2216#define FRF_AB_MAC_XOFF_VAL_LBN 16 2217#define FRF_AB_MAC_XOFF_VAL_WIDTH 16 2218#define FRF_BB_TXFIFO_DRAIN_EN_LBN 7 2219#define FRF_BB_TXFIFO_DRAIN_EN_WIDTH 1 2220#define FRF_AB_MAC_XG_DISTXCRC_LBN 5 2221#define FRF_AB_MAC_XG_DISTXCRC_WIDTH 1 2222#define FRF_AB_MAC_BCAD_ACPT_LBN 4 2223#define FRF_AB_MAC_BCAD_ACPT_WIDTH 1 2224#define FRF_AB_MAC_UC_PROM_LBN 3 2225#define FRF_AB_MAC_UC_PROM_WIDTH 1 2226#define FRF_AB_MAC_LINK_STATUS_LBN 2 2227#define FRF_AB_MAC_LINK_STATUS_WIDTH 1 2228#define FRF_AB_MAC_SPEED_LBN 0 2229#define FRF_AB_MAC_SPEED_WIDTH 2 2230#define FRF_AB_MAC_SPEED_10M 0 2231#define FRF_AB_MAC_SPEED_100M 1 2232#define FRF_AB_MAC_SPEED_1G 2 2233#define FRF_AB_MAC_SPEED_10G 3 2234 2235/* 2236 * FR_BB_GEN_MODE_REG(128bit): 2237 * General Purpose mode register (external interrupt mask) 2238 */ 2239#define FR_BB_GEN_MODE_REG_OFST 0x00000c90 2240/* falconb0=net_func_bar2 */ 2241 2242#define FRF_BB_XFP_PHY_INT_POL_SEL_LBN 3 2243#define FRF_BB_XFP_PHY_INT_POL_SEL_WIDTH 1 2244#define FRF_BB_XG_PHY_INT_POL_SEL_LBN 2 2245#define FRF_BB_XG_PHY_INT_POL_SEL_WIDTH 1 2246#define FRF_BB_XFP_PHY_INT_MASK_LBN 1 2247#define FRF_BB_XFP_PHY_INT_MASK_WIDTH 1 2248#define FRF_BB_XG_PHY_INT_MASK_LBN 0 2249#define FRF_BB_XG_PHY_INT_MASK_WIDTH 1 2250 2251 2252/* 2253 * FR_AB_MAC_MC_HASH_REG0(128bit): 2254 * Multicast address hash table 2255 */ 2256#define FR_AB_MAC_MC_HASH0_REG_OFST 0x00000ca0 2257/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2258 2259#define FRF_AB_MAC_MCAST_HASH0_LBN 0 2260#define FRF_AB_MAC_MCAST_HASH0_WIDTH 128 2261#define FRF_AB_MAC_MCAST_HASH0_DW0_LBN 0 2262#define FRF_AB_MAC_MCAST_HASH0_DW0_WIDTH 32 2263#define FRF_AB_MAC_MCAST_HASH0_DW1_LBN 32 2264#define FRF_AB_MAC_MCAST_HASH0_DW1_WIDTH 32 2265#define FRF_AB_MAC_MCAST_HASH0_DW2_LBN 64 2266#define FRF_AB_MAC_MCAST_HASH0_DW2_WIDTH 32 2267#define FRF_AB_MAC_MCAST_HASH0_DW3_LBN 96 2268#define FRF_AB_MAC_MCAST_HASH0_DW3_WIDTH 32 2269 2270 2271/* 2272 * FR_AB_MAC_MC_HASH_REG1(128bit): 2273 * Multicast address hash table 2274 */ 2275#define FR_AB_MAC_MC_HASH1_REG_OFST 0x00000cb0 2276/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2277 2278#define FRF_AB_MAC_MCAST_HASH1_LBN 0 2279#define FRF_AB_MAC_MCAST_HASH1_WIDTH 128 2280#define FRF_AB_MAC_MCAST_HASH1_DW0_LBN 0 2281#define FRF_AB_MAC_MCAST_HASH1_DW0_WIDTH 32 2282#define FRF_AB_MAC_MCAST_HASH1_DW1_LBN 32 2283#define FRF_AB_MAC_MCAST_HASH1_DW1_WIDTH 32 2284#define FRF_AB_MAC_MCAST_HASH1_DW2_LBN 64 2285#define FRF_AB_MAC_MCAST_HASH1_DW2_WIDTH 32 2286#define FRF_AB_MAC_MCAST_HASH1_DW3_LBN 96 2287#define FRF_AB_MAC_MCAST_HASH1_DW3_WIDTH 32 2288 2289 2290/* 2291 * FR_AB_GM_CFG1_REG(32bit): 2292 * GMAC configuration register 1 2293 */ 2294#define FR_AB_GM_CFG1_REG_OFST 0x00000e00 2295/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2296 2297#define FRF_AB_GM_SW_RST_LBN 31 2298#define FRF_AB_GM_SW_RST_WIDTH 1 2299#define FRF_AB_GM_SIM_RST_LBN 30 2300#define FRF_AB_GM_SIM_RST_WIDTH 1 2301#define FRF_AB_GM_RST_RX_MAC_CTL_LBN 19 2302#define FRF_AB_GM_RST_RX_MAC_CTL_WIDTH 1 2303#define FRF_AB_GM_RST_TX_MAC_CTL_LBN 18 2304#define FRF_AB_GM_RST_TX_MAC_CTL_WIDTH 1 2305#define FRF_AB_GM_RST_RX_FUNC_LBN 17 2306#define FRF_AB_GM_RST_RX_FUNC_WIDTH 1 2307#define FRF_AB_GM_RST_TX_FUNC_LBN 16 2308#define FRF_AB_GM_RST_TX_FUNC_WIDTH 1 2309#define FRF_AB_GM_LOOP_LBN 8 2310#define FRF_AB_GM_LOOP_WIDTH 1 2311#define FRF_AB_GM_RX_FC_EN_LBN 5 2312#define FRF_AB_GM_RX_FC_EN_WIDTH 1 2313#define FRF_AB_GM_TX_FC_EN_LBN 4 2314#define FRF_AB_GM_TX_FC_EN_WIDTH 1 2315#define FRF_AB_GM_SYNC_RXEN_LBN 3 2316#define FRF_AB_GM_SYNC_RXEN_WIDTH 1 2317#define FRF_AB_GM_RX_EN_LBN 2 2318#define FRF_AB_GM_RX_EN_WIDTH 1 2319#define FRF_AB_GM_SYNC_TXEN_LBN 1 2320#define FRF_AB_GM_SYNC_TXEN_WIDTH 1 2321#define FRF_AB_GM_TX_EN_LBN 0 2322#define FRF_AB_GM_TX_EN_WIDTH 1 2323 2324 2325/* 2326 * FR_AB_GM_CFG2_REG(32bit): 2327 * GMAC configuration register 2 2328 */ 2329#define FR_AB_GM_CFG2_REG_OFST 0x00000e10 2330/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2331 2332#define FRF_AB_GM_PAMBL_LEN_LBN 12 2333#define FRF_AB_GM_PAMBL_LEN_WIDTH 4 2334#define FRF_AB_GM_IF_MODE_LBN 8 2335#define FRF_AB_GM_IF_MODE_WIDTH 2 2336#define FRF_AB_GM_IF_MODE_BYTE_MODE 2 2337#define FRF_AB_GM_IF_MODE_NIBBLE_MODE 1 2338#define FRF_AB_GM_HUGE_FRM_EN_LBN 5 2339#define FRF_AB_GM_HUGE_FRM_EN_WIDTH 1 2340#define FRF_AB_GM_LEN_CHK_LBN 4 2341#define FRF_AB_GM_LEN_CHK_WIDTH 1 2342#define FRF_AB_GM_PAD_CRC_EN_LBN 2 2343#define FRF_AB_GM_PAD_CRC_EN_WIDTH 1 2344#define FRF_AB_GM_CRC_EN_LBN 1 2345#define FRF_AB_GM_CRC_EN_WIDTH 1 2346#define FRF_AB_GM_FD_LBN 0 2347#define FRF_AB_GM_FD_WIDTH 1 2348 2349 2350/* 2351 * FR_AB_GM_IPG_REG(32bit): 2352 * GMAC IPG register 2353 */ 2354#define FR_AB_GM_IPG_REG_OFST 0x00000e20 2355/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2356 2357#define FRF_AB_GM_NONB2B_IPG1_LBN 24 2358#define FRF_AB_GM_NONB2B_IPG1_WIDTH 7 2359#define FRF_AB_GM_NONB2B_IPG2_LBN 16 2360#define FRF_AB_GM_NONB2B_IPG2_WIDTH 7 2361#define FRF_AB_GM_MIN_IPG_ENF_LBN 8 2362#define FRF_AB_GM_MIN_IPG_ENF_WIDTH 8 2363#define FRF_AB_GM_B2B_IPG_LBN 0 2364#define FRF_AB_GM_B2B_IPG_WIDTH 7 2365 2366 2367/* 2368 * FR_AB_GM_HD_REG(32bit): 2369 * GMAC half duplex register 2370 */ 2371#define FR_AB_GM_HD_REG_OFST 0x00000e30 2372/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2373 2374#define FRF_AB_GM_ALT_BOFF_VAL_LBN 20 2375#define FRF_AB_GM_ALT_BOFF_VAL_WIDTH 4 2376#define FRF_AB_GM_ALT_BOFF_EN_LBN 19 2377#define FRF_AB_GM_ALT_BOFF_EN_WIDTH 1 2378#define FRF_AB_GM_BP_NO_BOFF_LBN 18 2379#define FRF_AB_GM_BP_NO_BOFF_WIDTH 1 2380#define FRF_AB_GM_DIS_BOFF_LBN 17 2381#define FRF_AB_GM_DIS_BOFF_WIDTH 1 2382#define FRF_AB_GM_EXDEF_TX_EN_LBN 16 2383#define FRF_AB_GM_EXDEF_TX_EN_WIDTH 1 2384#define FRF_AB_GM_RTRY_LIMIT_LBN 12 2385#define FRF_AB_GM_RTRY_LIMIT_WIDTH 4 2386#define FRF_AB_GM_COL_WIN_LBN 0 2387#define FRF_AB_GM_COL_WIN_WIDTH 10 2388 2389 2390/* 2391 * FR_AB_GM_MAX_FLEN_REG(32bit): 2392 * GMAC maximum frame length register 2393 */ 2394#define FR_AB_GM_MAX_FLEN_REG_OFST 0x00000e40 2395/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2396 2397#define FRF_AB_GM_MAX_FLEN_LBN 0 2398#define FRF_AB_GM_MAX_FLEN_WIDTH 16 2399 2400 2401/* 2402 * FR_AB_GM_TEST_REG(32bit): 2403 * GMAC test register 2404 */ 2405#define FR_AB_GM_TEST_REG_OFST 0x00000e70 2406/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2407 2408#define FRF_AB_GM_MAX_BOFF_LBN 3 2409#define FRF_AB_GM_MAX_BOFF_WIDTH 1 2410#define FRF_AB_GM_REG_TX_FLOW_EN_LBN 2 2411#define FRF_AB_GM_REG_TX_FLOW_EN_WIDTH 1 2412#define FRF_AB_GM_TEST_PAUSE_LBN 1 2413#define FRF_AB_GM_TEST_PAUSE_WIDTH 1 2414#define FRF_AB_GM_SHORT_SLOT_LBN 0 2415#define FRF_AB_GM_SHORT_SLOT_WIDTH 1 2416 2417 2418/* 2419 * FR_AB_GM_ADR1_REG(32bit): 2420 * GMAC station address register 1 2421 */ 2422#define FR_AB_GM_ADR1_REG_OFST 0x00000f00 2423/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2424 2425#define FRF_AB_GM_ADR_B0_LBN 24 2426#define FRF_AB_GM_ADR_B0_WIDTH 8 2427#define FRF_AB_GM_ADR_B1_LBN 16 2428#define FRF_AB_GM_ADR_B1_WIDTH 8 2429#define FRF_AB_GM_ADR_B2_LBN 8 2430#define FRF_AB_GM_ADR_B2_WIDTH 8 2431#define FRF_AB_GM_ADR_B3_LBN 0 2432#define FRF_AB_GM_ADR_B3_WIDTH 8 2433 2434 2435/* 2436 * FR_AB_GM_ADR2_REG(32bit): 2437 * GMAC station address register 2 2438 */ 2439#define FR_AB_GM_ADR2_REG_OFST 0x00000f10 2440/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2441 2442#define FRF_AB_GM_ADR_B4_LBN 24 2443#define FRF_AB_GM_ADR_B4_WIDTH 8 2444#define FRF_AB_GM_ADR_B5_LBN 16 2445#define FRF_AB_GM_ADR_B5_WIDTH 8 2446 2447 2448/* 2449 * FR_AB_GMF_CFG0_REG(32bit): 2450 * GMAC FIFO configuration register 0 2451 */ 2452#define FR_AB_GMF_CFG0_REG_OFST 0x00000f20 2453/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2454 2455#define FRF_AB_GMF_FTFENRPLY_LBN 20 2456#define FRF_AB_GMF_FTFENRPLY_WIDTH 1 2457#define FRF_AB_GMF_STFENRPLY_LBN 19 2458#define FRF_AB_GMF_STFENRPLY_WIDTH 1 2459#define FRF_AB_GMF_FRFENRPLY_LBN 18 2460#define FRF_AB_GMF_FRFENRPLY_WIDTH 1 2461#define FRF_AB_GMF_SRFENRPLY_LBN 17 2462#define FRF_AB_GMF_SRFENRPLY_WIDTH 1 2463#define FRF_AB_GMF_WTMENRPLY_LBN 16 2464#define FRF_AB_GMF_WTMENRPLY_WIDTH 1 2465#define FRF_AB_GMF_FTFENREQ_LBN 12 2466#define FRF_AB_GMF_FTFENREQ_WIDTH 1 2467#define FRF_AB_GMF_STFENREQ_LBN 11 2468#define FRF_AB_GMF_STFENREQ_WIDTH 1 2469#define FRF_AB_GMF_FRFENREQ_LBN 10 2470#define FRF_AB_GMF_FRFENREQ_WIDTH 1 2471#define FRF_AB_GMF_SRFENREQ_LBN 9 2472#define FRF_AB_GMF_SRFENREQ_WIDTH 1 2473#define FRF_AB_GMF_WTMENREQ_LBN 8 2474#define FRF_AB_GMF_WTMENREQ_WIDTH 1 2475#define FRF_AB_GMF_HSTRSTFT_LBN 4 2476#define FRF_AB_GMF_HSTRSTFT_WIDTH 1 2477#define FRF_AB_GMF_HSTRSTST_LBN 3 2478#define FRF_AB_GMF_HSTRSTST_WIDTH 1 2479#define FRF_AB_GMF_HSTRSTFR_LBN 2 2480#define FRF_AB_GMF_HSTRSTFR_WIDTH 1 2481#define FRF_AB_GMF_HSTRSTSR_LBN 1 2482#define FRF_AB_GMF_HSTRSTSR_WIDTH 1 2483#define FRF_AB_GMF_HSTRSTWT_LBN 0 2484#define FRF_AB_GMF_HSTRSTWT_WIDTH 1 2485 2486 2487/* 2488 * FR_AB_GMF_CFG1_REG(32bit): 2489 * GMAC FIFO configuration register 1 2490 */ 2491#define FR_AB_GMF_CFG1_REG_OFST 0x00000f30 2492/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2493 2494#define FRF_AB_GMF_CFGFRTH_LBN 16 2495#define FRF_AB_GMF_CFGFRTH_WIDTH 5 2496#define FRF_AB_GMF_CFGXOFFRTX_LBN 0 2497#define FRF_AB_GMF_CFGXOFFRTX_WIDTH 16 2498 2499 2500/* 2501 * FR_AB_GMF_CFG2_REG(32bit): 2502 * GMAC FIFO configuration register 2 2503 */ 2504#define FR_AB_GMF_CFG2_REG_OFST 0x00000f40 2505/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2506 2507#define FRF_AB_GMF_CFGHWM_LBN 16 2508#define FRF_AB_GMF_CFGHWM_WIDTH 6 2509#define FRF_AB_GMF_CFGLWM_LBN 0 2510#define FRF_AB_GMF_CFGLWM_WIDTH 6 2511 2512 2513/* 2514 * FR_AB_GMF_CFG3_REG(32bit): 2515 * GMAC FIFO configuration register 3 2516 */ 2517#define FR_AB_GMF_CFG3_REG_OFST 0x00000f50 2518/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2519 2520#define FRF_AB_GMF_CFGHWMFT_LBN 16 2521#define FRF_AB_GMF_CFGHWMFT_WIDTH 6 2522#define FRF_AB_GMF_CFGFTTH_LBN 0 2523#define FRF_AB_GMF_CFGFTTH_WIDTH 6 2524 2525 2526/* 2527 * FR_AB_GMF_CFG4_REG(32bit): 2528 * GMAC FIFO configuration register 4 2529 */ 2530#define FR_AB_GMF_CFG4_REG_OFST 0x00000f60 2531/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2532 2533#define FRF_AB_GMF_HSTFLTRFRM_LBN 0 2534#define FRF_AB_GMF_HSTFLTRFRM_WIDTH 18 2535 2536 2537/* 2538 * FR_AB_GMF_CFG5_REG(32bit): 2539 * GMAC FIFO configuration register 5 2540 */ 2541#define FR_AB_GMF_CFG5_REG_OFST 0x00000f70 2542/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2543 2544#define FRF_AB_GMF_CFGHDPLX_LBN 22 2545#define FRF_AB_GMF_CFGHDPLX_WIDTH 1 2546#define FRF_AB_GMF_SRFULL_LBN 21 2547#define FRF_AB_GMF_SRFULL_WIDTH 1 2548#define FRF_AB_GMF_HSTSRFULLCLR_LBN 20 2549#define FRF_AB_GMF_HSTSRFULLCLR_WIDTH 1 2550#define FRF_AB_GMF_CFGBYTMODE_LBN 19 2551#define FRF_AB_GMF_CFGBYTMODE_WIDTH 1 2552#define FRF_AB_GMF_HSTDRPLT64_LBN 18 2553#define FRF_AB_GMF_HSTDRPLT64_WIDTH 1 2554#define FRF_AB_GMF_HSTFLTRFRMDC_LBN 0 2555#define FRF_AB_GMF_HSTFLTRFRMDC_WIDTH 18 2556 2557 2558/* 2559 * FR_BB_TX_SRC_MAC_TBL(128bit): 2560 * Transmit IP source address filter table 2561 */ 2562#define FR_BB_TX_SRC_MAC_TBL_OFST 0x00001000 2563/* falconb0=net_func_bar2 */ 2564#define FR_BB_TX_SRC_MAC_TBL_STEP 16 2565#define FR_BB_TX_SRC_MAC_TBL_ROWS 16 2566 2567#define FRF_BB_TX_SRC_MAC_ADR_1_LBN 64 2568#define FRF_BB_TX_SRC_MAC_ADR_1_WIDTH 48 2569#define FRF_BB_TX_SRC_MAC_ADR_1_DW0_LBN 64 2570#define FRF_BB_TX_SRC_MAC_ADR_1_DW0_WIDTH 32 2571#define FRF_BB_TX_SRC_MAC_ADR_1_DW1_LBN 96 2572#define FRF_BB_TX_SRC_MAC_ADR_1_DW1_WIDTH 16 2573#define FRF_BB_TX_SRC_MAC_ADR_0_LBN 0 2574#define FRF_BB_TX_SRC_MAC_ADR_0_WIDTH 48 2575#define FRF_BB_TX_SRC_MAC_ADR_0_DW0_LBN 0 2576#define FRF_BB_TX_SRC_MAC_ADR_0_DW0_WIDTH 32 2577#define FRF_BB_TX_SRC_MAC_ADR_0_DW1_LBN 32 2578#define FRF_BB_TX_SRC_MAC_ADR_0_DW1_WIDTH 16 2579 2580 2581/* 2582 * FR_BB_TX_SRC_MAC_CTL_REG(128bit): 2583 * Transmit MAC source address filter control 2584 */ 2585#define FR_BB_TX_SRC_MAC_CTL_REG_OFST 0x00001100 2586/* falconb0=net_func_bar2 */ 2587 2588#define FRF_BB_TX_SRC_DROP_CTR_LBN 16 2589#define FRF_BB_TX_SRC_DROP_CTR_WIDTH 16 2590#define FRF_BB_TX_SRC_FLTR_EN_LBN 15 2591#define FRF_BB_TX_SRC_FLTR_EN_WIDTH 1 2592#define FRF_BB_TX_DROP_CTR_CLR_LBN 12 2593#define FRF_BB_TX_DROP_CTR_CLR_WIDTH 1 2594#define FRF_BB_TX_MAC_QID_SEL_LBN 0 2595#define FRF_BB_TX_MAC_QID_SEL_WIDTH 3 2596 2597 2598/* 2599 * FR_AB_XM_ADR_LO_REG(128bit): 2600 * XGMAC address register low 2601 */ 2602#define FR_AB_XM_ADR_LO_REG_OFST 0x00001200 2603/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2604 2605#define FRF_AB_XM_ADR_LO_LBN 0 2606#define FRF_AB_XM_ADR_LO_WIDTH 32 2607 2608 2609/* 2610 * FR_AB_XM_ADR_HI_REG(128bit): 2611 * XGMAC address register high 2612 */ 2613#define FR_AB_XM_ADR_HI_REG_OFST 0x00001210 2614/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2615 2616#define FRF_AB_XM_ADR_HI_LBN 0 2617#define FRF_AB_XM_ADR_HI_WIDTH 16 2618 2619 2620/* 2621 * FR_AB_XM_GLB_CFG_REG(128bit): 2622 * XGMAC global configuration 2623 */ 2624#define FR_AB_XM_GLB_CFG_REG_OFST 0x00001220 2625/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2626 2627#define FRF_AB_XM_RMTFLT_GEN_LBN 17 2628#define FRF_AB_XM_RMTFLT_GEN_WIDTH 1 2629#define FRF_AB_XM_DEBUG_MODE_LBN 16 2630#define FRF_AB_XM_DEBUG_MODE_WIDTH 1 2631#define FRF_AB_XM_RX_STAT_EN_LBN 11 2632#define FRF_AB_XM_RX_STAT_EN_WIDTH 1 2633#define FRF_AB_XM_TX_STAT_EN_LBN 10 2634#define FRF_AB_XM_TX_STAT_EN_WIDTH 1 2635#define FRF_AB_XM_RX_JUMBO_MODE_LBN 6 2636#define FRF_AB_XM_RX_JUMBO_MODE_WIDTH 1 2637#define FRF_AB_XM_WAN_MODE_LBN 5 2638#define FRF_AB_XM_WAN_MODE_WIDTH 1 2639#define FRF_AB_XM_INTCLR_MODE_LBN 3 2640#define FRF_AB_XM_INTCLR_MODE_WIDTH 1 2641#define FRF_AB_XM_CORE_RST_LBN 0 2642#define FRF_AB_XM_CORE_RST_WIDTH 1 2643 2644 2645/* 2646 * FR_AB_XM_TX_CFG_REG(128bit): 2647 * XGMAC transmit configuration 2648 */ 2649#define FR_AB_XM_TX_CFG_REG_OFST 0x00001230 2650/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2651 2652#define FRF_AB_XM_TX_PROG_LBN 24 2653#define FRF_AB_XM_TX_PROG_WIDTH 1 2654#define FRF_AB_XM_IPG_LBN 16 2655#define FRF_AB_XM_IPG_WIDTH 4 2656#define FRF_AB_XM_FCNTL_LBN 10 2657#define FRF_AB_XM_FCNTL_WIDTH 1 2658#define FRF_AB_XM_TXCRC_LBN 8 2659#define FRF_AB_XM_TXCRC_WIDTH 1 2660#define FRF_AB_XM_EDRC_LBN 6 2661#define FRF_AB_XM_EDRC_WIDTH 1 2662#define FRF_AB_XM_AUTO_PAD_LBN 5 2663#define FRF_AB_XM_AUTO_PAD_WIDTH 1 2664#define FRF_AB_XM_TX_PRMBL_LBN 2 2665#define FRF_AB_XM_TX_PRMBL_WIDTH 1 2666#define FRF_AB_XM_TXEN_LBN 1 2667#define FRF_AB_XM_TXEN_WIDTH 1 2668#define FRF_AB_XM_TX_RST_LBN 0 2669#define FRF_AB_XM_TX_RST_WIDTH 1 2670 2671 2672/* 2673 * FR_AB_XM_RX_CFG_REG(128bit): 2674 * XGMAC receive configuration 2675 */ 2676#define FR_AB_XM_RX_CFG_REG_OFST 0x00001240 2677/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2678 2679#define FRF_AB_XM_PASS_LENERR_LBN 26 2680#define FRF_AB_XM_PASS_LENERR_WIDTH 1 2681#define FRF_AB_XM_PASS_CRC_ERR_LBN 25 2682#define FRF_AB_XM_PASS_CRC_ERR_WIDTH 1 2683#define FRF_AB_XM_PASS_PRMBLE_ERR_LBN 24 2684#define FRF_AB_XM_PASS_PRMBLE_ERR_WIDTH 1 2685#define FRF_AB_XM_REJ_BCAST_LBN 20 2686#define FRF_AB_XM_REJ_BCAST_WIDTH 1 2687#define FRF_AB_XM_ACPT_ALL_MCAST_LBN 11 2688#define FRF_AB_XM_ACPT_ALL_MCAST_WIDTH 1 2689#define FRF_AB_XM_ACPT_ALL_UCAST_LBN 9 2690#define FRF_AB_XM_ACPT_ALL_UCAST_WIDTH 1 2691#define FRF_AB_XM_AUTO_DEPAD_LBN 8 2692#define FRF_AB_XM_AUTO_DEPAD_WIDTH 1 2693#define FRF_AB_XM_RXCRC_LBN 3 2694#define FRF_AB_XM_RXCRC_WIDTH 1 2695#define FRF_AB_XM_RX_PRMBL_LBN 2 2696#define FRF_AB_XM_RX_PRMBL_WIDTH 1 2697#define FRF_AB_XM_RXEN_LBN 1 2698#define FRF_AB_XM_RXEN_WIDTH 1 2699#define FRF_AB_XM_RX_RST_LBN 0 2700#define FRF_AB_XM_RX_RST_WIDTH 1 2701 2702 2703/* 2704 * FR_AB_XM_MGT_INT_MASK(128bit): 2705 * documentation to be written for sum_XM_MGT_INT_MASK 2706 */ 2707#define FR_AB_XM_MGT_INT_MASK_OFST 0x00001250 2708/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2709 2710#define FRF_AB_XM_MSK_STA_INTR_LBN 16 2711#define FRF_AB_XM_MSK_STA_INTR_WIDTH 1 2712#define FRF_AB_XM_MSK_STAT_CNTR_HF_LBN 9 2713#define FRF_AB_XM_MSK_STAT_CNTR_HF_WIDTH 1 2714#define FRF_AB_XM_MSK_STAT_CNTR_OF_LBN 8 2715#define FRF_AB_XM_MSK_STAT_CNTR_OF_WIDTH 1 2716#define FRF_AB_XM_MSK_PRMBLE_ERR_LBN 2 2717#define FRF_AB_XM_MSK_PRMBLE_ERR_WIDTH 1 2718#define FRF_AB_XM_MSK_RMTFLT_LBN 1 2719#define FRF_AB_XM_MSK_RMTFLT_WIDTH 1 2720#define FRF_AB_XM_MSK_LCLFLT_LBN 0 2721#define FRF_AB_XM_MSK_LCLFLT_WIDTH 1 2722 2723 2724/* 2725 * FR_AB_XM_FC_REG(128bit): 2726 * XGMAC flow control register 2727 */ 2728#define FR_AB_XM_FC_REG_OFST 0x00001270 2729/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2730 2731#define FRF_AB_XM_PAUSE_TIME_LBN 16 2732#define FRF_AB_XM_PAUSE_TIME_WIDTH 16 2733#define FRF_AB_XM_RX_MAC_STAT_LBN 11 2734#define FRF_AB_XM_RX_MAC_STAT_WIDTH 1 2735#define FRF_AB_XM_TX_MAC_STAT_LBN 10 2736#define FRF_AB_XM_TX_MAC_STAT_WIDTH 1 2737#define FRF_AB_XM_MCNTL_PASS_LBN 8 2738#define FRF_AB_XM_MCNTL_PASS_WIDTH 2 2739#define FRF_AB_XM_REJ_CNTL_UCAST_LBN 6 2740#define FRF_AB_XM_REJ_CNTL_UCAST_WIDTH 1 2741#define FRF_AB_XM_REJ_CNTL_MCAST_LBN 5 2742#define FRF_AB_XM_REJ_CNTL_MCAST_WIDTH 1 2743#define FRF_AB_XM_ZPAUSE_LBN 2 2744#define FRF_AB_XM_ZPAUSE_WIDTH 1 2745#define FRF_AB_XM_XMIT_PAUSE_LBN 1 2746#define FRF_AB_XM_XMIT_PAUSE_WIDTH 1 2747#define FRF_AB_XM_DIS_FCNTL_LBN 0 2748#define FRF_AB_XM_DIS_FCNTL_WIDTH 1 2749 2750 2751/* 2752 * FR_AB_XM_PAUSE_TIME_REG(128bit): 2753 * XGMAC pause time register 2754 */ 2755#define FR_AB_XM_PAUSE_TIME_REG_OFST 0x00001290 2756/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2757 2758#define FRF_AB_XM_TX_PAUSE_CNT_LBN 16 2759#define FRF_AB_XM_TX_PAUSE_CNT_WIDTH 16 2760#define FRF_AB_XM_RX_PAUSE_CNT_LBN 0 2761#define FRF_AB_XM_RX_PAUSE_CNT_WIDTH 16 2762 2763 2764/* 2765 * FR_AB_XM_TX_PARAM_REG(128bit): 2766 * XGMAC transmit parameter register 2767 */ 2768#define FR_AB_XM_TX_PARAM_REG_OFST 0x000012d0 2769/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2770 2771#define FRF_AB_XM_TX_JUMBO_MODE_LBN 31 2772#define FRF_AB_XM_TX_JUMBO_MODE_WIDTH 1 2773#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_LBN 19 2774#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH 11 2775#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN 16 2776#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH 3 2777#define FRF_AB_XM_PAD_CHAR_LBN 0 2778#define FRF_AB_XM_PAD_CHAR_WIDTH 8 2779 2780 2781/* 2782 * FR_AB_XM_RX_PARAM_REG(128bit): 2783 * XGMAC receive parameter register 2784 */ 2785#define FR_AB_XM_RX_PARAM_REG_OFST 0x000012e0 2786/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2787 2788#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_LBN 3 2789#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH 11 2790#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN 0 2791#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH 3 2792 2793 2794/* 2795 * FR_AB_XM_MGT_INT_MSK_REG(128bit): 2796 * XGMAC management interrupt mask register 2797 */ 2798#define FR_AB_XM_MGT_INT_REG_OFST 0x000012f0 2799/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2800 2801#define FRF_AB_XM_STAT_CNTR_OF_LBN 9 2802#define FRF_AB_XM_STAT_CNTR_OF_WIDTH 1 2803#define FRF_AB_XM_STAT_CNTR_HF_LBN 8 2804#define FRF_AB_XM_STAT_CNTR_HF_WIDTH 1 2805#define FRF_AB_XM_PRMBLE_ERR_LBN 2 2806#define FRF_AB_XM_PRMBLE_ERR_WIDTH 1 2807#define FRF_AB_XM_RMTFLT_LBN 1 2808#define FRF_AB_XM_RMTFLT_WIDTH 1 2809#define FRF_AB_XM_LCLFLT_LBN 0 2810#define FRF_AB_XM_LCLFLT_WIDTH 1 2811 2812 2813/* 2814 * FR_AB_XX_PWR_RST_REG(128bit): 2815 * XGXS/XAUI powerdown/reset register 2816 */ 2817#define FR_AB_XX_PWR_RST_REG_OFST 0x00001300 2818/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2819 2820#define FRF_AB_XX_PWRDND_SIG_LBN 31 2821#define FRF_AB_XX_PWRDND_SIG_WIDTH 1 2822#define FRF_AB_XX_PWRDNC_SIG_LBN 30 2823#define FRF_AB_XX_PWRDNC_SIG_WIDTH 1 2824#define FRF_AB_XX_PWRDNB_SIG_LBN 29 2825#define FRF_AB_XX_PWRDNB_SIG_WIDTH 1 2826#define FRF_AB_XX_PWRDNA_SIG_LBN 28 2827#define FRF_AB_XX_PWRDNA_SIG_WIDTH 1 2828#define FRF_AB_XX_SIM_MODE_LBN 27 2829#define FRF_AB_XX_SIM_MODE_WIDTH 1 2830#define FRF_AB_XX_RSTPLLCD_SIG_LBN 25 2831#define FRF_AB_XX_RSTPLLCD_SIG_WIDTH 1 2832#define FRF_AB_XX_RSTPLLAB_SIG_LBN 24 2833#define FRF_AB_XX_RSTPLLAB_SIG_WIDTH 1 2834#define FRF_AB_XX_RESETD_SIG_LBN 23 2835#define FRF_AB_XX_RESETD_SIG_WIDTH 1 2836#define FRF_AB_XX_RESETC_SIG_LBN 22 2837#define FRF_AB_XX_RESETC_SIG_WIDTH 1 2838#define FRF_AB_XX_RESETB_SIG_LBN 21 2839#define FRF_AB_XX_RESETB_SIG_WIDTH 1 2840#define FRF_AB_XX_RESETA_SIG_LBN 20 2841#define FRF_AB_XX_RESETA_SIG_WIDTH 1 2842#define FRF_AB_XX_RSTXGXSRX_SIG_LBN 18 2843#define FRF_AB_XX_RSTXGXSRX_SIG_WIDTH 1 2844#define FRF_AB_XX_RSTXGXSTX_SIG_LBN 17 2845#define FRF_AB_XX_RSTXGXSTX_SIG_WIDTH 1 2846#define FRF_AB_XX_SD_RST_ACT_LBN 16 2847#define FRF_AB_XX_SD_RST_ACT_WIDTH 1 2848#define FRF_AB_XX_PWRDND_EN_LBN 15 2849#define FRF_AB_XX_PWRDND_EN_WIDTH 1 2850#define FRF_AB_XX_PWRDNC_EN_LBN 14 2851#define FRF_AB_XX_PWRDNC_EN_WIDTH 1 2852#define FRF_AB_XX_PWRDNB_EN_LBN 13 2853#define FRF_AB_XX_PWRDNB_EN_WIDTH 1 2854#define FRF_AB_XX_PWRDNA_EN_LBN 12 2855#define FRF_AB_XX_PWRDNA_EN_WIDTH 1 2856#define FRF_AB_XX_RSTPLLCD_EN_LBN 9 2857#define FRF_AB_XX_RSTPLLCD_EN_WIDTH 1 2858#define FRF_AB_XX_RSTPLLAB_EN_LBN 8 2859#define FRF_AB_XX_RSTPLLAB_EN_WIDTH 1 2860#define FRF_AB_XX_RESETD_EN_LBN 7 2861#define FRF_AB_XX_RESETD_EN_WIDTH 1 2862#define FRF_AB_XX_RESETC_EN_LBN 6 2863#define FRF_AB_XX_RESETC_EN_WIDTH 1 2864#define FRF_AB_XX_RESETB_EN_LBN 5 2865#define FRF_AB_XX_RESETB_EN_WIDTH 1 2866#define FRF_AB_XX_RESETA_EN_LBN 4 2867#define FRF_AB_XX_RESETA_EN_WIDTH 1 2868#define FRF_AB_XX_RSTXGXSRX_EN_LBN 2 2869#define FRF_AB_XX_RSTXGXSRX_EN_WIDTH 1 2870#define FRF_AB_XX_RSTXGXSTX_EN_LBN 1 2871#define FRF_AB_XX_RSTXGXSTX_EN_WIDTH 1 2872#define FRF_AB_XX_RST_XX_EN_LBN 0 2873#define FRF_AB_XX_RST_XX_EN_WIDTH 1 2874 2875 2876/* 2877 * FR_AB_XX_SD_CTL_REG(128bit): 2878 * XGXS/XAUI powerdown/reset control register 2879 */ 2880#define FR_AB_XX_SD_CTL_REG_OFST 0x00001310 2881/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2882 2883#define FRF_AB_XX_TERMADJ1_LBN 17 2884#define FRF_AB_XX_TERMADJ1_WIDTH 1 2885#define FRF_AB_XX_TERMADJ0_LBN 16 2886#define FRF_AB_XX_TERMADJ0_WIDTH 1 2887#define FRF_AB_XX_HIDRVD_LBN 15 2888#define FRF_AB_XX_HIDRVD_WIDTH 1 2889#define FRF_AB_XX_LODRVD_LBN 14 2890#define FRF_AB_XX_LODRVD_WIDTH 1 2891#define FRF_AB_XX_HIDRVC_LBN 13 2892#define FRF_AB_XX_HIDRVC_WIDTH 1 2893#define FRF_AB_XX_LODRVC_LBN 12 2894#define FRF_AB_XX_LODRVC_WIDTH 1 2895#define FRF_AB_XX_HIDRVB_LBN 11 2896#define FRF_AB_XX_HIDRVB_WIDTH 1 2897#define FRF_AB_XX_LODRVB_LBN 10 2898#define FRF_AB_XX_LODRVB_WIDTH 1 2899#define FRF_AB_XX_HIDRVA_LBN 9 2900#define FRF_AB_XX_HIDRVA_WIDTH 1 2901#define FRF_AB_XX_LODRVA_LBN 8 2902#define FRF_AB_XX_LODRVA_WIDTH 1 2903#define FRF_AB_XX_LPBKD_LBN 3 2904#define FRF_AB_XX_LPBKD_WIDTH 1 2905#define FRF_AB_XX_LPBKC_LBN 2 2906#define FRF_AB_XX_LPBKC_WIDTH 1 2907#define FRF_AB_XX_LPBKB_LBN 1 2908#define FRF_AB_XX_LPBKB_WIDTH 1 2909#define FRF_AB_XX_LPBKA_LBN 0 2910#define FRF_AB_XX_LPBKA_WIDTH 1 2911 2912 2913/* 2914 * FR_AB_XX_TXDRV_CTL_REG(128bit): 2915 * XAUI SerDes transmit drive control register 2916 */ 2917#define FR_AB_XX_TXDRV_CTL_REG_OFST 0x00001320 2918/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2919 2920#define FRF_AB_XX_DEQD_LBN 28 2921#define FRF_AB_XX_DEQD_WIDTH 4 2922#define FRF_AB_XX_DEQC_LBN 24 2923#define FRF_AB_XX_DEQC_WIDTH 4 2924#define FRF_AB_XX_DEQB_LBN 20 2925#define FRF_AB_XX_DEQB_WIDTH 4 2926#define FRF_AB_XX_DEQA_LBN 16 2927#define FRF_AB_XX_DEQA_WIDTH 4 2928#define FRF_AB_XX_DTXD_LBN 12 2929#define FRF_AB_XX_DTXD_WIDTH 4 2930#define FRF_AB_XX_DTXC_LBN 8 2931#define FRF_AB_XX_DTXC_WIDTH 4 2932#define FRF_AB_XX_DTXB_LBN 4 2933#define FRF_AB_XX_DTXB_WIDTH 4 2934#define FRF_AB_XX_DTXA_LBN 0 2935#define FRF_AB_XX_DTXA_WIDTH 4 2936 2937 2938/* 2939 * FR_AB_XX_PRBS_CTL_REG(128bit): 2940 * documentation to be written for sum_XX_PRBS_CTL_REG 2941 */ 2942#define FR_AB_XX_PRBS_CTL_REG_OFST 0x00001330 2943/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2944 2945#define FRF_AB_XX_CH3_RX_PRBS_SEL_LBN 30 2946#define FRF_AB_XX_CH3_RX_PRBS_SEL_WIDTH 2 2947#define FRF_AB_XX_CH3_RX_PRBS_INV_LBN 29 2948#define FRF_AB_XX_CH3_RX_PRBS_INV_WIDTH 1 2949#define FRF_AB_XX_CH3_RX_PRBS_CHKEN_LBN 28 2950#define FRF_AB_XX_CH3_RX_PRBS_CHKEN_WIDTH 1 2951#define FRF_AB_XX_CH2_RX_PRBS_SEL_LBN 26 2952#define FRF_AB_XX_CH2_RX_PRBS_SEL_WIDTH 2 2953#define FRF_AB_XX_CH2_RX_PRBS_INV_LBN 25 2954#define FRF_AB_XX_CH2_RX_PRBS_INV_WIDTH 1 2955#define FRF_AB_XX_CH2_RX_PRBS_CHKEN_LBN 24 2956#define FRF_AB_XX_CH2_RX_PRBS_CHKEN_WIDTH 1 2957#define FRF_AB_XX_CH1_RX_PRBS_SEL_LBN 22 2958#define FRF_AB_XX_CH1_RX_PRBS_SEL_WIDTH 2 2959#define FRF_AB_XX_CH1_RX_PRBS_INV_LBN 21 2960#define FRF_AB_XX_CH1_RX_PRBS_INV_WIDTH 1 2961#define FRF_AB_XX_CH1_RX_PRBS_CHKEN_LBN 20 2962#define FRF_AB_XX_CH1_RX_PRBS_CHKEN_WIDTH 1 2963#define FRF_AB_XX_CH0_RX_PRBS_SEL_LBN 18 2964#define FRF_AB_XX_CH0_RX_PRBS_SEL_WIDTH 2 2965#define FRF_AB_XX_CH0_RX_PRBS_INV_LBN 17 2966#define FRF_AB_XX_CH0_RX_PRBS_INV_WIDTH 1 2967#define FRF_AB_XX_CH0_RX_PRBS_CHKEN_LBN 16 2968#define FRF_AB_XX_CH0_RX_PRBS_CHKEN_WIDTH 1 2969#define FRF_AB_XX_CH3_TX_PRBS_SEL_LBN 14 2970#define FRF_AB_XX_CH3_TX_PRBS_SEL_WIDTH 2 2971#define FRF_AB_XX_CH3_TX_PRBS_INV_LBN 13 2972#define FRF_AB_XX_CH3_TX_PRBS_INV_WIDTH 1 2973#define FRF_AB_XX_CH3_TX_PRBS_CHKEN_LBN 12 2974#define FRF_AB_XX_CH3_TX_PRBS_CHKEN_WIDTH 1 2975#define FRF_AB_XX_CH2_TX_PRBS_SEL_LBN 10 2976#define FRF_AB_XX_CH2_TX_PRBS_SEL_WIDTH 2 2977#define FRF_AB_XX_CH2_TX_PRBS_INV_LBN 9 2978#define FRF_AB_XX_CH2_TX_PRBS_INV_WIDTH 1 2979#define FRF_AB_XX_CH2_TX_PRBS_CHKEN_LBN 8 2980#define FRF_AB_XX_CH2_TX_PRBS_CHKEN_WIDTH 1 2981#define FRF_AB_XX_CH1_TX_PRBS_SEL_LBN 6 2982#define FRF_AB_XX_CH1_TX_PRBS_SEL_WIDTH 2 2983#define FRF_AB_XX_CH1_TX_PRBS_INV_LBN 5 2984#define FRF_AB_XX_CH1_TX_PRBS_INV_WIDTH 1 2985#define FRF_AB_XX_CH1_TX_PRBS_CHKEN_LBN 4 2986#define FRF_AB_XX_CH1_TX_PRBS_CHKEN_WIDTH 1 2987#define FRF_AB_XX_CH0_TX_PRBS_SEL_LBN 2 2988#define FRF_AB_XX_CH0_TX_PRBS_SEL_WIDTH 2 2989#define FRF_AB_XX_CH0_TX_PRBS_INV_LBN 1 2990#define FRF_AB_XX_CH0_TX_PRBS_INV_WIDTH 1 2991#define FRF_AB_XX_CH0_TX_PRBS_CHKEN_LBN 0 2992#define FRF_AB_XX_CH0_TX_PRBS_CHKEN_WIDTH 1 2993 2994 2995/* 2996 * FR_AB_XX_PRBS_CHK_REG(128bit): 2997 * documentation to be written for sum_XX_PRBS_CHK_REG 2998 */ 2999#define FR_AB_XX_PRBS_CHK_REG_OFST 0x00001340 3000/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3001 3002#define FRF_AB_XX_REV_LB_EN_LBN 16 3003#define FRF_AB_XX_REV_LB_EN_WIDTH 1 3004#define FRF_AB_XX_CH3_DEG_DET_LBN 15 3005#define FRF_AB_XX_CH3_DEG_DET_WIDTH 1 3006#define FRF_AB_XX_CH3_LFSR_LOCK_IND_LBN 14 3007#define FRF_AB_XX_CH3_LFSR_LOCK_IND_WIDTH 1 3008#define FRF_AB_XX_CH3_PRBS_FRUN_LBN 13 3009#define FRF_AB_XX_CH3_PRBS_FRUN_WIDTH 1 3010#define FRF_AB_XX_CH3_ERR_CHK_LBN 12 3011#define FRF_AB_XX_CH3_ERR_CHK_WIDTH 1 3012#define FRF_AB_XX_CH2_DEG_DET_LBN 11 3013#define FRF_AB_XX_CH2_DEG_DET_WIDTH 1 3014#define FRF_AB_XX_CH2_LFSR_LOCK_IND_LBN 10 3015#define FRF_AB_XX_CH2_LFSR_LOCK_IND_WIDTH 1 3016#define FRF_AB_XX_CH2_PRBS_FRUN_LBN 9 3017#define FRF_AB_XX_CH2_PRBS_FRUN_WIDTH 1 3018#define FRF_AB_XX_CH2_ERR_CHK_LBN 8 3019#define FRF_AB_XX_CH2_ERR_CHK_WIDTH 1 3020#define FRF_AB_XX_CH1_DEG_DET_LBN 7 3021#define FRF_AB_XX_CH1_DEG_DET_WIDTH 1 3022#define FRF_AB_XX_CH1_LFSR_LOCK_IND_LBN 6 3023#define FRF_AB_XX_CH1_LFSR_LOCK_IND_WIDTH 1 3024#define FRF_AB_XX_CH1_PRBS_FRUN_LBN 5 3025#define FRF_AB_XX_CH1_PRBS_FRUN_WIDTH 1 3026#define FRF_AB_XX_CH1_ERR_CHK_LBN 4 3027#define FRF_AB_XX_CH1_ERR_CHK_WIDTH 1 3028#define FRF_AB_XX_CH0_DEG_DET_LBN 3 3029#define FRF_AB_XX_CH0_DEG_DET_WIDTH 1 3030#define FRF_AB_XX_CH0_LFSR_LOCK_IND_LBN 2 3031#define FRF_AB_XX_CH0_LFSR_LOCK_IND_WIDTH 1 3032#define FRF_AB_XX_CH0_PRBS_FRUN_LBN 1 3033#define FRF_AB_XX_CH0_PRBS_FRUN_WIDTH 1 3034#define FRF_AB_XX_CH0_ERR_CHK_LBN 0 3035#define FRF_AB_XX_CH0_ERR_CHK_WIDTH 1 3036 3037 3038/* 3039 * FR_AB_XX_PRBS_ERR_REG(128bit): 3040 * documentation to be written for sum_XX_PRBS_ERR_REG 3041 */ 3042#define FR_AB_XX_PRBS_ERR_REG_OFST 0x00001350 3043/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3044 3045#define FRF_AB_XX_CH3_PRBS_ERR_CNT_LBN 24 3046#define FRF_AB_XX_CH3_PRBS_ERR_CNT_WIDTH 8 3047#define FRF_AB_XX_CH2_PRBS_ERR_CNT_LBN 16 3048#define FRF_AB_XX_CH2_PRBS_ERR_CNT_WIDTH 8 3049#define FRF_AB_XX_CH1_PRBS_ERR_CNT_LBN 8 3050#define FRF_AB_XX_CH1_PRBS_ERR_CNT_WIDTH 8 3051#define FRF_AB_XX_CH0_PRBS_ERR_CNT_LBN 0 3052#define FRF_AB_XX_CH0_PRBS_ERR_CNT_WIDTH 8 3053 3054 3055/* 3056 * FR_AB_XX_CORE_STAT_REG(128bit): 3057 * XAUI XGXS core status register 3058 */ 3059#define FR_AB_XX_CORE_STAT_REG_OFST 0x00001360 3060/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3061 3062#define FRF_AB_XX_FORCE_SIG3_LBN 31 3063#define FRF_AB_XX_FORCE_SIG3_WIDTH 1 3064#define FRF_AB_XX_FORCE_SIG3_VAL_LBN 30 3065#define FRF_AB_XX_FORCE_SIG3_VAL_WIDTH 1 3066#define FRF_AB_XX_FORCE_SIG2_LBN 29 3067#define FRF_AB_XX_FORCE_SIG2_WIDTH 1 3068#define FRF_AB_XX_FORCE_SIG2_VAL_LBN 28 3069#define FRF_AB_XX_FORCE_SIG2_VAL_WIDTH 1 3070#define FRF_AB_XX_FORCE_SIG1_LBN 27 3071#define FRF_AB_XX_FORCE_SIG1_WIDTH 1 3072#define FRF_AB_XX_FORCE_SIG1_VAL_LBN 26 3073#define FRF_AB_XX_FORCE_SIG1_VAL_WIDTH 1 3074#define FRF_AB_XX_FORCE_SIG0_LBN 25 3075#define FRF_AB_XX_FORCE_SIG0_WIDTH 1 3076#define FRF_AB_XX_FORCE_SIG0_VAL_LBN 24 3077#define FRF_AB_XX_FORCE_SIG0_VAL_WIDTH 1 3078#define FRF_AB_XX_XGXS_LB_EN_LBN 23 3079#define FRF_AB_XX_XGXS_LB_EN_WIDTH 1 3080#define FRF_AB_XX_XGMII_LB_EN_LBN 22 3081#define FRF_AB_XX_XGMII_LB_EN_WIDTH 1 3082#define FRF_AB_XX_MATCH_FAULT_LBN 21 3083#define FRF_AB_XX_MATCH_FAULT_WIDTH 1 3084#define FRF_AB_XX_ALIGN_DONE_LBN 20 3085#define FRF_AB_XX_ALIGN_DONE_WIDTH 1 3086#define FRF_AB_XX_SYNC_STAT3_LBN 19 3087#define FRF_AB_XX_SYNC_STAT3_WIDTH 1 3088#define FRF_AB_XX_SYNC_STAT2_LBN 18 3089#define FRF_AB_XX_SYNC_STAT2_WIDTH 1 3090#define FRF_AB_XX_SYNC_STAT1_LBN 17 3091#define FRF_AB_XX_SYNC_STAT1_WIDTH 1 3092#define FRF_AB_XX_SYNC_STAT0_LBN 16 3093#define FRF_AB_XX_SYNC_STAT0_WIDTH 1 3094#define FRF_AB_XX_COMMA_DET_CH3_LBN 15 3095#define FRF_AB_XX_COMMA_DET_CH3_WIDTH 1 3096#define FRF_AB_XX_COMMA_DET_CH2_LBN 14 3097#define FRF_AB_XX_COMMA_DET_CH2_WIDTH 1 3098#define FRF_AB_XX_COMMA_DET_CH1_LBN 13 3099#define FRF_AB_XX_COMMA_DET_CH1_WIDTH 1 3100#define FRF_AB_XX_COMMA_DET_CH0_LBN 12 3101#define FRF_AB_XX_COMMA_DET_CH0_WIDTH 1 3102#define FRF_AB_XX_CGRP_ALIGN_CH3_LBN 11 3103#define FRF_AB_XX_CGRP_ALIGN_CH3_WIDTH 1 3104#define FRF_AB_XX_CGRP_ALIGN_CH2_LBN 10 3105#define FRF_AB_XX_CGRP_ALIGN_CH2_WIDTH 1 3106#define FRF_AB_XX_CGRP_ALIGN_CH1_LBN 9 3107#define FRF_AB_XX_CGRP_ALIGN_CH1_WIDTH 1 3108#define FRF_AB_XX_CGRP_ALIGN_CH0_LBN 8 3109#define FRF_AB_XX_CGRP_ALIGN_CH0_WIDTH 1 3110#define FRF_AB_XX_CHAR_ERR_CH3_LBN 7 3111#define FRF_AB_XX_CHAR_ERR_CH3_WIDTH 1 3112#define FRF_AB_XX_CHAR_ERR_CH2_LBN 6 3113#define FRF_AB_XX_CHAR_ERR_CH2_WIDTH 1 3114#define FRF_AB_XX_CHAR_ERR_CH1_LBN 5 3115#define FRF_AB_XX_CHAR_ERR_CH1_WIDTH 1 3116#define FRF_AB_XX_CHAR_ERR_CH0_LBN 4 3117#define FRF_AB_XX_CHAR_ERR_CH0_WIDTH 1 3118#define FRF_AB_XX_DISPERR_CH3_LBN 3 3119#define FRF_AB_XX_DISPERR_CH3_WIDTH 1 3120#define FRF_AB_XX_DISPERR_CH2_LBN 2 3121#define FRF_AB_XX_DISPERR_CH2_WIDTH 1 3122#define FRF_AB_XX_DISPERR_CH1_LBN 1 3123#define FRF_AB_XX_DISPERR_CH1_WIDTH 1 3124#define FRF_AB_XX_DISPERR_CH0_LBN 0 3125#define FRF_AB_XX_DISPERR_CH0_WIDTH 1 3126 3127 3128/* 3129 * FR_AA_RX_DESC_PTR_TBL_KER(128bit): 3130 * Receive descriptor pointer table 3131 */ 3132#define FR_AA_RX_DESC_PTR_TBL_KER_OFST 0x00011800 3133/* falcona0=net_func_bar2 */ 3134#define FR_AA_RX_DESC_PTR_TBL_KER_STEP 16 3135#define FR_AA_RX_DESC_PTR_TBL_KER_ROWS 4 3136/* 3137 * FR_AZ_RX_DESC_PTR_TBL(128bit): 3138 * Receive descriptor pointer table 3139 */ 3140#define FR_AZ_RX_DESC_PTR_TBL_OFST 0x00f40000 3141/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3142#define FR_AZ_RX_DESC_PTR_TBL_STEP 16 3143#define FR_CZ_RX_DESC_PTR_TBL_ROWS 1024 3144#define FR_AB_RX_DESC_PTR_TBL_ROWS 4096 3145 3146#define FRF_CZ_RX_HDR_SPLIT_LBN 90 3147#define FRF_CZ_RX_HDR_SPLIT_WIDTH 1 3148#define FRF_AZ_RX_RESET_LBN 89 3149#define FRF_AZ_RX_RESET_WIDTH 1 3150#define FRF_AZ_RX_ISCSI_DDIG_EN_LBN 88 3151#define FRF_AZ_RX_ISCSI_DDIG_EN_WIDTH 1 3152#define FRF_AZ_RX_ISCSI_HDIG_EN_LBN 87 3153#define FRF_AZ_RX_ISCSI_HDIG_EN_WIDTH 1 3154#define FRF_AZ_RX_DESC_PREF_ACT_LBN 86 3155#define FRF_AZ_RX_DESC_PREF_ACT_WIDTH 1 3156#define FRF_AZ_RX_DC_HW_RPTR_LBN 80 3157#define FRF_AZ_RX_DC_HW_RPTR_WIDTH 6 3158#define FRF_AZ_RX_DESCQ_HW_RPTR_LBN 68 3159#define FRF_AZ_RX_DESCQ_HW_RPTR_WIDTH 12 3160#define FRF_AZ_RX_DESCQ_SW_WPTR_LBN 56 3161#define FRF_AZ_RX_DESCQ_SW_WPTR_WIDTH 12 3162#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_LBN 36 3163#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_WIDTH 20 3164#define FRF_AZ_RX_DESCQ_EVQ_ID_LBN 24 3165#define FRF_AZ_RX_DESCQ_EVQ_ID_WIDTH 12 3166#define FRF_AZ_RX_DESCQ_OWNER_ID_LBN 10 3167#define FRF_AZ_RX_DESCQ_OWNER_ID_WIDTH 14 3168#define FRF_AZ_RX_DESCQ_LABEL_LBN 5 3169#define FRF_AZ_RX_DESCQ_LABEL_WIDTH 5 3170#define FRF_AZ_RX_DESCQ_SIZE_LBN 3 3171#define FRF_AZ_RX_DESCQ_SIZE_WIDTH 2 3172#define FFE_AZ_RX_DESCQ_SIZE_4K 3 3173#define FFE_AZ_RX_DESCQ_SIZE_2K 2 3174#define FFE_AZ_RX_DESCQ_SIZE_1K 1 3175#define FFE_AZ_RX_DESCQ_SIZE_512 0 3176#define FRF_AZ_RX_DESCQ_TYPE_LBN 2 3177#define FRF_AZ_RX_DESCQ_TYPE_WIDTH 1 3178#define FRF_AZ_RX_DESCQ_JUMBO_LBN 1 3179#define FRF_AZ_RX_DESCQ_JUMBO_WIDTH 1 3180#define FRF_AZ_RX_DESCQ_EN_LBN 0 3181#define FRF_AZ_RX_DESCQ_EN_WIDTH 1 3182 3183 3184/* 3185 * FR_AA_TX_DESC_PTR_TBL_KER(128bit): 3186 * Transmit descriptor pointer 3187 */ 3188#define FR_AA_TX_DESC_PTR_TBL_KER_OFST 0x00011900 3189/* falcona0=net_func_bar2 */ 3190#define FR_AA_TX_DESC_PTR_TBL_KER_STEP 16 3191#define FR_AA_TX_DESC_PTR_TBL_KER_ROWS 8 3192/* 3193 * FR_AZ_TX_DESC_PTR_TBL(128bit): 3194 * Transmit descriptor pointer 3195 */ 3196#define FR_AZ_TX_DESC_PTR_TBL_OFST 0x00f50000 3197/* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 3198#define FR_AZ_TX_DESC_PTR_TBL_STEP 16 3199#define FR_AB_TX_DESC_PTR_TBL_ROWS 4096 3200#define FR_CZ_TX_DESC_PTR_TBL_ROWS 1024 3201 3202#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_LBN 94 3203#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_WIDTH 2 3204#define FRF_CZ_TX_DPT_ETH_FILT_EN_LBN 93 3205#define FRF_CZ_TX_DPT_ETH_FILT_EN_WIDTH 1 3206#define FRF_CZ_TX_DPT_IP_FILT_EN_LBN 92 3207#define FRF_CZ_TX_DPT_IP_FILT_EN_WIDTH 1 3208#define FRF_BZ_TX_NON_IP_DROP_DIS_LBN 91 3209#define FRF_BZ_TX_NON_IP_DROP_DIS_WIDTH 1 3210#define FRF_BZ_TX_IP_CHKSM_DIS_LBN 90 3211#define FRF_BZ_TX_IP_CHKSM_DIS_WIDTH 1 3212#define FRF_BZ_TX_TCP_CHKSM_DIS_LBN 89 3213#define FRF_BZ_TX_TCP_CHKSM_DIS_WIDTH 1 3214#define FRF_AZ_TX_DESCQ_EN_LBN 88 3215#define FRF_AZ_TX_DESCQ_EN_WIDTH 1 3216#define FRF_AZ_TX_ISCSI_DDIG_EN_LBN 87 3217#define FRF_AZ_TX_ISCSI_DDIG_EN_WIDTH 1 3218#define FRF_AZ_TX_ISCSI_HDIG_EN_LBN 86 3219#define FRF_AZ_TX_ISCSI_HDIG_EN_WIDTH 1 3220#define FRF_AZ_TX_DC_HW_RPTR_LBN 80 3221#define FRF_AZ_TX_DC_HW_RPTR_WIDTH 6 3222#define FRF_AZ_TX_DESCQ_HW_RPTR_LBN 68 3223#define FRF_AZ_TX_DESCQ_HW_RPTR_WIDTH 12 3224#define FRF_AZ_TX_DESCQ_SW_WPTR_LBN 56 3225#define FRF_AZ_TX_DESCQ_SW_WPTR_WIDTH 12 3226#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_LBN 36 3227#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_WIDTH 20 3228#define FRF_AZ_TX_DESCQ_EVQ_ID_LBN 24 3229#define FRF_AZ_TX_DESCQ_EVQ_ID_WIDTH 12 3230#define FRF_AZ_TX_DESCQ_OWNER_ID_LBN 10 3231#define FRF_AZ_TX_DESCQ_OWNER_ID_WIDTH 14 3232#define FRF_AZ_TX_DESCQ_LABEL_LBN 5 3233#define FRF_AZ_TX_DESCQ_LABEL_WIDTH 5 3234#define FRF_AZ_TX_DESCQ_SIZE_LBN 3 3235#define FRF_AZ_TX_DESCQ_SIZE_WIDTH 2 3236#define FFE_AZ_TX_DESCQ_SIZE_4K 3 3237#define FFE_AZ_TX_DESCQ_SIZE_2K 2 3238#define FFE_AZ_TX_DESCQ_SIZE_1K 1 3239#define FFE_AZ_TX_DESCQ_SIZE_512 0 3240#define FRF_AZ_TX_DESCQ_TYPE_LBN 1 3241#define FRF_AZ_TX_DESCQ_TYPE_WIDTH 2 3242#define FRF_AZ_TX_DESCQ_FLUSH_LBN 0 3243#define FRF_AZ_TX_DESCQ_FLUSH_WIDTH 1 3244 3245 3246/* 3247 * FR_AA_EVQ_PTR_TBL_KER(128bit): 3248 * Event queue pointer table 3249 */ 3250#define FR_AA_EVQ_PTR_TBL_KER_OFST 0x00011a00 3251/* falcona0=net_func_bar2 */ 3252#define FR_AA_EVQ_PTR_TBL_KER_STEP 16 3253#define FR_AA_EVQ_PTR_TBL_KER_ROWS 4 3254/* 3255 * FR_AZ_EVQ_PTR_TBL(128bit): 3256 * Event queue pointer table 3257 */ 3258#define FR_AZ_EVQ_PTR_TBL_OFST 0x00f60000 3259/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3260#define FR_AZ_EVQ_PTR_TBL_STEP 16 3261#define FR_CZ_EVQ_PTR_TBL_ROWS 1024 3262#define FR_AB_EVQ_PTR_TBL_ROWS 4096 3263 3264#define FRF_BZ_EVQ_RPTR_IGN_LBN 40 3265#define FRF_BZ_EVQ_RPTR_IGN_WIDTH 1 3266#define FRF_AZ_EVQ_WKUP_OR_INT_EN_LBN 39 3267#define FRF_AZ_EVQ_WKUP_OR_INT_EN_WIDTH 1 3268#define FRF_AZ_EVQ_NXT_WPTR_LBN 24 3269#define FRF_AZ_EVQ_NXT_WPTR_WIDTH 15 3270#define FRF_AZ_EVQ_EN_LBN 23 3271#define FRF_AZ_EVQ_EN_WIDTH 1 3272#define FRF_AZ_EVQ_SIZE_LBN 20 3273#define FRF_AZ_EVQ_SIZE_WIDTH 3 3274#define FFE_AZ_EVQ_SIZE_32K 6 3275#define FFE_AZ_EVQ_SIZE_16K 5 3276#define FFE_AZ_EVQ_SIZE_8K 4 3277#define FFE_AZ_EVQ_SIZE_4K 3 3278#define FFE_AZ_EVQ_SIZE_2K 2 3279#define FFE_AZ_EVQ_SIZE_1K 1 3280#define FFE_AZ_EVQ_SIZE_512 0 3281#define FRF_AZ_EVQ_BUF_BASE_ID_LBN 0 3282#define FRF_AZ_EVQ_BUF_BASE_ID_WIDTH 20 3283 3284 3285/* 3286 * FR_AA_BUF_HALF_TBL_KER(64bit): 3287 * Buffer table in half buffer table mode direct access by driver 3288 */ 3289#define FR_AA_BUF_HALF_TBL_KER_OFST 0x00018000 3290/* falcona0=net_func_bar2 */ 3291#define FR_AA_BUF_HALF_TBL_KER_STEP 8 3292#define FR_AA_BUF_HALF_TBL_KER_ROWS 4096 3293/* 3294 * FR_AZ_BUF_HALF_TBL(64bit): 3295 * Buffer table in half buffer table mode direct access by driver 3296 */ 3297#define FR_AZ_BUF_HALF_TBL_OFST 0x00800000 3298/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3299#define FR_AZ_BUF_HALF_TBL_STEP 8 3300#define FR_CZ_BUF_HALF_TBL_ROWS 147456 3301#define FR_AB_BUF_HALF_TBL_ROWS 524288 3302 3303#define FRF_AZ_BUF_ADR_HBUF_ODD_LBN 44 3304#define FRF_AZ_BUF_ADR_HBUF_ODD_WIDTH 20 3305#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN 32 3306#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_WIDTH 12 3307#define FRF_AZ_BUF_ADR_HBUF_EVEN_LBN 12 3308#define FRF_AZ_BUF_ADR_HBUF_EVEN_WIDTH 20 3309#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN 0 3310#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH 12 3311 3312 3313/* 3314 * FR_AA_BUF_FULL_TBL_KER(64bit): 3315 * Buffer table in full buffer table mode direct access by driver 3316 */ 3317#define FR_AA_BUF_FULL_TBL_KER_OFST 0x00018000 3318/* falcona0=net_func_bar2 */ 3319#define FR_AA_BUF_FULL_TBL_KER_STEP 8 3320#define FR_AA_BUF_FULL_TBL_KER_ROWS 4096 3321/* 3322 * FR_AZ_BUF_FULL_TBL(64bit): 3323 * Buffer table in full buffer table mode direct access by driver 3324 */ 3325#define FR_AZ_BUF_FULL_TBL_OFST 0x00800000 3326/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3327#define FR_AZ_BUF_FULL_TBL_STEP 8 3328 3329#define FR_CZ_BUF_FULL_TBL_ROWS 147456 3330#define FR_AB_BUF_FULL_TBL_ROWS 917504 3331 3332#define FRF_AZ_BUF_FULL_UNUSED_LBN 51 3333#define FRF_AZ_BUF_FULL_UNUSED_WIDTH 13 3334#define FRF_AZ_IP_DAT_BUF_SIZE_LBN 50 3335#define FRF_AZ_IP_DAT_BUF_SIZE_WIDTH 1 3336#define FRF_AZ_BUF_ADR_REGION_LBN 48 3337#define FRF_AZ_BUF_ADR_REGION_WIDTH 2 3338#define FFE_AZ_BUF_ADR_REGN3 3 3339#define FFE_AZ_BUF_ADR_REGN2 2 3340#define FFE_AZ_BUF_ADR_REGN1 1 3341#define FFE_AZ_BUF_ADR_REGN0 0 3342#define FRF_AZ_BUF_ADR_FBUF_LBN 14 3343#define FRF_AZ_BUF_ADR_FBUF_WIDTH 34 3344#define FRF_AZ_BUF_ADR_FBUF_DW0_LBN 14 3345#define FRF_AZ_BUF_ADR_FBUF_DW0_WIDTH 32 3346#define FRF_AZ_BUF_ADR_FBUF_DW1_LBN 46 3347#define FRF_AZ_BUF_ADR_FBUF_DW1_WIDTH 2 3348#define FRF_AZ_BUF_OWNER_ID_FBUF_LBN 0 3349#define FRF_AZ_BUF_OWNER_ID_FBUF_WIDTH 14 3350 3351 3352/* 3353 * FR_AZ_RX_FILTER_TBL0(128bit): 3354 * TCP/IPv4 Receive filter table 3355 */ 3356#define FR_AZ_RX_FILTER_TBL0_OFST 0x00f00000 3357/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 3358#define FR_AZ_RX_FILTER_TBL0_STEP 32 3359#define FR_AZ_RX_FILTER_TBL0_ROWS 8192 3360/* 3361 * FR_AB_RX_FILTER_TBL1(128bit): 3362 * TCP/IPv4 Receive filter table 3363 */ 3364#define FR_AB_RX_FILTER_TBL1_OFST 0x00f00010 3365/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3366#define FR_AB_RX_FILTER_TBL1_STEP 32 3367#define FR_AB_RX_FILTER_TBL1_ROWS 8192 3368 3369#define FRF_BZ_RSS_EN_LBN 110 3370#define FRF_BZ_RSS_EN_WIDTH 1 3371#define FRF_BZ_SCATTER_EN_LBN 109 3372#define FRF_BZ_SCATTER_EN_WIDTH 1 3373#define FRF_AZ_TCP_UDP_LBN 108 3374#define FRF_AZ_TCP_UDP_WIDTH 1 3375#define FRF_AZ_RXQ_ID_LBN 96 3376#define FRF_AZ_RXQ_ID_WIDTH 12 3377#define FRF_AZ_DEST_IP_LBN 64 3378#define FRF_AZ_DEST_IP_WIDTH 32 3379#define FRF_AZ_DEST_PORT_TCP_LBN 48 3380#define FRF_AZ_DEST_PORT_TCP_WIDTH 16 3381#define FRF_AZ_SRC_IP_LBN 16 3382#define FRF_AZ_SRC_IP_WIDTH 32 3383#define FRF_AZ_SRC_TCP_DEST_UDP_LBN 0 3384#define FRF_AZ_SRC_TCP_DEST_UDP_WIDTH 16 3385 3386 3387/* 3388 * FR_CZ_RX_MAC_FILTER_TBL0(128bit): 3389 * Receive Ethernet filter table 3390 */ 3391#define FR_CZ_RX_MAC_FILTER_TBL0_OFST 0x00f00010 3392/* sienaa0=net_func_bar2 */ 3393#define FR_CZ_RX_MAC_FILTER_TBL0_STEP 32 3394#define FR_CZ_RX_MAC_FILTER_TBL0_ROWS 512 3395 3396#define FRF_CZ_RMFT_RSS_EN_LBN 75 3397#define FRF_CZ_RMFT_RSS_EN_WIDTH 1 3398#define FRF_CZ_RMFT_SCATTER_EN_LBN 74 3399#define FRF_CZ_RMFT_SCATTER_EN_WIDTH 1 3400#define FRF_CZ_RMFT_IP_OVERRIDE_LBN 73 3401#define FRF_CZ_RMFT_IP_OVERRIDE_WIDTH 1 3402#define FRF_CZ_RMFT_RXQ_ID_LBN 61 3403#define FRF_CZ_RMFT_RXQ_ID_WIDTH 12 3404#define FRF_CZ_RMFT_WILDCARD_MATCH_LBN 60 3405#define FRF_CZ_RMFT_WILDCARD_MATCH_WIDTH 1 3406#define FRF_CZ_RMFT_DEST_MAC_LBN 12 3407#define FRF_CZ_RMFT_DEST_MAC_WIDTH 48 3408#define FRF_CZ_RMFT_DEST_MAC_DW0_LBN 12 3409#define FRF_CZ_RMFT_DEST_MAC_DW0_WIDTH 32 3410#define FRF_CZ_RMFT_DEST_MAC_DW1_LBN 44 3411#define FRF_CZ_RMFT_DEST_MAC_DW1_WIDTH 16 3412#define FRF_CZ_RMFT_VLAN_ID_LBN 0 3413#define FRF_CZ_RMFT_VLAN_ID_WIDTH 12 3414 3415 3416/* 3417 * FR_AZ_TIMER_TBL(128bit): 3418 * Timer table 3419 */ 3420#define FR_AZ_TIMER_TBL_OFST 0x00f70000 3421/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3422#define FR_AZ_TIMER_TBL_STEP 16 3423#define FR_CZ_TIMER_TBL_ROWS 1024 3424#define FR_AB_TIMER_TBL_ROWS 4096 3425 3426#define FRF_CZ_TIMER_Q_EN_LBN 33 3427#define FRF_CZ_TIMER_Q_EN_WIDTH 1 3428#define FRF_CZ_INT_ARMD_LBN 32 3429#define FRF_CZ_INT_ARMD_WIDTH 1 3430#define FRF_CZ_INT_PEND_LBN 31 3431#define FRF_CZ_INT_PEND_WIDTH 1 3432#define FRF_CZ_HOST_NOTIFY_MODE_LBN 30 3433#define FRF_CZ_HOST_NOTIFY_MODE_WIDTH 1 3434#define FRF_CZ_RELOAD_TIMER_VAL_LBN 16 3435#define FRF_CZ_RELOAD_TIMER_VAL_WIDTH 14 3436#define FRF_CZ_TIMER_MODE_LBN 14 3437#define FRF_CZ_TIMER_MODE_WIDTH 2 3438#define FFE_CZ_TIMER_MODE_INT_HLDOFF 3 3439#define FFE_CZ_TIMER_MODE_TRIG_START 2 3440#define FFE_CZ_TIMER_MODE_IMMED_START 1 3441#define FFE_CZ_TIMER_MODE_DIS 0 3442#define FRF_AB_TIMER_MODE_LBN 12 3443#define FRF_AB_TIMER_MODE_WIDTH 2 3444#define FFE_AB_TIMER_MODE_INT_HLDOFF 2 3445#define FFE_AB_TIMER_MODE_TRIG_START 2 3446#define FFE_AB_TIMER_MODE_IMMED_START 1 3447#define FFE_AB_TIMER_MODE_DIS 0 3448#define FRF_CZ_TIMER_VAL_LBN 0 3449#define FRF_CZ_TIMER_VAL_WIDTH 14 3450#define FRF_AB_TIMER_VAL_LBN 0 3451#define FRF_AB_TIMER_VAL_WIDTH 12 3452 3453 3454/* 3455 * FR_BZ_TX_PACE_TBL(128bit): 3456 * Transmit pacing table 3457 */ 3458#define FR_BZ_TX_PACE_TBL_OFST 0x00f80000 3459/* sienaa0=net_func_bar2,falconb0=net_func_bar2 */ 3460#define FR_AZ_TX_PACE_TBL_STEP 16 3461#define FR_CZ_TX_PACE_TBL_ROWS 1024 3462#define FR_BB_TX_PACE_TBL_ROWS 4096 3463/* 3464 * FR_AA_TX_PACE_TBL(128bit): 3465 * Transmit pacing table 3466 */ 3467#define FR_AA_TX_PACE_TBL_OFST 0x00f80040 3468/* falcona0=char_func_bar0 */ 3469/* FR_AZ_TX_PACE_TBL_STEP 16 */ 3470#define FR_AA_TX_PACE_TBL_ROWS 4092 3471 3472#define FRF_AZ_TX_PACE_LBN 0 3473#define FRF_AZ_TX_PACE_WIDTH 5 3474 3475 3476/* 3477 * FR_BZ_RX_INDIRECTION_TBL(7bit): 3478 * RX Indirection Table 3479 */ 3480#define FR_BZ_RX_INDIRECTION_TBL_OFST 0x00fb0000 3481/* falconb0,sienaa0=net_func_bar2 */ 3482#define FR_BZ_RX_INDIRECTION_TBL_STEP 16 3483#define FR_BZ_RX_INDIRECTION_TBL_ROWS 128 3484 3485#define FRF_BZ_IT_QUEUE_LBN 0 3486#define FRF_BZ_IT_QUEUE_WIDTH 6 3487 3488 3489/* 3490 * FR_CZ_TX_FILTER_TBL0(128bit): 3491 * TCP/IPv4 Transmit filter table 3492 */ 3493#define FR_CZ_TX_FILTER_TBL0_OFST 0x00fc0000 3494/* sienaa0=net_func_bar2 */ 3495#define FR_CZ_TX_FILTER_TBL0_STEP 16 3496#define FR_CZ_TX_FILTER_TBL0_ROWS 8192 3497 3498#define FRF_CZ_TIFT_TCP_UDP_LBN 108 3499#define FRF_CZ_TIFT_TCP_UDP_WIDTH 1 3500#define FRF_CZ_TIFT_TXQ_ID_LBN 96 3501#define FRF_CZ_TIFT_TXQ_ID_WIDTH 12 3502#define FRF_CZ_TIFT_DEST_IP_LBN 64 3503#define FRF_CZ_TIFT_DEST_IP_WIDTH 32 3504#define FRF_CZ_TIFT_DEST_PORT_TCP_LBN 48 3505#define FRF_CZ_TIFT_DEST_PORT_TCP_WIDTH 16 3506#define FRF_CZ_TIFT_SRC_IP_LBN 16 3507#define FRF_CZ_TIFT_SRC_IP_WIDTH 32 3508#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_LBN 0 3509#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_WIDTH 16 3510 3511 3512/* 3513 * FR_CZ_TX_MAC_FILTER_TBL0(128bit): 3514 * Transmit Ethernet filter table 3515 */ 3516#define FR_CZ_TX_MAC_FILTER_TBL0_OFST 0x00fe0000 3517/* sienaa0=net_func_bar2 */ 3518#define FR_CZ_TX_MAC_FILTER_TBL0_STEP 16 3519#define FR_CZ_TX_MAC_FILTER_TBL0_ROWS 512 3520 3521#define FRF_CZ_TMFT_TXQ_ID_LBN 61 3522#define FRF_CZ_TMFT_TXQ_ID_WIDTH 12 3523#define FRF_CZ_TMFT_WILDCARD_MATCH_LBN 60 3524#define FRF_CZ_TMFT_WILDCARD_MATCH_WIDTH 1 3525#define FRF_CZ_TMFT_SRC_MAC_LBN 12 3526#define FRF_CZ_TMFT_SRC_MAC_WIDTH 48 3527#define FRF_CZ_TMFT_SRC_MAC_DW0_LBN 12 3528#define FRF_CZ_TMFT_SRC_MAC_DW0_WIDTH 32 3529#define FRF_CZ_TMFT_SRC_MAC_DW1_LBN 44 3530#define FRF_CZ_TMFT_SRC_MAC_DW1_WIDTH 16 3531#define FRF_CZ_TMFT_VLAN_ID_LBN 0 3532#define FRF_CZ_TMFT_VLAN_ID_WIDTH 12 3533 3534 3535/* 3536 * FR_CZ_MC_TREG_SMEM(32bit): 3537 * MC Shared Memory 3538 */ 3539#define FR_CZ_MC_TREG_SMEM_OFST 0x00ff0000 3540/* sienaa0=net_func_bar2 */ 3541#define FR_CZ_MC_TREG_SMEM_STEP 4 3542#define FR_CZ_MC_TREG_SMEM_ROWS 512 3543 3544#define FRF_CZ_MC_TREG_SMEM_ROW_LBN 0 3545#define FRF_CZ_MC_TREG_SMEM_ROW_WIDTH 32 3546 3547 3548/* 3549 * FR_BB_MSIX_VECTOR_TABLE(128bit): 3550 * MSIX Vector Table 3551 */ 3552#define FR_BB_MSIX_VECTOR_TABLE_OFST 0x00ff0000 3553/* falconb0=net_func_bar2 */ 3554#define FR_BZ_MSIX_VECTOR_TABLE_STEP 16 3555#define FR_BB_MSIX_VECTOR_TABLE_ROWS 64 3556/* 3557 * FR_CZ_MSIX_VECTOR_TABLE(128bit): 3558 * MSIX Vector Table 3559 */ 3560#define FR_CZ_MSIX_VECTOR_TABLE_OFST 0x00000000 3561/* sienaa0=pci_f0_bar4 */ 3562/* FR_BZ_MSIX_VECTOR_TABLE_STEP 16 */ 3563#define FR_CZ_MSIX_VECTOR_TABLE_ROWS 1024 3564 3565#define FRF_BZ_MSIX_VECTOR_RESERVED_LBN 97 3566#define FRF_BZ_MSIX_VECTOR_RESERVED_WIDTH 31 3567#define FRF_BZ_MSIX_VECTOR_MASK_LBN 96 3568#define FRF_BZ_MSIX_VECTOR_MASK_WIDTH 1 3569#define FRF_BZ_MSIX_MESSAGE_DATA_LBN 64 3570#define FRF_BZ_MSIX_MESSAGE_DATA_WIDTH 32 3571#define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_LBN 32 3572#define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_WIDTH 32 3573#define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_LBN 0 3574#define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_WIDTH 32 3575 3576 3577/* 3578 * FR_BB_MSIX_PBA_TABLE(32bit): 3579 * MSIX Pending Bit Array 3580 */ 3581#define FR_BB_MSIX_PBA_TABLE_OFST 0x00ff2000 3582/* falconb0=net_func_bar2 */ 3583#define FR_BZ_MSIX_PBA_TABLE_STEP 4 3584#define FR_BB_MSIX_PBA_TABLE_ROWS 2 3585/* 3586 * FR_CZ_MSIX_PBA_TABLE(32bit): 3587 * MSIX Pending Bit Array 3588 */ 3589#define FR_CZ_MSIX_PBA_TABLE_OFST 0x00008000 3590/* sienaa0=pci_f0_bar4 */ 3591/* FR_BZ_MSIX_PBA_TABLE_STEP 4 */ 3592#define FR_CZ_MSIX_PBA_TABLE_ROWS 32 3593 3594#define FRF_BZ_MSIX_PBA_PEND_DWORD_LBN 0 3595#define FRF_BZ_MSIX_PBA_PEND_DWORD_WIDTH 32 3596 3597 3598/* 3599 * FR_AZ_SRM_DBG_REG(64bit): 3600 * SRAM debug access 3601 */ 3602#define FR_AZ_SRM_DBG_REG_OFST 0x03000000 3603/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3604#define FR_AZ_SRM_DBG_REG_STEP 8 3605 3606#define FR_CZ_SRM_DBG_REG_ROWS 262144 3607#define FR_AB_SRM_DBG_REG_ROWS 2097152 3608 3609#define FRF_AZ_SRM_DBG_LBN 0 3610#define FRF_AZ_SRM_DBG_WIDTH 64 3611#define FRF_AZ_SRM_DBG_DW0_LBN 0 3612#define FRF_AZ_SRM_DBG_DW0_WIDTH 32 3613#define FRF_AZ_SRM_DBG_DW1_LBN 32 3614#define FRF_AZ_SRM_DBG_DW1_WIDTH 32 3615 3616 3617/* 3618 * FR_AA_INT_ACK_CHAR(32bit): 3619 * CHAR interrupt acknowledge register 3620 */ 3621#define FR_AA_INT_ACK_CHAR_OFST 0x00000060 3622/* falcona0=char_func_bar0 */ 3623 3624#define FRF_AA_INT_ACK_CHAR_FIELD_LBN 0 3625#define FRF_AA_INT_ACK_CHAR_FIELD_WIDTH 32 3626 3627 3628/* FS_DRIVER_EV */ 3629#define FSF_AZ_DRIVER_EV_SUBCODE_LBN 56 3630#define FSF_AZ_DRIVER_EV_SUBCODE_WIDTH 4 3631#define FSE_AZ_TX_DSC_ERROR_EV 15 3632#define FSE_AZ_RX_DSC_ERROR_EV 14 3633#define FSE_AZ_RX_RECOVER_EV 11 3634#define FSE_AZ_TIMER_EV 10 3635#define FSE_AZ_TX_PKT_NON_TCP_UDP 9 3636#define FSE_AZ_WAKE_UP_EV 6 3637#define FSE_AZ_SRM_UPD_DONE_EV 5 3638#define FSE_AZ_EVQ_NOT_EN_EV 3 3639#define FSE_AZ_EVQ_INIT_DONE_EV 2 3640#define FSE_AZ_RX_DESCQ_FLS_DONE_EV 1 3641#define FSE_AZ_TX_DESCQ_FLS_DONE_EV 0 3642#define FSF_AZ_DRIVER_EV_SUBDATA_LBN 0 3643#define FSF_AZ_DRIVER_EV_SUBDATA_WIDTH 14 3644 3645 3646/* FS_EVENT_ENTRY */ 3647#define FSF_AZ_EV_CODE_LBN 60 3648#define FSF_AZ_EV_CODE_WIDTH 4 3649#define FSE_AZ_EV_CODE_USER_EV 8 3650#define FSE_AZ_EV_CODE_DRV_GEN_EV 7 3651#define FSE_AZ_EV_CODE_GLOBAL_EV 6 3652#define FSE_AZ_EV_CODE_DRIVER_EV 5 3653#define FSE_AZ_EV_CODE_TX_EV 2 3654#define FSE_AZ_EV_CODE_RX_EV 0 3655#define FSF_AZ_EV_DATA_LBN 0 3656#define FSF_AZ_EV_DATA_WIDTH 60 3657#define FSF_AZ_EV_DATA_DW0_LBN 0 3658#define FSF_AZ_EV_DATA_DW0_WIDTH 32 3659#define FSF_AZ_EV_DATA_DW1_LBN 32 3660#define FSF_AZ_EV_DATA_DW1_WIDTH 28 3661 3662 3663/* FS_GLOBAL_EV */ 3664#define FSF_AA_GLB_EV_RX_RECOVERY_LBN 12 3665#define FSF_AA_GLB_EV_RX_RECOVERY_WIDTH 1 3666#define FSF_BZ_GLB_EV_XG_MNT_INTR_LBN 11 3667#define FSF_BZ_GLB_EV_XG_MNT_INTR_WIDTH 1 3668#define FSF_AZ_GLB_EV_XFP_PHY0_INTR_LBN 10 3669#define FSF_AZ_GLB_EV_XFP_PHY0_INTR_WIDTH 1 3670#define FSF_AZ_GLB_EV_XG_PHY0_INTR_LBN 9 3671#define FSF_AZ_GLB_EV_XG_PHY0_INTR_WIDTH 1 3672#define FSF_AZ_GLB_EV_G_PHY0_INTR_LBN 7 3673#define FSF_AZ_GLB_EV_G_PHY0_INTR_WIDTH 1 3674 3675 3676/* FS_RX_EV */ 3677#define FSF_CZ_RX_EV_PKT_NOT_PARSED_LBN 58 3678#define FSF_CZ_RX_EV_PKT_NOT_PARSED_WIDTH 1 3679#define FSF_CZ_RX_EV_IPV6_PKT_LBN 57 3680#define FSF_CZ_RX_EV_IPV6_PKT_WIDTH 1 3681#define FSF_AZ_RX_EV_PKT_OK_LBN 56 3682#define FSF_AZ_RX_EV_PKT_OK_WIDTH 1 3683#define FSF_AZ_RX_EV_PAUSE_FRM_ERR_LBN 55 3684#define FSF_AZ_RX_EV_PAUSE_FRM_ERR_WIDTH 1 3685#define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_LBN 54 3686#define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_WIDTH 1 3687#define FSF_AZ_RX_EV_IP_FRAG_ERR_LBN 53 3688#define FSF_AZ_RX_EV_IP_FRAG_ERR_WIDTH 1 3689#define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_LBN 52 3690#define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 1 3691#define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_LBN 51 3692#define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 1 3693#define FSF_AZ_RX_EV_ETH_CRC_ERR_LBN 50 3694#define FSF_AZ_RX_EV_ETH_CRC_ERR_WIDTH 1 3695#define FSF_AZ_RX_EV_FRM_TRUNC_LBN 49 3696#define FSF_AZ_RX_EV_FRM_TRUNC_WIDTH 1 3697#define FSF_AZ_RX_EV_TOBE_DISC_LBN 47 3698#define FSF_AZ_RX_EV_TOBE_DISC_WIDTH 1 3699#define FSF_AZ_RX_EV_PKT_TYPE_LBN 44 3700#define FSF_AZ_RX_EV_PKT_TYPE_WIDTH 3 3701#define FSE_AZ_RX_EV_PKT_TYPE_VLAN_JUMBO 5 3702#define FSE_AZ_RX_EV_PKT_TYPE_VLAN_LLC 4 3703#define FSE_AZ_RX_EV_PKT_TYPE_VLAN 3 3704#define FSE_AZ_RX_EV_PKT_TYPE_JUMBO 2 3705#define FSE_AZ_RX_EV_PKT_TYPE_LLC 1 3706#define FSE_AZ_RX_EV_PKT_TYPE_ETH 0 3707#define FSF_AZ_RX_EV_HDR_TYPE_LBN 42 3708#define FSF_AZ_RX_EV_HDR_TYPE_WIDTH 2 3709#define FSE_AZ_RX_EV_HDR_TYPE_OTHER 3 3710#define FSE_AZ_RX_EV_HDR_TYPE_IPV4_OTHER 2 3711#define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER 2 3712#define FSE_AZ_RX_EV_HDR_TYPE_IPV4_UDP 1 3713#define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP 1 3714#define FSE_AZ_RX_EV_HDR_TYPE_IPV4_TCP 0 3715#define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP 0 3716#define FSF_AZ_RX_EV_DESC_Q_EMPTY_LBN 41 3717#define FSF_AZ_RX_EV_DESC_Q_EMPTY_WIDTH 1 3718#define FSF_AZ_RX_EV_MCAST_HASH_MATCH_LBN 40 3719#define FSF_AZ_RX_EV_MCAST_HASH_MATCH_WIDTH 1 3720#define FSF_AZ_RX_EV_MCAST_PKT_LBN 39 3721#define FSF_AZ_RX_EV_MCAST_PKT_WIDTH 1 3722#define FSF_AA_RX_EV_RECOVERY_FLAG_LBN 37 3723#define FSF_AA_RX_EV_RECOVERY_FLAG_WIDTH 1 3724#define FSF_AZ_RX_EV_Q_LABEL_LBN 32 3725#define FSF_AZ_RX_EV_Q_LABEL_WIDTH 5 3726#define FSF_AZ_RX_EV_JUMBO_CONT_LBN 31 3727#define FSF_AZ_RX_EV_JUMBO_CONT_WIDTH 1 3728#define FSF_AZ_RX_EV_PORT_LBN 30 3729#define FSF_AZ_RX_EV_PORT_WIDTH 1 3730#define FSF_AZ_RX_EV_BYTE_CNT_LBN 16 3731#define FSF_AZ_RX_EV_BYTE_CNT_WIDTH 14 3732#define FSF_AZ_RX_EV_SOP_LBN 15 3733#define FSF_AZ_RX_EV_SOP_WIDTH 1 3734#define FSF_AZ_RX_EV_ISCSI_PKT_OK_LBN 14 3735#define FSF_AZ_RX_EV_ISCSI_PKT_OK_WIDTH 1 3736#define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_LBN 13 3737#define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_WIDTH 1 3738#define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_LBN 12 3739#define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_WIDTH 1 3740#define FSF_AZ_RX_EV_DESC_PTR_LBN 0 3741#define FSF_AZ_RX_EV_DESC_PTR_WIDTH 12 3742 3743 3744/* FS_RX_KER_DESC */ 3745#define FSF_AZ_RX_KER_BUF_SIZE_LBN 48 3746#define FSF_AZ_RX_KER_BUF_SIZE_WIDTH 14 3747#define FSF_AZ_RX_KER_BUF_REGION_LBN 46 3748#define FSF_AZ_RX_KER_BUF_REGION_WIDTH 2 3749#define FSF_AZ_RX_KER_BUF_ADDR_LBN 0 3750#define FSF_AZ_RX_KER_BUF_ADDR_WIDTH 46 3751#define FSF_AZ_RX_KER_BUF_ADDR_DW0_LBN 0 3752#define FSF_AZ_RX_KER_BUF_ADDR_DW0_WIDTH 32 3753#define FSF_AZ_RX_KER_BUF_ADDR_DW1_LBN 32 3754#define FSF_AZ_RX_KER_BUF_ADDR_DW1_WIDTH 14 3755 3756 3757/* FS_RX_USER_DESC */ 3758#define FSF_AZ_RX_USER_2BYTE_OFFSET_LBN 20 3759#define FSF_AZ_RX_USER_2BYTE_OFFSET_WIDTH 12 3760#define FSF_AZ_RX_USER_BUF_ID_LBN 0 3761#define FSF_AZ_RX_USER_BUF_ID_WIDTH 20 3762 3763 3764/* FS_TX_EV */ 3765#define FSF_AZ_TX_EV_PKT_ERR_LBN 38 3766#define FSF_AZ_TX_EV_PKT_ERR_WIDTH 1 3767#define FSF_AZ_TX_EV_PKT_TOO_BIG_LBN 37 3768#define FSF_AZ_TX_EV_PKT_TOO_BIG_WIDTH 1 3769#define FSF_AZ_TX_EV_Q_LABEL_LBN 32 3770#define FSF_AZ_TX_EV_Q_LABEL_WIDTH 5 3771#define FSF_AZ_TX_EV_PORT_LBN 16 3772#define FSF_AZ_TX_EV_PORT_WIDTH 1 3773#define FSF_AZ_TX_EV_WQ_FF_FULL_LBN 15 3774#define FSF_AZ_TX_EV_WQ_FF_FULL_WIDTH 1 3775#define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_LBN 14 3776#define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_WIDTH 1 3777#define FSF_AZ_TX_EV_COMP_LBN 12 3778#define FSF_AZ_TX_EV_COMP_WIDTH 1 3779#define FSF_AZ_TX_EV_DESC_PTR_LBN 0 3780#define FSF_AZ_TX_EV_DESC_PTR_WIDTH 12 3781 3782 3783/* FS_TX_KER_DESC */ 3784#define FSF_AZ_TX_KER_CONT_LBN 62 3785#define FSF_AZ_TX_KER_CONT_WIDTH 1 3786#define FSF_AZ_TX_KER_BYTE_COUNT_LBN 48 3787#define FSF_AZ_TX_KER_BYTE_COUNT_WIDTH 14 3788#define FSF_AZ_TX_KER_BUF_REGION_LBN 46 3789#define FSF_AZ_TX_KER_BUF_REGION_WIDTH 2 3790#define FSF_AZ_TX_KER_BUF_ADDR_LBN 0 3791#define FSF_AZ_TX_KER_BUF_ADDR_WIDTH 46 3792#define FSF_AZ_TX_KER_BUF_ADDR_DW0_LBN 0 3793#define FSF_AZ_TX_KER_BUF_ADDR_DW0_WIDTH 32 3794#define FSF_AZ_TX_KER_BUF_ADDR_DW1_LBN 32 3795#define FSF_AZ_TX_KER_BUF_ADDR_DW1_WIDTH 14 3796 3797 3798/* FS_TX_USER_DESC */ 3799#define FSF_AZ_TX_USER_SW_EV_EN_LBN 48 3800#define FSF_AZ_TX_USER_SW_EV_EN_WIDTH 1 3801#define FSF_AZ_TX_USER_CONT_LBN 46 3802#define FSF_AZ_TX_USER_CONT_WIDTH 1 3803#define FSF_AZ_TX_USER_BYTE_CNT_LBN 33 3804#define FSF_AZ_TX_USER_BYTE_CNT_WIDTH 13 3805#define FSF_AZ_TX_USER_BUF_ID_LBN 13 3806#define FSF_AZ_TX_USER_BUF_ID_WIDTH 20 3807#define FSF_AZ_TX_USER_BYTE_OFS_LBN 0 3808#define FSF_AZ_TX_USER_BYTE_OFS_WIDTH 13 3809 3810 3811/* FS_USER_EV */ 3812#define FSF_CZ_USER_QID_LBN 32 3813#define FSF_CZ_USER_QID_WIDTH 10 3814#define FSF_CZ_USER_EV_REG_VALUE_LBN 0 3815#define FSF_CZ_USER_EV_REG_VALUE_WIDTH 32 3816 3817 3818/* FS_NET_IVEC */ 3819#define FSF_AZ_NET_IVEC_FATAL_INT_LBN 64 3820#define FSF_AZ_NET_IVEC_FATAL_INT_WIDTH 1 3821#define FSF_AZ_NET_IVEC_INT_Q_LBN 40 3822#define FSF_AZ_NET_IVEC_INT_Q_WIDTH 4 3823#define FSF_AZ_NET_IVEC_INT_FLAG_LBN 32 3824#define FSF_AZ_NET_IVEC_INT_FLAG_WIDTH 1 3825#define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_LBN 1 3826#define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_WIDTH 1 3827#define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_LBN 0 3828#define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_WIDTH 1 3829 3830 3831/* DRIVER_EV */ 3832/* Sub-fields of an RX flush completion event */ 3833#define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_LBN 12 3834#define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_WIDTH 1 3835#define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_LBN 0 3836#define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_WIDTH 12 3837 3838 3839#ifdef __cplusplus 3840} 3841#endif 3842 3843 3844 3845 3846#endif /* _SYS_EFX_REGS_H */ 3847