efx_ev.c revision 278839
1227569Sphilip/*- 2227569Sphilip * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. 3227569Sphilip * 4227569Sphilip * Redistribution and use in source and binary forms, with or without 5227569Sphilip * modification, are permitted provided that the following conditions 6227569Sphilip * are met: 7227569Sphilip * 1. Redistributions of source code must retain the above copyright 8227569Sphilip * notice, this list of conditions and the following disclaimer. 9227569Sphilip * 2. Redistributions in binary form must reproduce the above copyright 10227569Sphilip * notice, this list of conditions and the following disclaimer in the 11227569Sphilip * documentation and/or other materials provided with the distribution. 12227569Sphilip * 13227569Sphilip * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 14227569Sphilip * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15227569Sphilip * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16227569Sphilip * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17227569Sphilip * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18227569Sphilip * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19227569Sphilip * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20227569Sphilip * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21227569Sphilip * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22227569Sphilip * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23227569Sphilip * SUCH DAMAGE. 24227569Sphilip */ 25227569Sphilip 26228078Sphilip#include <sys/cdefs.h> 27228078Sphilip__FBSDID("$FreeBSD: head/sys/dev/sfxge/common/efx_ev.c 278839 2015-02-16 06:12:04Z arybchik $"); 28228078Sphilip 29227569Sphilip#include "efsys.h" 30227569Sphilip#include "efx.h" 31227569Sphilip#include "efx_types.h" 32227569Sphilip#include "efx_regs.h" 33227569Sphilip#include "efx_impl.h" 34227569Sphilip 35227569Sphilip#if EFSYS_OPT_QSTATS 36227569Sphilip#define EFX_EV_QSTAT_INCR(_eep, _stat) \ 37227569Sphilip do { \ 38227569Sphilip (_eep)->ee_stat[_stat]++; \ 39227569Sphilip _NOTE(CONSTANTCONDITION) \ 40227569Sphilip } while (B_FALSE) 41227569Sphilip#else 42227569Sphilip#define EFX_EV_QSTAT_INCR(_eep, _stat) 43227569Sphilip#endif 44227569Sphilip 45227569Sphilip __checkReturn int 46227569Sphilipefx_ev_init( 47227569Sphilip __in efx_nic_t *enp) 48227569Sphilip{ 49227569Sphilip efx_oword_t oword; 50227569Sphilip int rc; 51227569Sphilip 52227569Sphilip EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 53227569Sphilip EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 54227569Sphilip 55227569Sphilip if (enp->en_mod_flags & EFX_MOD_EV) { 56227569Sphilip rc = EINVAL; 57227569Sphilip goto fail1; 58227569Sphilip } 59227569Sphilip 60227569Sphilip EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0); 61227569Sphilip 62227569Sphilip /* 63227569Sphilip * Program the event queue for receive and transmit queue 64227569Sphilip * flush events. 65227569Sphilip */ 66227569Sphilip EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword); 67227569Sphilip EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0); 68227569Sphilip EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword); 69227569Sphilip 70227569Sphilip enp->en_mod_flags |= EFX_MOD_EV; 71227569Sphilip return (0); 72227569Sphilip 73227569Sphilipfail1: 74227569Sphilip EFSYS_PROBE1(fail1, int, rc); 75227569Sphilip 76227569Sphilip return (rc); 77227569Sphilip} 78227569Sphilip 79227569Sphilipstatic __checkReturn boolean_t 80227569Sphilipefx_ev_rx_not_ok( 81227569Sphilip __in efx_evq_t *eep, 82227569Sphilip __in efx_qword_t *eqp, 83227569Sphilip __in uint32_t label, 84227569Sphilip __in uint32_t id, 85227569Sphilip __inout uint16_t *flagsp) 86227569Sphilip{ 87227569Sphilip boolean_t ignore = B_FALSE; 88227569Sphilip 89227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) { 90227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC); 91227569Sphilip EFSYS_PROBE(tobe_disc); 92278839Sarybchik /* 93278839Sarybchik * Assume this is a unicast address mismatch, unless below 94227569Sphilip * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or 95227569Sphilip * EV_RX_PAUSE_FRM_ERR is set. 96227569Sphilip */ 97227569Sphilip (*flagsp) |= EFX_ADDR_MISMATCH; 98227569Sphilip } 99227569Sphilip 100227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) { 101227569Sphilip EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id); 102227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC); 103227569Sphilip (*flagsp) |= EFX_DISCARD; 104227569Sphilip 105227569Sphilip#if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER) 106278839Sarybchik /* 107278839Sarybchik * Lookout for payload queue ran dry errors and ignore them. 108227569Sphilip * 109227569Sphilip * Sadly for the header/data split cases, the descriptor 110227569Sphilip * pointer in this event refers to the header queue and 111227569Sphilip * therefore cannot be easily detected as duplicate. 112227569Sphilip * So we drop these and rely on the receive processing seeing 113227569Sphilip * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard 114227569Sphilip * the partially received packet. 115227569Sphilip */ 116227569Sphilip if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) && 117227569Sphilip (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) && 118227569Sphilip (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0)) 119227569Sphilip ignore = B_TRUE; 120227569Sphilip#endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */ 121227569Sphilip } 122227569Sphilip 123227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) { 124227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR); 125227569Sphilip EFSYS_PROBE(crc_err); 126227569Sphilip (*flagsp) &= ~EFX_ADDR_MISMATCH; 127227569Sphilip (*flagsp) |= EFX_DISCARD; 128227569Sphilip } 129227569Sphilip 130227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) { 131227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR); 132227569Sphilip EFSYS_PROBE(pause_frm_err); 133227569Sphilip (*flagsp) &= ~EFX_ADDR_MISMATCH; 134227569Sphilip (*flagsp) |= EFX_DISCARD; 135227569Sphilip } 136227569Sphilip 137227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) { 138227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR); 139227569Sphilip EFSYS_PROBE(owner_id_err); 140227569Sphilip (*flagsp) |= EFX_DISCARD; 141227569Sphilip } 142227569Sphilip 143227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) { 144227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR); 145227569Sphilip EFSYS_PROBE(ipv4_err); 146227569Sphilip (*flagsp) &= ~EFX_CKSUM_IPV4; 147227569Sphilip } 148227569Sphilip 149227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) { 150227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR); 151227569Sphilip EFSYS_PROBE(udp_chk_err); 152227569Sphilip (*flagsp) &= ~EFX_CKSUM_TCPUDP; 153227569Sphilip } 154227569Sphilip 155227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) { 156227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR); 157227569Sphilip 158227569Sphilip /* 159227569Sphilip * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This 160227569Sphilip * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error 161227569Sphilip * condition. 162227569Sphilip */ 163227569Sphilip (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP); 164227569Sphilip } 165227569Sphilip 166227569Sphilip return (ignore); 167227569Sphilip} 168227569Sphilip 169227569Sphilipstatic __checkReturn boolean_t 170227569Sphilipefx_ev_rx( 171227569Sphilip __in efx_evq_t *eep, 172227569Sphilip __in efx_qword_t *eqp, 173227569Sphilip __in const efx_ev_callbacks_t *eecp, 174227569Sphilip __in_opt void *arg) 175227569Sphilip{ 176227569Sphilip efx_nic_t *enp = eep->ee_enp; 177227569Sphilip uint32_t id; 178227569Sphilip uint32_t size; 179227569Sphilip uint32_t label; 180227569Sphilip boolean_t ok; 181227569Sphilip#if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER) 182227569Sphilip boolean_t sop; 183227569Sphilip boolean_t jumbo_cont; 184227569Sphilip#endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */ 185227569Sphilip uint32_t hdr_type; 186227569Sphilip boolean_t is_v6; 187227569Sphilip uint16_t flags; 188227569Sphilip boolean_t ignore; 189227569Sphilip boolean_t should_abort; 190227569Sphilip 191227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX); 192227569Sphilip 193227569Sphilip /* Basic packet information */ 194227569Sphilip id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR); 195227569Sphilip size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT); 196227569Sphilip label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL); 197227569Sphilip ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0); 198227569Sphilip 199227569Sphilip#if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER) 200227569Sphilip sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0); 201227569Sphilip jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0); 202227569Sphilip#endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */ 203227569Sphilip 204227569Sphilip hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE); 205227569Sphilip 206227569Sphilip is_v6 = (enp->en_family != EFX_FAMILY_FALCON && 207227569Sphilip EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0); 208227569Sphilip 209227569Sphilip /* 210227569Sphilip * If packet is marked as OK and packet type is TCP/IP or 211227569Sphilip * UDP/IP or other IP, then we can rely on the hardware checksums. 212227569Sphilip */ 213227569Sphilip switch (hdr_type) { 214227569Sphilip case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP: 215227569Sphilip flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP; 216227569Sphilip if (is_v6) { 217227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6); 218227569Sphilip flags |= EFX_PKT_IPV6; 219227569Sphilip } else { 220227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4); 221227569Sphilip flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 222227569Sphilip } 223227569Sphilip break; 224227569Sphilip 225227569Sphilip case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP: 226227569Sphilip flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP; 227227569Sphilip if (is_v6) { 228227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6); 229227569Sphilip flags |= EFX_PKT_IPV6; 230227569Sphilip } else { 231227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4); 232227569Sphilip flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 233227569Sphilip } 234227569Sphilip break; 235227569Sphilip 236227569Sphilip case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER: 237227569Sphilip if (is_v6) { 238227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6); 239227569Sphilip flags = EFX_PKT_IPV6; 240227569Sphilip } else { 241227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4); 242227569Sphilip flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 243227569Sphilip } 244227569Sphilip break; 245227569Sphilip 246227569Sphilip case FSE_AZ_RX_EV_HDR_TYPE_OTHER: 247227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP); 248227569Sphilip flags = 0; 249227569Sphilip break; 250227569Sphilip 251227569Sphilip default: 252227569Sphilip EFSYS_ASSERT(B_FALSE); 253227569Sphilip flags = 0; 254227569Sphilip break; 255227569Sphilip } 256227569Sphilip 257227569Sphilip#if EFSYS_OPT_RX_SCATTER || EFSYS_OPT_RX_HDR_SPLIT 258227569Sphilip /* Report scatter and header/lookahead split buffer flags */ 259227569Sphilip if (sop) 260227569Sphilip flags |= EFX_PKT_START; 261227569Sphilip if (jumbo_cont) 262227569Sphilip flags |= EFX_PKT_CONT; 263227569Sphilip#endif /* EFSYS_OPT_RX_SCATTER || EFSYS_OPT_RX_HDR_SPLIT */ 264227569Sphilip 265227569Sphilip /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */ 266227569Sphilip if (!ok) { 267227569Sphilip ignore = efx_ev_rx_not_ok(eep, eqp, label, id, &flags); 268227569Sphilip if (ignore) { 269227569Sphilip EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id, 270227569Sphilip uint32_t, size, uint16_t, flags); 271227569Sphilip 272227569Sphilip return (B_FALSE); 273227569Sphilip } 274227569Sphilip } 275227569Sphilip 276227569Sphilip /* If we're not discarding the packet then it is ok */ 277227569Sphilip if (~flags & EFX_DISCARD) 278227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_OK); 279227569Sphilip 280227569Sphilip /* Detect multicast packets that didn't match the filter */ 281227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) { 282227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT); 283227569Sphilip 284227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) { 285227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH); 286227569Sphilip } else { 287227569Sphilip EFSYS_PROBE(mcast_mismatch); 288227569Sphilip flags |= EFX_ADDR_MISMATCH; 289227569Sphilip } 290227569Sphilip } else { 291227569Sphilip flags |= EFX_PKT_UNICAST; 292227569Sphilip } 293227569Sphilip 294227569Sphilip /* 295227569Sphilip * The packet parser in Siena can abort parsing packets under 296227569Sphilip * certain error conditions, setting the PKT_NOT_PARSED bit 297227569Sphilip * (which clears PKT_OK). If this is set, then don't trust 298227569Sphilip * the PKT_TYPE field. 299227569Sphilip */ 300227569Sphilip if (enp->en_family != EFX_FAMILY_FALCON && !ok) { 301227569Sphilip uint32_t parse_err; 302227569Sphilip 303227569Sphilip parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED); 304227569Sphilip if (parse_err != 0) 305227569Sphilip flags |= EFX_CHECK_VLAN; 306227569Sphilip } 307227569Sphilip 308227569Sphilip if (~flags & EFX_CHECK_VLAN) { 309227569Sphilip uint32_t pkt_type; 310227569Sphilip 311227569Sphilip pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE); 312227569Sphilip if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN) 313227569Sphilip flags |= EFX_PKT_VLAN_TAGGED; 314227569Sphilip } 315227569Sphilip 316227569Sphilip EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id, 317227569Sphilip uint32_t, size, uint16_t, flags); 318227569Sphilip 319227569Sphilip EFSYS_ASSERT(eecp->eec_rx != NULL); 320227569Sphilip should_abort = eecp->eec_rx(arg, label, id, size, flags); 321227569Sphilip 322227569Sphilip return (should_abort); 323227569Sphilip} 324227569Sphilip 325227569Sphilipstatic __checkReturn boolean_t 326227569Sphilipefx_ev_tx( 327227569Sphilip __in efx_evq_t *eep, 328227569Sphilip __in efx_qword_t *eqp, 329227569Sphilip __in const efx_ev_callbacks_t *eecp, 330227569Sphilip __in_opt void *arg) 331227569Sphilip{ 332227569Sphilip uint32_t id; 333227569Sphilip uint32_t label; 334227569Sphilip boolean_t should_abort; 335227569Sphilip 336227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_TX); 337227569Sphilip 338227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 && 339227569Sphilip EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 && 340227569Sphilip EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 && 341227569Sphilip EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) { 342227569Sphilip 343227569Sphilip id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR); 344227569Sphilip label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL); 345227569Sphilip 346227569Sphilip EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id); 347227569Sphilip 348227569Sphilip EFSYS_ASSERT(eecp->eec_tx != NULL); 349227569Sphilip should_abort = eecp->eec_tx(arg, label, id); 350227569Sphilip 351227569Sphilip return (should_abort); 352227569Sphilip } 353227569Sphilip 354227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0) 355227569Sphilip EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index, 356227569Sphilip uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1), 357227569Sphilip uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0)); 358227569Sphilip 359227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0) 360227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR); 361227569Sphilip 362227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0) 363227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG); 364227569Sphilip 365227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0) 366227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL); 367227569Sphilip 368227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED); 369227569Sphilip return (B_FALSE); 370227569Sphilip} 371227569Sphilip 372227569Sphilipstatic __checkReturn boolean_t 373227569Sphilipefx_ev_global( 374227569Sphilip __in efx_evq_t *eep, 375227569Sphilip __in efx_qword_t *eqp, 376227569Sphilip __in const efx_ev_callbacks_t *eecp, 377227569Sphilip __in_opt void *arg) 378227569Sphilip{ 379227569Sphilip efx_nic_t *enp = eep->ee_enp; 380227569Sphilip efx_port_t *epp = &(enp->en_port); 381227569Sphilip boolean_t should_abort; 382227569Sphilip 383227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_GLOBAL); 384227569Sphilip should_abort = B_FALSE; 385227569Sphilip 386227569Sphilip /* Check for a link management event */ 387227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_BZ_GLB_EV_XG_MNT_INTR) != 0) { 388227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_GLOBAL_MNT); 389227569Sphilip 390227569Sphilip EFSYS_PROBE(xg_mgt); 391227569Sphilip 392227569Sphilip epp->ep_mac_poll_needed = B_TRUE; 393227569Sphilip } 394227569Sphilip 395227569Sphilip return (should_abort); 396227569Sphilip} 397227569Sphilip 398227569Sphilipstatic __checkReturn boolean_t 399227569Sphilipefx_ev_driver( 400227569Sphilip __in efx_evq_t *eep, 401227569Sphilip __in efx_qword_t *eqp, 402227569Sphilip __in const efx_ev_callbacks_t *eecp, 403227569Sphilip __in_opt void *arg) 404227569Sphilip{ 405227569Sphilip boolean_t should_abort; 406227569Sphilip 407227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_DRIVER); 408227569Sphilip should_abort = B_FALSE; 409227569Sphilip 410227569Sphilip switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) { 411227569Sphilip case FSE_AZ_TX_DESCQ_FLS_DONE_EV: { 412264461Sgnn uint32_t txq_index; 413227569Sphilip 414227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE); 415227569Sphilip 416264461Sgnn txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 417227569Sphilip 418264461Sgnn EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index); 419227569Sphilip 420227569Sphilip EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL); 421264461Sgnn should_abort = eecp->eec_txq_flush_done(arg, txq_index); 422227569Sphilip 423227569Sphilip break; 424227569Sphilip } 425227569Sphilip case FSE_AZ_RX_DESCQ_FLS_DONE_EV: { 426264461Sgnn uint32_t rxq_index; 427227569Sphilip uint32_t failed; 428227569Sphilip 429264461Sgnn rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID); 430227569Sphilip failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL); 431227569Sphilip 432227569Sphilip EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL); 433227569Sphilip EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL); 434227569Sphilip 435227569Sphilip if (failed) { 436227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED); 437227569Sphilip 438264461Sgnn EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index); 439227569Sphilip 440264461Sgnn should_abort = eecp->eec_rxq_flush_failed(arg, rxq_index); 441227569Sphilip } else { 442227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE); 443227569Sphilip 444264461Sgnn EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index); 445227569Sphilip 446264461Sgnn should_abort = eecp->eec_rxq_flush_done(arg, rxq_index); 447227569Sphilip } 448227569Sphilip 449227569Sphilip break; 450227569Sphilip } 451227569Sphilip case FSE_AZ_EVQ_INIT_DONE_EV: 452227569Sphilip EFSYS_ASSERT(eecp->eec_initialized != NULL); 453227569Sphilip should_abort = eecp->eec_initialized(arg); 454227569Sphilip 455227569Sphilip break; 456227569Sphilip 457227569Sphilip case FSE_AZ_EVQ_NOT_EN_EV: 458227569Sphilip EFSYS_PROBE(evq_not_en); 459227569Sphilip break; 460227569Sphilip 461227569Sphilip case FSE_AZ_SRM_UPD_DONE_EV: { 462227569Sphilip uint32_t code; 463227569Sphilip 464227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE); 465227569Sphilip 466227569Sphilip code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 467227569Sphilip 468227569Sphilip EFSYS_ASSERT(eecp->eec_sram != NULL); 469227569Sphilip should_abort = eecp->eec_sram(arg, code); 470227569Sphilip 471227569Sphilip break; 472227569Sphilip } 473227569Sphilip case FSE_AZ_WAKE_UP_EV: { 474227569Sphilip uint32_t id; 475227569Sphilip 476227569Sphilip id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 477227569Sphilip 478227569Sphilip EFSYS_ASSERT(eecp->eec_wake_up != NULL); 479227569Sphilip should_abort = eecp->eec_wake_up(arg, id); 480227569Sphilip 481227569Sphilip break; 482227569Sphilip } 483227569Sphilip case FSE_AZ_TX_PKT_NON_TCP_UDP: 484227569Sphilip EFSYS_PROBE(tx_pkt_non_tcp_udp); 485227569Sphilip break; 486227569Sphilip 487227569Sphilip case FSE_AZ_TIMER_EV: { 488227569Sphilip uint32_t id; 489227569Sphilip 490227569Sphilip id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 491227569Sphilip 492227569Sphilip EFSYS_ASSERT(eecp->eec_timer != NULL); 493227569Sphilip should_abort = eecp->eec_timer(arg, id); 494227569Sphilip 495227569Sphilip break; 496227569Sphilip } 497227569Sphilip case FSE_AZ_RX_DSC_ERROR_EV: 498227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR); 499227569Sphilip 500227569Sphilip EFSYS_PROBE(rx_dsc_error); 501227569Sphilip 502227569Sphilip EFSYS_ASSERT(eecp->eec_exception != NULL); 503227569Sphilip should_abort = eecp->eec_exception(arg, 504227569Sphilip EFX_EXCEPTION_RX_DSC_ERROR, 0); 505227569Sphilip 506227569Sphilip break; 507227569Sphilip 508227569Sphilip case FSE_AZ_TX_DSC_ERROR_EV: 509227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR); 510227569Sphilip 511227569Sphilip EFSYS_PROBE(tx_dsc_error); 512227569Sphilip 513227569Sphilip EFSYS_ASSERT(eecp->eec_exception != NULL); 514227569Sphilip should_abort = eecp->eec_exception(arg, 515227569Sphilip EFX_EXCEPTION_TX_DSC_ERROR, 0); 516227569Sphilip 517227569Sphilip break; 518227569Sphilip 519227569Sphilip default: 520227569Sphilip break; 521227569Sphilip } 522227569Sphilip 523227569Sphilip return (should_abort); 524227569Sphilip} 525227569Sphilip 526227569Sphilipstatic __checkReturn boolean_t 527227569Sphilipefx_ev_drv_gen( 528227569Sphilip __in efx_evq_t *eep, 529227569Sphilip __in efx_qword_t *eqp, 530227569Sphilip __in const efx_ev_callbacks_t *eecp, 531227569Sphilip __in_opt void *arg) 532227569Sphilip{ 533227569Sphilip uint32_t data; 534227569Sphilip boolean_t should_abort; 535227569Sphilip 536227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN); 537227569Sphilip 538227569Sphilip data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0); 539227569Sphilip if (data >= ((uint32_t)1 << 16)) { 540227569Sphilip EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index, 541227569Sphilip uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1), 542227569Sphilip uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0)); 543227569Sphilip return (B_TRUE); 544227569Sphilip } 545227569Sphilip 546227569Sphilip EFSYS_ASSERT(eecp->eec_software != NULL); 547227569Sphilip should_abort = eecp->eec_software(arg, (uint16_t)data); 548227569Sphilip 549227569Sphilip return (should_abort); 550227569Sphilip} 551227569Sphilip 552227569Sphilip#if EFSYS_OPT_MCDI 553227569Sphilip 554227569Sphilipstatic __checkReturn boolean_t 555227569Sphilipefx_ev_mcdi( 556227569Sphilip __in efx_evq_t *eep, 557227569Sphilip __in efx_qword_t *eqp, 558227569Sphilip __in const efx_ev_callbacks_t *eecp, 559227569Sphilip __in_opt void *arg) 560227569Sphilip{ 561227569Sphilip efx_nic_t *enp = eep->ee_enp; 562227569Sphilip unsigned code; 563227569Sphilip boolean_t should_abort = B_FALSE; 564227569Sphilip 565227569Sphilip EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); 566227569Sphilip 567227569Sphilip if (enp->en_family != EFX_FAMILY_SIENA) 568227569Sphilip goto out; 569227569Sphilip 570227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE); 571227569Sphilip 572227569Sphilip code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE); 573227569Sphilip switch (code) { 574227569Sphilip case MCDI_EVENT_CODE_BADSSERT: 575227569Sphilip efx_mcdi_ev_death(enp, EINTR); 576227569Sphilip break; 577227569Sphilip 578227569Sphilip case MCDI_EVENT_CODE_CMDDONE: 579227569Sphilip efx_mcdi_ev_cpl(enp, 580227569Sphilip MCDI_EV_FIELD(*eqp, CMDDONE_SEQ), 581227569Sphilip MCDI_EV_FIELD(*eqp, CMDDONE_DATALEN), 582227569Sphilip MCDI_EV_FIELD(*eqp, CMDDONE_ERRNO)); 583227569Sphilip break; 584227569Sphilip 585227569Sphilip case MCDI_EVENT_CODE_LINKCHANGE: { 586227569Sphilip efx_link_mode_t link_mode; 587227569Sphilip 588227569Sphilip siena_phy_link_ev(enp, eqp, &link_mode); 589227569Sphilip should_abort = eecp->eec_link_change(arg, link_mode); 590227569Sphilip break; 591227569Sphilip } 592227569Sphilip case MCDI_EVENT_CODE_SENSOREVT: { 593227569Sphilip#if EFSYS_OPT_MON_STATS 594227569Sphilip efx_mon_stat_t id; 595227569Sphilip efx_mon_stat_value_t value; 596227569Sphilip int rc; 597227569Sphilip 598227569Sphilip if ((rc = siena_mon_ev(enp, eqp, &id, &value)) == 0) 599227569Sphilip should_abort = eecp->eec_monitor(arg, id, value); 600227569Sphilip else if (rc == ENOTSUP) { 601227569Sphilip should_abort = eecp->eec_exception(arg, 602227569Sphilip EFX_EXCEPTION_UNKNOWN_SENSOREVT, 603227569Sphilip MCDI_EV_FIELD(eqp, DATA)); 604227569Sphilip } else 605227569Sphilip EFSYS_ASSERT(rc == ENODEV); /* Wrong port */ 606227569Sphilip#else 607227569Sphilip should_abort = B_FALSE; 608227569Sphilip#endif 609227569Sphilip break; 610227569Sphilip } 611227569Sphilip case MCDI_EVENT_CODE_SCHEDERR: 612227569Sphilip /* Informational only */ 613227569Sphilip break; 614227569Sphilip 615227569Sphilip case MCDI_EVENT_CODE_REBOOT: 616227569Sphilip efx_mcdi_ev_death(enp, EIO); 617227569Sphilip break; 618227569Sphilip 619227569Sphilip case MCDI_EVENT_CODE_MAC_STATS_DMA: 620227569Sphilip#if EFSYS_OPT_MAC_STATS 621227569Sphilip if (eecp->eec_mac_stats != NULL) { 622227569Sphilip eecp->eec_mac_stats(arg, 623227569Sphilip MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION)); 624227569Sphilip } 625227569Sphilip#endif 626227569Sphilip break; 627227569Sphilip 628227569Sphilip case MCDI_EVENT_CODE_FWALERT: { 629227569Sphilip uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON); 630227569Sphilip 631227569Sphilip if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS) 632227569Sphilip should_abort = eecp->eec_exception(arg, 633227569Sphilip EFX_EXCEPTION_FWALERT_SRAM, 634227569Sphilip MCDI_EV_FIELD(eqp, FWALERT_DATA)); 635227569Sphilip else 636227569Sphilip should_abort = eecp->eec_exception(arg, 637227569Sphilip EFX_EXCEPTION_UNKNOWN_FWALERT, 638227569Sphilip MCDI_EV_FIELD(eqp, DATA)); 639227569Sphilip break; 640227569Sphilip } 641227569Sphilip 642227569Sphilip default: 643227569Sphilip EFSYS_PROBE1(mc_pcol_error, int, code); 644227569Sphilip break; 645227569Sphilip } 646227569Sphilip 647227569Sphilipout: 648227569Sphilip return (should_abort); 649227569Sphilip} 650227569Sphilip 651227569Sphilip#endif /* EFSYS_OPT_SIENA */ 652227569Sphilip 653227569Sphilip __checkReturn int 654227569Sphilipefx_ev_qprime( 655227569Sphilip __in efx_evq_t *eep, 656227569Sphilip __in unsigned int count) 657227569Sphilip{ 658227569Sphilip efx_nic_t *enp = eep->ee_enp; 659227569Sphilip uint32_t rptr; 660227569Sphilip efx_dword_t dword; 661227569Sphilip int rc; 662227569Sphilip 663227569Sphilip EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 664227569Sphilip 665227569Sphilip if (!(enp->en_mod_flags & EFX_MOD_INTR)) { 666227569Sphilip rc = EINVAL; 667227569Sphilip goto fail1; 668227569Sphilip } 669227569Sphilip 670227569Sphilip rptr = count & eep->ee_mask; 671227569Sphilip 672227569Sphilip EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr); 673227569Sphilip 674227569Sphilip EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index, 675227569Sphilip &dword, B_FALSE); 676227569Sphilip 677227569Sphilip return (0); 678227569Sphilip 679227569Sphilipfail1: 680227569Sphilip EFSYS_PROBE1(fail1, int, rc); 681227569Sphilip 682227569Sphilip return (rc); 683227569Sphilip} 684227569Sphilip 685227569Sphilip __checkReturn boolean_t 686227569Sphilipefx_ev_qpending( 687227569Sphilip __in efx_evq_t *eep, 688227569Sphilip __in unsigned int count) 689227569Sphilip{ 690227569Sphilip size_t offset; 691227569Sphilip efx_qword_t qword; 692227569Sphilip 693227569Sphilip EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 694227569Sphilip 695227569Sphilip offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 696227569Sphilip EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword); 697227569Sphilip 698227569Sphilip return (EFX_QWORD_FIELD(qword, EFX_DWORD_0) != 0xffffffff && 699227569Sphilip EFX_QWORD_FIELD(qword, EFX_DWORD_1) != 0xffffffff); 700227569Sphilip} 701227569Sphilip 702227569Sphilip#if EFSYS_OPT_EV_PREFETCH 703227569Sphilip 704227569Sphilip void 705227569Sphilipefx_ev_qprefetch( 706227569Sphilip __in efx_evq_t *eep, 707227569Sphilip __in unsigned int count) 708227569Sphilip{ 709227569Sphilip unsigned int offset; 710227569Sphilip 711227569Sphilip EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 712227569Sphilip 713227569Sphilip offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 714227569Sphilip EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 715227569Sphilip} 716227569Sphilip 717227569Sphilip#endif /* EFSYS_OPT_EV_PREFETCH */ 718227569Sphilip 719227569Sphilip#define EFX_EV_BATCH 8 720227569Sphilip 721227569Sphilip#define EFX_EV_PRESENT(_qword) \ 722227569Sphilip (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \ 723227569Sphilip EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff) 724227569Sphilip 725227569Sphilip void 726227569Sphilipefx_ev_qpoll( 727227569Sphilip __in efx_evq_t *eep, 728227569Sphilip __inout unsigned int *countp, 729227569Sphilip __in const efx_ev_callbacks_t *eecp, 730227569Sphilip __in_opt void *arg) 731227569Sphilip{ 732227569Sphilip efx_qword_t ev[EFX_EV_BATCH]; 733227569Sphilip unsigned int batch; 734227569Sphilip unsigned int total; 735227569Sphilip unsigned int count; 736227569Sphilip unsigned int index; 737227569Sphilip size_t offset; 738227569Sphilip 739227569Sphilip EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 740227569Sphilip EFSYS_ASSERT(countp != NULL); 741227569Sphilip EFSYS_ASSERT(eecp != NULL); 742227569Sphilip 743227569Sphilip count = *countp; 744227569Sphilip do { 745227569Sphilip /* Read up until the end of the batch period */ 746227569Sphilip batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1)); 747227569Sphilip offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 748227569Sphilip for (total = 0; total < batch; ++total) { 749227569Sphilip EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total])); 750227569Sphilip 751227569Sphilip if (!EFX_EV_PRESENT(ev[total])) 752227569Sphilip break; 753227569Sphilip 754227569Sphilip EFSYS_PROBE3(event, unsigned int, eep->ee_index, 755227569Sphilip uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1), 756227569Sphilip uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0)); 757227569Sphilip 758227569Sphilip offset += sizeof (efx_qword_t); 759227569Sphilip } 760227569Sphilip 761227569Sphilip#if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1) 762227569Sphilip /* 763227569Sphilip * Prefetch the next batch when we get within PREFETCH_PERIOD 764227569Sphilip * of a completed batch. If the batch is smaller, then prefetch 765227569Sphilip * immediately. 766227569Sphilip */ 767227569Sphilip if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD) 768227569Sphilip EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 769227569Sphilip#endif /* EFSYS_OPT_EV_PREFETCH */ 770227569Sphilip 771227569Sphilip /* Process the batch of events */ 772227569Sphilip for (index = 0; index < total; ++index) { 773227569Sphilip boolean_t should_abort; 774227569Sphilip uint32_t code; 775227569Sphilip efx_ev_handler_t handler; 776227569Sphilip 777227569Sphilip#if EFSYS_OPT_EV_PREFETCH 778227569Sphilip /* Prefetch if we've now reached the batch period */ 779227569Sphilip if (total == batch && 780227569Sphilip index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) { 781227569Sphilip offset = (count + batch) & eep->ee_mask; 782227569Sphilip offset *= sizeof (efx_qword_t); 783227569Sphilip 784227569Sphilip EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 785227569Sphilip } 786227569Sphilip#endif /* EFSYS_OPT_EV_PREFETCH */ 787227569Sphilip 788227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_ALL); 789227569Sphilip 790227569Sphilip code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE); 791227569Sphilip handler = eep->ee_handler[code]; 792227569Sphilip EFSYS_ASSERT(handler != NULL); 793227569Sphilip should_abort = handler(eep, &(ev[index]), eecp, arg); 794227569Sphilip if (should_abort) { 795227569Sphilip /* Ignore subsequent events */ 796227569Sphilip total = index + 1; 797227569Sphilip break; 798227569Sphilip } 799227569Sphilip } 800227569Sphilip 801227569Sphilip /* 802227569Sphilip * Now that the hardware has most likely moved onto dma'ing 803227569Sphilip * into the next cache line, clear the processed events. Take 804227569Sphilip * care to only clear out events that we've processed 805227569Sphilip */ 806227569Sphilip EFX_SET_QWORD(ev[0]); 807227569Sphilip offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 808227569Sphilip for (index = 0; index < total; ++index) { 809227569Sphilip EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0])); 810227569Sphilip offset += sizeof (efx_qword_t); 811227569Sphilip } 812227569Sphilip 813227569Sphilip count += total; 814227569Sphilip 815227569Sphilip } while (total == batch); 816227569Sphilip 817227569Sphilip *countp = count; 818227569Sphilip} 819227569Sphilip 820227569Sphilip void 821227569Sphilipefx_ev_qpost( 822227569Sphilip __in efx_evq_t *eep, 823227569Sphilip __in uint16_t data) 824227569Sphilip{ 825227569Sphilip efx_nic_t *enp = eep->ee_enp; 826227569Sphilip efx_qword_t ev; 827227569Sphilip efx_oword_t oword; 828227569Sphilip 829227569Sphilip EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 830227569Sphilip 831227569Sphilip EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV, 832227569Sphilip FSF_AZ_EV_DATA_DW0, (uint32_t)data); 833227569Sphilip 834227569Sphilip EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index, 835227569Sphilip EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0), 836227569Sphilip EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1)); 837227569Sphilip 838227569Sphilip EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword); 839227569Sphilip} 840227569Sphilip 841227569Sphilip __checkReturn int 842227569Sphilipefx_ev_qmoderate( 843227569Sphilip __in efx_evq_t *eep, 844227569Sphilip __in unsigned int us) 845227569Sphilip{ 846227569Sphilip efx_nic_t *enp = eep->ee_enp; 847227569Sphilip unsigned int locked; 848227569Sphilip efx_dword_t dword; 849227569Sphilip int rc; 850227569Sphilip 851227569Sphilip EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 852227569Sphilip 853227569Sphilip if (us > enp->en_nic_cfg.enc_evq_moderation_max) { 854227569Sphilip rc = EINVAL; 855227569Sphilip goto fail1; 856227569Sphilip } 857227569Sphilip 858227569Sphilip /* If the value is zero then disable the timer */ 859227569Sphilip if (us == 0) { 860227569Sphilip if (enp->en_family == EFX_FAMILY_FALCON) 861227569Sphilip EFX_POPULATE_DWORD_2(dword, 862227569Sphilip FRF_AB_TC_TIMER_MODE, FFE_AB_TIMER_MODE_DIS, 863227569Sphilip FRF_AB_TC_TIMER_VAL, 0); 864227569Sphilip else 865227569Sphilip EFX_POPULATE_DWORD_2(dword, 866227569Sphilip FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS, 867227569Sphilip FRF_CZ_TC_TIMER_VAL, 0); 868227569Sphilip } else { 869227569Sphilip uint32_t timer_val; 870227569Sphilip 871227569Sphilip /* Calculate the timer value in quanta */ 872227569Sphilip us -= (us % EFX_EV_TIMER_QUANTUM); 873227569Sphilip if (us < EFX_EV_TIMER_QUANTUM) 874227569Sphilip us = EFX_EV_TIMER_QUANTUM; 875227569Sphilip 876227569Sphilip timer_val = us / EFX_EV_TIMER_QUANTUM; 877227569Sphilip 878227569Sphilip /* Moderation value is base 0 so we need to deduct 1 */ 879227569Sphilip if (enp->en_family == EFX_FAMILY_FALCON) 880227569Sphilip EFX_POPULATE_DWORD_2(dword, 881227569Sphilip FRF_AB_TC_TIMER_MODE, FFE_AB_TIMER_MODE_INT_HLDOFF, 882227569Sphilip FRF_AB_TIMER_VAL, timer_val - 1); 883227569Sphilip else 884227569Sphilip EFX_POPULATE_DWORD_2(dword, 885227569Sphilip FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF, 886227569Sphilip FRF_CZ_TC_TIMER_VAL, timer_val - 1); 887227569Sphilip } 888227569Sphilip 889227569Sphilip locked = (eep->ee_index == 0) ? 1 : 0; 890227569Sphilip 891227569Sphilip EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0, 892227569Sphilip eep->ee_index, &dword, locked); 893227569Sphilip 894227569Sphilip return (0); 895227569Sphilip 896227569Sphilipfail1: 897227569Sphilip EFSYS_PROBE1(fail1, int, rc); 898227569Sphilip 899227569Sphilip return (rc); 900227569Sphilip} 901227569Sphilip 902227569Sphilip __checkReturn int 903227569Sphilipefx_ev_qcreate( 904227569Sphilip __in efx_nic_t *enp, 905227569Sphilip __in unsigned int index, 906227569Sphilip __in efsys_mem_t *esmp, 907227569Sphilip __in size_t n, 908227569Sphilip __in uint32_t id, 909227569Sphilip __deref_out efx_evq_t **eepp) 910227569Sphilip{ 911227569Sphilip efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 912227569Sphilip uint32_t size; 913227569Sphilip efx_evq_t *eep; 914227569Sphilip efx_oword_t oword; 915227569Sphilip int rc; 916227569Sphilip 917227569Sphilip EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 918227569Sphilip EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV); 919227569Sphilip 920227569Sphilip EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit); 921227569Sphilip 922227569Sphilip if (!ISP2(n) || !(n & EFX_EVQ_NEVS_MASK)) { 923227569Sphilip rc = EINVAL; 924227569Sphilip goto fail1; 925227569Sphilip } 926227569Sphilip if (index >= encp->enc_evq_limit) { 927227569Sphilip rc = EINVAL; 928227569Sphilip goto fail2; 929227569Sphilip } 930227569Sphilip#if EFSYS_OPT_RX_SCALE 931227569Sphilip if (enp->en_intr.ei_type == EFX_INTR_LINE && 932227569Sphilip index >= EFX_MAXRSS_LEGACY) { 933227569Sphilip rc = EINVAL; 934227569Sphilip goto fail3; 935227569Sphilip } 936227569Sphilip#endif 937227569Sphilip for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS); 938227569Sphilip size++) 939227569Sphilip if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS)) 940227569Sphilip break; 941227569Sphilip if (id + (1 << size) >= encp->enc_buftbl_limit) { 942227569Sphilip rc = EINVAL; 943227569Sphilip goto fail4; 944227569Sphilip } 945227569Sphilip 946227569Sphilip /* Allocate an EVQ object */ 947227569Sphilip EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep); 948227569Sphilip if (eep == NULL) { 949227569Sphilip rc = ENOMEM; 950227569Sphilip goto fail5; 951227569Sphilip } 952227569Sphilip 953227569Sphilip eep->ee_magic = EFX_EVQ_MAGIC; 954227569Sphilip eep->ee_enp = enp; 955227569Sphilip eep->ee_index = index; 956227569Sphilip eep->ee_mask = n - 1; 957227569Sphilip eep->ee_esmp = esmp; 958227569Sphilip 959227569Sphilip /* Set up the handler table */ 960227569Sphilip eep->ee_handler[FSE_AZ_EV_CODE_RX_EV] = efx_ev_rx; 961227569Sphilip eep->ee_handler[FSE_AZ_EV_CODE_TX_EV] = efx_ev_tx; 962227569Sphilip eep->ee_handler[FSE_AZ_EV_CODE_DRIVER_EV] = efx_ev_driver; 963227569Sphilip eep->ee_handler[FSE_AZ_EV_CODE_GLOBAL_EV] = efx_ev_global; 964227569Sphilip eep->ee_handler[FSE_AZ_EV_CODE_DRV_GEN_EV] = efx_ev_drv_gen; 965227569Sphilip#if EFSYS_OPT_MCDI 966227569Sphilip eep->ee_handler[FSE_AZ_EV_CODE_MCDI_EVRESPONSE] = efx_ev_mcdi; 967227569Sphilip#endif /* EFSYS_OPT_SIENA */ 968227569Sphilip 969227569Sphilip /* Set up the new event queue */ 970227569Sphilip if (enp->en_family != EFX_FAMILY_FALCON) { 971227569Sphilip EFX_POPULATE_OWORD_1(oword, FRF_CZ_TIMER_Q_EN, 1); 972227569Sphilip EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword); 973227569Sphilip } 974227569Sphilip 975227569Sphilip EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size, 976227569Sphilip FRF_AZ_EVQ_BUF_BASE_ID, id); 977227569Sphilip 978227569Sphilip EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword); 979227569Sphilip 980227569Sphilip enp->en_ev_qcount++; 981227569Sphilip *eepp = eep; 982227569Sphilip return (0); 983227569Sphilip 984227569Sphilipfail5: 985227569Sphilip EFSYS_PROBE(fail5); 986227569Sphilipfail4: 987227569Sphilip EFSYS_PROBE(fail4); 988227569Sphilip#if EFSYS_OPT_RX_SCALE 989227569Sphilipfail3: 990227569Sphilip EFSYS_PROBE(fail3); 991227569Sphilip#endif 992227569Sphilipfail2: 993227569Sphilip EFSYS_PROBE(fail2); 994227569Sphilipfail1: 995227569Sphilip EFSYS_PROBE1(fail1, int, rc); 996227569Sphilip 997227569Sphilip return (rc); 998227569Sphilip} 999227569Sphilip 1000277886Sarybchik#if EFSYS_OPT_QSTATS 1001227569Sphilip#if EFSYS_OPT_NAMES 1002227569Sphilip/* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock 67e9bdcd920059bd */ 1003227569Sphilipstatic const char __cs * __cs __efx_ev_qstat_name[] = { 1004227569Sphilip "all", 1005227569Sphilip "rx", 1006227569Sphilip "rx_ok", 1007227569Sphilip "rx_recovery", 1008227569Sphilip "rx_frm_trunc", 1009227569Sphilip "rx_tobe_disc", 1010227569Sphilip "rx_pause_frm_err", 1011227569Sphilip "rx_buf_owner_id_err", 1012227569Sphilip "rx_ipv4_hdr_chksum_err", 1013227569Sphilip "rx_tcp_udp_chksum_err", 1014227569Sphilip "rx_eth_crc_err", 1015227569Sphilip "rx_ip_frag_err", 1016227569Sphilip "rx_mcast_pkt", 1017227569Sphilip "rx_mcast_hash_match", 1018227569Sphilip "rx_tcp_ipv4", 1019227569Sphilip "rx_tcp_ipv6", 1020227569Sphilip "rx_udp_ipv4", 1021227569Sphilip "rx_udp_ipv6", 1022227569Sphilip "rx_other_ipv4", 1023227569Sphilip "rx_other_ipv6", 1024227569Sphilip "rx_non_ip", 1025227569Sphilip "rx_overrun", 1026227569Sphilip "tx", 1027227569Sphilip "tx_wq_ff_full", 1028227569Sphilip "tx_pkt_err", 1029227569Sphilip "tx_pkt_too_big", 1030227569Sphilip "tx_unexpected", 1031227569Sphilip "global", 1032227569Sphilip "global_phy", 1033227569Sphilip "global_mnt", 1034227569Sphilip "global_rx_recovery", 1035227569Sphilip "driver", 1036227569Sphilip "driver_srm_upd_done", 1037227569Sphilip "driver_tx_descq_fls_done", 1038227569Sphilip "driver_rx_descq_fls_done", 1039227569Sphilip "driver_rx_descq_fls_failed", 1040227569Sphilip "driver_rx_dsc_error", 1041227569Sphilip "driver_tx_dsc_error", 1042227569Sphilip "drv_gen", 1043227569Sphilip "mcdi_response", 1044227569Sphilip}; 1045227569Sphilip/* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */ 1046227569Sphilip 1047227569Sphilip const char __cs * 1048227569Sphilipefx_ev_qstat_name( 1049227569Sphilip __in efx_nic_t *enp, 1050227569Sphilip __in unsigned int id) 1051227569Sphilip{ 1052227569Sphilip EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 1053227569Sphilip EFSYS_ASSERT3U(id, <, EV_NQSTATS); 1054227569Sphilip 1055227569Sphilip return (__efx_ev_qstat_name[id]); 1056227569Sphilip} 1057227569Sphilip#endif /* EFSYS_OPT_NAMES */ 1058277886Sarybchik#endif /* EFSYS_OPT_QSTATS */ 1059227569Sphilip 1060227569Sphilip#if EFSYS_OPT_QSTATS 1061227569Sphilip void 1062227569Sphilipefx_ev_qstats_update( 1063227569Sphilip __in efx_evq_t *eep, 1064227569Sphilip __inout_ecount(EV_NQSTATS) efsys_stat_t *stat) 1065227569Sphilip{ 1066227569Sphilip unsigned int id; 1067227569Sphilip 1068227569Sphilip EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 1069227569Sphilip 1070227569Sphilip for (id = 0; id < EV_NQSTATS; id++) { 1071227569Sphilip efsys_stat_t *essp = &stat[id]; 1072227569Sphilip 1073227569Sphilip EFSYS_STAT_INCR(essp, eep->ee_stat[id]); 1074227569Sphilip eep->ee_stat[id] = 0; 1075227569Sphilip } 1076227569Sphilip} 1077227569Sphilip#endif /* EFSYS_OPT_QSTATS */ 1078227569Sphilip 1079227569Sphilip void 1080227569Sphilipefx_ev_qdestroy( 1081227569Sphilip __in efx_evq_t *eep) 1082227569Sphilip{ 1083227569Sphilip efx_nic_t *enp = eep->ee_enp; 1084227569Sphilip efx_oword_t oword; 1085227569Sphilip 1086227569Sphilip EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 1087227569Sphilip 1088227569Sphilip EFSYS_ASSERT(enp->en_ev_qcount != 0); 1089227569Sphilip --enp->en_ev_qcount; 1090227569Sphilip 1091227569Sphilip /* Purge event queue */ 1092227569Sphilip EFX_ZERO_OWORD(oword); 1093227569Sphilip 1094227569Sphilip EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, 1095227569Sphilip eep->ee_index, &oword); 1096227569Sphilip 1097227569Sphilip if (enp->en_family != EFX_FAMILY_FALCON) { 1098227569Sphilip EFX_ZERO_OWORD(oword); 1099227569Sphilip EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, 1100227569Sphilip eep->ee_index, &oword); 1101227569Sphilip } 1102227569Sphilip 1103227569Sphilip /* Free the EVQ object */ 1104227569Sphilip EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep); 1105227569Sphilip} 1106227569Sphilip 1107227569Sphilip void 1108227569Sphilipefx_ev_fini( 1109227569Sphilip __in efx_nic_t *enp) 1110227569Sphilip{ 1111227569Sphilip EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 1112227569Sphilip EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 1113227569Sphilip EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV); 1114227569Sphilip EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX)); 1115227569Sphilip EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX)); 1116227569Sphilip EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0); 1117227569Sphilip 1118227569Sphilip enp->en_mod_flags &= ~EFX_MOD_EV; 1119227569Sphilip} 1120