safe.c revision 158651
1184299Snwhitehorn/*- 2184299Snwhitehorn * Copyright (c) 2003 Sam Leffler, Errno Consulting 3184299Snwhitehorn * Copyright (c) 2003 Global Technology Associates, Inc. 4184299Snwhitehorn * All rights reserved. 5184299Snwhitehorn * 6184299Snwhitehorn * Redistribution and use in source and binary forms, with or without 7184299Snwhitehorn * modification, are permitted provided that the following conditions 8184299Snwhitehorn * are met: 9184299Snwhitehorn * 1. Redistributions of source code must retain the above copyright 10184299Snwhitehorn * notice, this list of conditions and the following disclaimer. 11184299Snwhitehorn * 2. Redistributions in binary form must reproduce the above copyright 12184299Snwhitehorn * notice, this list of conditions and the following disclaimer in the 13184299Snwhitehorn * documentation and/or other materials provided with the distribution. 14184299Snwhitehorn * 15184299Snwhitehorn * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16184299Snwhitehorn * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17184299Snwhitehorn * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18184299Snwhitehorn * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19184299Snwhitehorn * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20184299Snwhitehorn * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21184299Snwhitehorn * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22184299Snwhitehorn * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23184299Snwhitehorn * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24184299Snwhitehorn * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25184299Snwhitehorn * SUCH DAMAGE. 26184299Snwhitehorn */ 27184299Snwhitehorn 28184299Snwhitehorn#include <sys/cdefs.h> 29184299Snwhitehorn__FBSDID("$FreeBSD: head/sys/dev/safe/safe.c 158651 2006-05-16 14:37:58Z phk $"); 30184299Snwhitehorn 31184299Snwhitehorn/* 32184299Snwhitehorn * SafeNet SafeXcel-1141 hardware crypto accelerator 33184299Snwhitehorn */ 34184299Snwhitehorn#include "opt_safe.h" 35184299Snwhitehorn 36184299Snwhitehorn#include <sys/param.h> 37184299Snwhitehorn#include <sys/systm.h> 38226449Snwhitehorn#include <sys/proc.h> 39184299Snwhitehorn#include <sys/errno.h> 40184299Snwhitehorn#include <sys/malloc.h> 41184299Snwhitehorn#include <sys/kernel.h> 42184299Snwhitehorn#include <sys/mbuf.h> 43184299Snwhitehorn#include <sys/module.h> 44184299Snwhitehorn#include <sys/lock.h> 45226449Snwhitehorn#include <sys/mutex.h> 46226449Snwhitehorn#include <sys/sysctl.h> 47184299Snwhitehorn#include <sys/endian.h> 48184299Snwhitehorn 49184299Snwhitehorn#include <vm/vm.h> 50184299Snwhitehorn#include <vm/pmap.h> 51184299Snwhitehorn 52184299Snwhitehorn#include <machine/bus.h> 53184299Snwhitehorn#include <machine/resource.h> 54184299Snwhitehorn#include <sys/bus.h> 55184299Snwhitehorn#include <sys/rman.h> 56184299Snwhitehorn 57184299Snwhitehorn#include <crypto/sha1.h> 58184299Snwhitehorn#include <opencrypto/cryptodev.h> 59184299Snwhitehorn#include <opencrypto/cryptosoft.h> 60184299Snwhitehorn#include <sys/md5.h> 61226449Snwhitehorn#include <sys/random.h> 62184299Snwhitehorn 63184299Snwhitehorn#include <dev/pci/pcivar.h> 64184299Snwhitehorn#include <dev/pci/pcireg.h> 65184299Snwhitehorn 66184299Snwhitehorn#ifdef SAFE_RNDTEST 67184299Snwhitehorn#include <dev/rndtest/rndtest.h> 68184299Snwhitehorn#endif 69184299Snwhitehorn#include <dev/safe/safereg.h> 70184299Snwhitehorn#include <dev/safe/safevar.h> 71184299Snwhitehorn 72184299Snwhitehorn#ifndef bswap32 73184299Snwhitehorn#define bswap32 NTOHL 74184299Snwhitehorn#endif 75184299Snwhitehorn 76184299Snwhitehorn/* 77184299Snwhitehorn * Prototypes and count for the pci_device structure 78184299Snwhitehorn */ 79186906Snwhitehornstatic int safe_probe(device_t); 80186906Snwhitehornstatic int safe_attach(device_t); 81186906Snwhitehornstatic int safe_detach(device_t); 82184299Snwhitehornstatic int safe_suspend(device_t); 83184299Snwhitehornstatic int safe_resume(device_t); 84184299Snwhitehornstatic void safe_shutdown(device_t); 85184299Snwhitehorn 86184299Snwhitehornstatic device_method_t safe_methods[] = { 87184299Snwhitehorn /* Device interface */ 88184299Snwhitehorn DEVMETHOD(device_probe, safe_probe), 89184299Snwhitehorn DEVMETHOD(device_attach, safe_attach), 90184299Snwhitehorn DEVMETHOD(device_detach, safe_detach), 91184299Snwhitehorn DEVMETHOD(device_suspend, safe_suspend), 92184299Snwhitehorn DEVMETHOD(device_resume, safe_resume), 93184299Snwhitehorn DEVMETHOD(device_shutdown, safe_shutdown), 94184299Snwhitehorn 95184299Snwhitehorn /* bus interface */ 96184299Snwhitehorn DEVMETHOD(bus_print_child, bus_generic_print_child), 97184299Snwhitehorn DEVMETHOD(bus_driver_added, bus_generic_driver_added), 98184299Snwhitehorn 99184299Snwhitehorn { 0, 0 } 100184299Snwhitehorn}; 101184299Snwhitehornstatic driver_t safe_driver = { 102184299Snwhitehorn "safe", 103184299Snwhitehorn safe_methods, 104184299Snwhitehorn sizeof (struct safe_softc) 105184299Snwhitehorn}; 106184299Snwhitehornstatic devclass_t safe_devclass; 107184299Snwhitehorn 108184299SnwhitehornDRIVER_MODULE(safe, pci, safe_driver, safe_devclass, 0, 0); 109184299SnwhitehornMODULE_DEPEND(safe, crypto, 1, 1, 1); 110184299Snwhitehorn#ifdef SAFE_RNDTEST 111184299SnwhitehornMODULE_DEPEND(safe, rndtest, 1, 1, 1); 112184299Snwhitehorn#endif 113184299Snwhitehorn 114184299Snwhitehornstatic void safe_intr(void *); 115186906Snwhitehornstatic int safe_newsession(void *, u_int32_t *, struct cryptoini *); 116186906Snwhitehornstatic int safe_freesession(void *, u_int64_t); 117186906Snwhitehornstatic int safe_process(void *, struct cryptop *, int); 118186906Snwhitehornstatic void safe_callback(struct safe_softc *, struct safe_ringentry *); 119186906Snwhitehornstatic void safe_feed(struct safe_softc *, struct safe_ringentry *); 120186906Snwhitehornstatic void safe_mcopy(struct mbuf *, struct mbuf *, u_int); 121186906Snwhitehorn#ifndef SAFE_NO_RNG 122186906Snwhitehornstatic void safe_rng_init(struct safe_softc *); 123186906Snwhitehornstatic void safe_rng(void *); 124186906Snwhitehorn#endif /* SAFE_NO_RNG */ 125186906Snwhitehornstatic int safe_dma_malloc(struct safe_softc *, bus_size_t, 126184299Snwhitehorn struct safe_dma_alloc *, int); 127184299Snwhitehorn#define safe_dma_sync(_dma, _flags) \ 128184299Snwhitehorn bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags)) 129184299Snwhitehornstatic void safe_dma_free(struct safe_softc *, struct safe_dma_alloc *); 130184299Snwhitehornstatic int safe_dmamap_aligned(const struct safe_operand *); 131184299Snwhitehornstatic int safe_dmamap_uniform(const struct safe_operand *); 132184299Snwhitehorn 133184299Snwhitehornstatic void safe_reset_board(struct safe_softc *); 134184299Snwhitehornstatic void safe_init_board(struct safe_softc *); 135186906Snwhitehornstatic void safe_init_pciregs(device_t dev); 136186906Snwhitehornstatic void safe_cleanchip(struct safe_softc *); 137186906Snwhitehornstatic void safe_totalreset(struct safe_softc *); 138186906Snwhitehorn 139186906Snwhitehornstatic int safe_free_entry(struct safe_softc *, struct safe_ringentry *); 140186906Snwhitehorn 141186906SnwhitehornSYSCTL_NODE(_hw, OID_AUTO, safe, CTLFLAG_RD, 0, "SafeNet driver parameters"); 142186906Snwhitehorn 143186906Snwhitehorn#ifdef SAFE_DEBUG 144186906Snwhitehornstatic void safe_dump_dmastatus(struct safe_softc *, const char *); 145186906Snwhitehornstatic void safe_dump_ringstate(struct safe_softc *, const char *); 146186906Snwhitehornstatic void safe_dump_intrstate(struct safe_softc *, const char *); 147186906Snwhitehornstatic void safe_dump_request(struct safe_softc *, const char *, 148186906Snwhitehorn struct safe_ringentry *); 149186906Snwhitehorn 150186906Snwhitehornstatic struct safe_softc *safec; /* for use by hw.safe.dump */ 151186906Snwhitehorn 152186906Snwhitehornstatic int safe_debug = 0; 153186906SnwhitehornSYSCTL_INT(_hw_safe, OID_AUTO, debug, CTLFLAG_RW, &safe_debug, 154186906Snwhitehorn 0, "control debugging msgs"); 155186906Snwhitehorn#define DPRINTF(_x) if (safe_debug) printf _x 156186906Snwhitehorn#else 157186906Snwhitehorn#define DPRINTF(_x) 158186906Snwhitehorn#endif 159186906Snwhitehorn 160186906Snwhitehorn#define READ_REG(sc,r) \ 161186906Snwhitehorn bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 162186906Snwhitehorn 163186906Snwhitehorn#define WRITE_REG(sc,reg,val) \ 164186906Snwhitehorn bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 165298307Spfg 166186906Snwhitehornstruct safe_stats safestats; 167186906SnwhitehornSYSCTL_STRUCT(_hw_safe, OID_AUTO, stats, CTLFLAG_RD, &safestats, 168186906Snwhitehorn safe_stats, "driver statistics"); 169186906Snwhitehorn#ifndef SAFE_NO_RNG 170186906Snwhitehornstatic int safe_rnginterval = 1; /* poll once a second */ 171186906SnwhitehornSYSCTL_INT(_hw_safe, OID_AUTO, rnginterval, CTLFLAG_RW, &safe_rnginterval, 172186906Snwhitehorn 0, "RNG polling interval (secs)"); 173186906Snwhitehornstatic int safe_rngbufsize = 16; /* 64 bytes each poll */ 174186906SnwhitehornSYSCTL_INT(_hw_safe, OID_AUTO, rngbufsize, CTLFLAG_RW, &safe_rngbufsize, 175186906Snwhitehorn 0, "RNG polling buffer size (32-bit words)"); 176184299Snwhitehornstatic int safe_rngmaxalarm = 8; /* max alarms before reset */ 177184299SnwhitehornSYSCTL_INT(_hw_safe, OID_AUTO, rngmaxalarm, CTLFLAG_RW, &safe_rngmaxalarm, 178184299Snwhitehorn 0, "RNG max alarms before reset"); 179184299Snwhitehorn#endif /* SAFE_NO_RNG */ 180184299Snwhitehorn 181184299Snwhitehornstatic int 182184299Snwhitehornsafe_probe(device_t dev) 183184299Snwhitehorn{ 184184299Snwhitehorn if (pci_get_vendor(dev) == PCI_VENDOR_SAFENET && 185184299Snwhitehorn pci_get_device(dev) == PCI_PRODUCT_SAFEXCEL) 186184299Snwhitehorn return (BUS_PROBE_DEFAULT); 187184299Snwhitehorn return (ENXIO); 188184299Snwhitehorn} 189184299Snwhitehorn 190184299Snwhitehornstatic const char* 191184299Snwhitehornsafe_partname(struct safe_softc *sc) 192184299Snwhitehorn{ 193184299Snwhitehorn /* XXX sprintf numbers when not decoded */ 194184299Snwhitehorn switch (pci_get_vendor(sc->sc_dev)) { 195184299Snwhitehorn case PCI_VENDOR_SAFENET: 196184299Snwhitehorn switch (pci_get_device(sc->sc_dev)) { 197184299Snwhitehorn case PCI_PRODUCT_SAFEXCEL: return "SafeNet SafeXcel-1141"; 198184299Snwhitehorn } 199184299Snwhitehorn return "SafeNet unknown-part"; 200184299Snwhitehorn } 201184299Snwhitehorn return "Unknown-vendor unknown-part"; 202184299Snwhitehorn} 203184299Snwhitehorn 204184299Snwhitehorn#ifndef SAFE_NO_RNG 205184299Snwhitehornstatic void 206184299Snwhitehorndefault_harvest(struct rndtest_state *rsp, void *buf, u_int count) 207184299Snwhitehorn{ 208184299Snwhitehorn random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 209184299Snwhitehorn} 210184299Snwhitehorn#endif /* SAFE_NO_RNG */ 211184299Snwhitehorn 212184299Snwhitehornstatic int 213184299Snwhitehornsafe_attach(device_t dev) 214184299Snwhitehorn{ 215184299Snwhitehorn struct safe_softc *sc = device_get_softc(dev); 216184299Snwhitehorn u_int32_t raddr; 217184299Snwhitehorn u_int32_t cmd, i, devinfo; 218184299Snwhitehorn int rid; 219184299Snwhitehorn 220184299Snwhitehorn bzero(sc, sizeof (*sc)); 221184299Snwhitehorn sc->sc_dev = dev; 222184299Snwhitehorn 223184299Snwhitehorn /* XXX handle power management */ 224184299Snwhitehorn 225184299Snwhitehorn cmd = pci_read_config(dev, PCIR_COMMAND, 4); 226184299Snwhitehorn cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 227184299Snwhitehorn pci_write_config(dev, PCIR_COMMAND, cmd, 4); 228184299Snwhitehorn cmd = pci_read_config(dev, PCIR_COMMAND, 4); 229184299Snwhitehorn 230184299Snwhitehorn if (!(cmd & PCIM_CMD_MEMEN)) { 231184299Snwhitehorn device_printf(dev, "failed to enable memory mapping\n"); 232184299Snwhitehorn goto bad; 233184299Snwhitehorn } 234184299Snwhitehorn 235184299Snwhitehorn if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 236184299Snwhitehorn device_printf(dev, "failed to enable bus mastering\n"); 237184299Snwhitehorn goto bad; 238184299Snwhitehorn } 239184299Snwhitehorn 240184299Snwhitehorn /* 241184299Snwhitehorn * Setup memory-mapping of PCI registers. 242184299Snwhitehorn */ 243184299Snwhitehorn rid = BS_BAR; 244184299Snwhitehorn sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 245184299Snwhitehorn RF_ACTIVE); 246184299Snwhitehorn if (sc->sc_sr == NULL) { 247184299Snwhitehorn device_printf(dev, "cannot map register space\n"); 248184299Snwhitehorn goto bad; 249184299Snwhitehorn } 250184299Snwhitehorn sc->sc_st = rman_get_bustag(sc->sc_sr); 251184299Snwhitehorn sc->sc_sh = rman_get_bushandle(sc->sc_sr); 252184299Snwhitehorn 253184299Snwhitehorn /* 254184299Snwhitehorn * Arrange interrupt line. 255184299Snwhitehorn */ 256184299Snwhitehorn rid = 0; 257184299Snwhitehorn sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 258184299Snwhitehorn RF_SHAREABLE|RF_ACTIVE); 259184299Snwhitehorn if (sc->sc_irq == NULL) { 260184299Snwhitehorn device_printf(dev, "could not map interrupt\n"); 261184299Snwhitehorn goto bad1; 262184299Snwhitehorn } 263184299Snwhitehorn /* 264184299Snwhitehorn * NB: Network code assumes we are blocked with splimp() 265184299Snwhitehorn * so make sure the IRQ is mapped appropriately. 266184299Snwhitehorn */ 267184299Snwhitehorn if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 268184299Snwhitehorn safe_intr, sc, &sc->sc_ih)) { 269184299Snwhitehorn device_printf(dev, "could not establish interrupt\n"); 270184299Snwhitehorn goto bad2; 271184299Snwhitehorn } 272184299Snwhitehorn 273184299Snwhitehorn sc->sc_cid = crypto_get_driverid(0); 274184299Snwhitehorn if (sc->sc_cid < 0) { 275184299Snwhitehorn device_printf(dev, "could not get crypto driver id\n"); 276184299Snwhitehorn goto bad3; 277184299Snwhitehorn } 278184299Snwhitehorn 279184299Snwhitehorn sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) & 280184299Snwhitehorn (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN); 281184299Snwhitehorn 282184299Snwhitehorn /* 283184299Snwhitehorn * Setup DMA descriptor area. 284184299Snwhitehorn */ 285184299Snwhitehorn if (bus_dma_tag_create(NULL, /* parent */ 286184299Snwhitehorn 1, /* alignment */ 287184299Snwhitehorn SAFE_DMA_BOUNDARY, /* boundary */ 288184299Snwhitehorn BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 289226449Snwhitehorn BUS_SPACE_MAXADDR, /* highaddr */ 290226449Snwhitehorn NULL, NULL, /* filter, filterarg */ 291184299Snwhitehorn SAFE_MAX_DMA, /* maxsize */ 292184299Snwhitehorn SAFE_MAX_PART, /* nsegments */ 293184299Snwhitehorn SAFE_MAX_SSIZE, /* maxsegsize */ 294184299Snwhitehorn BUS_DMA_ALLOCNOW, /* flags */ 295184299Snwhitehorn NULL, NULL, /* locking */ 296184299Snwhitehorn &sc->sc_srcdmat)) { 297184299Snwhitehorn device_printf(dev, "cannot allocate DMA tag\n"); 298184299Snwhitehorn goto bad4; 299184299Snwhitehorn } 300184299Snwhitehorn if (bus_dma_tag_create(NULL, /* parent */ 301184299Snwhitehorn sizeof(u_int32_t), /* alignment */ 302184299Snwhitehorn SAFE_MAX_DSIZE, /* boundary */ 303184299Snwhitehorn BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 304184299Snwhitehorn BUS_SPACE_MAXADDR, /* highaddr */ 305184299Snwhitehorn NULL, NULL, /* filter, filterarg */ 306184299Snwhitehorn SAFE_MAX_DMA, /* maxsize */ 307261068Sjhibbits SAFE_MAX_PART, /* nsegments */ 308184299Snwhitehorn SAFE_MAX_DSIZE, /* maxsegsize */ 309184299Snwhitehorn BUS_DMA_ALLOCNOW, /* flags */ 310184299Snwhitehorn NULL, NULL, /* locking */ 311184299Snwhitehorn &sc->sc_dstdmat)) { 312184299Snwhitehorn device_printf(dev, "cannot allocate DMA tag\n"); 313184299Snwhitehorn goto bad4; 314184299Snwhitehorn } 315184299Snwhitehorn 316184299Snwhitehorn /* 317184299Snwhitehorn * Allocate packet engine descriptors. 318184299Snwhitehorn */ 319184299Snwhitehorn if (safe_dma_malloc(sc, 320184299Snwhitehorn SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), 321184299Snwhitehorn &sc->sc_ringalloc, 0)) { 322184299Snwhitehorn device_printf(dev, "cannot allocate PE descriptor ring\n"); 323184299Snwhitehorn bus_dma_tag_destroy(sc->sc_srcdmat); 324184299Snwhitehorn goto bad4; 325184299Snwhitehorn } 326184299Snwhitehorn /* 327184299Snwhitehorn * Hookup the static portion of all our data structures. 328184299Snwhitehorn */ 329184299Snwhitehorn sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr; 330184299Snwhitehorn sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE; 331184299Snwhitehorn sc->sc_front = sc->sc_ring; 332184299Snwhitehorn sc->sc_back = sc->sc_ring; 333184299Snwhitehorn raddr = sc->sc_ringalloc.dma_paddr; 334184299Snwhitehorn bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry)); 335185724Snwhitehorn for (i = 0; i < SAFE_MAX_NQUEUE; i++) { 336185724Snwhitehorn struct safe_ringentry *re = &sc->sc_ring[i]; 337185724Snwhitehorn 338185724Snwhitehorn re->re_desc.d_sa = raddr + 339185724Snwhitehorn offsetof(struct safe_ringentry, re_sa); 340184299Snwhitehorn re->re_sa.sa_staterec = raddr + 341184299Snwhitehorn offsetof(struct safe_ringentry, re_sastate); 342226449Snwhitehorn 343226449Snwhitehorn raddr += sizeof (struct safe_ringentry); 344226449Snwhitehorn } 345226449Snwhitehorn mtx_init(&sc->sc_ringmtx, device_get_nameunit(dev), 346226449Snwhitehorn "packet engine ring", MTX_DEF); 347226449Snwhitehorn 348226449Snwhitehorn /* 349226449Snwhitehorn * Allocate scatter and gather particle descriptors. 350226449Snwhitehorn */ 351226449Snwhitehorn if (safe_dma_malloc(sc, SAFE_TOTAL_SPART * sizeof (struct safe_pdesc), 352226449Snwhitehorn &sc->sc_spalloc, 0)) { 353226449Snwhitehorn device_printf(dev, "cannot allocate source particle " 354226449Snwhitehorn "descriptor ring\n"); 355226449Snwhitehorn mtx_destroy(&sc->sc_ringmtx); 356226449Snwhitehorn safe_dma_free(sc, &sc->sc_ringalloc); 357226449Snwhitehorn bus_dma_tag_destroy(sc->sc_srcdmat); 358226449Snwhitehorn goto bad4; 359226449Snwhitehorn } 360226449Snwhitehorn sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr; 361226449Snwhitehorn sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART; 362226449Snwhitehorn sc->sc_spfree = sc->sc_spring; 363226449Snwhitehorn bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc)); 364226449Snwhitehorn 365226449Snwhitehorn if (safe_dma_malloc(sc, SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), 366226449Snwhitehorn &sc->sc_dpalloc, 0)) { 367226449Snwhitehorn device_printf(dev, "cannot allocate destination particle " 368226449Snwhitehorn "descriptor ring\n"); 369226449Snwhitehorn mtx_destroy(&sc->sc_ringmtx); 370226449Snwhitehorn safe_dma_free(sc, &sc->sc_spalloc); 371226449Snwhitehorn safe_dma_free(sc, &sc->sc_ringalloc); 372226449Snwhitehorn bus_dma_tag_destroy(sc->sc_dstdmat); 373226449Snwhitehorn goto bad4; 374226449Snwhitehorn } 375226449Snwhitehorn sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr; 376184299Snwhitehorn sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART; 377184299Snwhitehorn sc->sc_dpfree = sc->sc_dpring; 378184299Snwhitehorn bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc)); 379184299Snwhitehorn 380184299Snwhitehorn device_printf(sc->sc_dev, "%s", safe_partname(sc)); 381184299Snwhitehorn 382184299Snwhitehorn devinfo = READ_REG(sc, SAFE_DEVINFO); 383184299Snwhitehorn if (devinfo & SAFE_DEVINFO_RNG) { 384184299Snwhitehorn sc->sc_flags |= SAFE_FLAGS_RNG; 385184299Snwhitehorn printf(" rng"); 386184299Snwhitehorn } 387184299Snwhitehorn if (devinfo & SAFE_DEVINFO_PKEY) { 388184299Snwhitehorn#if 0 389184299Snwhitehorn printf(" key"); 390184299Snwhitehorn sc->sc_flags |= SAFE_FLAGS_KEY; 391184299Snwhitehorn crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 392184299Snwhitehorn safe_kprocess, sc); 393184299Snwhitehorn crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 394184299Snwhitehorn safe_kprocess, sc); 395184299Snwhitehorn#endif 396184299Snwhitehorn } 397184299Snwhitehorn if (devinfo & SAFE_DEVINFO_DES) { 398184299Snwhitehorn printf(" des/3des"); 399184299Snwhitehorn crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 400184299Snwhitehorn safe_newsession, safe_freesession, safe_process, sc); 401184299Snwhitehorn crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 402184299Snwhitehorn safe_newsession, safe_freesession, safe_process, sc); 403184299Snwhitehorn } 404184299Snwhitehorn if (devinfo & SAFE_DEVINFO_AES) { 405184299Snwhitehorn printf(" aes"); 406184299Snwhitehorn crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0, 407184299Snwhitehorn safe_newsession, safe_freesession, safe_process, sc); 408184299Snwhitehorn } 409184299Snwhitehorn if (devinfo & SAFE_DEVINFO_MD5) { 410184299Snwhitehorn printf(" md5"); 411184299Snwhitehorn crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 412184299Snwhitehorn safe_newsession, safe_freesession, safe_process, sc); 413184299Snwhitehorn } 414184299Snwhitehorn if (devinfo & SAFE_DEVINFO_SHA1) { 415184299Snwhitehorn printf(" sha1"); 416184299Snwhitehorn crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 417184299Snwhitehorn safe_newsession, safe_freesession, safe_process, sc); 418184299Snwhitehorn } 419184299Snwhitehorn printf(" null"); 420184299Snwhitehorn crypto_register(sc->sc_cid, CRYPTO_NULL_CBC, 0, 0, 421184299Snwhitehorn safe_newsession, safe_freesession, safe_process, sc); 422184299Snwhitehorn crypto_register(sc->sc_cid, CRYPTO_NULL_HMAC, 0, 0, 423184299Snwhitehorn safe_newsession, safe_freesession, safe_process, sc); 424184299Snwhitehorn /* XXX other supported algorithms */ 425184299Snwhitehorn printf("\n"); 426226449Snwhitehorn 427267697Sjhibbits safe_reset_board(sc); /* reset h/w */ 428226449Snwhitehorn safe_init_pciregs(dev); /* init pci settings */ 429237480Sjhibbits safe_init_board(sc); /* init h/w */ 430226449Snwhitehorn 431226449Snwhitehorn#ifndef SAFE_NO_RNG 432237480Sjhibbits if (sc->sc_flags & SAFE_FLAGS_RNG) { 433226449Snwhitehorn#ifdef SAFE_RNDTEST 434226449Snwhitehorn sc->sc_rndtest = rndtest_attach(dev); 435184299Snwhitehorn if (sc->sc_rndtest) 436184299Snwhitehorn sc->sc_harvest = rndtest_harvest; 437184299Snwhitehorn else 438184299Snwhitehorn sc->sc_harvest = default_harvest; 439184299Snwhitehorn#else 440184299Snwhitehorn sc->sc_harvest = default_harvest; 441184299Snwhitehorn#endif 442184299Snwhitehorn safe_rng_init(sc); 443184299Snwhitehorn 444184299Snwhitehorn callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); 445184299Snwhitehorn callout_reset(&sc->sc_rngto, hz*safe_rnginterval, safe_rng, sc); 446184299Snwhitehorn } 447184299Snwhitehorn#endif /* SAFE_NO_RNG */ 448184299Snwhitehorn#ifdef SAFE_DEBUG 449184299Snwhitehorn safec = sc; /* for use by hw.safe.dump */ 450184299Snwhitehorn#endif 451184299Snwhitehorn return (0); 452184299Snwhitehornbad4: 453184299Snwhitehorn crypto_unregister_all(sc->sc_cid); 454184299Snwhitehornbad3: 455184299Snwhitehorn bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 456184299Snwhitehornbad2: 457184299Snwhitehorn bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 458184299Snwhitehornbad1: 459184299Snwhitehorn bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 460184299Snwhitehornbad: 461184299Snwhitehorn return (ENXIO); 462184299Snwhitehorn} 463184299Snwhitehorn 464184299Snwhitehorn/* 465184299Snwhitehorn * Detach a device that successfully probed. 466184299Snwhitehorn */ 467184299Snwhitehornstatic int 468184299Snwhitehornsafe_detach(device_t dev) 469184299Snwhitehorn{ 470184299Snwhitehorn struct safe_softc *sc = device_get_softc(dev); 471184299Snwhitehorn 472184299Snwhitehorn /* XXX wait/abort active ops */ 473184299Snwhitehorn 474184299Snwhitehorn WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */ 475184299Snwhitehorn 476184299Snwhitehorn callout_stop(&sc->sc_rngto); 477184299Snwhitehorn 478184299Snwhitehorn crypto_unregister_all(sc->sc_cid); 479184299Snwhitehorn 480184299Snwhitehorn#ifdef SAFE_RNDTEST 481184299Snwhitehorn if (sc->sc_rndtest) 482184299Snwhitehorn rndtest_detach(sc->sc_rndtest); 483184299Snwhitehorn#endif 484184299Snwhitehorn 485184299Snwhitehorn safe_cleanchip(sc); 486184299Snwhitehorn safe_dma_free(sc, &sc->sc_dpalloc); 487184299Snwhitehorn safe_dma_free(sc, &sc->sc_spalloc); 488184299Snwhitehorn mtx_destroy(&sc->sc_ringmtx); 489184299Snwhitehorn safe_dma_free(sc, &sc->sc_ringalloc); 490184299Snwhitehorn 491184299Snwhitehorn bus_generic_detach(dev); 492184299Snwhitehorn bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 493184299Snwhitehorn bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 494184299Snwhitehorn 495184299Snwhitehorn bus_dma_tag_destroy(sc->sc_srcdmat); 496184299Snwhitehorn bus_dma_tag_destroy(sc->sc_dstdmat); 497184299Snwhitehorn bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 498184299Snwhitehorn 499184299Snwhitehorn return (0); 500184299Snwhitehorn} 501184299Snwhitehorn 502184299Snwhitehorn/* 503184299Snwhitehorn * Stop all chip i/o so that the kernel's probe routines don't 504184299Snwhitehorn * get confused by errant DMAs when rebooting. 505184299Snwhitehorn */ 506184299Snwhitehornstatic void 507184299Snwhitehornsafe_shutdown(device_t dev) 508184299Snwhitehorn{ 509184299Snwhitehorn#ifdef notyet 510184299Snwhitehorn safe_stop(device_get_softc(dev)); 511184299Snwhitehorn#endif 512184299Snwhitehorn} 513184299Snwhitehorn 514184299Snwhitehorn/* 515184299Snwhitehorn * Device suspend routine. 516184299Snwhitehorn */ 517184299Snwhitehornstatic int 518184299Snwhitehornsafe_suspend(device_t dev) 519184299Snwhitehorn{ 520184299Snwhitehorn struct safe_softc *sc = device_get_softc(dev); 521184299Snwhitehorn 522184299Snwhitehorn#ifdef notyet 523184299Snwhitehorn /* XXX stop the device and save PCI settings */ 524184299Snwhitehorn#endif 525184299Snwhitehorn sc->sc_suspended = 1; 526184299Snwhitehorn 527184299Snwhitehorn return (0); 528184299Snwhitehorn} 529184299Snwhitehorn 530184299Snwhitehornstatic int 531184299Snwhitehornsafe_resume(device_t dev) 532184299Snwhitehorn{ 533184299Snwhitehorn struct safe_softc *sc = device_get_softc(dev); 534184299Snwhitehorn 535184299Snwhitehorn#ifdef notyet 536184299Snwhitehorn /* XXX retore PCI settings and start the device */ 537184299Snwhitehorn#endif 538184299Snwhitehorn sc->sc_suspended = 0; 539184299Snwhitehorn return (0); 540184299Snwhitehorn} 541184299Snwhitehorn 542184299Snwhitehorn/* 543184299Snwhitehorn * SafeXcel Interrupt routine 544184299Snwhitehorn */ 545184299Snwhitehornstatic void 546184299Snwhitehornsafe_intr(void *arg) 547184299Snwhitehorn{ 548184299Snwhitehorn struct safe_softc *sc = arg; 549184299Snwhitehorn volatile u_int32_t stat; 550184299Snwhitehorn 551184299Snwhitehorn stat = READ_REG(sc, SAFE_HM_STAT); 552184299Snwhitehorn if (stat == 0) /* shared irq, not for us */ 553184299Snwhitehorn return; 554184299Snwhitehorn 555184299Snwhitehorn WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */ 556184299Snwhitehorn 557184299Snwhitehorn if ((stat & SAFE_INT_PE_DDONE)) { 558184299Snwhitehorn /* 559184299Snwhitehorn * Descriptor(s) done; scan the ring and 560184299Snwhitehorn * process completed operations. 561184299Snwhitehorn */ 562184299Snwhitehorn mtx_lock(&sc->sc_ringmtx); 563184299Snwhitehorn while (sc->sc_back != sc->sc_front) { 564184299Snwhitehorn struct safe_ringentry *re = sc->sc_back; 565184299Snwhitehorn#ifdef SAFE_DEBUG 566184299Snwhitehorn if (safe_debug) { 567184299Snwhitehorn safe_dump_ringstate(sc, __func__); 568184299Snwhitehorn safe_dump_request(sc, __func__, re); 569184299Snwhitehorn } 570184299Snwhitehorn#endif 571184299Snwhitehorn /* 572184299Snwhitehorn * safe_process marks ring entries that were allocated 573184299Snwhitehorn * but not used with a csr of zero. This insures the 574186906Snwhitehorn * ring front pointer never needs to be set backwards 575186906Snwhitehorn * in the event that an entry is allocated but not used 576186906Snwhitehorn * because of a setup error. 577186906Snwhitehorn */ 578186906Snwhitehorn if (re->re_desc.d_csr != 0) { 579186906Snwhitehorn if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr)) 580186906Snwhitehorn break; 581184299Snwhitehorn if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len)) 582184299Snwhitehorn break; 583184299Snwhitehorn sc->sc_nqchip--; 584184299Snwhitehorn safe_callback(sc, re); 585184299Snwhitehorn } 586184299Snwhitehorn if (++(sc->sc_back) == sc->sc_ringtop) 587184299Snwhitehorn sc->sc_back = sc->sc_ring; 588184299Snwhitehorn } 589184299Snwhitehorn mtx_unlock(&sc->sc_ringmtx); 590184299Snwhitehorn } 591184299Snwhitehorn 592184299Snwhitehorn /* 593184299Snwhitehorn * Check to see if we got any DMA Error 594186906Snwhitehorn */ 595186906Snwhitehorn if (stat & SAFE_INT_PE_ERROR) { 596184299Snwhitehorn DPRINTF(("dmaerr dmastat %08x\n", 597184299Snwhitehorn READ_REG(sc, SAFE_PE_DMASTAT))); 598184299Snwhitehorn safestats.st_dmaerr++; 599184299Snwhitehorn safe_totalreset(sc); 600184299Snwhitehorn#if 0 601184299Snwhitehorn safe_feed(sc); 602186906Snwhitehorn#endif 603186906Snwhitehorn } 604186906Snwhitehorn 605186906Snwhitehorn if (sc->sc_needwakeup) { /* XXX check high watermark */ 606186906Snwhitehorn int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 607186906Snwhitehorn DPRINTF(("%s: wakeup crypto %x\n", __func__, 608186906Snwhitehorn sc->sc_needwakeup)); 609186906Snwhitehorn sc->sc_needwakeup &= ~wakeup; 610186906Snwhitehorn crypto_unblock(sc->sc_cid, wakeup); 611184299Snwhitehorn } 612184299Snwhitehorn} 613186906Snwhitehorn 614184299Snwhitehorn/* 615186906Snwhitehorn * safe_feed() - post a request to chip 616186906Snwhitehorn */ 617186906Snwhitehornstatic void 618184299Snwhitehornsafe_feed(struct safe_softc *sc, struct safe_ringentry *re) 619186906Snwhitehorn{ 620186906Snwhitehorn bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_PREWRITE); 621184299Snwhitehorn if (re->re_dst_map != NULL) 622186906Snwhitehorn bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map, 623186906Snwhitehorn BUS_DMASYNC_PREREAD); 624257295Snwhitehorn /* XXX have no smaller granularity */ 625186906Snwhitehorn safe_dma_sync(&sc->sc_ringalloc, 626186906Snwhitehorn BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 627186906Snwhitehorn safe_dma_sync(&sc->sc_spalloc, BUS_DMASYNC_PREWRITE); 628186906Snwhitehorn safe_dma_sync(&sc->sc_dpalloc, BUS_DMASYNC_PREWRITE); 629186906Snwhitehorn 630186906Snwhitehorn#ifdef SAFE_DEBUG 631186906Snwhitehorn if (safe_debug) { 632186906Snwhitehorn safe_dump_ringstate(sc, __func__); 633186906Snwhitehorn safe_dump_request(sc, __func__, re); 634184299Snwhitehorn } 635186906Snwhitehorn#endif 636186906Snwhitehorn sc->sc_nqchip++; 637186906Snwhitehorn if (sc->sc_nqchip > safestats.st_maxqchip) 638186906Snwhitehorn safestats.st_maxqchip = sc->sc_nqchip; 639186906Snwhitehorn /* poke h/w to check descriptor ring, any value can be written */ 640186906Snwhitehorn WRITE_REG(sc, SAFE_HI_RD_DESCR, 0); 641186906Snwhitehorn} 642186906Snwhitehorn 643186906Snwhitehorn/* 644186906Snwhitehorn * Allocate a new 'session' and return an encoded session id. 'sidp' 645186906Snwhitehorn * contains our registration id, and should contain an encoded session 646186906Snwhitehorn * id on successful allocation. 647186906Snwhitehorn */ 648186906Snwhitehornstatic int 649186906Snwhitehornsafe_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 650186906Snwhitehorn{ 651186906Snwhitehorn#define N(a) (sizeof(a) / sizeof (a[0])) 652186906Snwhitehorn struct cryptoini *c, *encini = NULL, *macini = NULL; 653186906Snwhitehorn struct safe_softc *sc = arg; 654186906Snwhitehorn struct safe_session *ses = NULL; 655186906Snwhitehorn MD5_CTX md5ctx; 656186906Snwhitehorn SHA1_CTX sha1ctx; 657186906Snwhitehorn int i, sesn; 658186906Snwhitehorn 659186906Snwhitehorn if (sidp == NULL || cri == NULL || sc == NULL) 660186906Snwhitehorn return (EINVAL); 661186906Snwhitehorn 662186906Snwhitehorn for (c = cri; c != NULL; c = c->cri_next) { 663186906Snwhitehorn if (c->cri_alg == CRYPTO_MD5_HMAC || 664186906Snwhitehorn c->cri_alg == CRYPTO_SHA1_HMAC || 665186906Snwhitehorn c->cri_alg == CRYPTO_NULL_HMAC) { 666186906Snwhitehorn if (macini) 667186906Snwhitehorn return (EINVAL); 668186906Snwhitehorn macini = c; 669186906Snwhitehorn } else if (c->cri_alg == CRYPTO_DES_CBC || 670184299Snwhitehorn c->cri_alg == CRYPTO_3DES_CBC || 671186906Snwhitehorn c->cri_alg == CRYPTO_AES_CBC || 672184299Snwhitehorn c->cri_alg == CRYPTO_NULL_CBC) { 673184299Snwhitehorn if (encini) 674186906Snwhitehorn return (EINVAL); 675186906Snwhitehorn encini = c; 676186906Snwhitehorn } else 677184299Snwhitehorn return (EINVAL); 678184299Snwhitehorn } 679184299Snwhitehorn if (encini == NULL && macini == NULL) 680184299Snwhitehorn return (EINVAL); 681184299Snwhitehorn if (encini) { /* validate key length */ 682184299Snwhitehorn switch (encini->cri_alg) { 683184299Snwhitehorn case CRYPTO_DES_CBC: 684184299Snwhitehorn if (encini->cri_klen != 64) 685184299Snwhitehorn return (EINVAL); 686184299Snwhitehorn break; 687184299Snwhitehorn case CRYPTO_3DES_CBC: 688184299Snwhitehorn if (encini->cri_klen != 192) 689184299Snwhitehorn return (EINVAL); 690184299Snwhitehorn break; 691184299Snwhitehorn case CRYPTO_AES_CBC: 692184299Snwhitehorn if (encini->cri_klen != 128 && 693184299Snwhitehorn encini->cri_klen != 192 && 694184299Snwhitehorn encini->cri_klen != 256) 695184299Snwhitehorn return (EINVAL); 696184299Snwhitehorn break; 697184299Snwhitehorn } 698184299Snwhitehorn } 699184299Snwhitehorn 700184299Snwhitehorn if (sc->sc_sessions == NULL) { 701184299Snwhitehorn ses = sc->sc_sessions = (struct safe_session *)malloc( 702184299Snwhitehorn sizeof(struct safe_session), M_DEVBUF, M_NOWAIT); 703184299Snwhitehorn if (ses == NULL) 704184299Snwhitehorn return (ENOMEM); 705184299Snwhitehorn sesn = 0; 706184299Snwhitehorn sc->sc_nsessions = 1; 707184299Snwhitehorn } else { 708184299Snwhitehorn for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 709184299Snwhitehorn if (sc->sc_sessions[sesn].ses_used == 0) { 710184299Snwhitehorn ses = &sc->sc_sessions[sesn]; 711184299Snwhitehorn break; 712184299Snwhitehorn } 713184299Snwhitehorn } 714184299Snwhitehorn 715184299Snwhitehorn if (ses == NULL) { 716184299Snwhitehorn sesn = sc->sc_nsessions; 717184299Snwhitehorn ses = (struct safe_session *)malloc((sesn + 1) * 718184299Snwhitehorn sizeof(struct safe_session), M_DEVBUF, M_NOWAIT); 719184299Snwhitehorn if (ses == NULL) 720184299Snwhitehorn return (ENOMEM); 721184299Snwhitehorn bcopy(sc->sc_sessions, ses, sesn * 722184299Snwhitehorn sizeof(struct safe_session)); 723184299Snwhitehorn bzero(sc->sc_sessions, sesn * 724184299Snwhitehorn sizeof(struct safe_session)); 725184299Snwhitehorn free(sc->sc_sessions, M_DEVBUF); 726184299Snwhitehorn sc->sc_sessions = ses; 727184299Snwhitehorn ses = &sc->sc_sessions[sesn]; 728184299Snwhitehorn sc->sc_nsessions++; 729184299Snwhitehorn } 730184299Snwhitehorn } 731184299Snwhitehorn 732184299Snwhitehorn bzero(ses, sizeof(struct safe_session)); 733184299Snwhitehorn ses->ses_used = 1; 734184299Snwhitehorn 735184299Snwhitehorn if (encini) { 736184299Snwhitehorn /* get an IV */ 737184299Snwhitehorn /* XXX may read fewer than requested */ 738184299Snwhitehorn read_random(ses->ses_iv, sizeof(ses->ses_iv)); 739184299Snwhitehorn 740184299Snwhitehorn ses->ses_klen = encini->cri_klen; 741184299Snwhitehorn bcopy(encini->cri_key, ses->ses_key, ses->ses_klen / 8); 742184299Snwhitehorn 743184299Snwhitehorn /* PE is little-endian, insure proper byte order */ 744184299Snwhitehorn for (i = 0; i < N(ses->ses_key); i++) 745184299Snwhitehorn ses->ses_key[i] = htole32(ses->ses_key[i]); 746184299Snwhitehorn } 747184299Snwhitehorn 748184299Snwhitehorn if (macini) { 749184299Snwhitehorn for (i = 0; i < macini->cri_klen / 8; i++) 750184299Snwhitehorn macini->cri_key[i] ^= HMAC_IPAD_VAL; 751184299Snwhitehorn 752184299Snwhitehorn if (macini->cri_alg == CRYPTO_MD5_HMAC) { 753184299Snwhitehorn MD5Init(&md5ctx); 754184299Snwhitehorn MD5Update(&md5ctx, macini->cri_key, 755184299Snwhitehorn macini->cri_klen / 8); 756184299Snwhitehorn MD5Update(&md5ctx, hmac_ipad_buffer, 757184299Snwhitehorn HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 758184299Snwhitehorn bcopy(md5ctx.state, ses->ses_hminner, 759184299Snwhitehorn sizeof(md5ctx.state)); 760184299Snwhitehorn } else { 761184299Snwhitehorn SHA1Init(&sha1ctx); 762184299Snwhitehorn SHA1Update(&sha1ctx, macini->cri_key, 763184299Snwhitehorn macini->cri_klen / 8); 764184299Snwhitehorn SHA1Update(&sha1ctx, hmac_ipad_buffer, 765184299Snwhitehorn HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 766184299Snwhitehorn bcopy(sha1ctx.h.b32, ses->ses_hminner, 767184299Snwhitehorn sizeof(sha1ctx.h.b32)); 768184299Snwhitehorn } 769184299Snwhitehorn 770184299Snwhitehorn for (i = 0; i < macini->cri_klen / 8; i++) 771184299Snwhitehorn macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 772184299Snwhitehorn 773184299Snwhitehorn if (macini->cri_alg == CRYPTO_MD5_HMAC) { 774184299Snwhitehorn MD5Init(&md5ctx); 775184299Snwhitehorn MD5Update(&md5ctx, macini->cri_key, 776184299Snwhitehorn macini->cri_klen / 8); 777184299Snwhitehorn MD5Update(&md5ctx, hmac_opad_buffer, 778184299Snwhitehorn HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 779184299Snwhitehorn bcopy(md5ctx.state, ses->ses_hmouter, 780184299Snwhitehorn sizeof(md5ctx.state)); 781184299Snwhitehorn } else { 782184299Snwhitehorn SHA1Init(&sha1ctx); 783184299Snwhitehorn SHA1Update(&sha1ctx, macini->cri_key, 784184299Snwhitehorn macini->cri_klen / 8); 785184299Snwhitehorn SHA1Update(&sha1ctx, hmac_opad_buffer, 786184299Snwhitehorn HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 787184299Snwhitehorn bcopy(sha1ctx.h.b32, ses->ses_hmouter, 788184299Snwhitehorn sizeof(sha1ctx.h.b32)); 789184299Snwhitehorn } 790184299Snwhitehorn 791184299Snwhitehorn for (i = 0; i < macini->cri_klen / 8; i++) 792184299Snwhitehorn macini->cri_key[i] ^= HMAC_OPAD_VAL; 793184299Snwhitehorn 794184299Snwhitehorn /* PE is little-endian, insure proper byte order */ 795184299Snwhitehorn for (i = 0; i < N(ses->ses_hminner); i++) { 796184299Snwhitehorn ses->ses_hminner[i] = htole32(ses->ses_hminner[i]); 797184299Snwhitehorn ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]); 798224126Sed } 799184299Snwhitehorn } 800184299Snwhitehorn 801184299Snwhitehorn *sidp = SAFE_SID(device_get_unit(sc->sc_dev), sesn); 802184299Snwhitehorn return (0); 803184299Snwhitehorn#undef N 804184299Snwhitehorn} 805184299Snwhitehorn 806184299Snwhitehorn/* 807184299Snwhitehorn * Deallocate a session. 808184299Snwhitehorn */ 809184299Snwhitehornstatic int 810184299Snwhitehornsafe_freesession(void *arg, u_int64_t tid) 811184299Snwhitehorn{ 812184299Snwhitehorn struct safe_softc *sc = arg; 813184299Snwhitehorn int session, ret; 814184299Snwhitehorn u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 815186906Snwhitehorn 816186906Snwhitehorn if (sc == NULL) 817186906Snwhitehorn return (EINVAL); 818186906Snwhitehorn 819186906Snwhitehorn session = SAFE_SESSION(sid); 820186906Snwhitehorn if (session < sc->sc_nsessions) { 821186906Snwhitehorn bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 822186906Snwhitehorn ret = 0; 823186906Snwhitehorn } else 824186906Snwhitehorn ret = EINVAL; 825186906Snwhitehorn return (ret); 826186906Snwhitehorn} 827186906Snwhitehorn 828186906Snwhitehornstatic void 829184299Snwhitehornsafe_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 830184299Snwhitehorn{ 831184299Snwhitehorn struct safe_operand *op = arg; 832184299Snwhitehorn 833184299Snwhitehorn DPRINTF(("%s: mapsize %u nsegs %d error %d\n", __func__, 834184299Snwhitehorn (u_int) mapsize, nsegs, error)); 835184299Snwhitehorn if (error != 0) 836184299Snwhitehorn return; 837184299Snwhitehorn op->mapsize = mapsize; 838184299Snwhitehorn op->nsegs = nsegs; 839184299Snwhitehorn bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 840184299Snwhitehorn} 841184299Snwhitehorn 842184299Snwhitehornstatic int 843184299Snwhitehornsafe_process(void *arg, struct cryptop *crp, int hint) 844184299Snwhitehorn{ 845184299Snwhitehorn int err = 0, i, nicealign, uniform; 846184299Snwhitehorn struct safe_softc *sc = arg; 847184299Snwhitehorn struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 848184299Snwhitehorn int bypass, oplen, ivsize; 849184299Snwhitehorn caddr_t iv; 850184299Snwhitehorn int16_t coffset; 851184299Snwhitehorn struct safe_session *ses; 852184299Snwhitehorn struct safe_ringentry *re; 853184299Snwhitehorn struct safe_sarec *sa; 854184299Snwhitehorn struct safe_pdesc *pd; 855184299Snwhitehorn u_int32_t cmd0, cmd1, staterec; 856184299Snwhitehorn 857184299Snwhitehorn if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 858184299Snwhitehorn safestats.st_invalid++; 859184299Snwhitehorn return (EINVAL); 860184299Snwhitehorn } 861184299Snwhitehorn if (SAFE_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 862184299Snwhitehorn safestats.st_badsession++; 863184299Snwhitehorn return (EINVAL); 864184299Snwhitehorn } 865226449Snwhitehorn 866226449Snwhitehorn mtx_lock(&sc->sc_ringmtx); 867226449Snwhitehorn if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) { 868226449Snwhitehorn safestats.st_ringfull++; 869226449Snwhitehorn sc->sc_needwakeup |= CRYPTO_SYMQ; 870226449Snwhitehorn mtx_unlock(&sc->sc_ringmtx); 871226449Snwhitehorn return (ERESTART); 872226449Snwhitehorn } 873226449Snwhitehorn re = sc->sc_front; 874226449Snwhitehorn 875226449Snwhitehorn staterec = re->re_sa.sa_staterec; /* save */ 876226449Snwhitehorn /* NB: zero everything but the PE descriptor */ 877226449Snwhitehorn bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc)); 878226449Snwhitehorn re->re_sa.sa_staterec = staterec; /* restore */ 879226449Snwhitehorn 880226449Snwhitehorn re->re_crp = crp; 881226449Snwhitehorn re->re_sesn = SAFE_SESSION(crp->crp_sid); 882226449Snwhitehorn 883226449Snwhitehorn if (crp->crp_flags & CRYPTO_F_IMBUF) { 884226449Snwhitehorn re->re_src_m = (struct mbuf *)crp->crp_buf; 885226449Snwhitehorn re->re_dst_m = (struct mbuf *)crp->crp_buf; 886226449Snwhitehorn } else if (crp->crp_flags & CRYPTO_F_IOV) { 887226449Snwhitehorn re->re_src_io = (struct uio *)crp->crp_buf; 888226449Snwhitehorn re->re_dst_io = (struct uio *)crp->crp_buf; 889184299Snwhitehorn } else { 890184299Snwhitehorn safestats.st_badflags++; 891 err = EINVAL; 892 goto errout; /* XXX we don't handle contiguous blocks! */ 893 } 894 895 sa = &re->re_sa; 896 ses = &sc->sc_sessions[re->re_sesn]; 897 898 crd1 = crp->crp_desc; 899 if (crd1 == NULL) { 900 safestats.st_nodesc++; 901 err = EINVAL; 902 goto errout; 903 } 904 crd2 = crd1->crd_next; 905 906 if ((crd1->crd_flags & CRD_F_KEY_EXPLICIT) || 907 (crd2 != NULL && (crd2->crd_flags & CRD_F_KEY_EXPLICIT))) { 908 safestats.st_badflags++; 909 err = EINVAL; 910 goto errout; 911 } 912 913 cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */ 914 cmd1 = 0; 915 if (crd2 == NULL) { 916 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 917 crd1->crd_alg == CRYPTO_SHA1_HMAC || 918 crd1->crd_alg == CRYPTO_NULL_HMAC) { 919 maccrd = crd1; 920 enccrd = NULL; 921 cmd0 |= SAFE_SA_CMD0_OP_HASH; 922 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 923 crd1->crd_alg == CRYPTO_3DES_CBC || 924 crd1->crd_alg == CRYPTO_AES_CBC || 925 crd1->crd_alg == CRYPTO_NULL_CBC) { 926 maccrd = NULL; 927 enccrd = crd1; 928 cmd0 |= SAFE_SA_CMD0_OP_CRYPT; 929 } else { 930 safestats.st_badalg++; 931 err = EINVAL; 932 goto errout; 933 } 934 } else { 935 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 936 crd1->crd_alg == CRYPTO_SHA1_HMAC || 937 crd1->crd_alg == CRYPTO_NULL_HMAC) && 938 (crd2->crd_alg == CRYPTO_DES_CBC || 939 crd2->crd_alg == CRYPTO_3DES_CBC || 940 crd2->crd_alg == CRYPTO_AES_CBC || 941 crd2->crd_alg == CRYPTO_NULL_CBC) && 942 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 943 maccrd = crd1; 944 enccrd = crd2; 945 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 946 crd1->crd_alg == CRYPTO_3DES_CBC || 947 crd1->crd_alg == CRYPTO_AES_CBC || 948 crd1->crd_alg == CRYPTO_NULL_CBC) && 949 (crd2->crd_alg == CRYPTO_MD5_HMAC || 950 crd2->crd_alg == CRYPTO_SHA1_HMAC || 951 crd2->crd_alg == CRYPTO_NULL_HMAC) && 952 (crd1->crd_flags & CRD_F_ENCRYPT)) { 953 enccrd = crd1; 954 maccrd = crd2; 955 } else { 956 safestats.st_badalg++; 957 err = EINVAL; 958 goto errout; 959 } 960 cmd0 |= SAFE_SA_CMD0_OP_BOTH; 961 } 962 963 if (enccrd) { 964 if (enccrd->crd_alg == CRYPTO_DES_CBC) { 965 cmd0 |= SAFE_SA_CMD0_DES; 966 cmd1 |= SAFE_SA_CMD1_CBC; 967 ivsize = 2*sizeof(u_int32_t); 968 } else if (enccrd->crd_alg == CRYPTO_3DES_CBC) { 969 cmd0 |= SAFE_SA_CMD0_3DES; 970 cmd1 |= SAFE_SA_CMD1_CBC; 971 ivsize = 2*sizeof(u_int32_t); 972 } else if (enccrd->crd_alg == CRYPTO_AES_CBC) { 973 cmd0 |= SAFE_SA_CMD0_AES; 974 cmd1 |= SAFE_SA_CMD1_CBC; 975 if (ses->ses_klen == 128) 976 cmd1 |= SAFE_SA_CMD1_AES128; 977 else if (ses->ses_klen == 192) 978 cmd1 |= SAFE_SA_CMD1_AES192; 979 else 980 cmd1 |= SAFE_SA_CMD1_AES256; 981 ivsize = 4*sizeof(u_int32_t); 982 } else { 983 cmd0 |= SAFE_SA_CMD0_CRYPT_NULL; 984 ivsize = 0; 985 } 986 987 /* 988 * Setup encrypt/decrypt state. When using basic ops 989 * we can't use an inline IV because hash/crypt offset 990 * must be from the end of the IV to the start of the 991 * crypt data and this leaves out the preceding header 992 * from the hash calculation. Instead we place the IV 993 * in the state record and set the hash/crypt offset to 994 * copy both the header+IV. 995 */ 996 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 997 cmd0 |= SAFE_SA_CMD0_OUTBOUND; 998 999 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1000 iv = enccrd->crd_iv; 1001 else 1002 iv = (caddr_t) ses->ses_iv; 1003 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1004 if (crp->crp_flags & CRYPTO_F_IMBUF) 1005 m_copyback(re->re_src_m, 1006 enccrd->crd_inject, ivsize, iv); 1007 else if (crp->crp_flags & CRYPTO_F_IOV) 1008 cuio_copyback(re->re_src_io, 1009 enccrd->crd_inject, ivsize, iv); 1010 } 1011 bcopy(iv, re->re_sastate.sa_saved_iv, ivsize); 1012 cmd0 |= SAFE_SA_CMD0_IVLD_STATE | SAFE_SA_CMD0_SAVEIV; 1013 re->re_flags |= SAFE_QFLAGS_COPYOUTIV; 1014 } else { 1015 cmd0 |= SAFE_SA_CMD0_INBOUND; 1016 1017 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1018 bcopy(enccrd->crd_iv, 1019 re->re_sastate.sa_saved_iv, ivsize); 1020 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1021 m_copydata(re->re_src_m, enccrd->crd_inject, 1022 ivsize, 1023 (caddr_t)re->re_sastate.sa_saved_iv); 1024 else if (crp->crp_flags & CRYPTO_F_IOV) 1025 cuio_copydata(re->re_src_io, enccrd->crd_inject, 1026 ivsize, 1027 (caddr_t)re->re_sastate.sa_saved_iv); 1028 cmd0 |= SAFE_SA_CMD0_IVLD_STATE; 1029 } 1030 /* 1031 * For basic encryption use the zero pad algorithm. 1032 * This pads results to an 8-byte boundary and 1033 * suppresses padding verification for inbound (i.e. 1034 * decrypt) operations. 1035 * 1036 * NB: Not sure if the 8-byte pad boundary is a problem. 1037 */ 1038 cmd0 |= SAFE_SA_CMD0_PAD_ZERO; 1039 1040 /* XXX assert key bufs have the same size */ 1041 bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key)); 1042 } 1043 1044 if (maccrd) { 1045 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) { 1046 cmd0 |= SAFE_SA_CMD0_MD5; 1047 cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ 1048 } else if (maccrd->crd_alg == CRYPTO_SHA1_HMAC) { 1049 cmd0 |= SAFE_SA_CMD0_SHA1; 1050 cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ 1051 } else { 1052 cmd0 |= SAFE_SA_CMD0_HASH_NULL; 1053 } 1054 /* 1055 * Digest data is loaded from the SA and the hash 1056 * result is saved to the state block where we 1057 * retrieve it for return to the caller. 1058 */ 1059 /* XXX assert digest bufs have the same size */ 1060 bcopy(ses->ses_hminner, sa->sa_indigest, 1061 sizeof(sa->sa_indigest)); 1062 bcopy(ses->ses_hmouter, sa->sa_outdigest, 1063 sizeof(sa->sa_outdigest)); 1064 1065 cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH; 1066 re->re_flags |= SAFE_QFLAGS_COPYOUTICV; 1067 } 1068 1069 if (enccrd && maccrd) { 1070 /* 1071 * The offset from hash data to the start of 1072 * crypt data is the difference in the skips. 1073 */ 1074 bypass = maccrd->crd_skip; 1075 coffset = enccrd->crd_skip - maccrd->crd_skip; 1076 if (coffset < 0) { 1077 DPRINTF(("%s: hash does not precede crypt; " 1078 "mac skip %u enc skip %u\n", 1079 __func__, maccrd->crd_skip, enccrd->crd_skip)); 1080 safestats.st_skipmismatch++; 1081 err = EINVAL; 1082 goto errout; 1083 } 1084 oplen = enccrd->crd_skip + enccrd->crd_len; 1085 if (maccrd->crd_skip + maccrd->crd_len != oplen) { 1086 DPRINTF(("%s: hash amount %u != crypt amount %u\n", 1087 __func__, maccrd->crd_skip + maccrd->crd_len, 1088 oplen)); 1089 safestats.st_lenmismatch++; 1090 err = EINVAL; 1091 goto errout; 1092 } 1093#ifdef SAFE_DEBUG 1094 if (safe_debug) { 1095 printf("mac: skip %d, len %d, inject %d\n", 1096 maccrd->crd_skip, maccrd->crd_len, 1097 maccrd->crd_inject); 1098 printf("enc: skip %d, len %d, inject %d\n", 1099 enccrd->crd_skip, enccrd->crd_len, 1100 enccrd->crd_inject); 1101 printf("bypass %d coffset %d oplen %d\n", 1102 bypass, coffset, oplen); 1103 } 1104#endif 1105 if (coffset & 3) { /* offset must be 32-bit aligned */ 1106 DPRINTF(("%s: coffset %u misaligned\n", 1107 __func__, coffset)); 1108 safestats.st_coffmisaligned++; 1109 err = EINVAL; 1110 goto errout; 1111 } 1112 coffset >>= 2; 1113 if (coffset > 255) { /* offset must be <256 dwords */ 1114 DPRINTF(("%s: coffset %u too big\n", 1115 __func__, coffset)); 1116 safestats.st_cofftoobig++; 1117 err = EINVAL; 1118 goto errout; 1119 } 1120 /* 1121 * Tell the hardware to copy the header to the output. 1122 * The header is defined as the data from the end of 1123 * the bypass to the start of data to be encrypted. 1124 * Typically this is the inline IV. Note that you need 1125 * to do this even if src+dst are the same; it appears 1126 * that w/o this bit the crypted data is written 1127 * immediately after the bypass data. 1128 */ 1129 cmd1 |= SAFE_SA_CMD1_HDRCOPY; 1130 /* 1131 * Disable IP header mutable bit handling. This is 1132 * needed to get correct HMAC calculations. 1133 */ 1134 cmd1 |= SAFE_SA_CMD1_MUTABLE; 1135 } else { 1136 if (enccrd) { 1137 bypass = enccrd->crd_skip; 1138 oplen = bypass + enccrd->crd_len; 1139 } else { 1140 bypass = maccrd->crd_skip; 1141 oplen = bypass + maccrd->crd_len; 1142 } 1143 coffset = 0; 1144 } 1145 /* XXX verify multiple of 4 when using s/g */ 1146 if (bypass > 96) { /* bypass offset must be <= 96 bytes */ 1147 DPRINTF(("%s: bypass %u too big\n", __func__, bypass)); 1148 safestats.st_bypasstoobig++; 1149 err = EINVAL; 1150 goto errout; 1151 } 1152 1153 if (bus_dmamap_create(sc->sc_srcdmat, BUS_DMA_NOWAIT, &re->re_src_map)) { 1154 safestats.st_nomap++; 1155 err = ENOMEM; 1156 goto errout; 1157 } 1158 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1159 if (bus_dmamap_load_mbuf(sc->sc_srcdmat, re->re_src_map, 1160 re->re_src_m, safe_op_cb, 1161 &re->re_src, BUS_DMA_NOWAIT) != 0) { 1162 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1163 re->re_src_map = NULL; 1164 safestats.st_noload++; 1165 err = ENOMEM; 1166 goto errout; 1167 } 1168 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1169 if (bus_dmamap_load_uio(sc->sc_srcdmat, re->re_src_map, 1170 re->re_src_io, safe_op_cb, 1171 &re->re_src, BUS_DMA_NOWAIT) != 0) { 1172 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1173 re->re_src_map = NULL; 1174 safestats.st_noload++; 1175 err = ENOMEM; 1176 goto errout; 1177 } 1178 } 1179 nicealign = safe_dmamap_aligned(&re->re_src); 1180 uniform = safe_dmamap_uniform(&re->re_src); 1181 1182 DPRINTF(("src nicealign %u uniform %u nsegs %u\n", 1183 nicealign, uniform, re->re_src.nsegs)); 1184 if (re->re_src.nsegs > 1) { 1185 re->re_desc.d_src = sc->sc_spalloc.dma_paddr + 1186 ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring); 1187 for (i = 0; i < re->re_src_nsegs; i++) { 1188 /* NB: no need to check if there's space */ 1189 pd = sc->sc_spfree; 1190 if (++(sc->sc_spfree) == sc->sc_springtop) 1191 sc->sc_spfree = sc->sc_spring; 1192 1193 KASSERT((pd->pd_flags&3) == 0 || 1194 (pd->pd_flags&3) == SAFE_PD_DONE, 1195 ("bogus source particle descriptor; flags %x", 1196 pd->pd_flags)); 1197 pd->pd_addr = re->re_src_segs[i].ds_addr; 1198 pd->pd_size = re->re_src_segs[i].ds_len; 1199 pd->pd_flags = SAFE_PD_READY; 1200 } 1201 cmd0 |= SAFE_SA_CMD0_IGATHER; 1202 } else { 1203 /* 1204 * No need for gather, reference the operand directly. 1205 */ 1206 re->re_desc.d_src = re->re_src_segs[0].ds_addr; 1207 } 1208 1209 if (enccrd == NULL && maccrd != NULL) { 1210 /* 1211 * Hash op; no destination needed. 1212 */ 1213 } else { 1214 if (crp->crp_flags & CRYPTO_F_IOV) { 1215 if (!nicealign) { 1216 safestats.st_iovmisaligned++; 1217 err = EINVAL; 1218 goto errout; 1219 } 1220 if (uniform != 1) { 1221 /* 1222 * Source is not suitable for direct use as 1223 * the destination. Create a new scatter/gather 1224 * list based on the destination requirements 1225 * and check if that's ok. 1226 */ 1227 if (bus_dmamap_create(sc->sc_dstdmat, 1228 BUS_DMA_NOWAIT, &re->re_dst_map)) { 1229 safestats.st_nomap++; 1230 err = ENOMEM; 1231 goto errout; 1232 } 1233 if (bus_dmamap_load_uio(sc->sc_dstdmat, 1234 re->re_dst_map, re->re_dst_io, 1235 safe_op_cb, &re->re_dst, 1236 BUS_DMA_NOWAIT) != 0) { 1237 bus_dmamap_destroy(sc->sc_dstdmat, 1238 re->re_dst_map); 1239 re->re_dst_map = NULL; 1240 safestats.st_noload++; 1241 err = ENOMEM; 1242 goto errout; 1243 } 1244 uniform = safe_dmamap_uniform(&re->re_dst); 1245 if (!uniform) { 1246 /* 1247 * There's no way to handle the DMA 1248 * requirements with this uio. We 1249 * could create a separate DMA area for 1250 * the result and then copy it back, 1251 * but for now we just bail and return 1252 * an error. Note that uio requests 1253 * > SAFE_MAX_DSIZE are handled because 1254 * the DMA map and segment list for the 1255 * destination wil result in a 1256 * destination particle list that does 1257 * the necessary scatter DMA. 1258 */ 1259 safestats.st_iovnotuniform++; 1260 err = EINVAL; 1261 goto errout; 1262 } 1263 } else 1264 re->re_dst = re->re_src; 1265 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1266 if (nicealign && uniform == 1) { 1267 /* 1268 * Source layout is suitable for direct 1269 * sharing of the DMA map and segment list. 1270 */ 1271 re->re_dst = re->re_src; 1272 } else if (nicealign && uniform == 2) { 1273 /* 1274 * The source is properly aligned but requires a 1275 * different particle list to handle DMA of the 1276 * result. Create a new map and do the load to 1277 * create the segment list. The particle 1278 * descriptor setup code below will handle the 1279 * rest. 1280 */ 1281 if (bus_dmamap_create(sc->sc_dstdmat, 1282 BUS_DMA_NOWAIT, &re->re_dst_map)) { 1283 safestats.st_nomap++; 1284 err = ENOMEM; 1285 goto errout; 1286 } 1287 if (bus_dmamap_load_mbuf(sc->sc_dstdmat, 1288 re->re_dst_map, re->re_dst_m, 1289 safe_op_cb, &re->re_dst, 1290 BUS_DMA_NOWAIT) != 0) { 1291 bus_dmamap_destroy(sc->sc_dstdmat, 1292 re->re_dst_map); 1293 re->re_dst_map = NULL; 1294 safestats.st_noload++; 1295 err = ENOMEM; 1296 goto errout; 1297 } 1298 } else { /* !(aligned and/or uniform) */ 1299 int totlen, len; 1300 struct mbuf *m, *top, **mp; 1301 1302 /* 1303 * DMA constraints require that we allocate a 1304 * new mbuf chain for the destination. We 1305 * allocate an entire new set of mbufs of 1306 * optimal/required size and then tell the 1307 * hardware to copy any bits that are not 1308 * created as a byproduct of the operation. 1309 */ 1310 if (!nicealign) 1311 safestats.st_unaligned++; 1312 if (!uniform) 1313 safestats.st_notuniform++; 1314 totlen = re->re_src_mapsize; 1315 if (re->re_src_m->m_flags & M_PKTHDR) { 1316 len = MHLEN; 1317 MGETHDR(m, M_DONTWAIT, MT_DATA); 1318 if (m && !m_dup_pkthdr(m, re->re_src_m, 1319 M_DONTWAIT)) { 1320 m_free(m); 1321 m = NULL; 1322 } 1323 } else { 1324 len = MLEN; 1325 MGET(m, M_DONTWAIT, MT_DATA); 1326 } 1327 if (m == NULL) { 1328 safestats.st_nombuf++; 1329 err = sc->sc_nqchip ? ERESTART : ENOMEM; 1330 goto errout; 1331 } 1332 if (totlen >= MINCLSIZE) { 1333 MCLGET(m, M_DONTWAIT); 1334 if ((m->m_flags & M_EXT) == 0) { 1335 m_free(m); 1336 safestats.st_nomcl++; 1337 err = sc->sc_nqchip ? 1338 ERESTART : ENOMEM; 1339 goto errout; 1340 } 1341 len = MCLBYTES; 1342 } 1343 m->m_len = len; 1344 top = NULL; 1345 mp = ⊤ 1346 1347 while (totlen > 0) { 1348 if (top) { 1349 MGET(m, M_DONTWAIT, MT_DATA); 1350 if (m == NULL) { 1351 m_freem(top); 1352 safestats.st_nombuf++; 1353 err = sc->sc_nqchip ? 1354 ERESTART : ENOMEM; 1355 goto errout; 1356 } 1357 len = MLEN; 1358 } 1359 if (top && totlen >= MINCLSIZE) { 1360 MCLGET(m, M_DONTWAIT); 1361 if ((m->m_flags & M_EXT) == 0) { 1362 *mp = m; 1363 m_freem(top); 1364 safestats.st_nomcl++; 1365 err = sc->sc_nqchip ? 1366 ERESTART : ENOMEM; 1367 goto errout; 1368 } 1369 len = MCLBYTES; 1370 } 1371 m->m_len = len = min(totlen, len); 1372 totlen -= len; 1373 *mp = m; 1374 mp = &m->m_next; 1375 } 1376 re->re_dst_m = top; 1377 if (bus_dmamap_create(sc->sc_dstdmat, 1378 BUS_DMA_NOWAIT, &re->re_dst_map) != 0) { 1379 safestats.st_nomap++; 1380 err = ENOMEM; 1381 goto errout; 1382 } 1383 if (bus_dmamap_load_mbuf(sc->sc_dstdmat, 1384 re->re_dst_map, re->re_dst_m, 1385 safe_op_cb, &re->re_dst, 1386 BUS_DMA_NOWAIT) != 0) { 1387 bus_dmamap_destroy(sc->sc_dstdmat, 1388 re->re_dst_map); 1389 re->re_dst_map = NULL; 1390 safestats.st_noload++; 1391 err = ENOMEM; 1392 goto errout; 1393 } 1394 if (re->re_src.mapsize > oplen) { 1395 /* 1396 * There's data following what the 1397 * hardware will copy for us. If this 1398 * isn't just the ICV (that's going to 1399 * be written on completion), copy it 1400 * to the new mbufs 1401 */ 1402 if (!(maccrd && 1403 (re->re_src.mapsize-oplen) == 12 && 1404 maccrd->crd_inject == oplen)) 1405 safe_mcopy(re->re_src_m, 1406 re->re_dst_m, 1407 oplen); 1408 else 1409 safestats.st_noicvcopy++; 1410 } 1411 } 1412 } else { 1413 safestats.st_badflags++; 1414 err = EINVAL; 1415 goto errout; 1416 } 1417 1418 if (re->re_dst.nsegs > 1) { 1419 re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr + 1420 ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring); 1421 for (i = 0; i < re->re_dst_nsegs; i++) { 1422 pd = sc->sc_dpfree; 1423 KASSERT((pd->pd_flags&3) == 0 || 1424 (pd->pd_flags&3) == SAFE_PD_DONE, 1425 ("bogus dest particle descriptor; flags %x", 1426 pd->pd_flags)); 1427 if (++(sc->sc_dpfree) == sc->sc_dpringtop) 1428 sc->sc_dpfree = sc->sc_dpring; 1429 pd->pd_addr = re->re_dst_segs[i].ds_addr; 1430 pd->pd_flags = SAFE_PD_READY; 1431 } 1432 cmd0 |= SAFE_SA_CMD0_OSCATTER; 1433 } else { 1434 /* 1435 * No need for scatter, reference the operand directly. 1436 */ 1437 re->re_desc.d_dst = re->re_dst_segs[0].ds_addr; 1438 } 1439 } 1440 1441 /* 1442 * All done with setup; fillin the SA command words 1443 * and the packet engine descriptor. The operation 1444 * is now ready for submission to the hardware. 1445 */ 1446 sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI; 1447 sa->sa_cmd1 = cmd1 1448 | (coffset << SAFE_SA_CMD1_OFFSET_S) 1449 | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */ 1450 | SAFE_SA_CMD1_SRPCI 1451 ; 1452 /* 1453 * NB: the order of writes is important here. In case the 1454 * chip is scanning the ring because of an outstanding request 1455 * it might nab this one too. In that case we need to make 1456 * sure the setup is complete before we write the length 1457 * field of the descriptor as it signals the descriptor is 1458 * ready for processing. 1459 */ 1460 re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI; 1461 if (maccrd) 1462 re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL; 1463 re->re_desc.d_len = oplen 1464 | SAFE_PE_LEN_READY 1465 | (bypass << SAFE_PE_LEN_BYPASS_S) 1466 ; 1467 1468 safestats.st_ipackets++; 1469 safestats.st_ibytes += oplen; 1470 1471 if (++(sc->sc_front) == sc->sc_ringtop) 1472 sc->sc_front = sc->sc_ring; 1473 1474 /* XXX honor batching */ 1475 safe_feed(sc, re); 1476 mtx_unlock(&sc->sc_ringmtx); 1477 return (0); 1478 1479errout: 1480 if ((re->re_dst_m != NULL) && (re->re_src_m != re->re_dst_m)) 1481 m_freem(re->re_dst_m); 1482 1483 if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) { 1484 bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map); 1485 bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map); 1486 } 1487 if (re->re_src_map != NULL) { 1488 bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map); 1489 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1490 } 1491 mtx_unlock(&sc->sc_ringmtx); 1492 if (err != ERESTART) { 1493 crp->crp_etype = err; 1494 crypto_done(crp); 1495 } else { 1496 sc->sc_needwakeup |= CRYPTO_SYMQ; 1497 } 1498 return (err); 1499} 1500 1501static void 1502safe_callback(struct safe_softc *sc, struct safe_ringentry *re) 1503{ 1504 struct cryptop *crp = (struct cryptop *)re->re_crp; 1505 struct cryptodesc *crd; 1506 1507 safestats.st_opackets++; 1508 safestats.st_obytes += re->re_dst.mapsize; 1509 1510 safe_dma_sync(&sc->sc_ringalloc, 1511 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1512 if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) { 1513 device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n", 1514 re->re_desc.d_csr, 1515 re->re_sa.sa_cmd0, re->re_sa.sa_cmd1); 1516 safestats.st_peoperr++; 1517 crp->crp_etype = EIO; /* something more meaningful? */ 1518 } 1519 if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) { 1520 bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map, 1521 BUS_DMASYNC_POSTREAD); 1522 bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map); 1523 bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map); 1524 } 1525 bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_POSTWRITE); 1526 bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map); 1527 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1528 1529 /* 1530 * If result was written to a differet mbuf chain, swap 1531 * it in as the return value and reclaim the original. 1532 */ 1533 if ((crp->crp_flags & CRYPTO_F_IMBUF) && re->re_src_m != re->re_dst_m) { 1534 m_freem(re->re_src_m); 1535 crp->crp_buf = (caddr_t)re->re_dst_m; 1536 } 1537 1538 if (re->re_flags & SAFE_QFLAGS_COPYOUTIV) { 1539 /* copy out IV for future use */ 1540 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1541 int ivsize; 1542 1543 if (crd->crd_alg == CRYPTO_DES_CBC || 1544 crd->crd_alg == CRYPTO_3DES_CBC) { 1545 ivsize = 2*sizeof(u_int32_t); 1546 } else if (crd->crd_alg == CRYPTO_AES_CBC) { 1547 ivsize = 4*sizeof(u_int32_t); 1548 } else 1549 continue; 1550 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1551 m_copydata((struct mbuf *)crp->crp_buf, 1552 crd->crd_skip + crd->crd_len - ivsize, 1553 ivsize, 1554 (caddr_t) sc->sc_sessions[re->re_sesn].ses_iv); 1555 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1556 cuio_copydata((struct uio *)crp->crp_buf, 1557 crd->crd_skip + crd->crd_len - ivsize, 1558 ivsize, 1559 (caddr_t)sc->sc_sessions[re->re_sesn].ses_iv); 1560 } 1561 break; 1562 } 1563 } 1564 1565 if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) { 1566 /* copy out ICV result */ 1567 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1568 if (!(crd->crd_alg == CRYPTO_MD5_HMAC || 1569 crd->crd_alg == CRYPTO_SHA1_HMAC || 1570 crd->crd_alg == CRYPTO_NULL_HMAC)) 1571 continue; 1572 if (crd->crd_alg == CRYPTO_SHA1_HMAC) { 1573 /* 1574 * SHA-1 ICV's are byte-swapped; fix 'em up 1575 * before copy them to their destination. 1576 */ 1577 bswap32(re->re_sastate.sa_saved_indigest[0]); 1578 bswap32(re->re_sastate.sa_saved_indigest[1]); 1579 bswap32(re->re_sastate.sa_saved_indigest[2]); 1580 } 1581 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1582 m_copyback((struct mbuf *)crp->crp_buf, 1583 crd->crd_inject, 12, 1584 (caddr_t)re->re_sastate.sa_saved_indigest); 1585 } else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) { 1586 bcopy((caddr_t)re->re_sastate.sa_saved_indigest, 1587 crp->crp_mac, 12); 1588 } 1589 break; 1590 } 1591 } 1592 crypto_done(crp); 1593} 1594 1595/* 1596 * Copy all data past offset from srcm to dstm. 1597 */ 1598static void 1599safe_mcopy(struct mbuf *srcm, struct mbuf *dstm, u_int offset) 1600{ 1601 u_int j, dlen, slen; 1602 caddr_t dptr, sptr; 1603 1604 /* 1605 * Advance src and dst to offset. 1606 */ 1607 j = offset; 1608 while (j >= 0) { 1609 if (srcm->m_len > j) 1610 break; 1611 j -= srcm->m_len; 1612 srcm = srcm->m_next; 1613 if (srcm == NULL) 1614 return; 1615 } 1616 sptr = mtod(srcm, caddr_t) + j; 1617 slen = srcm->m_len - j; 1618 1619 j = offset; 1620 while (j >= 0) { 1621 if (dstm->m_len > j) 1622 break; 1623 j -= dstm->m_len; 1624 dstm = dstm->m_next; 1625 if (dstm == NULL) 1626 return; 1627 } 1628 dptr = mtod(dstm, caddr_t) + j; 1629 dlen = dstm->m_len - j; 1630 1631 /* 1632 * Copy everything that remains. 1633 */ 1634 for (;;) { 1635 j = min(slen, dlen); 1636 bcopy(sptr, dptr, j); 1637 if (slen == j) { 1638 srcm = srcm->m_next; 1639 if (srcm == NULL) 1640 return; 1641 sptr = srcm->m_data; 1642 slen = srcm->m_len; 1643 } else 1644 sptr += j, slen -= j; 1645 if (dlen == j) { 1646 dstm = dstm->m_next; 1647 if (dstm == NULL) 1648 return; 1649 dptr = dstm->m_data; 1650 dlen = dstm->m_len; 1651 } else 1652 dptr += j, dlen -= j; 1653 } 1654} 1655 1656#ifndef SAFE_NO_RNG 1657#define SAFE_RNG_MAXWAIT 1000 1658 1659static void 1660safe_rng_init(struct safe_softc *sc) 1661{ 1662 u_int32_t w, v; 1663 int i; 1664 1665 WRITE_REG(sc, SAFE_RNG_CTRL, 0); 1666 /* use default value according to the manual */ 1667 WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */ 1668 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1669 1670 /* 1671 * There is a bug in rev 1.0 of the 1140 that when the RNG 1672 * is brought out of reset the ready status flag does not 1673 * work until the RNG has finished its internal initialization. 1674 * 1675 * So in order to determine the device is through its 1676 * initialization we must read the data register, using the 1677 * status reg in the read in case it is initialized. Then read 1678 * the data register until it changes from the first read. 1679 * Once it changes read the data register until it changes 1680 * again. At this time the RNG is considered initialized. 1681 * This could take between 750ms - 1000ms in time. 1682 */ 1683 i = 0; 1684 w = READ_REG(sc, SAFE_RNG_OUT); 1685 do { 1686 v = READ_REG(sc, SAFE_RNG_OUT); 1687 if (v != w) { 1688 w = v; 1689 break; 1690 } 1691 DELAY(10); 1692 } while (++i < SAFE_RNG_MAXWAIT); 1693 1694 /* Wait Until data changes again */ 1695 i = 0; 1696 do { 1697 v = READ_REG(sc, SAFE_RNG_OUT); 1698 if (v != w) 1699 break; 1700 DELAY(10); 1701 } while (++i < SAFE_RNG_MAXWAIT); 1702} 1703 1704static __inline void 1705safe_rng_disable_short_cycle(struct safe_softc *sc) 1706{ 1707 WRITE_REG(sc, SAFE_RNG_CTRL, 1708 READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN); 1709} 1710 1711static __inline void 1712safe_rng_enable_short_cycle(struct safe_softc *sc) 1713{ 1714 WRITE_REG(sc, SAFE_RNG_CTRL, 1715 READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN); 1716} 1717 1718static __inline u_int32_t 1719safe_rng_read(struct safe_softc *sc) 1720{ 1721 int i; 1722 1723 i = 0; 1724 while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT) 1725 ; 1726 return READ_REG(sc, SAFE_RNG_OUT); 1727} 1728 1729static void 1730safe_rng(void *arg) 1731{ 1732 struct safe_softc *sc = arg; 1733 u_int32_t buf[SAFE_RNG_MAXBUFSIZ]; /* NB: maybe move to softc */ 1734 u_int maxwords; 1735 int i; 1736 1737 safestats.st_rng++; 1738 /* 1739 * Fetch the next block of data. 1740 */ 1741 maxwords = safe_rngbufsize; 1742 if (maxwords > SAFE_RNG_MAXBUFSIZ) 1743 maxwords = SAFE_RNG_MAXBUFSIZ; 1744retry: 1745 for (i = 0; i < maxwords; i++) 1746 buf[i] = safe_rng_read(sc); 1747 /* 1748 * Check the comparator alarm count and reset the h/w if 1749 * it exceeds our threshold. This guards against the 1750 * hardware oscillators resonating with external signals. 1751 */ 1752 if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) { 1753 u_int32_t freq_inc, w; 1754 1755 DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__, 1756 READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm)); 1757 safestats.st_rngalarm++; 1758 safe_rng_enable_short_cycle(sc); 1759 freq_inc = 18; 1760 for (i = 0; i < 64; i++) { 1761 w = READ_REG(sc, SAFE_RNG_CNFG); 1762 freq_inc = ((w + freq_inc) & 0x3fL); 1763 w = ((w & ~0x3fL) | freq_inc); 1764 WRITE_REG(sc, SAFE_RNG_CNFG, w); 1765 1766 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1767 1768 (void) safe_rng_read(sc); 1769 DELAY(25); 1770 1771 if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) { 1772 safe_rng_disable_short_cycle(sc); 1773 goto retry; 1774 } 1775 freq_inc = 1; 1776 } 1777 safe_rng_disable_short_cycle(sc); 1778 } else 1779 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1780 1781 (*sc->sc_harvest)(sc->sc_rndtest, buf, maxwords*sizeof (u_int32_t)); 1782 callout_reset(&sc->sc_rngto, 1783 hz * (safe_rnginterval ? safe_rnginterval : 1), safe_rng, sc); 1784} 1785#endif /* SAFE_NO_RNG */ 1786 1787static void 1788safe_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1789{ 1790 bus_addr_t *paddr = (bus_addr_t*) arg; 1791 *paddr = segs->ds_addr; 1792} 1793 1794static int 1795safe_dma_malloc( 1796 struct safe_softc *sc, 1797 bus_size_t size, 1798 struct safe_dma_alloc *dma, 1799 int mapflags 1800) 1801{ 1802 int r; 1803 1804 r = bus_dma_tag_create(NULL, /* parent */ 1805 sizeof(u_int32_t), 0, /* alignment, bounds */ 1806 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1807 BUS_SPACE_MAXADDR, /* highaddr */ 1808 NULL, NULL, /* filter, filterarg */ 1809 size, /* maxsize */ 1810 1, /* nsegments */ 1811 size, /* maxsegsize */ 1812 BUS_DMA_ALLOCNOW, /* flags */ 1813 NULL, NULL, /* locking */ 1814 &dma->dma_tag); 1815 if (r != 0) { 1816 device_printf(sc->sc_dev, "safe_dma_malloc: " 1817 "bus_dma_tag_create failed; error %u\n", r); 1818 goto fail_0; 1819 } 1820 1821 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map); 1822 if (r != 0) { 1823 device_printf(sc->sc_dev, "safe_dma_malloc: " 1824 "bus_dmamap_create failed; error %u\n", r); 1825 goto fail_1; 1826 } 1827 1828 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 1829 BUS_DMA_NOWAIT, &dma->dma_map); 1830 if (r != 0) { 1831 device_printf(sc->sc_dev, "safe_dma_malloc: " 1832 "bus_dmammem_alloc failed; size %zu, error %u\n", 1833 size, r); 1834 goto fail_2; 1835 } 1836 1837 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 1838 size, 1839 safe_dmamap_cb, 1840 &dma->dma_paddr, 1841 mapflags | BUS_DMA_NOWAIT); 1842 if (r != 0) { 1843 device_printf(sc->sc_dev, "safe_dma_malloc: " 1844 "bus_dmamap_load failed; error %u\n", r); 1845 goto fail_3; 1846 } 1847 1848 dma->dma_size = size; 1849 return (0); 1850 1851fail_3: 1852 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1853fail_2: 1854 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1855fail_1: 1856 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1857 bus_dma_tag_destroy(dma->dma_tag); 1858fail_0: 1859 dma->dma_map = NULL; 1860 dma->dma_tag = NULL; 1861 return (r); 1862} 1863 1864static void 1865safe_dma_free(struct safe_softc *sc, struct safe_dma_alloc *dma) 1866{ 1867 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1868 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1869 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1870 bus_dma_tag_destroy(dma->dma_tag); 1871} 1872 1873/* 1874 * Resets the board. Values in the regesters are left as is 1875 * from the reset (i.e. initial values are assigned elsewhere). 1876 */ 1877static void 1878safe_reset_board(struct safe_softc *sc) 1879{ 1880 u_int32_t v; 1881 /* 1882 * Reset the device. The manual says no delay 1883 * is needed between marking and clearing reset. 1884 */ 1885 v = READ_REG(sc, SAFE_PE_DMACFG) &~ 1886 (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET | 1887 SAFE_PE_DMACFG_SGRESET); 1888 WRITE_REG(sc, SAFE_PE_DMACFG, v 1889 | SAFE_PE_DMACFG_PERESET 1890 | SAFE_PE_DMACFG_PDRRESET 1891 | SAFE_PE_DMACFG_SGRESET); 1892 WRITE_REG(sc, SAFE_PE_DMACFG, v); 1893} 1894 1895/* 1896 * Initialize registers we need to touch only once. 1897 */ 1898static void 1899safe_init_board(struct safe_softc *sc) 1900{ 1901 u_int32_t v, dwords; 1902 1903 v = READ_REG(sc, SAFE_PE_DMACFG);; 1904 v &=~ SAFE_PE_DMACFG_PEMODE; 1905 v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */ 1906 | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ 1907 | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ 1908 | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ 1909 | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ 1910 | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ 1911 ; 1912 WRITE_REG(sc, SAFE_PE_DMACFG, v); 1913#if 0 1914 /* XXX select byte swap based on host byte order */ 1915 WRITE_REG(sc, SAFE_ENDIAN, 0x1b); 1916#endif 1917 if (sc->sc_chiprev == SAFE_REV(1,0)) { 1918 /* 1919 * Avoid large PCI DMA transfers. Rev 1.0 has a bug where 1920 * "target mode transfers" done while the chip is DMA'ing 1921 * >1020 bytes cause the hardware to lockup. To avoid this 1922 * we reduce the max PCI transfer size and use small source 1923 * particle descriptors (<= 256 bytes). 1924 */ 1925 WRITE_REG(sc, SAFE_DMA_CFG, 256); 1926 device_printf(sc->sc_dev, 1927 "Reduce max DMA size to %u words for rev %u.%u WAR\n", 1928 (READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff, 1929 SAFE_REV_MAJ(sc->sc_chiprev), 1930 SAFE_REV_MIN(sc->sc_chiprev)); 1931 } 1932 1933 /* NB: operands+results are overlaid */ 1934 WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr); 1935 WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr); 1936 /* 1937 * Configure ring entry size and number of items in the ring. 1938 */ 1939 KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0, 1940 ("PE ring entry not 32-bit aligned!")); 1941 dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t); 1942 WRITE_REG(sc, SAFE_PE_RINGCFG, 1943 (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE); 1944 WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */ 1945 1946 WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr); 1947 WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr); 1948 WRITE_REG(sc, SAFE_PE_PARTSIZE, 1949 (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART); 1950 /* 1951 * NB: destination particles are fixed size. We use 1952 * an mbuf cluster and require all results go to 1953 * clusters or smaller. 1954 */ 1955 WRITE_REG(sc, SAFE_PE_PARTCFG, SAFE_MAX_DSIZE); 1956 1957 /* it's now safe to enable PE mode, do it */ 1958 WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE); 1959 1960 /* 1961 * Configure hardware to use level-triggered interrupts and 1962 * to interrupt after each descriptor is processed. 1963 */ 1964 WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL); 1965 WRITE_REG(sc, SAFE_HI_DESC_CNT, 1); 1966 WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR); 1967} 1968 1969/* 1970 * Init PCI registers 1971 */ 1972static void 1973safe_init_pciregs(device_t dev) 1974{ 1975} 1976 1977/* 1978 * Clean up after a chip crash. 1979 * It is assumed that the caller in splimp() 1980 */ 1981static void 1982safe_cleanchip(struct safe_softc *sc) 1983{ 1984 1985 if (sc->sc_nqchip != 0) { 1986 struct safe_ringentry *re = sc->sc_back; 1987 1988 while (re != sc->sc_front) { 1989 if (re->re_desc.d_csr != 0) 1990 safe_free_entry(sc, re); 1991 if (++re == sc->sc_ringtop) 1992 re = sc->sc_ring; 1993 } 1994 sc->sc_back = re; 1995 sc->sc_nqchip = 0; 1996 } 1997} 1998 1999/* 2000 * free a safe_q 2001 * It is assumed that the caller is within splimp(). 2002 */ 2003static int 2004safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re) 2005{ 2006 struct cryptop *crp; 2007 2008 /* 2009 * Free header MCR 2010 */ 2011 if ((re->re_dst_m != NULL) && (re->re_src_m != re->re_dst_m)) 2012 m_freem(re->re_dst_m); 2013 2014 crp = (struct cryptop *)re->re_crp; 2015 2016 re->re_desc.d_csr = 0; 2017 2018 crp->crp_etype = EFAULT; 2019 crypto_done(crp); 2020 return(0); 2021} 2022 2023/* 2024 * Routine to reset the chip and clean up. 2025 * It is assumed that the caller is in splimp() 2026 */ 2027static void 2028safe_totalreset(struct safe_softc *sc) 2029{ 2030 safe_reset_board(sc); 2031 safe_init_board(sc); 2032 safe_cleanchip(sc); 2033} 2034 2035/* 2036 * Is the operand suitable aligned for direct DMA. Each 2037 * segment must be aligned on a 32-bit boundary and all 2038 * but the last segment must be a multiple of 4 bytes. 2039 */ 2040static int 2041safe_dmamap_aligned(const struct safe_operand *op) 2042{ 2043 int i; 2044 2045 for (i = 0; i < op->nsegs; i++) { 2046 if (op->segs[i].ds_addr & 3) 2047 return (0); 2048 if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3)) 2049 return (0); 2050 } 2051 return (1); 2052} 2053 2054/* 2055 * Is the operand suitable for direct DMA as the destination 2056 * of an operation. The hardware requires that each ``particle'' 2057 * but the last in an operation result have the same size. We 2058 * fix that size at SAFE_MAX_DSIZE bytes. This routine returns 2059 * 0 if some segment is not a multiple of of this size, 1 if all 2060 * segments are exactly this size, or 2 if segments are at worst 2061 * a multple of this size. 2062 */ 2063static int 2064safe_dmamap_uniform(const struct safe_operand *op) 2065{ 2066 int result = 1; 2067 2068 if (op->nsegs > 0) { 2069 int i; 2070 2071 for (i = 0; i < op->nsegs-1; i++) { 2072 if (op->segs[i].ds_len % SAFE_MAX_DSIZE) 2073 return (0); 2074 if (op->segs[i].ds_len != SAFE_MAX_DSIZE) 2075 result = 2; 2076 } 2077 } 2078 return (result); 2079} 2080 2081#ifdef SAFE_DEBUG 2082static void 2083safe_dump_dmastatus(struct safe_softc *sc, const char *tag) 2084{ 2085 printf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n" 2086 , tag 2087 , READ_REG(sc, SAFE_DMA_ENDIAN) 2088 , READ_REG(sc, SAFE_DMA_SRCADDR) 2089 , READ_REG(sc, SAFE_DMA_DSTADDR) 2090 , READ_REG(sc, SAFE_DMA_STAT) 2091 ); 2092} 2093 2094static void 2095safe_dump_intrstate(struct safe_softc *sc, const char *tag) 2096{ 2097 printf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n" 2098 , tag 2099 , READ_REG(sc, SAFE_HI_CFG) 2100 , READ_REG(sc, SAFE_HI_MASK) 2101 , READ_REG(sc, SAFE_HI_DESC_CNT) 2102 , READ_REG(sc, SAFE_HU_STAT) 2103 , READ_REG(sc, SAFE_HM_STAT) 2104 ); 2105} 2106 2107static void 2108safe_dump_ringstate(struct safe_softc *sc, const char *tag) 2109{ 2110 u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT); 2111 2112 /* NB: assume caller has lock on ring */ 2113 printf("%s: ERNGSTAT %x (next %u) back %lu front %lu\n", 2114 tag, 2115 estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S), 2116 (unsigned long)(sc->sc_back - sc->sc_ring), 2117 (unsigned long)(sc->sc_front - sc->sc_ring)); 2118} 2119 2120static void 2121safe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re) 2122{ 2123 int ix, nsegs; 2124 2125 ix = re - sc->sc_ring; 2126 printf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n" 2127 , tag 2128 , re, ix 2129 , re->re_desc.d_csr 2130 , re->re_desc.d_src 2131 , re->re_desc.d_dst 2132 , re->re_desc.d_sa 2133 , re->re_desc.d_len 2134 ); 2135 if (re->re_src.nsegs > 1) { 2136 ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) / 2137 sizeof(struct safe_pdesc); 2138 for (nsegs = re->re_src.nsegs; nsegs; nsegs--) { 2139 printf(" spd[%u] %p: %p size %u flags %x" 2140 , ix, &sc->sc_spring[ix] 2141 , (caddr_t)(uintptr_t) sc->sc_spring[ix].pd_addr 2142 , sc->sc_spring[ix].pd_size 2143 , sc->sc_spring[ix].pd_flags 2144 ); 2145 if (sc->sc_spring[ix].pd_size == 0) 2146 printf(" (zero!)"); 2147 printf("\n"); 2148 if (++ix == SAFE_TOTAL_SPART) 2149 ix = 0; 2150 } 2151 } 2152 if (re->re_dst.nsegs > 1) { 2153 ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) / 2154 sizeof(struct safe_pdesc); 2155 for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) { 2156 printf(" dpd[%u] %p: %p flags %x\n" 2157 , ix, &sc->sc_dpring[ix] 2158 , (caddr_t)(uintptr_t) sc->sc_dpring[ix].pd_addr 2159 , sc->sc_dpring[ix].pd_flags 2160 ); 2161 if (++ix == SAFE_TOTAL_DPART) 2162 ix = 0; 2163 } 2164 } 2165 printf("sa: cmd0 %08x cmd1 %08x staterec %x\n", 2166 re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec); 2167 printf("sa: key %x %x %x %x %x %x %x %x\n" 2168 , re->re_sa.sa_key[0] 2169 , re->re_sa.sa_key[1] 2170 , re->re_sa.sa_key[2] 2171 , re->re_sa.sa_key[3] 2172 , re->re_sa.sa_key[4] 2173 , re->re_sa.sa_key[5] 2174 , re->re_sa.sa_key[6] 2175 , re->re_sa.sa_key[7] 2176 ); 2177 printf("sa: indigest %x %x %x %x %x\n" 2178 , re->re_sa.sa_indigest[0] 2179 , re->re_sa.sa_indigest[1] 2180 , re->re_sa.sa_indigest[2] 2181 , re->re_sa.sa_indigest[3] 2182 , re->re_sa.sa_indigest[4] 2183 ); 2184 printf("sa: outdigest %x %x %x %x %x\n" 2185 , re->re_sa.sa_outdigest[0] 2186 , re->re_sa.sa_outdigest[1] 2187 , re->re_sa.sa_outdigest[2] 2188 , re->re_sa.sa_outdigest[3] 2189 , re->re_sa.sa_outdigest[4] 2190 ); 2191 printf("sr: iv %x %x %x %x\n" 2192 , re->re_sastate.sa_saved_iv[0] 2193 , re->re_sastate.sa_saved_iv[1] 2194 , re->re_sastate.sa_saved_iv[2] 2195 , re->re_sastate.sa_saved_iv[3] 2196 ); 2197 printf("sr: hashbc %u indigest %x %x %x %x %x\n" 2198 , re->re_sastate.sa_saved_hashbc 2199 , re->re_sastate.sa_saved_indigest[0] 2200 , re->re_sastate.sa_saved_indigest[1] 2201 , re->re_sastate.sa_saved_indigest[2] 2202 , re->re_sastate.sa_saved_indigest[3] 2203 , re->re_sastate.sa_saved_indigest[4] 2204 ); 2205} 2206 2207static void 2208safe_dump_ring(struct safe_softc *sc, const char *tag) 2209{ 2210 mtx_lock(&sc->sc_ringmtx); 2211 printf("\nSafeNet Ring State:\n"); 2212 safe_dump_intrstate(sc, tag); 2213 safe_dump_dmastatus(sc, tag); 2214 safe_dump_ringstate(sc, tag); 2215 if (sc->sc_nqchip) { 2216 struct safe_ringentry *re = sc->sc_back; 2217 do { 2218 safe_dump_request(sc, tag, re); 2219 if (++re == sc->sc_ringtop) 2220 re = sc->sc_ring; 2221 } while (re != sc->sc_front); 2222 } 2223 mtx_unlock(&sc->sc_ringmtx); 2224} 2225 2226static int 2227sysctl_hw_safe_dump(SYSCTL_HANDLER_ARGS) 2228{ 2229 char dmode[64]; 2230 int error; 2231 2232 strncpy(dmode, "", sizeof(dmode) - 1); 2233 dmode[sizeof(dmode) - 1] = '\0'; 2234 error = sysctl_handle_string(oidp, &dmode[0], sizeof(dmode), req); 2235 2236 if (error == 0 && req->newptr != NULL) { 2237 struct safe_softc *sc = safec; 2238 2239 if (!sc) 2240 return EINVAL; 2241 if (strncmp(dmode, "dma", 3) == 0) 2242 safe_dump_dmastatus(sc, "safe0"); 2243 else if (strncmp(dmode, "int", 3) == 0) 2244 safe_dump_intrstate(sc, "safe0"); 2245 else if (strncmp(dmode, "ring", 4) == 0) 2246 safe_dump_ring(sc, "safe0"); 2247 else 2248 return EINVAL; 2249 } 2250 return error; 2251} 2252SYSCTL_PROC(_hw_safe, OID_AUTO, dump, CTLTYPE_STRING | CTLFLAG_RW, 2253 0, 0, sysctl_hw_safe_dump, "A", "Dump driver state"); 2254#endif /* SAFE_DEBUG */ 2255