safe.c revision 223026
1117845Ssam/*- 2117845Ssam * Copyright (c) 2003 Sam Leffler, Errno Consulting 3117845Ssam * Copyright (c) 2003 Global Technology Associates, Inc. 4117845Ssam * All rights reserved. 5117845Ssam * 6117845Ssam * Redistribution and use in source and binary forms, with or without 7117845Ssam * modification, are permitted provided that the following conditions 8117845Ssam * are met: 9117845Ssam * 1. Redistributions of source code must retain the above copyright 10117845Ssam * notice, this list of conditions and the following disclaimer. 11117845Ssam * 2. Redistributions in binary form must reproduce the above copyright 12117845Ssam * notice, this list of conditions and the following disclaimer in the 13117845Ssam * documentation and/or other materials provided with the distribution. 14117845Ssam * 15117845Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16117845Ssam * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17117845Ssam * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18117845Ssam * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19117845Ssam * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20117845Ssam * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21117845Ssam * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22117845Ssam * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23117845Ssam * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24117845Ssam * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25117845Ssam * SUCH DAMAGE. 26117845Ssam */ 27117845Ssam 28117845Ssam#include <sys/cdefs.h> 29117845Ssam__FBSDID("$FreeBSD: head/sys/dev/safe/safe.c 223026 2011-06-12 23:33:08Z delphij $"); 30117845Ssam 31117845Ssam/* 32117845Ssam * SafeNet SafeXcel-1141 hardware crypto accelerator 33117845Ssam */ 34117845Ssam#include "opt_safe.h" 35117845Ssam 36117845Ssam#include <sys/param.h> 37117845Ssam#include <sys/systm.h> 38117845Ssam#include <sys/proc.h> 39117845Ssam#include <sys/errno.h> 40117845Ssam#include <sys/malloc.h> 41117845Ssam#include <sys/kernel.h> 42117845Ssam#include <sys/mbuf.h> 43129879Sphk#include <sys/module.h> 44117845Ssam#include <sys/lock.h> 45117845Ssam#include <sys/mutex.h> 46117845Ssam#include <sys/sysctl.h> 47117845Ssam#include <sys/endian.h> 48117845Ssam 49117845Ssam#include <vm/vm.h> 50117845Ssam#include <vm/pmap.h> 51117845Ssam 52117845Ssam#include <machine/bus.h> 53117845Ssam#include <machine/resource.h> 54117845Ssam#include <sys/bus.h> 55117845Ssam#include <sys/rman.h> 56117845Ssam 57117845Ssam#include <crypto/sha1.h> 58117845Ssam#include <opencrypto/cryptodev.h> 59117845Ssam#include <opencrypto/cryptosoft.h> 60117845Ssam#include <sys/md5.h> 61117845Ssam#include <sys/random.h> 62167755Ssam#include <sys/kobj.h> 63117845Ssam 64167755Ssam#include "cryptodev_if.h" 65167755Ssam 66119287Simp#include <dev/pci/pcivar.h> 67119287Simp#include <dev/pci/pcireg.h> 68117845Ssam 69117845Ssam#ifdef SAFE_RNDTEST 70117845Ssam#include <dev/rndtest/rndtest.h> 71117845Ssam#endif 72117845Ssam#include <dev/safe/safereg.h> 73117845Ssam#include <dev/safe/safevar.h> 74117845Ssam 75117845Ssam#ifndef bswap32 76117845Ssam#define bswap32 NTOHL 77117845Ssam#endif 78117845Ssam 79117845Ssam/* 80117845Ssam * Prototypes and count for the pci_device structure 81117845Ssam */ 82117845Ssamstatic int safe_probe(device_t); 83117845Ssamstatic int safe_attach(device_t); 84117845Ssamstatic int safe_detach(device_t); 85117845Ssamstatic int safe_suspend(device_t); 86117845Ssamstatic int safe_resume(device_t); 87188178Simpstatic int safe_shutdown(device_t); 88117845Ssam 89167755Ssamstatic int safe_newsession(device_t, u_int32_t *, struct cryptoini *); 90167755Ssamstatic int safe_freesession(device_t, u_int64_t); 91167755Ssamstatic int safe_process(device_t, struct cryptop *, int); 92167755Ssam 93117845Ssamstatic device_method_t safe_methods[] = { 94117845Ssam /* Device interface */ 95117845Ssam DEVMETHOD(device_probe, safe_probe), 96117845Ssam DEVMETHOD(device_attach, safe_attach), 97117845Ssam DEVMETHOD(device_detach, safe_detach), 98117845Ssam DEVMETHOD(device_suspend, safe_suspend), 99117845Ssam DEVMETHOD(device_resume, safe_resume), 100117845Ssam DEVMETHOD(device_shutdown, safe_shutdown), 101117845Ssam 102117845Ssam /* bus interface */ 103117845Ssam DEVMETHOD(bus_print_child, bus_generic_print_child), 104117845Ssam DEVMETHOD(bus_driver_added, bus_generic_driver_added), 105117845Ssam 106167755Ssam /* crypto device methods */ 107167755Ssam DEVMETHOD(cryptodev_newsession, safe_newsession), 108167755Ssam DEVMETHOD(cryptodev_freesession,safe_freesession), 109167755Ssam DEVMETHOD(cryptodev_process, safe_process), 110167755Ssam 111117845Ssam { 0, 0 } 112117845Ssam}; 113117845Ssamstatic driver_t safe_driver = { 114117845Ssam "safe", 115117845Ssam safe_methods, 116117845Ssam sizeof (struct safe_softc) 117117845Ssam}; 118117845Ssamstatic devclass_t safe_devclass; 119117845Ssam 120117845SsamDRIVER_MODULE(safe, pci, safe_driver, safe_devclass, 0, 0); 121117845SsamMODULE_DEPEND(safe, crypto, 1, 1, 1); 122117845Ssam#ifdef SAFE_RNDTEST 123117845SsamMODULE_DEPEND(safe, rndtest, 1, 1, 1); 124117845Ssam#endif 125117845Ssam 126117845Ssamstatic void safe_intr(void *); 127117845Ssamstatic void safe_callback(struct safe_softc *, struct safe_ringentry *); 128117845Ssamstatic void safe_feed(struct safe_softc *, struct safe_ringentry *); 129117845Ssamstatic void safe_mcopy(struct mbuf *, struct mbuf *, u_int); 130117845Ssam#ifndef SAFE_NO_RNG 131117845Ssamstatic void safe_rng_init(struct safe_softc *); 132117845Ssamstatic void safe_rng(void *); 133117845Ssam#endif /* SAFE_NO_RNG */ 134117845Ssamstatic int safe_dma_malloc(struct safe_softc *, bus_size_t, 135117845Ssam struct safe_dma_alloc *, int); 136117845Ssam#define safe_dma_sync(_dma, _flags) \ 137117845Ssam bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags)) 138117845Ssamstatic void safe_dma_free(struct safe_softc *, struct safe_dma_alloc *); 139117845Ssamstatic int safe_dmamap_aligned(const struct safe_operand *); 140117845Ssamstatic int safe_dmamap_uniform(const struct safe_operand *); 141117845Ssam 142117845Ssamstatic void safe_reset_board(struct safe_softc *); 143117845Ssamstatic void safe_init_board(struct safe_softc *); 144117845Ssamstatic void safe_init_pciregs(device_t dev); 145117845Ssamstatic void safe_cleanchip(struct safe_softc *); 146117845Ssamstatic void safe_totalreset(struct safe_softc *); 147117845Ssam 148117845Ssamstatic int safe_free_entry(struct safe_softc *, struct safe_ringentry *); 149117845Ssam 150117845SsamSYSCTL_NODE(_hw, OID_AUTO, safe, CTLFLAG_RD, 0, "SafeNet driver parameters"); 151117845Ssam 152117845Ssam#ifdef SAFE_DEBUG 153117845Ssamstatic void safe_dump_dmastatus(struct safe_softc *, const char *); 154117845Ssamstatic void safe_dump_ringstate(struct safe_softc *, const char *); 155117845Ssamstatic void safe_dump_intrstate(struct safe_softc *, const char *); 156117845Ssamstatic void safe_dump_request(struct safe_softc *, const char *, 157117845Ssam struct safe_ringentry *); 158117845Ssam 159117845Ssamstatic struct safe_softc *safec; /* for use by hw.safe.dump */ 160117845Ssam 161117845Ssamstatic int safe_debug = 0; 162117845SsamSYSCTL_INT(_hw_safe, OID_AUTO, debug, CTLFLAG_RW, &safe_debug, 163117845Ssam 0, "control debugging msgs"); 164117845Ssam#define DPRINTF(_x) if (safe_debug) printf _x 165117845Ssam#else 166117845Ssam#define DPRINTF(_x) 167117845Ssam#endif 168117845Ssam 169117845Ssam#define READ_REG(sc,r) \ 170117845Ssam bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 171117845Ssam 172117845Ssam#define WRITE_REG(sc,reg,val) \ 173117845Ssam bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 174117845Ssam 175117845Ssamstruct safe_stats safestats; 176117845SsamSYSCTL_STRUCT(_hw_safe, OID_AUTO, stats, CTLFLAG_RD, &safestats, 177117845Ssam safe_stats, "driver statistics"); 178117845Ssam#ifndef SAFE_NO_RNG 179117845Ssamstatic int safe_rnginterval = 1; /* poll once a second */ 180117845SsamSYSCTL_INT(_hw_safe, OID_AUTO, rnginterval, CTLFLAG_RW, &safe_rnginterval, 181117845Ssam 0, "RNG polling interval (secs)"); 182117845Ssamstatic int safe_rngbufsize = 16; /* 64 bytes each poll */ 183117845SsamSYSCTL_INT(_hw_safe, OID_AUTO, rngbufsize, CTLFLAG_RW, &safe_rngbufsize, 184117845Ssam 0, "RNG polling buffer size (32-bit words)"); 185117845Ssamstatic int safe_rngmaxalarm = 8; /* max alarms before reset */ 186117845SsamSYSCTL_INT(_hw_safe, OID_AUTO, rngmaxalarm, CTLFLAG_RW, &safe_rngmaxalarm, 187117845Ssam 0, "RNG max alarms before reset"); 188117845Ssam#endif /* SAFE_NO_RNG */ 189117845Ssam 190117845Ssamstatic int 191117845Ssamsafe_probe(device_t dev) 192117845Ssam{ 193117845Ssam if (pci_get_vendor(dev) == PCI_VENDOR_SAFENET && 194117845Ssam pci_get_device(dev) == PCI_PRODUCT_SAFEXCEL) 195142890Simp return (BUS_PROBE_DEFAULT); 196117845Ssam return (ENXIO); 197117845Ssam} 198117845Ssam 199117845Ssamstatic const char* 200117845Ssamsafe_partname(struct safe_softc *sc) 201117845Ssam{ 202117845Ssam /* XXX sprintf numbers when not decoded */ 203117845Ssam switch (pci_get_vendor(sc->sc_dev)) { 204117845Ssam case PCI_VENDOR_SAFENET: 205117845Ssam switch (pci_get_device(sc->sc_dev)) { 206117845Ssam case PCI_PRODUCT_SAFEXCEL: return "SafeNet SafeXcel-1141"; 207117845Ssam } 208117845Ssam return "SafeNet unknown-part"; 209117845Ssam } 210117845Ssam return "Unknown-vendor unknown-part"; 211117845Ssam} 212117845Ssam 213117845Ssam#ifndef SAFE_NO_RNG 214117845Ssamstatic void 215117845Ssamdefault_harvest(struct rndtest_state *rsp, void *buf, u_int count) 216117845Ssam{ 217117845Ssam random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 218117845Ssam} 219117845Ssam#endif /* SAFE_NO_RNG */ 220117845Ssam 221117845Ssamstatic int 222117845Ssamsafe_attach(device_t dev) 223117845Ssam{ 224117845Ssam struct safe_softc *sc = device_get_softc(dev); 225117845Ssam u_int32_t raddr; 226117845Ssam u_int32_t cmd, i, devinfo; 227117845Ssam int rid; 228117845Ssam 229117845Ssam bzero(sc, sizeof (*sc)); 230117845Ssam sc->sc_dev = dev; 231117845Ssam 232117845Ssam /* XXX handle power management */ 233117845Ssam 234117845Ssam cmd = pci_read_config(dev, PCIR_COMMAND, 4); 235117845Ssam cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 236117845Ssam pci_write_config(dev, PCIR_COMMAND, cmd, 4); 237117845Ssam cmd = pci_read_config(dev, PCIR_COMMAND, 4); 238117845Ssam 239117845Ssam if (!(cmd & PCIM_CMD_MEMEN)) { 240117845Ssam device_printf(dev, "failed to enable memory mapping\n"); 241117845Ssam goto bad; 242117845Ssam } 243117845Ssam 244117845Ssam if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 245117845Ssam device_printf(dev, "failed to enable bus mastering\n"); 246117845Ssam goto bad; 247117845Ssam } 248117845Ssam 249117845Ssam /* 250117845Ssam * Setup memory-mapping of PCI registers. 251117845Ssam */ 252117845Ssam rid = BS_BAR; 253127135Snjl sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 254127135Snjl RF_ACTIVE); 255117845Ssam if (sc->sc_sr == NULL) { 256117845Ssam device_printf(dev, "cannot map register space\n"); 257117845Ssam goto bad; 258117845Ssam } 259117845Ssam sc->sc_st = rman_get_bustag(sc->sc_sr); 260117845Ssam sc->sc_sh = rman_get_bushandle(sc->sc_sr); 261117845Ssam 262117845Ssam /* 263117845Ssam * Arrange interrupt line. 264117845Ssam */ 265117845Ssam rid = 0; 266127135Snjl sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 267127135Snjl RF_SHAREABLE|RF_ACTIVE); 268117845Ssam if (sc->sc_irq == NULL) { 269117845Ssam device_printf(dev, "could not map interrupt\n"); 270117845Ssam goto bad1; 271117845Ssam } 272117845Ssam /* 273117845Ssam * NB: Network code assumes we are blocked with splimp() 274117845Ssam * so make sure the IRQ is mapped appropriately. 275117845Ssam */ 276117845Ssam if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 277166901Spiso NULL, safe_intr, sc, &sc->sc_ih)) { 278117845Ssam device_printf(dev, "could not establish interrupt\n"); 279117845Ssam goto bad2; 280117845Ssam } 281117845Ssam 282167755Ssam sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE); 283117845Ssam if (sc->sc_cid < 0) { 284117845Ssam device_printf(dev, "could not get crypto driver id\n"); 285117845Ssam goto bad3; 286117845Ssam } 287117845Ssam 288117845Ssam sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) & 289117845Ssam (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN); 290117845Ssam 291117845Ssam /* 292117845Ssam * Setup DMA descriptor area. 293117845Ssam */ 294117845Ssam if (bus_dma_tag_create(NULL, /* parent */ 295117845Ssam 1, /* alignment */ 296117845Ssam SAFE_DMA_BOUNDARY, /* boundary */ 297117845Ssam BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 298117845Ssam BUS_SPACE_MAXADDR, /* highaddr */ 299117845Ssam NULL, NULL, /* filter, filterarg */ 300117845Ssam SAFE_MAX_DMA, /* maxsize */ 301117845Ssam SAFE_MAX_PART, /* nsegments */ 302117845Ssam SAFE_MAX_SSIZE, /* maxsegsize */ 303117845Ssam BUS_DMA_ALLOCNOW, /* flags */ 304117845Ssam NULL, NULL, /* locking */ 305117845Ssam &sc->sc_srcdmat)) { 306117845Ssam device_printf(dev, "cannot allocate DMA tag\n"); 307117845Ssam goto bad4; 308117845Ssam } 309117845Ssam if (bus_dma_tag_create(NULL, /* parent */ 310173307Ssam 1, /* alignment */ 311117845Ssam SAFE_MAX_DSIZE, /* boundary */ 312117845Ssam BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 313117845Ssam BUS_SPACE_MAXADDR, /* highaddr */ 314117845Ssam NULL, NULL, /* filter, filterarg */ 315117845Ssam SAFE_MAX_DMA, /* maxsize */ 316117845Ssam SAFE_MAX_PART, /* nsegments */ 317117845Ssam SAFE_MAX_DSIZE, /* maxsegsize */ 318117845Ssam BUS_DMA_ALLOCNOW, /* flags */ 319117845Ssam NULL, NULL, /* locking */ 320117845Ssam &sc->sc_dstdmat)) { 321117845Ssam device_printf(dev, "cannot allocate DMA tag\n"); 322117845Ssam goto bad4; 323117845Ssam } 324117845Ssam 325117845Ssam /* 326117845Ssam * Allocate packet engine descriptors. 327117845Ssam */ 328117845Ssam if (safe_dma_malloc(sc, 329117845Ssam SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), 330117845Ssam &sc->sc_ringalloc, 0)) { 331117845Ssam device_printf(dev, "cannot allocate PE descriptor ring\n"); 332117845Ssam bus_dma_tag_destroy(sc->sc_srcdmat); 333117845Ssam goto bad4; 334117845Ssam } 335117845Ssam /* 336117845Ssam * Hookup the static portion of all our data structures. 337117845Ssam */ 338117845Ssam sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr; 339117845Ssam sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE; 340117845Ssam sc->sc_front = sc->sc_ring; 341117845Ssam sc->sc_back = sc->sc_ring; 342117845Ssam raddr = sc->sc_ringalloc.dma_paddr; 343117845Ssam bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry)); 344117845Ssam for (i = 0; i < SAFE_MAX_NQUEUE; i++) { 345117845Ssam struct safe_ringentry *re = &sc->sc_ring[i]; 346117845Ssam 347117845Ssam re->re_desc.d_sa = raddr + 348117845Ssam offsetof(struct safe_ringentry, re_sa); 349117845Ssam re->re_sa.sa_staterec = raddr + 350117845Ssam offsetof(struct safe_ringentry, re_sastate); 351117845Ssam 352117845Ssam raddr += sizeof (struct safe_ringentry); 353117845Ssam } 354117845Ssam mtx_init(&sc->sc_ringmtx, device_get_nameunit(dev), 355117845Ssam "packet engine ring", MTX_DEF); 356117845Ssam 357117845Ssam /* 358117845Ssam * Allocate scatter and gather particle descriptors. 359117845Ssam */ 360117845Ssam if (safe_dma_malloc(sc, SAFE_TOTAL_SPART * sizeof (struct safe_pdesc), 361117845Ssam &sc->sc_spalloc, 0)) { 362117845Ssam device_printf(dev, "cannot allocate source particle " 363117845Ssam "descriptor ring\n"); 364117845Ssam mtx_destroy(&sc->sc_ringmtx); 365117845Ssam safe_dma_free(sc, &sc->sc_ringalloc); 366117845Ssam bus_dma_tag_destroy(sc->sc_srcdmat); 367117845Ssam goto bad4; 368117845Ssam } 369117845Ssam sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr; 370117845Ssam sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART; 371117845Ssam sc->sc_spfree = sc->sc_spring; 372117845Ssam bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc)); 373117845Ssam 374117845Ssam if (safe_dma_malloc(sc, SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), 375117845Ssam &sc->sc_dpalloc, 0)) { 376117845Ssam device_printf(dev, "cannot allocate destination particle " 377117845Ssam "descriptor ring\n"); 378117845Ssam mtx_destroy(&sc->sc_ringmtx); 379117845Ssam safe_dma_free(sc, &sc->sc_spalloc); 380117845Ssam safe_dma_free(sc, &sc->sc_ringalloc); 381117845Ssam bus_dma_tag_destroy(sc->sc_dstdmat); 382117845Ssam goto bad4; 383117845Ssam } 384117845Ssam sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr; 385117845Ssam sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART; 386117845Ssam sc->sc_dpfree = sc->sc_dpring; 387117845Ssam bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc)); 388117845Ssam 389117845Ssam device_printf(sc->sc_dev, "%s", safe_partname(sc)); 390117845Ssam 391117845Ssam devinfo = READ_REG(sc, SAFE_DEVINFO); 392117845Ssam if (devinfo & SAFE_DEVINFO_RNG) { 393117845Ssam sc->sc_flags |= SAFE_FLAGS_RNG; 394117845Ssam printf(" rng"); 395117845Ssam } 396117845Ssam if (devinfo & SAFE_DEVINFO_PKEY) { 397117845Ssam#if 0 398117845Ssam printf(" key"); 399117845Ssam sc->sc_flags |= SAFE_FLAGS_KEY; 400167755Ssam crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0); 401167755Ssam crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0); 402117845Ssam#endif 403117845Ssam } 404117845Ssam if (devinfo & SAFE_DEVINFO_DES) { 405117845Ssam printf(" des/3des"); 406167755Ssam crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); 407167755Ssam crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); 408117845Ssam } 409117845Ssam if (devinfo & SAFE_DEVINFO_AES) { 410117845Ssam printf(" aes"); 411167755Ssam crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); 412117845Ssam } 413117845Ssam if (devinfo & SAFE_DEVINFO_MD5) { 414117845Ssam printf(" md5"); 415167755Ssam crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); 416117845Ssam } 417117845Ssam if (devinfo & SAFE_DEVINFO_SHA1) { 418117845Ssam printf(" sha1"); 419167755Ssam crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); 420117845Ssam } 421117845Ssam printf(" null"); 422167755Ssam crypto_register(sc->sc_cid, CRYPTO_NULL_CBC, 0, 0); 423167755Ssam crypto_register(sc->sc_cid, CRYPTO_NULL_HMAC, 0, 0); 424117845Ssam /* XXX other supported algorithms */ 425117845Ssam printf("\n"); 426117845Ssam 427117845Ssam safe_reset_board(sc); /* reset h/w */ 428117845Ssam safe_init_pciregs(dev); /* init pci settings */ 429117845Ssam safe_init_board(sc); /* init h/w */ 430117845Ssam 431117845Ssam#ifndef SAFE_NO_RNG 432117845Ssam if (sc->sc_flags & SAFE_FLAGS_RNG) { 433117845Ssam#ifdef SAFE_RNDTEST 434117845Ssam sc->sc_rndtest = rndtest_attach(dev); 435117845Ssam if (sc->sc_rndtest) 436117845Ssam sc->sc_harvest = rndtest_harvest; 437117845Ssam else 438117845Ssam sc->sc_harvest = default_harvest; 439117845Ssam#else 440117845Ssam sc->sc_harvest = default_harvest; 441117845Ssam#endif 442117845Ssam safe_rng_init(sc); 443117845Ssam 444119137Ssam callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); 445117845Ssam callout_reset(&sc->sc_rngto, hz*safe_rnginterval, safe_rng, sc); 446117845Ssam } 447117845Ssam#endif /* SAFE_NO_RNG */ 448117845Ssam#ifdef SAFE_DEBUG 449117845Ssam safec = sc; /* for use by hw.safe.dump */ 450117845Ssam#endif 451117845Ssam return (0); 452117845Ssambad4: 453117845Ssam crypto_unregister_all(sc->sc_cid); 454117845Ssambad3: 455117845Ssam bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 456117845Ssambad2: 457117845Ssam bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 458117845Ssambad1: 459117845Ssam bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 460117845Ssambad: 461117845Ssam return (ENXIO); 462117845Ssam} 463117845Ssam 464117845Ssam/* 465117845Ssam * Detach a device that successfully probed. 466117845Ssam */ 467117845Ssamstatic int 468117845Ssamsafe_detach(device_t dev) 469117845Ssam{ 470117845Ssam struct safe_softc *sc = device_get_softc(dev); 471117845Ssam 472117845Ssam /* XXX wait/abort active ops */ 473117845Ssam 474117845Ssam WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */ 475117845Ssam 476117845Ssam callout_stop(&sc->sc_rngto); 477117845Ssam 478117845Ssam crypto_unregister_all(sc->sc_cid); 479117845Ssam 480117845Ssam#ifdef SAFE_RNDTEST 481117845Ssam if (sc->sc_rndtest) 482117845Ssam rndtest_detach(sc->sc_rndtest); 483117845Ssam#endif 484117845Ssam 485117845Ssam safe_cleanchip(sc); 486117845Ssam safe_dma_free(sc, &sc->sc_dpalloc); 487117845Ssam safe_dma_free(sc, &sc->sc_spalloc); 488117845Ssam mtx_destroy(&sc->sc_ringmtx); 489117845Ssam safe_dma_free(sc, &sc->sc_ringalloc); 490117845Ssam 491117845Ssam bus_generic_detach(dev); 492117845Ssam bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 493117845Ssam bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 494117845Ssam 495117845Ssam bus_dma_tag_destroy(sc->sc_srcdmat); 496117845Ssam bus_dma_tag_destroy(sc->sc_dstdmat); 497117845Ssam bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 498117845Ssam 499117845Ssam return (0); 500117845Ssam} 501117845Ssam 502117845Ssam/* 503117845Ssam * Stop all chip i/o so that the kernel's probe routines don't 504117845Ssam * get confused by errant DMAs when rebooting. 505117845Ssam */ 506188178Simpstatic int 507117845Ssamsafe_shutdown(device_t dev) 508117845Ssam{ 509117845Ssam#ifdef notyet 510117845Ssam safe_stop(device_get_softc(dev)); 511117845Ssam#endif 512188178Simp return (0); 513117845Ssam} 514117845Ssam 515117845Ssam/* 516117845Ssam * Device suspend routine. 517117845Ssam */ 518117845Ssamstatic int 519117845Ssamsafe_suspend(device_t dev) 520117845Ssam{ 521117845Ssam struct safe_softc *sc = device_get_softc(dev); 522117845Ssam 523117845Ssam#ifdef notyet 524117845Ssam /* XXX stop the device and save PCI settings */ 525117845Ssam#endif 526117845Ssam sc->sc_suspended = 1; 527117845Ssam 528117845Ssam return (0); 529117845Ssam} 530117845Ssam 531117845Ssamstatic int 532117845Ssamsafe_resume(device_t dev) 533117845Ssam{ 534117845Ssam struct safe_softc *sc = device_get_softc(dev); 535117845Ssam 536117845Ssam#ifdef notyet 537117845Ssam /* XXX retore PCI settings and start the device */ 538117845Ssam#endif 539117845Ssam sc->sc_suspended = 0; 540117845Ssam return (0); 541117845Ssam} 542117845Ssam 543117845Ssam/* 544117845Ssam * SafeXcel Interrupt routine 545117845Ssam */ 546117845Ssamstatic void 547117845Ssamsafe_intr(void *arg) 548117845Ssam{ 549117845Ssam struct safe_softc *sc = arg; 550117845Ssam volatile u_int32_t stat; 551117845Ssam 552117845Ssam stat = READ_REG(sc, SAFE_HM_STAT); 553117845Ssam if (stat == 0) /* shared irq, not for us */ 554117845Ssam return; 555117845Ssam 556117845Ssam WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */ 557117845Ssam 558117845Ssam if ((stat & SAFE_INT_PE_DDONE)) { 559117845Ssam /* 560117845Ssam * Descriptor(s) done; scan the ring and 561117845Ssam * process completed operations. 562117845Ssam */ 563117845Ssam mtx_lock(&sc->sc_ringmtx); 564117845Ssam while (sc->sc_back != sc->sc_front) { 565117845Ssam struct safe_ringentry *re = sc->sc_back; 566117845Ssam#ifdef SAFE_DEBUG 567117845Ssam if (safe_debug) { 568117845Ssam safe_dump_ringstate(sc, __func__); 569117845Ssam safe_dump_request(sc, __func__, re); 570117845Ssam } 571117845Ssam#endif 572117845Ssam /* 573117845Ssam * safe_process marks ring entries that were allocated 574117845Ssam * but not used with a csr of zero. This insures the 575117845Ssam * ring front pointer never needs to be set backwards 576117845Ssam * in the event that an entry is allocated but not used 577117845Ssam * because of a setup error. 578117845Ssam */ 579117845Ssam if (re->re_desc.d_csr != 0) { 580117845Ssam if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr)) 581117845Ssam break; 582117845Ssam if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len)) 583117845Ssam break; 584117845Ssam sc->sc_nqchip--; 585117845Ssam safe_callback(sc, re); 586117845Ssam } 587117845Ssam if (++(sc->sc_back) == sc->sc_ringtop) 588117845Ssam sc->sc_back = sc->sc_ring; 589117845Ssam } 590117845Ssam mtx_unlock(&sc->sc_ringmtx); 591117845Ssam } 592117845Ssam 593117845Ssam /* 594117845Ssam * Check to see if we got any DMA Error 595117845Ssam */ 596117845Ssam if (stat & SAFE_INT_PE_ERROR) { 597117845Ssam DPRINTF(("dmaerr dmastat %08x\n", 598117845Ssam READ_REG(sc, SAFE_PE_DMASTAT))); 599117845Ssam safestats.st_dmaerr++; 600117845Ssam safe_totalreset(sc); 601117845Ssam#if 0 602117845Ssam safe_feed(sc); 603117845Ssam#endif 604117845Ssam } 605117845Ssam 606117845Ssam if (sc->sc_needwakeup) { /* XXX check high watermark */ 607117845Ssam int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 608117845Ssam DPRINTF(("%s: wakeup crypto %x\n", __func__, 609117845Ssam sc->sc_needwakeup)); 610117845Ssam sc->sc_needwakeup &= ~wakeup; 611117845Ssam crypto_unblock(sc->sc_cid, wakeup); 612117845Ssam } 613117845Ssam} 614117845Ssam 615117845Ssam/* 616117845Ssam * safe_feed() - post a request to chip 617117845Ssam */ 618117845Ssamstatic void 619117845Ssamsafe_feed(struct safe_softc *sc, struct safe_ringentry *re) 620117845Ssam{ 621117845Ssam bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_PREWRITE); 622117845Ssam if (re->re_dst_map != NULL) 623117845Ssam bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map, 624117845Ssam BUS_DMASYNC_PREREAD); 625117845Ssam /* XXX have no smaller granularity */ 626117845Ssam safe_dma_sync(&sc->sc_ringalloc, 627117845Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 628117845Ssam safe_dma_sync(&sc->sc_spalloc, BUS_DMASYNC_PREWRITE); 629117845Ssam safe_dma_sync(&sc->sc_dpalloc, BUS_DMASYNC_PREWRITE); 630117845Ssam 631117845Ssam#ifdef SAFE_DEBUG 632117845Ssam if (safe_debug) { 633117845Ssam safe_dump_ringstate(sc, __func__); 634117845Ssam safe_dump_request(sc, __func__, re); 635117845Ssam } 636117845Ssam#endif 637117845Ssam sc->sc_nqchip++; 638117845Ssam if (sc->sc_nqchip > safestats.st_maxqchip) 639117845Ssam safestats.st_maxqchip = sc->sc_nqchip; 640117845Ssam /* poke h/w to check descriptor ring, any value can be written */ 641117845Ssam WRITE_REG(sc, SAFE_HI_RD_DESCR, 0); 642117845Ssam} 643117845Ssam 644159226Spjd#define N(a) (sizeof(a) / sizeof (a[0])) 645159226Spjdstatic void 646159226Spjdsafe_setup_enckey(struct safe_session *ses, caddr_t key) 647159226Spjd{ 648159226Spjd int i; 649159226Spjd 650159226Spjd bcopy(key, ses->ses_key, ses->ses_klen / 8); 651159226Spjd 652159226Spjd /* PE is little-endian, insure proper byte order */ 653159226Spjd for (i = 0; i < N(ses->ses_key); i++) 654159226Spjd ses->ses_key[i] = htole32(ses->ses_key[i]); 655159226Spjd} 656159226Spjd 657159226Spjdstatic void 658159226Spjdsafe_setup_mackey(struct safe_session *ses, int algo, caddr_t key, int klen) 659159226Spjd{ 660159226Spjd MD5_CTX md5ctx; 661159226Spjd SHA1_CTX sha1ctx; 662159226Spjd int i; 663159226Spjd 664159226Spjd 665159226Spjd for (i = 0; i < klen; i++) 666159226Spjd key[i] ^= HMAC_IPAD_VAL; 667159226Spjd 668159226Spjd if (algo == CRYPTO_MD5_HMAC) { 669159226Spjd MD5Init(&md5ctx); 670159226Spjd MD5Update(&md5ctx, key, klen); 671159232Spjd MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); 672159226Spjd bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state)); 673159226Spjd } else { 674159226Spjd SHA1Init(&sha1ctx); 675159226Spjd SHA1Update(&sha1ctx, key, klen); 676159232Spjd SHA1Update(&sha1ctx, hmac_ipad_buffer, 677159232Spjd SHA1_HMAC_BLOCK_LEN - klen); 678159226Spjd bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); 679159226Spjd } 680159226Spjd 681159226Spjd for (i = 0; i < klen; i++) 682159226Spjd key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 683159226Spjd 684159226Spjd if (algo == CRYPTO_MD5_HMAC) { 685159226Spjd MD5Init(&md5ctx); 686159226Spjd MD5Update(&md5ctx, key, klen); 687159232Spjd MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); 688159226Spjd bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state)); 689159226Spjd } else { 690159226Spjd SHA1Init(&sha1ctx); 691159226Spjd SHA1Update(&sha1ctx, key, klen); 692159232Spjd SHA1Update(&sha1ctx, hmac_opad_buffer, 693159232Spjd SHA1_HMAC_BLOCK_LEN - klen); 694159226Spjd bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); 695159226Spjd } 696159226Spjd 697159226Spjd for (i = 0; i < klen; i++) 698159226Spjd key[i] ^= HMAC_OPAD_VAL; 699159226Spjd 700159226Spjd /* PE is little-endian, insure proper byte order */ 701159226Spjd for (i = 0; i < N(ses->ses_hminner); i++) { 702159226Spjd ses->ses_hminner[i] = htole32(ses->ses_hminner[i]); 703159226Spjd ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]); 704159226Spjd } 705159226Spjd} 706159226Spjd#undef N 707159226Spjd 708117845Ssam/* 709117845Ssam * Allocate a new 'session' and return an encoded session id. 'sidp' 710117845Ssam * contains our registration id, and should contain an encoded session 711117845Ssam * id on successful allocation. 712117845Ssam */ 713117845Ssamstatic int 714167755Ssamsafe_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) 715117845Ssam{ 716167755Ssam struct safe_softc *sc = device_get_softc(dev); 717117845Ssam struct cryptoini *c, *encini = NULL, *macini = NULL; 718117845Ssam struct safe_session *ses = NULL; 719159226Spjd int sesn; 720117845Ssam 721117845Ssam if (sidp == NULL || cri == NULL || sc == NULL) 722117845Ssam return (EINVAL); 723117845Ssam 724117845Ssam for (c = cri; c != NULL; c = c->cri_next) { 725117845Ssam if (c->cri_alg == CRYPTO_MD5_HMAC || 726117845Ssam c->cri_alg == CRYPTO_SHA1_HMAC || 727117845Ssam c->cri_alg == CRYPTO_NULL_HMAC) { 728117845Ssam if (macini) 729117845Ssam return (EINVAL); 730117845Ssam macini = c; 731117845Ssam } else if (c->cri_alg == CRYPTO_DES_CBC || 732117845Ssam c->cri_alg == CRYPTO_3DES_CBC || 733117845Ssam c->cri_alg == CRYPTO_AES_CBC || 734117845Ssam c->cri_alg == CRYPTO_NULL_CBC) { 735117845Ssam if (encini) 736117845Ssam return (EINVAL); 737117845Ssam encini = c; 738117845Ssam } else 739117845Ssam return (EINVAL); 740117845Ssam } 741117845Ssam if (encini == NULL && macini == NULL) 742117845Ssam return (EINVAL); 743117845Ssam if (encini) { /* validate key length */ 744117845Ssam switch (encini->cri_alg) { 745117845Ssam case CRYPTO_DES_CBC: 746117845Ssam if (encini->cri_klen != 64) 747117845Ssam return (EINVAL); 748117845Ssam break; 749117845Ssam case CRYPTO_3DES_CBC: 750117845Ssam if (encini->cri_klen != 192) 751117845Ssam return (EINVAL); 752117845Ssam break; 753117845Ssam case CRYPTO_AES_CBC: 754117845Ssam if (encini->cri_klen != 128 && 755117845Ssam encini->cri_klen != 192 && 756117845Ssam encini->cri_klen != 256) 757117845Ssam return (EINVAL); 758117845Ssam break; 759117845Ssam } 760117845Ssam } 761117845Ssam 762117845Ssam if (sc->sc_sessions == NULL) { 763117845Ssam ses = sc->sc_sessions = (struct safe_session *)malloc( 764117845Ssam sizeof(struct safe_session), M_DEVBUF, M_NOWAIT); 765117845Ssam if (ses == NULL) 766117845Ssam return (ENOMEM); 767117845Ssam sesn = 0; 768117845Ssam sc->sc_nsessions = 1; 769117845Ssam } else { 770117845Ssam for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 771117845Ssam if (sc->sc_sessions[sesn].ses_used == 0) { 772117845Ssam ses = &sc->sc_sessions[sesn]; 773117845Ssam break; 774117845Ssam } 775117845Ssam } 776117845Ssam 777117845Ssam if (ses == NULL) { 778117845Ssam sesn = sc->sc_nsessions; 779117845Ssam ses = (struct safe_session *)malloc((sesn + 1) * 780117845Ssam sizeof(struct safe_session), M_DEVBUF, M_NOWAIT); 781117845Ssam if (ses == NULL) 782117845Ssam return (ENOMEM); 783117845Ssam bcopy(sc->sc_sessions, ses, sesn * 784117845Ssam sizeof(struct safe_session)); 785117845Ssam bzero(sc->sc_sessions, sesn * 786117845Ssam sizeof(struct safe_session)); 787117845Ssam free(sc->sc_sessions, M_DEVBUF); 788117845Ssam sc->sc_sessions = ses; 789117845Ssam ses = &sc->sc_sessions[sesn]; 790117845Ssam sc->sc_nsessions++; 791117845Ssam } 792117845Ssam } 793117845Ssam 794117845Ssam bzero(ses, sizeof(struct safe_session)); 795117845Ssam ses->ses_used = 1; 796117845Ssam 797117845Ssam if (encini) { 798117845Ssam /* get an IV */ 799117845Ssam /* XXX may read fewer than requested */ 800117845Ssam read_random(ses->ses_iv, sizeof(ses->ses_iv)); 801117845Ssam 802117845Ssam ses->ses_klen = encini->cri_klen; 803159226Spjd if (encini->cri_key != NULL) 804159226Spjd safe_setup_enckey(ses, encini->cri_key); 805117845Ssam } 806117845Ssam 807117845Ssam if (macini) { 808158705Spjd ses->ses_mlen = macini->cri_mlen; 809158705Spjd if (ses->ses_mlen == 0) { 810158705Spjd if (macini->cri_alg == CRYPTO_MD5_HMAC) 811159233Spjd ses->ses_mlen = MD5_HASH_LEN; 812158705Spjd else 813159233Spjd ses->ses_mlen = SHA1_HASH_LEN; 814158705Spjd } 815158705Spjd 816159226Spjd if (macini->cri_key != NULL) { 817159226Spjd safe_setup_mackey(ses, macini->cri_alg, macini->cri_key, 818117845Ssam macini->cri_klen / 8); 819117845Ssam } 820117845Ssam } 821117845Ssam 822117845Ssam *sidp = SAFE_SID(device_get_unit(sc->sc_dev), sesn); 823117845Ssam return (0); 824117845Ssam} 825117845Ssam 826117845Ssam/* 827117845Ssam * Deallocate a session. 828117845Ssam */ 829117845Ssamstatic int 830167755Ssamsafe_freesession(device_t dev, u_int64_t tid) 831117845Ssam{ 832167755Ssam struct safe_softc *sc = device_get_softc(dev); 833117845Ssam int session, ret; 834117845Ssam u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 835117845Ssam 836117845Ssam if (sc == NULL) 837117845Ssam return (EINVAL); 838117845Ssam 839117845Ssam session = SAFE_SESSION(sid); 840117845Ssam if (session < sc->sc_nsessions) { 841117845Ssam bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 842117845Ssam ret = 0; 843117845Ssam } else 844117845Ssam ret = EINVAL; 845117845Ssam return (ret); 846117845Ssam} 847117845Ssam 848117845Ssamstatic void 849117845Ssamsafe_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 850117845Ssam{ 851117845Ssam struct safe_operand *op = arg; 852117845Ssam 853117845Ssam DPRINTF(("%s: mapsize %u nsegs %d error %d\n", __func__, 854117845Ssam (u_int) mapsize, nsegs, error)); 855117845Ssam if (error != 0) 856117845Ssam return; 857117845Ssam op->mapsize = mapsize; 858117845Ssam op->nsegs = nsegs; 859117845Ssam bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 860117845Ssam} 861117845Ssam 862117845Ssamstatic int 863167755Ssamsafe_process(device_t dev, struct cryptop *crp, int hint) 864117845Ssam{ 865167755Ssam struct safe_softc *sc = device_get_softc(dev); 866117845Ssam int err = 0, i, nicealign, uniform; 867117845Ssam struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 868117845Ssam int bypass, oplen, ivsize; 869117845Ssam caddr_t iv; 870117845Ssam int16_t coffset; 871117845Ssam struct safe_session *ses; 872117845Ssam struct safe_ringentry *re; 873117845Ssam struct safe_sarec *sa; 874117845Ssam struct safe_pdesc *pd; 875117845Ssam u_int32_t cmd0, cmd1, staterec; 876117845Ssam 877117845Ssam if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 878117845Ssam safestats.st_invalid++; 879117845Ssam return (EINVAL); 880117845Ssam } 881117845Ssam if (SAFE_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 882117845Ssam safestats.st_badsession++; 883117845Ssam return (EINVAL); 884117845Ssam } 885117845Ssam 886117845Ssam mtx_lock(&sc->sc_ringmtx); 887117845Ssam if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) { 888117845Ssam safestats.st_ringfull++; 889117845Ssam sc->sc_needwakeup |= CRYPTO_SYMQ; 890117845Ssam mtx_unlock(&sc->sc_ringmtx); 891117845Ssam return (ERESTART); 892117845Ssam } 893117845Ssam re = sc->sc_front; 894117845Ssam 895117845Ssam staterec = re->re_sa.sa_staterec; /* save */ 896117845Ssam /* NB: zero everything but the PE descriptor */ 897117845Ssam bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc)); 898117845Ssam re->re_sa.sa_staterec = staterec; /* restore */ 899117845Ssam 900117845Ssam re->re_crp = crp; 901117845Ssam re->re_sesn = SAFE_SESSION(crp->crp_sid); 902117845Ssam 903117845Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 904117845Ssam re->re_src_m = (struct mbuf *)crp->crp_buf; 905117845Ssam re->re_dst_m = (struct mbuf *)crp->crp_buf; 906117845Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 907117845Ssam re->re_src_io = (struct uio *)crp->crp_buf; 908117845Ssam re->re_dst_io = (struct uio *)crp->crp_buf; 909117845Ssam } else { 910117845Ssam safestats.st_badflags++; 911117845Ssam err = EINVAL; 912117845Ssam goto errout; /* XXX we don't handle contiguous blocks! */ 913117845Ssam } 914117845Ssam 915117845Ssam sa = &re->re_sa; 916117845Ssam ses = &sc->sc_sessions[re->re_sesn]; 917117845Ssam 918117845Ssam crd1 = crp->crp_desc; 919117845Ssam if (crd1 == NULL) { 920117845Ssam safestats.st_nodesc++; 921117845Ssam err = EINVAL; 922117845Ssam goto errout; 923117845Ssam } 924117845Ssam crd2 = crd1->crd_next; 925117845Ssam 926117845Ssam cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */ 927117845Ssam cmd1 = 0; 928117845Ssam if (crd2 == NULL) { 929117845Ssam if (crd1->crd_alg == CRYPTO_MD5_HMAC || 930117845Ssam crd1->crd_alg == CRYPTO_SHA1_HMAC || 931117845Ssam crd1->crd_alg == CRYPTO_NULL_HMAC) { 932117845Ssam maccrd = crd1; 933117845Ssam enccrd = NULL; 934117845Ssam cmd0 |= SAFE_SA_CMD0_OP_HASH; 935117845Ssam } else if (crd1->crd_alg == CRYPTO_DES_CBC || 936117845Ssam crd1->crd_alg == CRYPTO_3DES_CBC || 937117845Ssam crd1->crd_alg == CRYPTO_AES_CBC || 938117845Ssam crd1->crd_alg == CRYPTO_NULL_CBC) { 939117845Ssam maccrd = NULL; 940117845Ssam enccrd = crd1; 941117845Ssam cmd0 |= SAFE_SA_CMD0_OP_CRYPT; 942117845Ssam } else { 943117845Ssam safestats.st_badalg++; 944117845Ssam err = EINVAL; 945117845Ssam goto errout; 946117845Ssam } 947117845Ssam } else { 948117845Ssam if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 949117845Ssam crd1->crd_alg == CRYPTO_SHA1_HMAC || 950117845Ssam crd1->crd_alg == CRYPTO_NULL_HMAC) && 951117845Ssam (crd2->crd_alg == CRYPTO_DES_CBC || 952117845Ssam crd2->crd_alg == CRYPTO_3DES_CBC || 953117845Ssam crd2->crd_alg == CRYPTO_AES_CBC || 954117845Ssam crd2->crd_alg == CRYPTO_NULL_CBC) && 955117845Ssam ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 956117845Ssam maccrd = crd1; 957117845Ssam enccrd = crd2; 958117845Ssam } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 959117845Ssam crd1->crd_alg == CRYPTO_3DES_CBC || 960117845Ssam crd1->crd_alg == CRYPTO_AES_CBC || 961117845Ssam crd1->crd_alg == CRYPTO_NULL_CBC) && 962117845Ssam (crd2->crd_alg == CRYPTO_MD5_HMAC || 963117845Ssam crd2->crd_alg == CRYPTO_SHA1_HMAC || 964117845Ssam crd2->crd_alg == CRYPTO_NULL_HMAC) && 965117845Ssam (crd1->crd_flags & CRD_F_ENCRYPT)) { 966117845Ssam enccrd = crd1; 967117845Ssam maccrd = crd2; 968117845Ssam } else { 969117845Ssam safestats.st_badalg++; 970117845Ssam err = EINVAL; 971117845Ssam goto errout; 972117845Ssam } 973117845Ssam cmd0 |= SAFE_SA_CMD0_OP_BOTH; 974117845Ssam } 975117845Ssam 976117845Ssam if (enccrd) { 977159226Spjd if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) 978159226Spjd safe_setup_enckey(ses, enccrd->crd_key); 979159226Spjd 980117845Ssam if (enccrd->crd_alg == CRYPTO_DES_CBC) { 981117845Ssam cmd0 |= SAFE_SA_CMD0_DES; 982117845Ssam cmd1 |= SAFE_SA_CMD1_CBC; 983117845Ssam ivsize = 2*sizeof(u_int32_t); 984117845Ssam } else if (enccrd->crd_alg == CRYPTO_3DES_CBC) { 985117845Ssam cmd0 |= SAFE_SA_CMD0_3DES; 986117845Ssam cmd1 |= SAFE_SA_CMD1_CBC; 987117845Ssam ivsize = 2*sizeof(u_int32_t); 988117845Ssam } else if (enccrd->crd_alg == CRYPTO_AES_CBC) { 989117845Ssam cmd0 |= SAFE_SA_CMD0_AES; 990117845Ssam cmd1 |= SAFE_SA_CMD1_CBC; 991117845Ssam if (ses->ses_klen == 128) 992117845Ssam cmd1 |= SAFE_SA_CMD1_AES128; 993117845Ssam else if (ses->ses_klen == 192) 994117845Ssam cmd1 |= SAFE_SA_CMD1_AES192; 995117845Ssam else 996117845Ssam cmd1 |= SAFE_SA_CMD1_AES256; 997117845Ssam ivsize = 4*sizeof(u_int32_t); 998117845Ssam } else { 999117845Ssam cmd0 |= SAFE_SA_CMD0_CRYPT_NULL; 1000117845Ssam ivsize = 0; 1001117845Ssam } 1002117845Ssam 1003117845Ssam /* 1004117845Ssam * Setup encrypt/decrypt state. When using basic ops 1005117845Ssam * we can't use an inline IV because hash/crypt offset 1006117845Ssam * must be from the end of the IV to the start of the 1007117845Ssam * crypt data and this leaves out the preceding header 1008117845Ssam * from the hash calculation. Instead we place the IV 1009117845Ssam * in the state record and set the hash/crypt offset to 1010117845Ssam * copy both the header+IV. 1011117845Ssam */ 1012117845Ssam if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1013117845Ssam cmd0 |= SAFE_SA_CMD0_OUTBOUND; 1014117845Ssam 1015117845Ssam if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1016117845Ssam iv = enccrd->crd_iv; 1017117845Ssam else 1018117845Ssam iv = (caddr_t) ses->ses_iv; 1019117845Ssam if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1020159242Spjd crypto_copyback(crp->crp_flags, crp->crp_buf, 1021159242Spjd enccrd->crd_inject, ivsize, iv); 1022117845Ssam } 1023117845Ssam bcopy(iv, re->re_sastate.sa_saved_iv, ivsize); 1024117845Ssam cmd0 |= SAFE_SA_CMD0_IVLD_STATE | SAFE_SA_CMD0_SAVEIV; 1025117845Ssam re->re_flags |= SAFE_QFLAGS_COPYOUTIV; 1026117845Ssam } else { 1027117845Ssam cmd0 |= SAFE_SA_CMD0_INBOUND; 1028117845Ssam 1029159242Spjd if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { 1030117845Ssam bcopy(enccrd->crd_iv, 1031117845Ssam re->re_sastate.sa_saved_iv, ivsize); 1032159242Spjd } else { 1033159242Spjd crypto_copydata(crp->crp_flags, crp->crp_buf, 1034159242Spjd enccrd->crd_inject, ivsize, 1035159242Spjd (caddr_t)re->re_sastate.sa_saved_iv); 1036159242Spjd } 1037117845Ssam cmd0 |= SAFE_SA_CMD0_IVLD_STATE; 1038117845Ssam } 1039117845Ssam /* 1040117845Ssam * For basic encryption use the zero pad algorithm. 1041117845Ssam * This pads results to an 8-byte boundary and 1042117845Ssam * suppresses padding verification for inbound (i.e. 1043117845Ssam * decrypt) operations. 1044117845Ssam * 1045117845Ssam * NB: Not sure if the 8-byte pad boundary is a problem. 1046117845Ssam */ 1047117845Ssam cmd0 |= SAFE_SA_CMD0_PAD_ZERO; 1048117845Ssam 1049117845Ssam /* XXX assert key bufs have the same size */ 1050117845Ssam bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key)); 1051117845Ssam } 1052117845Ssam 1053117845Ssam if (maccrd) { 1054159226Spjd if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { 1055159226Spjd safe_setup_mackey(ses, maccrd->crd_alg, 1056159226Spjd maccrd->crd_key, maccrd->crd_klen / 8); 1057159226Spjd } 1058159226Spjd 1059117845Ssam if (maccrd->crd_alg == CRYPTO_MD5_HMAC) { 1060117845Ssam cmd0 |= SAFE_SA_CMD0_MD5; 1061117845Ssam cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ 1062117845Ssam } else if (maccrd->crd_alg == CRYPTO_SHA1_HMAC) { 1063117845Ssam cmd0 |= SAFE_SA_CMD0_SHA1; 1064117845Ssam cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ 1065117845Ssam } else { 1066117845Ssam cmd0 |= SAFE_SA_CMD0_HASH_NULL; 1067117845Ssam } 1068117845Ssam /* 1069117845Ssam * Digest data is loaded from the SA and the hash 1070117845Ssam * result is saved to the state block where we 1071117845Ssam * retrieve it for return to the caller. 1072117845Ssam */ 1073117845Ssam /* XXX assert digest bufs have the same size */ 1074117845Ssam bcopy(ses->ses_hminner, sa->sa_indigest, 1075117845Ssam sizeof(sa->sa_indigest)); 1076117845Ssam bcopy(ses->ses_hmouter, sa->sa_outdigest, 1077117845Ssam sizeof(sa->sa_outdigest)); 1078117845Ssam 1079117845Ssam cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH; 1080117845Ssam re->re_flags |= SAFE_QFLAGS_COPYOUTICV; 1081117845Ssam } 1082117845Ssam 1083117845Ssam if (enccrd && maccrd) { 1084117845Ssam /* 1085117845Ssam * The offset from hash data to the start of 1086117845Ssam * crypt data is the difference in the skips. 1087117845Ssam */ 1088117845Ssam bypass = maccrd->crd_skip; 1089117845Ssam coffset = enccrd->crd_skip - maccrd->crd_skip; 1090117845Ssam if (coffset < 0) { 1091117845Ssam DPRINTF(("%s: hash does not precede crypt; " 1092117845Ssam "mac skip %u enc skip %u\n", 1093117845Ssam __func__, maccrd->crd_skip, enccrd->crd_skip)); 1094117845Ssam safestats.st_skipmismatch++; 1095117845Ssam err = EINVAL; 1096117845Ssam goto errout; 1097117845Ssam } 1098117845Ssam oplen = enccrd->crd_skip + enccrd->crd_len; 1099117845Ssam if (maccrd->crd_skip + maccrd->crd_len != oplen) { 1100117845Ssam DPRINTF(("%s: hash amount %u != crypt amount %u\n", 1101117845Ssam __func__, maccrd->crd_skip + maccrd->crd_len, 1102117845Ssam oplen)); 1103117845Ssam safestats.st_lenmismatch++; 1104117845Ssam err = EINVAL; 1105117845Ssam goto errout; 1106117845Ssam } 1107117845Ssam#ifdef SAFE_DEBUG 1108117845Ssam if (safe_debug) { 1109117845Ssam printf("mac: skip %d, len %d, inject %d\n", 1110117845Ssam maccrd->crd_skip, maccrd->crd_len, 1111117845Ssam maccrd->crd_inject); 1112117845Ssam printf("enc: skip %d, len %d, inject %d\n", 1113117845Ssam enccrd->crd_skip, enccrd->crd_len, 1114117845Ssam enccrd->crd_inject); 1115117845Ssam printf("bypass %d coffset %d oplen %d\n", 1116117845Ssam bypass, coffset, oplen); 1117117845Ssam } 1118117845Ssam#endif 1119117845Ssam if (coffset & 3) { /* offset must be 32-bit aligned */ 1120117845Ssam DPRINTF(("%s: coffset %u misaligned\n", 1121117845Ssam __func__, coffset)); 1122117845Ssam safestats.st_coffmisaligned++; 1123117845Ssam err = EINVAL; 1124117845Ssam goto errout; 1125117845Ssam } 1126117845Ssam coffset >>= 2; 1127117845Ssam if (coffset > 255) { /* offset must be <256 dwords */ 1128117845Ssam DPRINTF(("%s: coffset %u too big\n", 1129117845Ssam __func__, coffset)); 1130117845Ssam safestats.st_cofftoobig++; 1131117845Ssam err = EINVAL; 1132117845Ssam goto errout; 1133117845Ssam } 1134117845Ssam /* 1135117845Ssam * Tell the hardware to copy the header to the output. 1136117845Ssam * The header is defined as the data from the end of 1137117845Ssam * the bypass to the start of data to be encrypted. 1138117845Ssam * Typically this is the inline IV. Note that you need 1139117845Ssam * to do this even if src+dst are the same; it appears 1140117845Ssam * that w/o this bit the crypted data is written 1141117845Ssam * immediately after the bypass data. 1142117845Ssam */ 1143117845Ssam cmd1 |= SAFE_SA_CMD1_HDRCOPY; 1144117845Ssam /* 1145117845Ssam * Disable IP header mutable bit handling. This is 1146117845Ssam * needed to get correct HMAC calculations. 1147117845Ssam */ 1148117845Ssam cmd1 |= SAFE_SA_CMD1_MUTABLE; 1149117845Ssam } else { 1150117845Ssam if (enccrd) { 1151117845Ssam bypass = enccrd->crd_skip; 1152117845Ssam oplen = bypass + enccrd->crd_len; 1153117845Ssam } else { 1154117845Ssam bypass = maccrd->crd_skip; 1155117845Ssam oplen = bypass + maccrd->crd_len; 1156117845Ssam } 1157117845Ssam coffset = 0; 1158117845Ssam } 1159117845Ssam /* XXX verify multiple of 4 when using s/g */ 1160117845Ssam if (bypass > 96) { /* bypass offset must be <= 96 bytes */ 1161117845Ssam DPRINTF(("%s: bypass %u too big\n", __func__, bypass)); 1162117845Ssam safestats.st_bypasstoobig++; 1163117845Ssam err = EINVAL; 1164117845Ssam goto errout; 1165117845Ssam } 1166117845Ssam 1167117845Ssam if (bus_dmamap_create(sc->sc_srcdmat, BUS_DMA_NOWAIT, &re->re_src_map)) { 1168117845Ssam safestats.st_nomap++; 1169117845Ssam err = ENOMEM; 1170117845Ssam goto errout; 1171117845Ssam } 1172117845Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1173117845Ssam if (bus_dmamap_load_mbuf(sc->sc_srcdmat, re->re_src_map, 1174117845Ssam re->re_src_m, safe_op_cb, 1175117845Ssam &re->re_src, BUS_DMA_NOWAIT) != 0) { 1176117845Ssam bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1177117845Ssam re->re_src_map = NULL; 1178117845Ssam safestats.st_noload++; 1179117845Ssam err = ENOMEM; 1180117845Ssam goto errout; 1181117845Ssam } 1182117845Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 1183117845Ssam if (bus_dmamap_load_uio(sc->sc_srcdmat, re->re_src_map, 1184117845Ssam re->re_src_io, safe_op_cb, 1185117845Ssam &re->re_src, BUS_DMA_NOWAIT) != 0) { 1186117845Ssam bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1187117845Ssam re->re_src_map = NULL; 1188117845Ssam safestats.st_noload++; 1189117845Ssam err = ENOMEM; 1190117845Ssam goto errout; 1191117845Ssam } 1192117845Ssam } 1193117845Ssam nicealign = safe_dmamap_aligned(&re->re_src); 1194117845Ssam uniform = safe_dmamap_uniform(&re->re_src); 1195117845Ssam 1196117845Ssam DPRINTF(("src nicealign %u uniform %u nsegs %u\n", 1197117845Ssam nicealign, uniform, re->re_src.nsegs)); 1198117845Ssam if (re->re_src.nsegs > 1) { 1199117845Ssam re->re_desc.d_src = sc->sc_spalloc.dma_paddr + 1200117845Ssam ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring); 1201117845Ssam for (i = 0; i < re->re_src_nsegs; i++) { 1202117845Ssam /* NB: no need to check if there's space */ 1203117845Ssam pd = sc->sc_spfree; 1204117845Ssam if (++(sc->sc_spfree) == sc->sc_springtop) 1205117845Ssam sc->sc_spfree = sc->sc_spring; 1206117845Ssam 1207117845Ssam KASSERT((pd->pd_flags&3) == 0 || 1208117845Ssam (pd->pd_flags&3) == SAFE_PD_DONE, 1209117845Ssam ("bogus source particle descriptor; flags %x", 1210117845Ssam pd->pd_flags)); 1211117845Ssam pd->pd_addr = re->re_src_segs[i].ds_addr; 1212117845Ssam pd->pd_size = re->re_src_segs[i].ds_len; 1213117845Ssam pd->pd_flags = SAFE_PD_READY; 1214117845Ssam } 1215117845Ssam cmd0 |= SAFE_SA_CMD0_IGATHER; 1216117845Ssam } else { 1217117845Ssam /* 1218117845Ssam * No need for gather, reference the operand directly. 1219117845Ssam */ 1220117845Ssam re->re_desc.d_src = re->re_src_segs[0].ds_addr; 1221117845Ssam } 1222117845Ssam 1223117845Ssam if (enccrd == NULL && maccrd != NULL) { 1224117845Ssam /* 1225117845Ssam * Hash op; no destination needed. 1226117845Ssam */ 1227117845Ssam } else { 1228117845Ssam if (crp->crp_flags & CRYPTO_F_IOV) { 1229117845Ssam if (!nicealign) { 1230117845Ssam safestats.st_iovmisaligned++; 1231117845Ssam err = EINVAL; 1232117845Ssam goto errout; 1233117845Ssam } 1234117845Ssam if (uniform != 1) { 1235117845Ssam /* 1236117845Ssam * Source is not suitable for direct use as 1237117845Ssam * the destination. Create a new scatter/gather 1238117845Ssam * list based on the destination requirements 1239117845Ssam * and check if that's ok. 1240117845Ssam */ 1241117845Ssam if (bus_dmamap_create(sc->sc_dstdmat, 1242117845Ssam BUS_DMA_NOWAIT, &re->re_dst_map)) { 1243117845Ssam safestats.st_nomap++; 1244117845Ssam err = ENOMEM; 1245117845Ssam goto errout; 1246117845Ssam } 1247117845Ssam if (bus_dmamap_load_uio(sc->sc_dstdmat, 1248117845Ssam re->re_dst_map, re->re_dst_io, 1249117845Ssam safe_op_cb, &re->re_dst, 1250117845Ssam BUS_DMA_NOWAIT) != 0) { 1251117845Ssam bus_dmamap_destroy(sc->sc_dstdmat, 1252117845Ssam re->re_dst_map); 1253117845Ssam re->re_dst_map = NULL; 1254117845Ssam safestats.st_noload++; 1255117845Ssam err = ENOMEM; 1256117845Ssam goto errout; 1257117845Ssam } 1258117845Ssam uniform = safe_dmamap_uniform(&re->re_dst); 1259117845Ssam if (!uniform) { 1260117845Ssam /* 1261117845Ssam * There's no way to handle the DMA 1262117845Ssam * requirements with this uio. We 1263117845Ssam * could create a separate DMA area for 1264117845Ssam * the result and then copy it back, 1265117845Ssam * but for now we just bail and return 1266117845Ssam * an error. Note that uio requests 1267117845Ssam * > SAFE_MAX_DSIZE are handled because 1268117845Ssam * the DMA map and segment list for the 1269117845Ssam * destination wil result in a 1270117845Ssam * destination particle list that does 1271117845Ssam * the necessary scatter DMA. 1272117845Ssam */ 1273117845Ssam safestats.st_iovnotuniform++; 1274117845Ssam err = EINVAL; 1275117845Ssam goto errout; 1276117845Ssam } 1277118882Ssam } else 1278118882Ssam re->re_dst = re->re_src; 1279117845Ssam } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1280117845Ssam if (nicealign && uniform == 1) { 1281117845Ssam /* 1282117845Ssam * Source layout is suitable for direct 1283117845Ssam * sharing of the DMA map and segment list. 1284117845Ssam */ 1285117845Ssam re->re_dst = re->re_src; 1286117845Ssam } else if (nicealign && uniform == 2) { 1287117845Ssam /* 1288117845Ssam * The source is properly aligned but requires a 1289117845Ssam * different particle list to handle DMA of the 1290117845Ssam * result. Create a new map and do the load to 1291117845Ssam * create the segment list. The particle 1292117845Ssam * descriptor setup code below will handle the 1293117845Ssam * rest. 1294117845Ssam */ 1295117845Ssam if (bus_dmamap_create(sc->sc_dstdmat, 1296117845Ssam BUS_DMA_NOWAIT, &re->re_dst_map)) { 1297117845Ssam safestats.st_nomap++; 1298117845Ssam err = ENOMEM; 1299117845Ssam goto errout; 1300117845Ssam } 1301117845Ssam if (bus_dmamap_load_mbuf(sc->sc_dstdmat, 1302117845Ssam re->re_dst_map, re->re_dst_m, 1303117845Ssam safe_op_cb, &re->re_dst, 1304117845Ssam BUS_DMA_NOWAIT) != 0) { 1305117845Ssam bus_dmamap_destroy(sc->sc_dstdmat, 1306117845Ssam re->re_dst_map); 1307117845Ssam re->re_dst_map = NULL; 1308117845Ssam safestats.st_noload++; 1309117845Ssam err = ENOMEM; 1310117845Ssam goto errout; 1311117845Ssam } 1312117845Ssam } else { /* !(aligned and/or uniform) */ 1313117845Ssam int totlen, len; 1314117845Ssam struct mbuf *m, *top, **mp; 1315117845Ssam 1316117845Ssam /* 1317117845Ssam * DMA constraints require that we allocate a 1318117845Ssam * new mbuf chain for the destination. We 1319117845Ssam * allocate an entire new set of mbufs of 1320117845Ssam * optimal/required size and then tell the 1321117845Ssam * hardware to copy any bits that are not 1322117845Ssam * created as a byproduct of the operation. 1323117845Ssam */ 1324117845Ssam if (!nicealign) 1325117845Ssam safestats.st_unaligned++; 1326117845Ssam if (!uniform) 1327117845Ssam safestats.st_notuniform++; 1328117845Ssam totlen = re->re_src_mapsize; 1329117845Ssam if (re->re_src_m->m_flags & M_PKTHDR) { 1330117845Ssam len = MHLEN; 1331117845Ssam MGETHDR(m, M_DONTWAIT, MT_DATA); 1332117845Ssam if (m && !m_dup_pkthdr(m, re->re_src_m, 1333117845Ssam M_DONTWAIT)) { 1334117845Ssam m_free(m); 1335117845Ssam m = NULL; 1336117845Ssam } 1337117845Ssam } else { 1338117845Ssam len = MLEN; 1339117845Ssam MGET(m, M_DONTWAIT, MT_DATA); 1340117845Ssam } 1341117845Ssam if (m == NULL) { 1342117845Ssam safestats.st_nombuf++; 1343117845Ssam err = sc->sc_nqchip ? ERESTART : ENOMEM; 1344117845Ssam goto errout; 1345117845Ssam } 1346117845Ssam if (totlen >= MINCLSIZE) { 1347117845Ssam MCLGET(m, M_DONTWAIT); 1348117845Ssam if ((m->m_flags & M_EXT) == 0) { 1349117845Ssam m_free(m); 1350117845Ssam safestats.st_nomcl++; 1351117845Ssam err = sc->sc_nqchip ? 1352117845Ssam ERESTART : ENOMEM; 1353117845Ssam goto errout; 1354117845Ssam } 1355117845Ssam len = MCLBYTES; 1356117845Ssam } 1357117845Ssam m->m_len = len; 1358117845Ssam top = NULL; 1359117845Ssam mp = ⊤ 1360117845Ssam 1361117845Ssam while (totlen > 0) { 1362117845Ssam if (top) { 1363117845Ssam MGET(m, M_DONTWAIT, MT_DATA); 1364117845Ssam if (m == NULL) { 1365117845Ssam m_freem(top); 1366117845Ssam safestats.st_nombuf++; 1367117845Ssam err = sc->sc_nqchip ? 1368117845Ssam ERESTART : ENOMEM; 1369117845Ssam goto errout; 1370117845Ssam } 1371117845Ssam len = MLEN; 1372117845Ssam } 1373117845Ssam if (top && totlen >= MINCLSIZE) { 1374117845Ssam MCLGET(m, M_DONTWAIT); 1375117845Ssam if ((m->m_flags & M_EXT) == 0) { 1376117845Ssam *mp = m; 1377117845Ssam m_freem(top); 1378117845Ssam safestats.st_nomcl++; 1379117845Ssam err = sc->sc_nqchip ? 1380117845Ssam ERESTART : ENOMEM; 1381117845Ssam goto errout; 1382117845Ssam } 1383117845Ssam len = MCLBYTES; 1384117845Ssam } 1385117845Ssam m->m_len = len = min(totlen, len); 1386117845Ssam totlen -= len; 1387117845Ssam *mp = m; 1388117845Ssam mp = &m->m_next; 1389117845Ssam } 1390117845Ssam re->re_dst_m = top; 1391117845Ssam if (bus_dmamap_create(sc->sc_dstdmat, 1392117845Ssam BUS_DMA_NOWAIT, &re->re_dst_map) != 0) { 1393117845Ssam safestats.st_nomap++; 1394117845Ssam err = ENOMEM; 1395117845Ssam goto errout; 1396117845Ssam } 1397117845Ssam if (bus_dmamap_load_mbuf(sc->sc_dstdmat, 1398117845Ssam re->re_dst_map, re->re_dst_m, 1399117845Ssam safe_op_cb, &re->re_dst, 1400117845Ssam BUS_DMA_NOWAIT) != 0) { 1401117845Ssam bus_dmamap_destroy(sc->sc_dstdmat, 1402117845Ssam re->re_dst_map); 1403117845Ssam re->re_dst_map = NULL; 1404117845Ssam safestats.st_noload++; 1405117845Ssam err = ENOMEM; 1406117845Ssam goto errout; 1407117845Ssam } 1408117845Ssam if (re->re_src.mapsize > oplen) { 1409117845Ssam /* 1410117845Ssam * There's data following what the 1411117845Ssam * hardware will copy for us. If this 1412117845Ssam * isn't just the ICV (that's going to 1413117845Ssam * be written on completion), copy it 1414117845Ssam * to the new mbufs 1415117845Ssam */ 1416117845Ssam if (!(maccrd && 1417117845Ssam (re->re_src.mapsize-oplen) == 12 && 1418117845Ssam maccrd->crd_inject == oplen)) 1419117845Ssam safe_mcopy(re->re_src_m, 1420117845Ssam re->re_dst_m, 1421117845Ssam oplen); 1422117845Ssam else 1423117845Ssam safestats.st_noicvcopy++; 1424117845Ssam } 1425117845Ssam } 1426117845Ssam } else { 1427117845Ssam safestats.st_badflags++; 1428117845Ssam err = EINVAL; 1429117845Ssam goto errout; 1430117845Ssam } 1431117845Ssam 1432117845Ssam if (re->re_dst.nsegs > 1) { 1433117845Ssam re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr + 1434117845Ssam ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring); 1435117845Ssam for (i = 0; i < re->re_dst_nsegs; i++) { 1436117845Ssam pd = sc->sc_dpfree; 1437117845Ssam KASSERT((pd->pd_flags&3) == 0 || 1438117845Ssam (pd->pd_flags&3) == SAFE_PD_DONE, 1439117845Ssam ("bogus dest particle descriptor; flags %x", 1440117845Ssam pd->pd_flags)); 1441117845Ssam if (++(sc->sc_dpfree) == sc->sc_dpringtop) 1442117845Ssam sc->sc_dpfree = sc->sc_dpring; 1443117845Ssam pd->pd_addr = re->re_dst_segs[i].ds_addr; 1444117845Ssam pd->pd_flags = SAFE_PD_READY; 1445117845Ssam } 1446117845Ssam cmd0 |= SAFE_SA_CMD0_OSCATTER; 1447117845Ssam } else { 1448117845Ssam /* 1449117845Ssam * No need for scatter, reference the operand directly. 1450117845Ssam */ 1451117845Ssam re->re_desc.d_dst = re->re_dst_segs[0].ds_addr; 1452117845Ssam } 1453117845Ssam } 1454117845Ssam 1455117845Ssam /* 1456117845Ssam * All done with setup; fillin the SA command words 1457117845Ssam * and the packet engine descriptor. The operation 1458117845Ssam * is now ready for submission to the hardware. 1459117845Ssam */ 1460117845Ssam sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI; 1461117845Ssam sa->sa_cmd1 = cmd1 1462117845Ssam | (coffset << SAFE_SA_CMD1_OFFSET_S) 1463117845Ssam | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */ 1464117845Ssam | SAFE_SA_CMD1_SRPCI 1465117845Ssam ; 1466117845Ssam /* 1467117845Ssam * NB: the order of writes is important here. In case the 1468117845Ssam * chip is scanning the ring because of an outstanding request 1469117845Ssam * it might nab this one too. In that case we need to make 1470117845Ssam * sure the setup is complete before we write the length 1471117845Ssam * field of the descriptor as it signals the descriptor is 1472117845Ssam * ready for processing. 1473117845Ssam */ 1474117845Ssam re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI; 1475117845Ssam if (maccrd) 1476117845Ssam re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL; 1477117845Ssam re->re_desc.d_len = oplen 1478117845Ssam | SAFE_PE_LEN_READY 1479117845Ssam | (bypass << SAFE_PE_LEN_BYPASS_S) 1480117845Ssam ; 1481117845Ssam 1482117845Ssam safestats.st_ipackets++; 1483117845Ssam safestats.st_ibytes += oplen; 1484117845Ssam 1485117845Ssam if (++(sc->sc_front) == sc->sc_ringtop) 1486117845Ssam sc->sc_front = sc->sc_ring; 1487117845Ssam 1488117845Ssam /* XXX honor batching */ 1489117845Ssam safe_feed(sc, re); 1490117845Ssam mtx_unlock(&sc->sc_ringmtx); 1491117845Ssam return (0); 1492117845Ssam 1493117845Ssamerrout: 1494117845Ssam if ((re->re_dst_m != NULL) && (re->re_src_m != re->re_dst_m)) 1495117845Ssam m_freem(re->re_dst_m); 1496117845Ssam 1497117845Ssam if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) { 1498117845Ssam bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map); 1499117845Ssam bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map); 1500117845Ssam } 1501117845Ssam if (re->re_src_map != NULL) { 1502117845Ssam bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map); 1503117845Ssam bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1504117845Ssam } 1505117845Ssam mtx_unlock(&sc->sc_ringmtx); 1506117845Ssam if (err != ERESTART) { 1507117845Ssam crp->crp_etype = err; 1508117845Ssam crypto_done(crp); 1509117845Ssam } else { 1510117845Ssam sc->sc_needwakeup |= CRYPTO_SYMQ; 1511117845Ssam } 1512117845Ssam return (err); 1513117845Ssam} 1514117845Ssam 1515117845Ssamstatic void 1516117845Ssamsafe_callback(struct safe_softc *sc, struct safe_ringentry *re) 1517117845Ssam{ 1518117845Ssam struct cryptop *crp = (struct cryptop *)re->re_crp; 1519117845Ssam struct cryptodesc *crd; 1520117845Ssam 1521117845Ssam safestats.st_opackets++; 1522117845Ssam safestats.st_obytes += re->re_dst.mapsize; 1523117845Ssam 1524117845Ssam safe_dma_sync(&sc->sc_ringalloc, 1525117845Ssam BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1526117845Ssam if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) { 1527117845Ssam device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n", 1528117845Ssam re->re_desc.d_csr, 1529117845Ssam re->re_sa.sa_cmd0, re->re_sa.sa_cmd1); 1530117845Ssam safestats.st_peoperr++; 1531117845Ssam crp->crp_etype = EIO; /* something more meaningful? */ 1532117845Ssam } 1533117845Ssam if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) { 1534117845Ssam bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map, 1535117845Ssam BUS_DMASYNC_POSTREAD); 1536117845Ssam bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map); 1537117845Ssam bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map); 1538117845Ssam } 1539117845Ssam bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_POSTWRITE); 1540117845Ssam bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map); 1541117845Ssam bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1542117845Ssam 1543117845Ssam /* 1544117845Ssam * If result was written to a differet mbuf chain, swap 1545117845Ssam * it in as the return value and reclaim the original. 1546117845Ssam */ 1547117845Ssam if ((crp->crp_flags & CRYPTO_F_IMBUF) && re->re_src_m != re->re_dst_m) { 1548117845Ssam m_freem(re->re_src_m); 1549117845Ssam crp->crp_buf = (caddr_t)re->re_dst_m; 1550117845Ssam } 1551117845Ssam 1552117845Ssam if (re->re_flags & SAFE_QFLAGS_COPYOUTIV) { 1553117845Ssam /* copy out IV for future use */ 1554117845Ssam for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1555117845Ssam int ivsize; 1556117845Ssam 1557117845Ssam if (crd->crd_alg == CRYPTO_DES_CBC || 1558117845Ssam crd->crd_alg == CRYPTO_3DES_CBC) { 1559117845Ssam ivsize = 2*sizeof(u_int32_t); 1560117845Ssam } else if (crd->crd_alg == CRYPTO_AES_CBC) { 1561117845Ssam ivsize = 4*sizeof(u_int32_t); 1562117845Ssam } else 1563117845Ssam continue; 1564159242Spjd crypto_copydata(crp->crp_flags, crp->crp_buf, 1565159242Spjd crd->crd_skip + crd->crd_len - ivsize, ivsize, 1566159242Spjd (caddr_t)sc->sc_sessions[re->re_sesn].ses_iv); 1567117845Ssam break; 1568117845Ssam } 1569117845Ssam } 1570117845Ssam 1571117845Ssam if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) { 1572117845Ssam /* copy out ICV result */ 1573117845Ssam for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1574117845Ssam if (!(crd->crd_alg == CRYPTO_MD5_HMAC || 1575117845Ssam crd->crd_alg == CRYPTO_SHA1_HMAC || 1576117845Ssam crd->crd_alg == CRYPTO_NULL_HMAC)) 1577117845Ssam continue; 1578117845Ssam if (crd->crd_alg == CRYPTO_SHA1_HMAC) { 1579117845Ssam /* 1580117845Ssam * SHA-1 ICV's are byte-swapped; fix 'em up 1581117845Ssam * before copy them to their destination. 1582117845Ssam */ 1583223026Sdelphij re->re_sastate.sa_saved_indigest[0] = 1584223026Sdelphij bswap32(re->re_sastate.sa_saved_indigest[0]); 1585223026Sdelphij re->re_sastate.sa_saved_indigest[1] = 1586223026Sdelphij bswap32(re->re_sastate.sa_saved_indigest[1]); 1587223026Sdelphij re->re_sastate.sa_saved_indigest[2] = 1588223026Sdelphij bswap32(re->re_sastate.sa_saved_indigest[2]); 1589117845Ssam } 1590159242Spjd crypto_copyback(crp->crp_flags, crp->crp_buf, 1591159242Spjd crd->crd_inject, 1592159242Spjd sc->sc_sessions[re->re_sesn].ses_mlen, 1593159242Spjd (caddr_t)re->re_sastate.sa_saved_indigest); 1594117845Ssam break; 1595117845Ssam } 1596117845Ssam } 1597117845Ssam crypto_done(crp); 1598117845Ssam} 1599117845Ssam 1600117845Ssam/* 1601117845Ssam * Copy all data past offset from srcm to dstm. 1602117845Ssam */ 1603117845Ssamstatic void 1604117845Ssamsafe_mcopy(struct mbuf *srcm, struct mbuf *dstm, u_int offset) 1605117845Ssam{ 1606117845Ssam u_int j, dlen, slen; 1607117845Ssam caddr_t dptr, sptr; 1608117845Ssam 1609117845Ssam /* 1610117845Ssam * Advance src and dst to offset. 1611117845Ssam */ 1612117845Ssam j = offset; 1613117845Ssam while (j >= 0) { 1614117845Ssam if (srcm->m_len > j) 1615117845Ssam break; 1616117845Ssam j -= srcm->m_len; 1617117845Ssam srcm = srcm->m_next; 1618117845Ssam if (srcm == NULL) 1619117845Ssam return; 1620117845Ssam } 1621117845Ssam sptr = mtod(srcm, caddr_t) + j; 1622117845Ssam slen = srcm->m_len - j; 1623117845Ssam 1624117845Ssam j = offset; 1625117845Ssam while (j >= 0) { 1626117845Ssam if (dstm->m_len > j) 1627117845Ssam break; 1628117845Ssam j -= dstm->m_len; 1629117845Ssam dstm = dstm->m_next; 1630117845Ssam if (dstm == NULL) 1631117845Ssam return; 1632117845Ssam } 1633117845Ssam dptr = mtod(dstm, caddr_t) + j; 1634117845Ssam dlen = dstm->m_len - j; 1635117845Ssam 1636117845Ssam /* 1637117845Ssam * Copy everything that remains. 1638117845Ssam */ 1639117845Ssam for (;;) { 1640117845Ssam j = min(slen, dlen); 1641117845Ssam bcopy(sptr, dptr, j); 1642117845Ssam if (slen == j) { 1643117845Ssam srcm = srcm->m_next; 1644117845Ssam if (srcm == NULL) 1645117845Ssam return; 1646117845Ssam sptr = srcm->m_data; 1647117845Ssam slen = srcm->m_len; 1648117845Ssam } else 1649117845Ssam sptr += j, slen -= j; 1650117845Ssam if (dlen == j) { 1651117845Ssam dstm = dstm->m_next; 1652117845Ssam if (dstm == NULL) 1653117845Ssam return; 1654117845Ssam dptr = dstm->m_data; 1655117845Ssam dlen = dstm->m_len; 1656117845Ssam } else 1657117845Ssam dptr += j, dlen -= j; 1658117845Ssam } 1659117845Ssam} 1660117845Ssam 1661117845Ssam#ifndef SAFE_NO_RNG 1662117845Ssam#define SAFE_RNG_MAXWAIT 1000 1663117845Ssam 1664117845Ssamstatic void 1665117845Ssamsafe_rng_init(struct safe_softc *sc) 1666117845Ssam{ 1667117845Ssam u_int32_t w, v; 1668117845Ssam int i; 1669117845Ssam 1670117845Ssam WRITE_REG(sc, SAFE_RNG_CTRL, 0); 1671117845Ssam /* use default value according to the manual */ 1672117845Ssam WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */ 1673117845Ssam WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1674117845Ssam 1675117845Ssam /* 1676117845Ssam * There is a bug in rev 1.0 of the 1140 that when the RNG 1677117845Ssam * is brought out of reset the ready status flag does not 1678117845Ssam * work until the RNG has finished its internal initialization. 1679117845Ssam * 1680117845Ssam * So in order to determine the device is through its 1681117845Ssam * initialization we must read the data register, using the 1682117845Ssam * status reg in the read in case it is initialized. Then read 1683117845Ssam * the data register until it changes from the first read. 1684117845Ssam * Once it changes read the data register until it changes 1685117845Ssam * again. At this time the RNG is considered initialized. 1686117845Ssam * This could take between 750ms - 1000ms in time. 1687117845Ssam */ 1688117845Ssam i = 0; 1689117845Ssam w = READ_REG(sc, SAFE_RNG_OUT); 1690117845Ssam do { 1691117845Ssam v = READ_REG(sc, SAFE_RNG_OUT); 1692117845Ssam if (v != w) { 1693117845Ssam w = v; 1694117845Ssam break; 1695117845Ssam } 1696117845Ssam DELAY(10); 1697117845Ssam } while (++i < SAFE_RNG_MAXWAIT); 1698117845Ssam 1699117845Ssam /* Wait Until data changes again */ 1700117845Ssam i = 0; 1701117845Ssam do { 1702117845Ssam v = READ_REG(sc, SAFE_RNG_OUT); 1703117845Ssam if (v != w) 1704117845Ssam break; 1705117845Ssam DELAY(10); 1706117845Ssam } while (++i < SAFE_RNG_MAXWAIT); 1707117845Ssam} 1708117845Ssam 1709117845Ssamstatic __inline void 1710117845Ssamsafe_rng_disable_short_cycle(struct safe_softc *sc) 1711117845Ssam{ 1712117845Ssam WRITE_REG(sc, SAFE_RNG_CTRL, 1713117845Ssam READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN); 1714117845Ssam} 1715117845Ssam 1716117845Ssamstatic __inline void 1717117845Ssamsafe_rng_enable_short_cycle(struct safe_softc *sc) 1718117845Ssam{ 1719117845Ssam WRITE_REG(sc, SAFE_RNG_CTRL, 1720117845Ssam READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN); 1721117845Ssam} 1722117845Ssam 1723117845Ssamstatic __inline u_int32_t 1724117845Ssamsafe_rng_read(struct safe_softc *sc) 1725117845Ssam{ 1726117845Ssam int i; 1727117845Ssam 1728117845Ssam i = 0; 1729117845Ssam while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT) 1730117845Ssam ; 1731117845Ssam return READ_REG(sc, SAFE_RNG_OUT); 1732117845Ssam} 1733117845Ssam 1734117845Ssamstatic void 1735117845Ssamsafe_rng(void *arg) 1736117845Ssam{ 1737117845Ssam struct safe_softc *sc = arg; 1738117845Ssam u_int32_t buf[SAFE_RNG_MAXBUFSIZ]; /* NB: maybe move to softc */ 1739117845Ssam u_int maxwords; 1740117845Ssam int i; 1741117845Ssam 1742117845Ssam safestats.st_rng++; 1743117845Ssam /* 1744117845Ssam * Fetch the next block of data. 1745117845Ssam */ 1746117845Ssam maxwords = safe_rngbufsize; 1747117845Ssam if (maxwords > SAFE_RNG_MAXBUFSIZ) 1748117845Ssam maxwords = SAFE_RNG_MAXBUFSIZ; 1749117845Ssamretry: 1750117845Ssam for (i = 0; i < maxwords; i++) 1751117845Ssam buf[i] = safe_rng_read(sc); 1752117845Ssam /* 1753117845Ssam * Check the comparator alarm count and reset the h/w if 1754117845Ssam * it exceeds our threshold. This guards against the 1755117845Ssam * hardware oscillators resonating with external signals. 1756117845Ssam */ 1757117845Ssam if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) { 1758117845Ssam u_int32_t freq_inc, w; 1759117845Ssam 1760117845Ssam DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__, 1761117845Ssam READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm)); 1762117845Ssam safestats.st_rngalarm++; 1763117845Ssam safe_rng_enable_short_cycle(sc); 1764117845Ssam freq_inc = 18; 1765117845Ssam for (i = 0; i < 64; i++) { 1766117845Ssam w = READ_REG(sc, SAFE_RNG_CNFG); 1767117845Ssam freq_inc = ((w + freq_inc) & 0x3fL); 1768117845Ssam w = ((w & ~0x3fL) | freq_inc); 1769117845Ssam WRITE_REG(sc, SAFE_RNG_CNFG, w); 1770117845Ssam 1771117845Ssam WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1772117845Ssam 1773117845Ssam (void) safe_rng_read(sc); 1774117845Ssam DELAY(25); 1775117845Ssam 1776117845Ssam if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) { 1777117845Ssam safe_rng_disable_short_cycle(sc); 1778117845Ssam goto retry; 1779117845Ssam } 1780117845Ssam freq_inc = 1; 1781117845Ssam } 1782117845Ssam safe_rng_disable_short_cycle(sc); 1783117845Ssam } else 1784117845Ssam WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1785117845Ssam 1786117845Ssam (*sc->sc_harvest)(sc->sc_rndtest, buf, maxwords*sizeof (u_int32_t)); 1787117845Ssam callout_reset(&sc->sc_rngto, 1788117845Ssam hz * (safe_rnginterval ? safe_rnginterval : 1), safe_rng, sc); 1789117845Ssam} 1790117845Ssam#endif /* SAFE_NO_RNG */ 1791117845Ssam 1792117845Ssamstatic void 1793117845Ssamsafe_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1794117845Ssam{ 1795117845Ssam bus_addr_t *paddr = (bus_addr_t*) arg; 1796117845Ssam *paddr = segs->ds_addr; 1797117845Ssam} 1798117845Ssam 1799117845Ssamstatic int 1800117845Ssamsafe_dma_malloc( 1801117845Ssam struct safe_softc *sc, 1802117845Ssam bus_size_t size, 1803117845Ssam struct safe_dma_alloc *dma, 1804117845Ssam int mapflags 1805117845Ssam) 1806117845Ssam{ 1807117845Ssam int r; 1808117845Ssam 1809117845Ssam r = bus_dma_tag_create(NULL, /* parent */ 1810117845Ssam sizeof(u_int32_t), 0, /* alignment, bounds */ 1811117845Ssam BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1812117845Ssam BUS_SPACE_MAXADDR, /* highaddr */ 1813117845Ssam NULL, NULL, /* filter, filterarg */ 1814117845Ssam size, /* maxsize */ 1815117845Ssam 1, /* nsegments */ 1816117845Ssam size, /* maxsegsize */ 1817117845Ssam BUS_DMA_ALLOCNOW, /* flags */ 1818117845Ssam NULL, NULL, /* locking */ 1819117845Ssam &dma->dma_tag); 1820117845Ssam if (r != 0) { 1821117845Ssam device_printf(sc->sc_dev, "safe_dma_malloc: " 1822117845Ssam "bus_dma_tag_create failed; error %u\n", r); 1823117845Ssam goto fail_0; 1824117845Ssam } 1825117845Ssam 1826117845Ssam r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map); 1827117845Ssam if (r != 0) { 1828117845Ssam device_printf(sc->sc_dev, "safe_dma_malloc: " 1829117845Ssam "bus_dmamap_create failed; error %u\n", r); 1830117845Ssam goto fail_1; 1831117845Ssam } 1832117845Ssam 1833117845Ssam r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 1834117845Ssam BUS_DMA_NOWAIT, &dma->dma_map); 1835117845Ssam if (r != 0) { 1836117845Ssam device_printf(sc->sc_dev, "safe_dma_malloc: " 1837117845Ssam "bus_dmammem_alloc failed; size %zu, error %u\n", 1838117845Ssam size, r); 1839117845Ssam goto fail_2; 1840117845Ssam } 1841117845Ssam 1842117845Ssam r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 1843117845Ssam size, 1844117845Ssam safe_dmamap_cb, 1845117845Ssam &dma->dma_paddr, 1846117845Ssam mapflags | BUS_DMA_NOWAIT); 1847117845Ssam if (r != 0) { 1848117845Ssam device_printf(sc->sc_dev, "safe_dma_malloc: " 1849117845Ssam "bus_dmamap_load failed; error %u\n", r); 1850117845Ssam goto fail_3; 1851117845Ssam } 1852117845Ssam 1853117845Ssam dma->dma_size = size; 1854117845Ssam return (0); 1855117845Ssam 1856117845Ssamfail_3: 1857117845Ssam bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1858117845Ssamfail_2: 1859117845Ssam bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1860117845Ssamfail_1: 1861117845Ssam bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1862117845Ssam bus_dma_tag_destroy(dma->dma_tag); 1863117845Ssamfail_0: 1864117845Ssam dma->dma_map = NULL; 1865117845Ssam dma->dma_tag = NULL; 1866117845Ssam return (r); 1867117845Ssam} 1868117845Ssam 1869117845Ssamstatic void 1870117845Ssamsafe_dma_free(struct safe_softc *sc, struct safe_dma_alloc *dma) 1871117845Ssam{ 1872117845Ssam bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1873117845Ssam bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1874117845Ssam bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1875117845Ssam bus_dma_tag_destroy(dma->dma_tag); 1876117845Ssam} 1877117845Ssam 1878117845Ssam/* 1879117845Ssam * Resets the board. Values in the regesters are left as is 1880117845Ssam * from the reset (i.e. initial values are assigned elsewhere). 1881117845Ssam */ 1882117845Ssamstatic void 1883117845Ssamsafe_reset_board(struct safe_softc *sc) 1884117845Ssam{ 1885117845Ssam u_int32_t v; 1886117845Ssam /* 1887117845Ssam * Reset the device. The manual says no delay 1888117845Ssam * is needed between marking and clearing reset. 1889117845Ssam */ 1890117845Ssam v = READ_REG(sc, SAFE_PE_DMACFG) &~ 1891117845Ssam (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET | 1892117845Ssam SAFE_PE_DMACFG_SGRESET); 1893117845Ssam WRITE_REG(sc, SAFE_PE_DMACFG, v 1894117845Ssam | SAFE_PE_DMACFG_PERESET 1895117845Ssam | SAFE_PE_DMACFG_PDRRESET 1896117845Ssam | SAFE_PE_DMACFG_SGRESET); 1897117845Ssam WRITE_REG(sc, SAFE_PE_DMACFG, v); 1898117845Ssam} 1899117845Ssam 1900117845Ssam/* 1901117845Ssam * Initialize registers we need to touch only once. 1902117845Ssam */ 1903117845Ssamstatic void 1904117845Ssamsafe_init_board(struct safe_softc *sc) 1905117845Ssam{ 1906117845Ssam u_int32_t v, dwords; 1907117845Ssam 1908201758Smbr v = READ_REG(sc, SAFE_PE_DMACFG); 1909117845Ssam v &=~ SAFE_PE_DMACFG_PEMODE; 1910117845Ssam v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */ 1911117845Ssam | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ 1912117845Ssam | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ 1913117845Ssam | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ 1914117845Ssam | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ 1915117845Ssam | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ 1916117845Ssam ; 1917117845Ssam WRITE_REG(sc, SAFE_PE_DMACFG, v); 1918117845Ssam#if 0 1919117845Ssam /* XXX select byte swap based on host byte order */ 1920117845Ssam WRITE_REG(sc, SAFE_ENDIAN, 0x1b); 1921117845Ssam#endif 1922117845Ssam if (sc->sc_chiprev == SAFE_REV(1,0)) { 1923117845Ssam /* 1924117845Ssam * Avoid large PCI DMA transfers. Rev 1.0 has a bug where 1925117845Ssam * "target mode transfers" done while the chip is DMA'ing 1926117845Ssam * >1020 bytes cause the hardware to lockup. To avoid this 1927117845Ssam * we reduce the max PCI transfer size and use small source 1928117845Ssam * particle descriptors (<= 256 bytes). 1929117845Ssam */ 1930117845Ssam WRITE_REG(sc, SAFE_DMA_CFG, 256); 1931117845Ssam device_printf(sc->sc_dev, 1932117845Ssam "Reduce max DMA size to %u words for rev %u.%u WAR\n", 1933117845Ssam (READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff, 1934117845Ssam SAFE_REV_MAJ(sc->sc_chiprev), 1935117845Ssam SAFE_REV_MIN(sc->sc_chiprev)); 1936117845Ssam } 1937117845Ssam 1938117845Ssam /* NB: operands+results are overlaid */ 1939117845Ssam WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr); 1940117845Ssam WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr); 1941117845Ssam /* 1942117845Ssam * Configure ring entry size and number of items in the ring. 1943117845Ssam */ 1944117845Ssam KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0, 1945117845Ssam ("PE ring entry not 32-bit aligned!")); 1946117845Ssam dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t); 1947117845Ssam WRITE_REG(sc, SAFE_PE_RINGCFG, 1948117845Ssam (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE); 1949117845Ssam WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */ 1950117845Ssam 1951117845Ssam WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr); 1952117845Ssam WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr); 1953117845Ssam WRITE_REG(sc, SAFE_PE_PARTSIZE, 1954117845Ssam (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART); 1955117845Ssam /* 1956117845Ssam * NB: destination particles are fixed size. We use 1957117845Ssam * an mbuf cluster and require all results go to 1958117845Ssam * clusters or smaller. 1959117845Ssam */ 1960117845Ssam WRITE_REG(sc, SAFE_PE_PARTCFG, SAFE_MAX_DSIZE); 1961117845Ssam 1962117845Ssam /* it's now safe to enable PE mode, do it */ 1963117845Ssam WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE); 1964117845Ssam 1965117845Ssam /* 1966117845Ssam * Configure hardware to use level-triggered interrupts and 1967117845Ssam * to interrupt after each descriptor is processed. 1968117845Ssam */ 1969117845Ssam WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL); 1970117845Ssam WRITE_REG(sc, SAFE_HI_DESC_CNT, 1); 1971117845Ssam WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR); 1972117845Ssam} 1973117845Ssam 1974117845Ssam/* 1975117845Ssam * Init PCI registers 1976117845Ssam */ 1977117845Ssamstatic void 1978117845Ssamsafe_init_pciregs(device_t dev) 1979117845Ssam{ 1980117845Ssam} 1981117845Ssam 1982117845Ssam/* 1983117845Ssam * Clean up after a chip crash. 1984117845Ssam * It is assumed that the caller in splimp() 1985117845Ssam */ 1986117845Ssamstatic void 1987117845Ssamsafe_cleanchip(struct safe_softc *sc) 1988117845Ssam{ 1989117845Ssam 1990117845Ssam if (sc->sc_nqchip != 0) { 1991117845Ssam struct safe_ringentry *re = sc->sc_back; 1992117845Ssam 1993117845Ssam while (re != sc->sc_front) { 1994117845Ssam if (re->re_desc.d_csr != 0) 1995117845Ssam safe_free_entry(sc, re); 1996117845Ssam if (++re == sc->sc_ringtop) 1997117845Ssam re = sc->sc_ring; 1998117845Ssam } 1999117845Ssam sc->sc_back = re; 2000117845Ssam sc->sc_nqchip = 0; 2001117845Ssam } 2002117845Ssam} 2003117845Ssam 2004117845Ssam/* 2005117845Ssam * free a safe_q 2006117845Ssam * It is assumed that the caller is within splimp(). 2007117845Ssam */ 2008117845Ssamstatic int 2009117845Ssamsafe_free_entry(struct safe_softc *sc, struct safe_ringentry *re) 2010117845Ssam{ 2011117845Ssam struct cryptop *crp; 2012117845Ssam 2013117845Ssam /* 2014117845Ssam * Free header MCR 2015117845Ssam */ 2016117845Ssam if ((re->re_dst_m != NULL) && (re->re_src_m != re->re_dst_m)) 2017117845Ssam m_freem(re->re_dst_m); 2018117845Ssam 2019117845Ssam crp = (struct cryptop *)re->re_crp; 2020117845Ssam 2021117845Ssam re->re_desc.d_csr = 0; 2022117845Ssam 2023117845Ssam crp->crp_etype = EFAULT; 2024117845Ssam crypto_done(crp); 2025117845Ssam return(0); 2026117845Ssam} 2027117845Ssam 2028117845Ssam/* 2029117845Ssam * Routine to reset the chip and clean up. 2030117845Ssam * It is assumed that the caller is in splimp() 2031117845Ssam */ 2032117845Ssamstatic void 2033117845Ssamsafe_totalreset(struct safe_softc *sc) 2034117845Ssam{ 2035117845Ssam safe_reset_board(sc); 2036117845Ssam safe_init_board(sc); 2037117845Ssam safe_cleanchip(sc); 2038117845Ssam} 2039117845Ssam 2040117845Ssam/* 2041117845Ssam * Is the operand suitable aligned for direct DMA. Each 2042117845Ssam * segment must be aligned on a 32-bit boundary and all 2043117845Ssam * but the last segment must be a multiple of 4 bytes. 2044117845Ssam */ 2045117845Ssamstatic int 2046117845Ssamsafe_dmamap_aligned(const struct safe_operand *op) 2047117845Ssam{ 2048117845Ssam int i; 2049117845Ssam 2050117845Ssam for (i = 0; i < op->nsegs; i++) { 2051117845Ssam if (op->segs[i].ds_addr & 3) 2052117845Ssam return (0); 2053117845Ssam if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3)) 2054117845Ssam return (0); 2055117845Ssam } 2056117845Ssam return (1); 2057117845Ssam} 2058117845Ssam 2059117845Ssam/* 2060117845Ssam * Is the operand suitable for direct DMA as the destination 2061117845Ssam * of an operation. The hardware requires that each ``particle'' 2062117845Ssam * but the last in an operation result have the same size. We 2063117845Ssam * fix that size at SAFE_MAX_DSIZE bytes. This routine returns 2064117845Ssam * 0 if some segment is not a multiple of of this size, 1 if all 2065117845Ssam * segments are exactly this size, or 2 if segments are at worst 2066117845Ssam * a multple of this size. 2067117845Ssam */ 2068117845Ssamstatic int 2069117845Ssamsafe_dmamap_uniform(const struct safe_operand *op) 2070117845Ssam{ 2071117845Ssam int result = 1; 2072117845Ssam 2073117845Ssam if (op->nsegs > 0) { 2074117845Ssam int i; 2075117845Ssam 2076118882Ssam for (i = 0; i < op->nsegs-1; i++) { 2077117845Ssam if (op->segs[i].ds_len % SAFE_MAX_DSIZE) 2078117845Ssam return (0); 2079117845Ssam if (op->segs[i].ds_len != SAFE_MAX_DSIZE) 2080117845Ssam result = 2; 2081118882Ssam } 2082117845Ssam } 2083117845Ssam return (result); 2084117845Ssam} 2085117845Ssam 2086117845Ssam#ifdef SAFE_DEBUG 2087117845Ssamstatic void 2088117845Ssamsafe_dump_dmastatus(struct safe_softc *sc, const char *tag) 2089117845Ssam{ 2090117845Ssam printf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n" 2091117845Ssam , tag 2092117845Ssam , READ_REG(sc, SAFE_DMA_ENDIAN) 2093117845Ssam , READ_REG(sc, SAFE_DMA_SRCADDR) 2094117845Ssam , READ_REG(sc, SAFE_DMA_DSTADDR) 2095117845Ssam , READ_REG(sc, SAFE_DMA_STAT) 2096117845Ssam ); 2097117845Ssam} 2098117845Ssam 2099117845Ssamstatic void 2100117845Ssamsafe_dump_intrstate(struct safe_softc *sc, const char *tag) 2101117845Ssam{ 2102117845Ssam printf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n" 2103117845Ssam , tag 2104117845Ssam , READ_REG(sc, SAFE_HI_CFG) 2105117845Ssam , READ_REG(sc, SAFE_HI_MASK) 2106117845Ssam , READ_REG(sc, SAFE_HI_DESC_CNT) 2107117845Ssam , READ_REG(sc, SAFE_HU_STAT) 2108117845Ssam , READ_REG(sc, SAFE_HM_STAT) 2109117845Ssam ); 2110117845Ssam} 2111117845Ssam 2112117845Ssamstatic void 2113117845Ssamsafe_dump_ringstate(struct safe_softc *sc, const char *tag) 2114117845Ssam{ 2115117845Ssam u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT); 2116117845Ssam 2117117845Ssam /* NB: assume caller has lock on ring */ 2118125466Speter printf("%s: ERNGSTAT %x (next %u) back %lu front %lu\n", 2119117845Ssam tag, 2120117845Ssam estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S), 2121125466Speter (unsigned long)(sc->sc_back - sc->sc_ring), 2122125466Speter (unsigned long)(sc->sc_front - sc->sc_ring)); 2123117845Ssam} 2124117845Ssam 2125117845Ssamstatic void 2126117845Ssamsafe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re) 2127117845Ssam{ 2128117845Ssam int ix, nsegs; 2129117845Ssam 2130117845Ssam ix = re - sc->sc_ring; 2131117845Ssam printf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n" 2132117845Ssam , tag 2133117845Ssam , re, ix 2134117845Ssam , re->re_desc.d_csr 2135117845Ssam , re->re_desc.d_src 2136117845Ssam , re->re_desc.d_dst 2137117845Ssam , re->re_desc.d_sa 2138117845Ssam , re->re_desc.d_len 2139117845Ssam ); 2140117845Ssam if (re->re_src.nsegs > 1) { 2141117845Ssam ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) / 2142117845Ssam sizeof(struct safe_pdesc); 2143117845Ssam for (nsegs = re->re_src.nsegs; nsegs; nsegs--) { 2144117845Ssam printf(" spd[%u] %p: %p size %u flags %x" 2145117845Ssam , ix, &sc->sc_spring[ix] 2146125466Speter , (caddr_t)(uintptr_t) sc->sc_spring[ix].pd_addr 2147117845Ssam , sc->sc_spring[ix].pd_size 2148117845Ssam , sc->sc_spring[ix].pd_flags 2149117845Ssam ); 2150117845Ssam if (sc->sc_spring[ix].pd_size == 0) 2151117845Ssam printf(" (zero!)"); 2152117845Ssam printf("\n"); 2153117845Ssam if (++ix == SAFE_TOTAL_SPART) 2154117845Ssam ix = 0; 2155117845Ssam } 2156117845Ssam } 2157117845Ssam if (re->re_dst.nsegs > 1) { 2158117845Ssam ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) / 2159117845Ssam sizeof(struct safe_pdesc); 2160117845Ssam for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) { 2161117845Ssam printf(" dpd[%u] %p: %p flags %x\n" 2162117845Ssam , ix, &sc->sc_dpring[ix] 2163125466Speter , (caddr_t)(uintptr_t) sc->sc_dpring[ix].pd_addr 2164117845Ssam , sc->sc_dpring[ix].pd_flags 2165117845Ssam ); 2166117845Ssam if (++ix == SAFE_TOTAL_DPART) 2167117845Ssam ix = 0; 2168117845Ssam } 2169117845Ssam } 2170117845Ssam printf("sa: cmd0 %08x cmd1 %08x staterec %x\n", 2171117845Ssam re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec); 2172117845Ssam printf("sa: key %x %x %x %x %x %x %x %x\n" 2173117845Ssam , re->re_sa.sa_key[0] 2174117845Ssam , re->re_sa.sa_key[1] 2175117845Ssam , re->re_sa.sa_key[2] 2176117845Ssam , re->re_sa.sa_key[3] 2177117845Ssam , re->re_sa.sa_key[4] 2178117845Ssam , re->re_sa.sa_key[5] 2179117845Ssam , re->re_sa.sa_key[6] 2180117845Ssam , re->re_sa.sa_key[7] 2181117845Ssam ); 2182117845Ssam printf("sa: indigest %x %x %x %x %x\n" 2183117845Ssam , re->re_sa.sa_indigest[0] 2184117845Ssam , re->re_sa.sa_indigest[1] 2185117845Ssam , re->re_sa.sa_indigest[2] 2186117845Ssam , re->re_sa.sa_indigest[3] 2187117845Ssam , re->re_sa.sa_indigest[4] 2188117845Ssam ); 2189117845Ssam printf("sa: outdigest %x %x %x %x %x\n" 2190117845Ssam , re->re_sa.sa_outdigest[0] 2191117845Ssam , re->re_sa.sa_outdigest[1] 2192117845Ssam , re->re_sa.sa_outdigest[2] 2193117845Ssam , re->re_sa.sa_outdigest[3] 2194117845Ssam , re->re_sa.sa_outdigest[4] 2195117845Ssam ); 2196117845Ssam printf("sr: iv %x %x %x %x\n" 2197117845Ssam , re->re_sastate.sa_saved_iv[0] 2198117845Ssam , re->re_sastate.sa_saved_iv[1] 2199117845Ssam , re->re_sastate.sa_saved_iv[2] 2200117845Ssam , re->re_sastate.sa_saved_iv[3] 2201117845Ssam ); 2202117845Ssam printf("sr: hashbc %u indigest %x %x %x %x %x\n" 2203117845Ssam , re->re_sastate.sa_saved_hashbc 2204117845Ssam , re->re_sastate.sa_saved_indigest[0] 2205117845Ssam , re->re_sastate.sa_saved_indigest[1] 2206117845Ssam , re->re_sastate.sa_saved_indigest[2] 2207117845Ssam , re->re_sastate.sa_saved_indigest[3] 2208117845Ssam , re->re_sastate.sa_saved_indigest[4] 2209117845Ssam ); 2210117845Ssam} 2211117845Ssam 2212117845Ssamstatic void 2213117845Ssamsafe_dump_ring(struct safe_softc *sc, const char *tag) 2214117845Ssam{ 2215117845Ssam mtx_lock(&sc->sc_ringmtx); 2216117845Ssam printf("\nSafeNet Ring State:\n"); 2217117845Ssam safe_dump_intrstate(sc, tag); 2218117845Ssam safe_dump_dmastatus(sc, tag); 2219117845Ssam safe_dump_ringstate(sc, tag); 2220117845Ssam if (sc->sc_nqchip) { 2221117845Ssam struct safe_ringentry *re = sc->sc_back; 2222117845Ssam do { 2223117845Ssam safe_dump_request(sc, tag, re); 2224117845Ssam if (++re == sc->sc_ringtop) 2225117845Ssam re = sc->sc_ring; 2226117845Ssam } while (re != sc->sc_front); 2227117845Ssam } 2228117845Ssam mtx_unlock(&sc->sc_ringmtx); 2229117845Ssam} 2230117845Ssam 2231117845Ssamstatic int 2232117845Ssamsysctl_hw_safe_dump(SYSCTL_HANDLER_ARGS) 2233117845Ssam{ 2234117845Ssam char dmode[64]; 2235117845Ssam int error; 2236117845Ssam 2237117845Ssam strncpy(dmode, "", sizeof(dmode) - 1); 2238117845Ssam dmode[sizeof(dmode) - 1] = '\0'; 2239117845Ssam error = sysctl_handle_string(oidp, &dmode[0], sizeof(dmode), req); 2240117845Ssam 2241117845Ssam if (error == 0 && req->newptr != NULL) { 2242117845Ssam struct safe_softc *sc = safec; 2243117845Ssam 2244117845Ssam if (!sc) 2245117845Ssam return EINVAL; 2246117845Ssam if (strncmp(dmode, "dma", 3) == 0) 2247117845Ssam safe_dump_dmastatus(sc, "safe0"); 2248117845Ssam else if (strncmp(dmode, "int", 3) == 0) 2249117845Ssam safe_dump_intrstate(sc, "safe0"); 2250117845Ssam else if (strncmp(dmode, "ring", 4) == 0) 2251117845Ssam safe_dump_ring(sc, "safe0"); 2252117845Ssam else 2253117845Ssam return EINVAL; 2254117845Ssam } 2255117845Ssam return error; 2256117845Ssam} 2257117845SsamSYSCTL_PROC(_hw_safe, OID_AUTO, dump, CTLTYPE_STRING | CTLFLAG_RW, 2258117845Ssam 0, 0, sysctl_hw_safe_dump, "A", "Dump driver state"); 2259117845Ssam#endif /* SAFE_DEBUG */ 2260