safe.c revision 159233
1/*- 2 * Copyright (c) 2003 Sam Leffler, Errno Consulting 3 * Copyright (c) 2003 Global Technology Associates, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/safe/safe.c 159233 2006-06-04 15:00:52Z pjd $"); 30 31/* 32 * SafeNet SafeXcel-1141 hardware crypto accelerator 33 */ 34#include "opt_safe.h" 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/proc.h> 39#include <sys/errno.h> 40#include <sys/malloc.h> 41#include <sys/kernel.h> 42#include <sys/mbuf.h> 43#include <sys/module.h> 44#include <sys/lock.h> 45#include <sys/mutex.h> 46#include <sys/sysctl.h> 47#include <sys/endian.h> 48 49#include <vm/vm.h> 50#include <vm/pmap.h> 51 52#include <machine/bus.h> 53#include <machine/resource.h> 54#include <sys/bus.h> 55#include <sys/rman.h> 56 57#include <crypto/sha1.h> 58#include <opencrypto/cryptodev.h> 59#include <opencrypto/cryptosoft.h> 60#include <sys/md5.h> 61#include <sys/random.h> 62 63#include <dev/pci/pcivar.h> 64#include <dev/pci/pcireg.h> 65 66#ifdef SAFE_RNDTEST 67#include <dev/rndtest/rndtest.h> 68#endif 69#include <dev/safe/safereg.h> 70#include <dev/safe/safevar.h> 71 72#ifndef bswap32 73#define bswap32 NTOHL 74#endif 75 76/* 77 * Prototypes and count for the pci_device structure 78 */ 79static int safe_probe(device_t); 80static int safe_attach(device_t); 81static int safe_detach(device_t); 82static int safe_suspend(device_t); 83static int safe_resume(device_t); 84static void safe_shutdown(device_t); 85 86static device_method_t safe_methods[] = { 87 /* Device interface */ 88 DEVMETHOD(device_probe, safe_probe), 89 DEVMETHOD(device_attach, safe_attach), 90 DEVMETHOD(device_detach, safe_detach), 91 DEVMETHOD(device_suspend, safe_suspend), 92 DEVMETHOD(device_resume, safe_resume), 93 DEVMETHOD(device_shutdown, safe_shutdown), 94 95 /* bus interface */ 96 DEVMETHOD(bus_print_child, bus_generic_print_child), 97 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 98 99 { 0, 0 } 100}; 101static driver_t safe_driver = { 102 "safe", 103 safe_methods, 104 sizeof (struct safe_softc) 105}; 106static devclass_t safe_devclass; 107 108DRIVER_MODULE(safe, pci, safe_driver, safe_devclass, 0, 0); 109MODULE_DEPEND(safe, crypto, 1, 1, 1); 110#ifdef SAFE_RNDTEST 111MODULE_DEPEND(safe, rndtest, 1, 1, 1); 112#endif 113 114static void safe_intr(void *); 115static int safe_newsession(void *, u_int32_t *, struct cryptoini *); 116static int safe_freesession(void *, u_int64_t); 117static int safe_process(void *, struct cryptop *, int); 118static void safe_callback(struct safe_softc *, struct safe_ringentry *); 119static void safe_feed(struct safe_softc *, struct safe_ringentry *); 120static void safe_mcopy(struct mbuf *, struct mbuf *, u_int); 121#ifndef SAFE_NO_RNG 122static void safe_rng_init(struct safe_softc *); 123static void safe_rng(void *); 124#endif /* SAFE_NO_RNG */ 125static int safe_dma_malloc(struct safe_softc *, bus_size_t, 126 struct safe_dma_alloc *, int); 127#define safe_dma_sync(_dma, _flags) \ 128 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags)) 129static void safe_dma_free(struct safe_softc *, struct safe_dma_alloc *); 130static int safe_dmamap_aligned(const struct safe_operand *); 131static int safe_dmamap_uniform(const struct safe_operand *); 132 133static void safe_reset_board(struct safe_softc *); 134static void safe_init_board(struct safe_softc *); 135static void safe_init_pciregs(device_t dev); 136static void safe_cleanchip(struct safe_softc *); 137static void safe_totalreset(struct safe_softc *); 138 139static int safe_free_entry(struct safe_softc *, struct safe_ringentry *); 140 141SYSCTL_NODE(_hw, OID_AUTO, safe, CTLFLAG_RD, 0, "SafeNet driver parameters"); 142 143#ifdef SAFE_DEBUG 144static void safe_dump_dmastatus(struct safe_softc *, const char *); 145static void safe_dump_ringstate(struct safe_softc *, const char *); 146static void safe_dump_intrstate(struct safe_softc *, const char *); 147static void safe_dump_request(struct safe_softc *, const char *, 148 struct safe_ringentry *); 149 150static struct safe_softc *safec; /* for use by hw.safe.dump */ 151 152static int safe_debug = 0; 153SYSCTL_INT(_hw_safe, OID_AUTO, debug, CTLFLAG_RW, &safe_debug, 154 0, "control debugging msgs"); 155#define DPRINTF(_x) if (safe_debug) printf _x 156#else 157#define DPRINTF(_x) 158#endif 159 160#define READ_REG(sc,r) \ 161 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 162 163#define WRITE_REG(sc,reg,val) \ 164 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 165 166struct safe_stats safestats; 167SYSCTL_STRUCT(_hw_safe, OID_AUTO, stats, CTLFLAG_RD, &safestats, 168 safe_stats, "driver statistics"); 169#ifndef SAFE_NO_RNG 170static int safe_rnginterval = 1; /* poll once a second */ 171SYSCTL_INT(_hw_safe, OID_AUTO, rnginterval, CTLFLAG_RW, &safe_rnginterval, 172 0, "RNG polling interval (secs)"); 173static int safe_rngbufsize = 16; /* 64 bytes each poll */ 174SYSCTL_INT(_hw_safe, OID_AUTO, rngbufsize, CTLFLAG_RW, &safe_rngbufsize, 175 0, "RNG polling buffer size (32-bit words)"); 176static int safe_rngmaxalarm = 8; /* max alarms before reset */ 177SYSCTL_INT(_hw_safe, OID_AUTO, rngmaxalarm, CTLFLAG_RW, &safe_rngmaxalarm, 178 0, "RNG max alarms before reset"); 179#endif /* SAFE_NO_RNG */ 180 181static int 182safe_probe(device_t dev) 183{ 184 if (pci_get_vendor(dev) == PCI_VENDOR_SAFENET && 185 pci_get_device(dev) == PCI_PRODUCT_SAFEXCEL) 186 return (BUS_PROBE_DEFAULT); 187 return (ENXIO); 188} 189 190static const char* 191safe_partname(struct safe_softc *sc) 192{ 193 /* XXX sprintf numbers when not decoded */ 194 switch (pci_get_vendor(sc->sc_dev)) { 195 case PCI_VENDOR_SAFENET: 196 switch (pci_get_device(sc->sc_dev)) { 197 case PCI_PRODUCT_SAFEXCEL: return "SafeNet SafeXcel-1141"; 198 } 199 return "SafeNet unknown-part"; 200 } 201 return "Unknown-vendor unknown-part"; 202} 203 204#ifndef SAFE_NO_RNG 205static void 206default_harvest(struct rndtest_state *rsp, void *buf, u_int count) 207{ 208 random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 209} 210#endif /* SAFE_NO_RNG */ 211 212static int 213safe_attach(device_t dev) 214{ 215 struct safe_softc *sc = device_get_softc(dev); 216 u_int32_t raddr; 217 u_int32_t cmd, i, devinfo; 218 int rid; 219 220 bzero(sc, sizeof (*sc)); 221 sc->sc_dev = dev; 222 223 /* XXX handle power management */ 224 225 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 226 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 227 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 228 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 229 230 if (!(cmd & PCIM_CMD_MEMEN)) { 231 device_printf(dev, "failed to enable memory mapping\n"); 232 goto bad; 233 } 234 235 if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 236 device_printf(dev, "failed to enable bus mastering\n"); 237 goto bad; 238 } 239 240 /* 241 * Setup memory-mapping of PCI registers. 242 */ 243 rid = BS_BAR; 244 sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 245 RF_ACTIVE); 246 if (sc->sc_sr == NULL) { 247 device_printf(dev, "cannot map register space\n"); 248 goto bad; 249 } 250 sc->sc_st = rman_get_bustag(sc->sc_sr); 251 sc->sc_sh = rman_get_bushandle(sc->sc_sr); 252 253 /* 254 * Arrange interrupt line. 255 */ 256 rid = 0; 257 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 258 RF_SHAREABLE|RF_ACTIVE); 259 if (sc->sc_irq == NULL) { 260 device_printf(dev, "could not map interrupt\n"); 261 goto bad1; 262 } 263 /* 264 * NB: Network code assumes we are blocked with splimp() 265 * so make sure the IRQ is mapped appropriately. 266 */ 267 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 268 safe_intr, sc, &sc->sc_ih)) { 269 device_printf(dev, "could not establish interrupt\n"); 270 goto bad2; 271 } 272 273 sc->sc_cid = crypto_get_driverid(0); 274 if (sc->sc_cid < 0) { 275 device_printf(dev, "could not get crypto driver id\n"); 276 goto bad3; 277 } 278 279 sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) & 280 (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN); 281 282 /* 283 * Setup DMA descriptor area. 284 */ 285 if (bus_dma_tag_create(NULL, /* parent */ 286 1, /* alignment */ 287 SAFE_DMA_BOUNDARY, /* boundary */ 288 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 289 BUS_SPACE_MAXADDR, /* highaddr */ 290 NULL, NULL, /* filter, filterarg */ 291 SAFE_MAX_DMA, /* maxsize */ 292 SAFE_MAX_PART, /* nsegments */ 293 SAFE_MAX_SSIZE, /* maxsegsize */ 294 BUS_DMA_ALLOCNOW, /* flags */ 295 NULL, NULL, /* locking */ 296 &sc->sc_srcdmat)) { 297 device_printf(dev, "cannot allocate DMA tag\n"); 298 goto bad4; 299 } 300 if (bus_dma_tag_create(NULL, /* parent */ 301 sizeof(u_int32_t), /* alignment */ 302 SAFE_MAX_DSIZE, /* boundary */ 303 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 304 BUS_SPACE_MAXADDR, /* highaddr */ 305 NULL, NULL, /* filter, filterarg */ 306 SAFE_MAX_DMA, /* maxsize */ 307 SAFE_MAX_PART, /* nsegments */ 308 SAFE_MAX_DSIZE, /* maxsegsize */ 309 BUS_DMA_ALLOCNOW, /* flags */ 310 NULL, NULL, /* locking */ 311 &sc->sc_dstdmat)) { 312 device_printf(dev, "cannot allocate DMA tag\n"); 313 goto bad4; 314 } 315 316 /* 317 * Allocate packet engine descriptors. 318 */ 319 if (safe_dma_malloc(sc, 320 SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), 321 &sc->sc_ringalloc, 0)) { 322 device_printf(dev, "cannot allocate PE descriptor ring\n"); 323 bus_dma_tag_destroy(sc->sc_srcdmat); 324 goto bad4; 325 } 326 /* 327 * Hookup the static portion of all our data structures. 328 */ 329 sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr; 330 sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE; 331 sc->sc_front = sc->sc_ring; 332 sc->sc_back = sc->sc_ring; 333 raddr = sc->sc_ringalloc.dma_paddr; 334 bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry)); 335 for (i = 0; i < SAFE_MAX_NQUEUE; i++) { 336 struct safe_ringentry *re = &sc->sc_ring[i]; 337 338 re->re_desc.d_sa = raddr + 339 offsetof(struct safe_ringentry, re_sa); 340 re->re_sa.sa_staterec = raddr + 341 offsetof(struct safe_ringentry, re_sastate); 342 343 raddr += sizeof (struct safe_ringentry); 344 } 345 mtx_init(&sc->sc_ringmtx, device_get_nameunit(dev), 346 "packet engine ring", MTX_DEF); 347 348 /* 349 * Allocate scatter and gather particle descriptors. 350 */ 351 if (safe_dma_malloc(sc, SAFE_TOTAL_SPART * sizeof (struct safe_pdesc), 352 &sc->sc_spalloc, 0)) { 353 device_printf(dev, "cannot allocate source particle " 354 "descriptor ring\n"); 355 mtx_destroy(&sc->sc_ringmtx); 356 safe_dma_free(sc, &sc->sc_ringalloc); 357 bus_dma_tag_destroy(sc->sc_srcdmat); 358 goto bad4; 359 } 360 sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr; 361 sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART; 362 sc->sc_spfree = sc->sc_spring; 363 bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc)); 364 365 if (safe_dma_malloc(sc, SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), 366 &sc->sc_dpalloc, 0)) { 367 device_printf(dev, "cannot allocate destination particle " 368 "descriptor ring\n"); 369 mtx_destroy(&sc->sc_ringmtx); 370 safe_dma_free(sc, &sc->sc_spalloc); 371 safe_dma_free(sc, &sc->sc_ringalloc); 372 bus_dma_tag_destroy(sc->sc_dstdmat); 373 goto bad4; 374 } 375 sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr; 376 sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART; 377 sc->sc_dpfree = sc->sc_dpring; 378 bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc)); 379 380 device_printf(sc->sc_dev, "%s", safe_partname(sc)); 381 382 devinfo = READ_REG(sc, SAFE_DEVINFO); 383 if (devinfo & SAFE_DEVINFO_RNG) { 384 sc->sc_flags |= SAFE_FLAGS_RNG; 385 printf(" rng"); 386 } 387 if (devinfo & SAFE_DEVINFO_PKEY) { 388#if 0 389 printf(" key"); 390 sc->sc_flags |= SAFE_FLAGS_KEY; 391 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 392 safe_kprocess, sc); 393 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 394 safe_kprocess, sc); 395#endif 396 } 397 if (devinfo & SAFE_DEVINFO_DES) { 398 printf(" des/3des"); 399 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 400 safe_newsession, safe_freesession, safe_process, sc); 401 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 402 safe_newsession, safe_freesession, safe_process, sc); 403 } 404 if (devinfo & SAFE_DEVINFO_AES) { 405 printf(" aes"); 406 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0, 407 safe_newsession, safe_freesession, safe_process, sc); 408 } 409 if (devinfo & SAFE_DEVINFO_MD5) { 410 printf(" md5"); 411 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 412 safe_newsession, safe_freesession, safe_process, sc); 413 } 414 if (devinfo & SAFE_DEVINFO_SHA1) { 415 printf(" sha1"); 416 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 417 safe_newsession, safe_freesession, safe_process, sc); 418 } 419 printf(" null"); 420 crypto_register(sc->sc_cid, CRYPTO_NULL_CBC, 0, 0, 421 safe_newsession, safe_freesession, safe_process, sc); 422 crypto_register(sc->sc_cid, CRYPTO_NULL_HMAC, 0, 0, 423 safe_newsession, safe_freesession, safe_process, sc); 424 /* XXX other supported algorithms */ 425 printf("\n"); 426 427 safe_reset_board(sc); /* reset h/w */ 428 safe_init_pciregs(dev); /* init pci settings */ 429 safe_init_board(sc); /* init h/w */ 430 431#ifndef SAFE_NO_RNG 432 if (sc->sc_flags & SAFE_FLAGS_RNG) { 433#ifdef SAFE_RNDTEST 434 sc->sc_rndtest = rndtest_attach(dev); 435 if (sc->sc_rndtest) 436 sc->sc_harvest = rndtest_harvest; 437 else 438 sc->sc_harvest = default_harvest; 439#else 440 sc->sc_harvest = default_harvest; 441#endif 442 safe_rng_init(sc); 443 444 callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); 445 callout_reset(&sc->sc_rngto, hz*safe_rnginterval, safe_rng, sc); 446 } 447#endif /* SAFE_NO_RNG */ 448#ifdef SAFE_DEBUG 449 safec = sc; /* for use by hw.safe.dump */ 450#endif 451 return (0); 452bad4: 453 crypto_unregister_all(sc->sc_cid); 454bad3: 455 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 456bad2: 457 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 458bad1: 459 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 460bad: 461 return (ENXIO); 462} 463 464/* 465 * Detach a device that successfully probed. 466 */ 467static int 468safe_detach(device_t dev) 469{ 470 struct safe_softc *sc = device_get_softc(dev); 471 472 /* XXX wait/abort active ops */ 473 474 WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */ 475 476 callout_stop(&sc->sc_rngto); 477 478 crypto_unregister_all(sc->sc_cid); 479 480#ifdef SAFE_RNDTEST 481 if (sc->sc_rndtest) 482 rndtest_detach(sc->sc_rndtest); 483#endif 484 485 safe_cleanchip(sc); 486 safe_dma_free(sc, &sc->sc_dpalloc); 487 safe_dma_free(sc, &sc->sc_spalloc); 488 mtx_destroy(&sc->sc_ringmtx); 489 safe_dma_free(sc, &sc->sc_ringalloc); 490 491 bus_generic_detach(dev); 492 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 493 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 494 495 bus_dma_tag_destroy(sc->sc_srcdmat); 496 bus_dma_tag_destroy(sc->sc_dstdmat); 497 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 498 499 return (0); 500} 501 502/* 503 * Stop all chip i/o so that the kernel's probe routines don't 504 * get confused by errant DMAs when rebooting. 505 */ 506static void 507safe_shutdown(device_t dev) 508{ 509#ifdef notyet 510 safe_stop(device_get_softc(dev)); 511#endif 512} 513 514/* 515 * Device suspend routine. 516 */ 517static int 518safe_suspend(device_t dev) 519{ 520 struct safe_softc *sc = device_get_softc(dev); 521 522#ifdef notyet 523 /* XXX stop the device and save PCI settings */ 524#endif 525 sc->sc_suspended = 1; 526 527 return (0); 528} 529 530static int 531safe_resume(device_t dev) 532{ 533 struct safe_softc *sc = device_get_softc(dev); 534 535#ifdef notyet 536 /* XXX retore PCI settings and start the device */ 537#endif 538 sc->sc_suspended = 0; 539 return (0); 540} 541 542/* 543 * SafeXcel Interrupt routine 544 */ 545static void 546safe_intr(void *arg) 547{ 548 struct safe_softc *sc = arg; 549 volatile u_int32_t stat; 550 551 stat = READ_REG(sc, SAFE_HM_STAT); 552 if (stat == 0) /* shared irq, not for us */ 553 return; 554 555 WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */ 556 557 if ((stat & SAFE_INT_PE_DDONE)) { 558 /* 559 * Descriptor(s) done; scan the ring and 560 * process completed operations. 561 */ 562 mtx_lock(&sc->sc_ringmtx); 563 while (sc->sc_back != sc->sc_front) { 564 struct safe_ringentry *re = sc->sc_back; 565#ifdef SAFE_DEBUG 566 if (safe_debug) { 567 safe_dump_ringstate(sc, __func__); 568 safe_dump_request(sc, __func__, re); 569 } 570#endif 571 /* 572 * safe_process marks ring entries that were allocated 573 * but not used with a csr of zero. This insures the 574 * ring front pointer never needs to be set backwards 575 * in the event that an entry is allocated but not used 576 * because of a setup error. 577 */ 578 if (re->re_desc.d_csr != 0) { 579 if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr)) 580 break; 581 if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len)) 582 break; 583 sc->sc_nqchip--; 584 safe_callback(sc, re); 585 } 586 if (++(sc->sc_back) == sc->sc_ringtop) 587 sc->sc_back = sc->sc_ring; 588 } 589 mtx_unlock(&sc->sc_ringmtx); 590 } 591 592 /* 593 * Check to see if we got any DMA Error 594 */ 595 if (stat & SAFE_INT_PE_ERROR) { 596 DPRINTF(("dmaerr dmastat %08x\n", 597 READ_REG(sc, SAFE_PE_DMASTAT))); 598 safestats.st_dmaerr++; 599 safe_totalreset(sc); 600#if 0 601 safe_feed(sc); 602#endif 603 } 604 605 if (sc->sc_needwakeup) { /* XXX check high watermark */ 606 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 607 DPRINTF(("%s: wakeup crypto %x\n", __func__, 608 sc->sc_needwakeup)); 609 sc->sc_needwakeup &= ~wakeup; 610 crypto_unblock(sc->sc_cid, wakeup); 611 } 612} 613 614/* 615 * safe_feed() - post a request to chip 616 */ 617static void 618safe_feed(struct safe_softc *sc, struct safe_ringentry *re) 619{ 620 bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_PREWRITE); 621 if (re->re_dst_map != NULL) 622 bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map, 623 BUS_DMASYNC_PREREAD); 624 /* XXX have no smaller granularity */ 625 safe_dma_sync(&sc->sc_ringalloc, 626 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 627 safe_dma_sync(&sc->sc_spalloc, BUS_DMASYNC_PREWRITE); 628 safe_dma_sync(&sc->sc_dpalloc, BUS_DMASYNC_PREWRITE); 629 630#ifdef SAFE_DEBUG 631 if (safe_debug) { 632 safe_dump_ringstate(sc, __func__); 633 safe_dump_request(sc, __func__, re); 634 } 635#endif 636 sc->sc_nqchip++; 637 if (sc->sc_nqchip > safestats.st_maxqchip) 638 safestats.st_maxqchip = sc->sc_nqchip; 639 /* poke h/w to check descriptor ring, any value can be written */ 640 WRITE_REG(sc, SAFE_HI_RD_DESCR, 0); 641} 642 643#define N(a) (sizeof(a) / sizeof (a[0])) 644static void 645safe_setup_enckey(struct safe_session *ses, caddr_t key) 646{ 647 int i; 648 649 bcopy(key, ses->ses_key, ses->ses_klen / 8); 650 651 /* PE is little-endian, insure proper byte order */ 652 for (i = 0; i < N(ses->ses_key); i++) 653 ses->ses_key[i] = htole32(ses->ses_key[i]); 654} 655 656static void 657safe_setup_mackey(struct safe_session *ses, int algo, caddr_t key, int klen) 658{ 659 MD5_CTX md5ctx; 660 SHA1_CTX sha1ctx; 661 int i; 662 663 664 for (i = 0; i < klen; i++) 665 key[i] ^= HMAC_IPAD_VAL; 666 667 if (algo == CRYPTO_MD5_HMAC) { 668 MD5Init(&md5ctx); 669 MD5Update(&md5ctx, key, klen); 670 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); 671 bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state)); 672 } else { 673 SHA1Init(&sha1ctx); 674 SHA1Update(&sha1ctx, key, klen); 675 SHA1Update(&sha1ctx, hmac_ipad_buffer, 676 SHA1_HMAC_BLOCK_LEN - klen); 677 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); 678 } 679 680 for (i = 0; i < klen; i++) 681 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 682 683 if (algo == CRYPTO_MD5_HMAC) { 684 MD5Init(&md5ctx); 685 MD5Update(&md5ctx, key, klen); 686 MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); 687 bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state)); 688 } else { 689 SHA1Init(&sha1ctx); 690 SHA1Update(&sha1ctx, key, klen); 691 SHA1Update(&sha1ctx, hmac_opad_buffer, 692 SHA1_HMAC_BLOCK_LEN - klen); 693 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); 694 } 695 696 for (i = 0; i < klen; i++) 697 key[i] ^= HMAC_OPAD_VAL; 698 699 /* PE is little-endian, insure proper byte order */ 700 for (i = 0; i < N(ses->ses_hminner); i++) { 701 ses->ses_hminner[i] = htole32(ses->ses_hminner[i]); 702 ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]); 703 } 704} 705#undef N 706 707/* 708 * Allocate a new 'session' and return an encoded session id. 'sidp' 709 * contains our registration id, and should contain an encoded session 710 * id on successful allocation. 711 */ 712static int 713safe_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 714{ 715 struct cryptoini *c, *encini = NULL, *macini = NULL; 716 struct safe_softc *sc = arg; 717 struct safe_session *ses = NULL; 718 int sesn; 719 720 if (sidp == NULL || cri == NULL || sc == NULL) 721 return (EINVAL); 722 723 for (c = cri; c != NULL; c = c->cri_next) { 724 if (c->cri_alg == CRYPTO_MD5_HMAC || 725 c->cri_alg == CRYPTO_SHA1_HMAC || 726 c->cri_alg == CRYPTO_NULL_HMAC) { 727 if (macini) 728 return (EINVAL); 729 macini = c; 730 } else if (c->cri_alg == CRYPTO_DES_CBC || 731 c->cri_alg == CRYPTO_3DES_CBC || 732 c->cri_alg == CRYPTO_AES_CBC || 733 c->cri_alg == CRYPTO_NULL_CBC) { 734 if (encini) 735 return (EINVAL); 736 encini = c; 737 } else 738 return (EINVAL); 739 } 740 if (encini == NULL && macini == NULL) 741 return (EINVAL); 742 if (encini) { /* validate key length */ 743 switch (encini->cri_alg) { 744 case CRYPTO_DES_CBC: 745 if (encini->cri_klen != 64) 746 return (EINVAL); 747 break; 748 case CRYPTO_3DES_CBC: 749 if (encini->cri_klen != 192) 750 return (EINVAL); 751 break; 752 case CRYPTO_AES_CBC: 753 if (encini->cri_klen != 128 && 754 encini->cri_klen != 192 && 755 encini->cri_klen != 256) 756 return (EINVAL); 757 break; 758 } 759 } 760 761 if (sc->sc_sessions == NULL) { 762 ses = sc->sc_sessions = (struct safe_session *)malloc( 763 sizeof(struct safe_session), M_DEVBUF, M_NOWAIT); 764 if (ses == NULL) 765 return (ENOMEM); 766 sesn = 0; 767 sc->sc_nsessions = 1; 768 } else { 769 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 770 if (sc->sc_sessions[sesn].ses_used == 0) { 771 ses = &sc->sc_sessions[sesn]; 772 break; 773 } 774 } 775 776 if (ses == NULL) { 777 sesn = sc->sc_nsessions; 778 ses = (struct safe_session *)malloc((sesn + 1) * 779 sizeof(struct safe_session), M_DEVBUF, M_NOWAIT); 780 if (ses == NULL) 781 return (ENOMEM); 782 bcopy(sc->sc_sessions, ses, sesn * 783 sizeof(struct safe_session)); 784 bzero(sc->sc_sessions, sesn * 785 sizeof(struct safe_session)); 786 free(sc->sc_sessions, M_DEVBUF); 787 sc->sc_sessions = ses; 788 ses = &sc->sc_sessions[sesn]; 789 sc->sc_nsessions++; 790 } 791 } 792 793 bzero(ses, sizeof(struct safe_session)); 794 ses->ses_used = 1; 795 796 if (encini) { 797 /* get an IV */ 798 /* XXX may read fewer than requested */ 799 read_random(ses->ses_iv, sizeof(ses->ses_iv)); 800 801 ses->ses_klen = encini->cri_klen; 802 if (encini->cri_key != NULL) 803 safe_setup_enckey(ses, encini->cri_key); 804 } 805 806 if (macini) { 807 ses->ses_mlen = macini->cri_mlen; 808 if (ses->ses_mlen == 0) { 809 if (macini->cri_alg == CRYPTO_MD5_HMAC) 810 ses->ses_mlen = MD5_HASH_LEN; 811 else 812 ses->ses_mlen = SHA1_HASH_LEN; 813 } 814 815 if (macini->cri_key != NULL) { 816 safe_setup_mackey(ses, macini->cri_alg, macini->cri_key, 817 macini->cri_klen / 8); 818 } 819 } 820 821 *sidp = SAFE_SID(device_get_unit(sc->sc_dev), sesn); 822 return (0); 823} 824 825/* 826 * Deallocate a session. 827 */ 828static int 829safe_freesession(void *arg, u_int64_t tid) 830{ 831 struct safe_softc *sc = arg; 832 int session, ret; 833 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 834 835 if (sc == NULL) 836 return (EINVAL); 837 838 session = SAFE_SESSION(sid); 839 if (session < sc->sc_nsessions) { 840 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 841 ret = 0; 842 } else 843 ret = EINVAL; 844 return (ret); 845} 846 847static void 848safe_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 849{ 850 struct safe_operand *op = arg; 851 852 DPRINTF(("%s: mapsize %u nsegs %d error %d\n", __func__, 853 (u_int) mapsize, nsegs, error)); 854 if (error != 0) 855 return; 856 op->mapsize = mapsize; 857 op->nsegs = nsegs; 858 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 859} 860 861static int 862safe_process(void *arg, struct cryptop *crp, int hint) 863{ 864 int err = 0, i, nicealign, uniform; 865 struct safe_softc *sc = arg; 866 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 867 int bypass, oplen, ivsize; 868 caddr_t iv; 869 int16_t coffset; 870 struct safe_session *ses; 871 struct safe_ringentry *re; 872 struct safe_sarec *sa; 873 struct safe_pdesc *pd; 874 u_int32_t cmd0, cmd1, staterec; 875 876 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 877 safestats.st_invalid++; 878 return (EINVAL); 879 } 880 if (SAFE_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 881 safestats.st_badsession++; 882 return (EINVAL); 883 } 884 885 mtx_lock(&sc->sc_ringmtx); 886 if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) { 887 safestats.st_ringfull++; 888 sc->sc_needwakeup |= CRYPTO_SYMQ; 889 mtx_unlock(&sc->sc_ringmtx); 890 return (ERESTART); 891 } 892 re = sc->sc_front; 893 894 staterec = re->re_sa.sa_staterec; /* save */ 895 /* NB: zero everything but the PE descriptor */ 896 bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc)); 897 re->re_sa.sa_staterec = staterec; /* restore */ 898 899 re->re_crp = crp; 900 re->re_sesn = SAFE_SESSION(crp->crp_sid); 901 902 if (crp->crp_flags & CRYPTO_F_IMBUF) { 903 re->re_src_m = (struct mbuf *)crp->crp_buf; 904 re->re_dst_m = (struct mbuf *)crp->crp_buf; 905 } else if (crp->crp_flags & CRYPTO_F_IOV) { 906 re->re_src_io = (struct uio *)crp->crp_buf; 907 re->re_dst_io = (struct uio *)crp->crp_buf; 908 } else { 909 safestats.st_badflags++; 910 err = EINVAL; 911 goto errout; /* XXX we don't handle contiguous blocks! */ 912 } 913 914 sa = &re->re_sa; 915 ses = &sc->sc_sessions[re->re_sesn]; 916 917 crd1 = crp->crp_desc; 918 if (crd1 == NULL) { 919 safestats.st_nodesc++; 920 err = EINVAL; 921 goto errout; 922 } 923 crd2 = crd1->crd_next; 924 925 cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */ 926 cmd1 = 0; 927 if (crd2 == NULL) { 928 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 929 crd1->crd_alg == CRYPTO_SHA1_HMAC || 930 crd1->crd_alg == CRYPTO_NULL_HMAC) { 931 maccrd = crd1; 932 enccrd = NULL; 933 cmd0 |= SAFE_SA_CMD0_OP_HASH; 934 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 935 crd1->crd_alg == CRYPTO_3DES_CBC || 936 crd1->crd_alg == CRYPTO_AES_CBC || 937 crd1->crd_alg == CRYPTO_NULL_CBC) { 938 maccrd = NULL; 939 enccrd = crd1; 940 cmd0 |= SAFE_SA_CMD0_OP_CRYPT; 941 } else { 942 safestats.st_badalg++; 943 err = EINVAL; 944 goto errout; 945 } 946 } else { 947 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 948 crd1->crd_alg == CRYPTO_SHA1_HMAC || 949 crd1->crd_alg == CRYPTO_NULL_HMAC) && 950 (crd2->crd_alg == CRYPTO_DES_CBC || 951 crd2->crd_alg == CRYPTO_3DES_CBC || 952 crd2->crd_alg == CRYPTO_AES_CBC || 953 crd2->crd_alg == CRYPTO_NULL_CBC) && 954 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 955 maccrd = crd1; 956 enccrd = crd2; 957 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 958 crd1->crd_alg == CRYPTO_3DES_CBC || 959 crd1->crd_alg == CRYPTO_AES_CBC || 960 crd1->crd_alg == CRYPTO_NULL_CBC) && 961 (crd2->crd_alg == CRYPTO_MD5_HMAC || 962 crd2->crd_alg == CRYPTO_SHA1_HMAC || 963 crd2->crd_alg == CRYPTO_NULL_HMAC) && 964 (crd1->crd_flags & CRD_F_ENCRYPT)) { 965 enccrd = crd1; 966 maccrd = crd2; 967 } else { 968 safestats.st_badalg++; 969 err = EINVAL; 970 goto errout; 971 } 972 cmd0 |= SAFE_SA_CMD0_OP_BOTH; 973 } 974 975 if (enccrd) { 976 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) 977 safe_setup_enckey(ses, enccrd->crd_key); 978 979 if (enccrd->crd_alg == CRYPTO_DES_CBC) { 980 cmd0 |= SAFE_SA_CMD0_DES; 981 cmd1 |= SAFE_SA_CMD1_CBC; 982 ivsize = 2*sizeof(u_int32_t); 983 } else if (enccrd->crd_alg == CRYPTO_3DES_CBC) { 984 cmd0 |= SAFE_SA_CMD0_3DES; 985 cmd1 |= SAFE_SA_CMD1_CBC; 986 ivsize = 2*sizeof(u_int32_t); 987 } else if (enccrd->crd_alg == CRYPTO_AES_CBC) { 988 cmd0 |= SAFE_SA_CMD0_AES; 989 cmd1 |= SAFE_SA_CMD1_CBC; 990 if (ses->ses_klen == 128) 991 cmd1 |= SAFE_SA_CMD1_AES128; 992 else if (ses->ses_klen == 192) 993 cmd1 |= SAFE_SA_CMD1_AES192; 994 else 995 cmd1 |= SAFE_SA_CMD1_AES256; 996 ivsize = 4*sizeof(u_int32_t); 997 } else { 998 cmd0 |= SAFE_SA_CMD0_CRYPT_NULL; 999 ivsize = 0; 1000 } 1001 1002 /* 1003 * Setup encrypt/decrypt state. When using basic ops 1004 * we can't use an inline IV because hash/crypt offset 1005 * must be from the end of the IV to the start of the 1006 * crypt data and this leaves out the preceding header 1007 * from the hash calculation. Instead we place the IV 1008 * in the state record and set the hash/crypt offset to 1009 * copy both the header+IV. 1010 */ 1011 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1012 cmd0 |= SAFE_SA_CMD0_OUTBOUND; 1013 1014 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1015 iv = enccrd->crd_iv; 1016 else 1017 iv = (caddr_t) ses->ses_iv; 1018 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1019 if (crp->crp_flags & CRYPTO_F_IMBUF) 1020 m_copyback(re->re_src_m, 1021 enccrd->crd_inject, ivsize, iv); 1022 else if (crp->crp_flags & CRYPTO_F_IOV) 1023 cuio_copyback(re->re_src_io, 1024 enccrd->crd_inject, ivsize, iv); 1025 } 1026 bcopy(iv, re->re_sastate.sa_saved_iv, ivsize); 1027 cmd0 |= SAFE_SA_CMD0_IVLD_STATE | SAFE_SA_CMD0_SAVEIV; 1028 re->re_flags |= SAFE_QFLAGS_COPYOUTIV; 1029 } else { 1030 cmd0 |= SAFE_SA_CMD0_INBOUND; 1031 1032 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1033 bcopy(enccrd->crd_iv, 1034 re->re_sastate.sa_saved_iv, ivsize); 1035 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1036 m_copydata(re->re_src_m, enccrd->crd_inject, 1037 ivsize, 1038 (caddr_t)re->re_sastate.sa_saved_iv); 1039 else if (crp->crp_flags & CRYPTO_F_IOV) 1040 cuio_copydata(re->re_src_io, enccrd->crd_inject, 1041 ivsize, 1042 (caddr_t)re->re_sastate.sa_saved_iv); 1043 cmd0 |= SAFE_SA_CMD0_IVLD_STATE; 1044 } 1045 /* 1046 * For basic encryption use the zero pad algorithm. 1047 * This pads results to an 8-byte boundary and 1048 * suppresses padding verification for inbound (i.e. 1049 * decrypt) operations. 1050 * 1051 * NB: Not sure if the 8-byte pad boundary is a problem. 1052 */ 1053 cmd0 |= SAFE_SA_CMD0_PAD_ZERO; 1054 1055 /* XXX assert key bufs have the same size */ 1056 bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key)); 1057 } 1058 1059 if (maccrd) { 1060 if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { 1061 safe_setup_mackey(ses, maccrd->crd_alg, 1062 maccrd->crd_key, maccrd->crd_klen / 8); 1063 } 1064 1065 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) { 1066 cmd0 |= SAFE_SA_CMD0_MD5; 1067 cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ 1068 } else if (maccrd->crd_alg == CRYPTO_SHA1_HMAC) { 1069 cmd0 |= SAFE_SA_CMD0_SHA1; 1070 cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ 1071 } else { 1072 cmd0 |= SAFE_SA_CMD0_HASH_NULL; 1073 } 1074 /* 1075 * Digest data is loaded from the SA and the hash 1076 * result is saved to the state block where we 1077 * retrieve it for return to the caller. 1078 */ 1079 /* XXX assert digest bufs have the same size */ 1080 bcopy(ses->ses_hminner, sa->sa_indigest, 1081 sizeof(sa->sa_indigest)); 1082 bcopy(ses->ses_hmouter, sa->sa_outdigest, 1083 sizeof(sa->sa_outdigest)); 1084 1085 cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH; 1086 re->re_flags |= SAFE_QFLAGS_COPYOUTICV; 1087 } 1088 1089 if (enccrd && maccrd) { 1090 /* 1091 * The offset from hash data to the start of 1092 * crypt data is the difference in the skips. 1093 */ 1094 bypass = maccrd->crd_skip; 1095 coffset = enccrd->crd_skip - maccrd->crd_skip; 1096 if (coffset < 0) { 1097 DPRINTF(("%s: hash does not precede crypt; " 1098 "mac skip %u enc skip %u\n", 1099 __func__, maccrd->crd_skip, enccrd->crd_skip)); 1100 safestats.st_skipmismatch++; 1101 err = EINVAL; 1102 goto errout; 1103 } 1104 oplen = enccrd->crd_skip + enccrd->crd_len; 1105 if (maccrd->crd_skip + maccrd->crd_len != oplen) { 1106 DPRINTF(("%s: hash amount %u != crypt amount %u\n", 1107 __func__, maccrd->crd_skip + maccrd->crd_len, 1108 oplen)); 1109 safestats.st_lenmismatch++; 1110 err = EINVAL; 1111 goto errout; 1112 } 1113#ifdef SAFE_DEBUG 1114 if (safe_debug) { 1115 printf("mac: skip %d, len %d, inject %d\n", 1116 maccrd->crd_skip, maccrd->crd_len, 1117 maccrd->crd_inject); 1118 printf("enc: skip %d, len %d, inject %d\n", 1119 enccrd->crd_skip, enccrd->crd_len, 1120 enccrd->crd_inject); 1121 printf("bypass %d coffset %d oplen %d\n", 1122 bypass, coffset, oplen); 1123 } 1124#endif 1125 if (coffset & 3) { /* offset must be 32-bit aligned */ 1126 DPRINTF(("%s: coffset %u misaligned\n", 1127 __func__, coffset)); 1128 safestats.st_coffmisaligned++; 1129 err = EINVAL; 1130 goto errout; 1131 } 1132 coffset >>= 2; 1133 if (coffset > 255) { /* offset must be <256 dwords */ 1134 DPRINTF(("%s: coffset %u too big\n", 1135 __func__, coffset)); 1136 safestats.st_cofftoobig++; 1137 err = EINVAL; 1138 goto errout; 1139 } 1140 /* 1141 * Tell the hardware to copy the header to the output. 1142 * The header is defined as the data from the end of 1143 * the bypass to the start of data to be encrypted. 1144 * Typically this is the inline IV. Note that you need 1145 * to do this even if src+dst are the same; it appears 1146 * that w/o this bit the crypted data is written 1147 * immediately after the bypass data. 1148 */ 1149 cmd1 |= SAFE_SA_CMD1_HDRCOPY; 1150 /* 1151 * Disable IP header mutable bit handling. This is 1152 * needed to get correct HMAC calculations. 1153 */ 1154 cmd1 |= SAFE_SA_CMD1_MUTABLE; 1155 } else { 1156 if (enccrd) { 1157 bypass = enccrd->crd_skip; 1158 oplen = bypass + enccrd->crd_len; 1159 } else { 1160 bypass = maccrd->crd_skip; 1161 oplen = bypass + maccrd->crd_len; 1162 } 1163 coffset = 0; 1164 } 1165 /* XXX verify multiple of 4 when using s/g */ 1166 if (bypass > 96) { /* bypass offset must be <= 96 bytes */ 1167 DPRINTF(("%s: bypass %u too big\n", __func__, bypass)); 1168 safestats.st_bypasstoobig++; 1169 err = EINVAL; 1170 goto errout; 1171 } 1172 1173 if (bus_dmamap_create(sc->sc_srcdmat, BUS_DMA_NOWAIT, &re->re_src_map)) { 1174 safestats.st_nomap++; 1175 err = ENOMEM; 1176 goto errout; 1177 } 1178 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1179 if (bus_dmamap_load_mbuf(sc->sc_srcdmat, re->re_src_map, 1180 re->re_src_m, safe_op_cb, 1181 &re->re_src, BUS_DMA_NOWAIT) != 0) { 1182 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1183 re->re_src_map = NULL; 1184 safestats.st_noload++; 1185 err = ENOMEM; 1186 goto errout; 1187 } 1188 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1189 if (bus_dmamap_load_uio(sc->sc_srcdmat, re->re_src_map, 1190 re->re_src_io, safe_op_cb, 1191 &re->re_src, BUS_DMA_NOWAIT) != 0) { 1192 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1193 re->re_src_map = NULL; 1194 safestats.st_noload++; 1195 err = ENOMEM; 1196 goto errout; 1197 } 1198 } 1199 nicealign = safe_dmamap_aligned(&re->re_src); 1200 uniform = safe_dmamap_uniform(&re->re_src); 1201 1202 DPRINTF(("src nicealign %u uniform %u nsegs %u\n", 1203 nicealign, uniform, re->re_src.nsegs)); 1204 if (re->re_src.nsegs > 1) { 1205 re->re_desc.d_src = sc->sc_spalloc.dma_paddr + 1206 ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring); 1207 for (i = 0; i < re->re_src_nsegs; i++) { 1208 /* NB: no need to check if there's space */ 1209 pd = sc->sc_spfree; 1210 if (++(sc->sc_spfree) == sc->sc_springtop) 1211 sc->sc_spfree = sc->sc_spring; 1212 1213 KASSERT((pd->pd_flags&3) == 0 || 1214 (pd->pd_flags&3) == SAFE_PD_DONE, 1215 ("bogus source particle descriptor; flags %x", 1216 pd->pd_flags)); 1217 pd->pd_addr = re->re_src_segs[i].ds_addr; 1218 pd->pd_size = re->re_src_segs[i].ds_len; 1219 pd->pd_flags = SAFE_PD_READY; 1220 } 1221 cmd0 |= SAFE_SA_CMD0_IGATHER; 1222 } else { 1223 /* 1224 * No need for gather, reference the operand directly. 1225 */ 1226 re->re_desc.d_src = re->re_src_segs[0].ds_addr; 1227 } 1228 1229 if (enccrd == NULL && maccrd != NULL) { 1230 /* 1231 * Hash op; no destination needed. 1232 */ 1233 } else { 1234 if (crp->crp_flags & CRYPTO_F_IOV) { 1235 if (!nicealign) { 1236 safestats.st_iovmisaligned++; 1237 err = EINVAL; 1238 goto errout; 1239 } 1240 if (uniform != 1) { 1241 /* 1242 * Source is not suitable for direct use as 1243 * the destination. Create a new scatter/gather 1244 * list based on the destination requirements 1245 * and check if that's ok. 1246 */ 1247 if (bus_dmamap_create(sc->sc_dstdmat, 1248 BUS_DMA_NOWAIT, &re->re_dst_map)) { 1249 safestats.st_nomap++; 1250 err = ENOMEM; 1251 goto errout; 1252 } 1253 if (bus_dmamap_load_uio(sc->sc_dstdmat, 1254 re->re_dst_map, re->re_dst_io, 1255 safe_op_cb, &re->re_dst, 1256 BUS_DMA_NOWAIT) != 0) { 1257 bus_dmamap_destroy(sc->sc_dstdmat, 1258 re->re_dst_map); 1259 re->re_dst_map = NULL; 1260 safestats.st_noload++; 1261 err = ENOMEM; 1262 goto errout; 1263 } 1264 uniform = safe_dmamap_uniform(&re->re_dst); 1265 if (!uniform) { 1266 /* 1267 * There's no way to handle the DMA 1268 * requirements with this uio. We 1269 * could create a separate DMA area for 1270 * the result and then copy it back, 1271 * but for now we just bail and return 1272 * an error. Note that uio requests 1273 * > SAFE_MAX_DSIZE are handled because 1274 * the DMA map and segment list for the 1275 * destination wil result in a 1276 * destination particle list that does 1277 * the necessary scatter DMA. 1278 */ 1279 safestats.st_iovnotuniform++; 1280 err = EINVAL; 1281 goto errout; 1282 } 1283 } else 1284 re->re_dst = re->re_src; 1285 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1286 if (nicealign && uniform == 1) { 1287 /* 1288 * Source layout is suitable for direct 1289 * sharing of the DMA map and segment list. 1290 */ 1291 re->re_dst = re->re_src; 1292 } else if (nicealign && uniform == 2) { 1293 /* 1294 * The source is properly aligned but requires a 1295 * different particle list to handle DMA of the 1296 * result. Create a new map and do the load to 1297 * create the segment list. The particle 1298 * descriptor setup code below will handle the 1299 * rest. 1300 */ 1301 if (bus_dmamap_create(sc->sc_dstdmat, 1302 BUS_DMA_NOWAIT, &re->re_dst_map)) { 1303 safestats.st_nomap++; 1304 err = ENOMEM; 1305 goto errout; 1306 } 1307 if (bus_dmamap_load_mbuf(sc->sc_dstdmat, 1308 re->re_dst_map, re->re_dst_m, 1309 safe_op_cb, &re->re_dst, 1310 BUS_DMA_NOWAIT) != 0) { 1311 bus_dmamap_destroy(sc->sc_dstdmat, 1312 re->re_dst_map); 1313 re->re_dst_map = NULL; 1314 safestats.st_noload++; 1315 err = ENOMEM; 1316 goto errout; 1317 } 1318 } else { /* !(aligned and/or uniform) */ 1319 int totlen, len; 1320 struct mbuf *m, *top, **mp; 1321 1322 /* 1323 * DMA constraints require that we allocate a 1324 * new mbuf chain for the destination. We 1325 * allocate an entire new set of mbufs of 1326 * optimal/required size and then tell the 1327 * hardware to copy any bits that are not 1328 * created as a byproduct of the operation. 1329 */ 1330 if (!nicealign) 1331 safestats.st_unaligned++; 1332 if (!uniform) 1333 safestats.st_notuniform++; 1334 totlen = re->re_src_mapsize; 1335 if (re->re_src_m->m_flags & M_PKTHDR) { 1336 len = MHLEN; 1337 MGETHDR(m, M_DONTWAIT, MT_DATA); 1338 if (m && !m_dup_pkthdr(m, re->re_src_m, 1339 M_DONTWAIT)) { 1340 m_free(m); 1341 m = NULL; 1342 } 1343 } else { 1344 len = MLEN; 1345 MGET(m, M_DONTWAIT, MT_DATA); 1346 } 1347 if (m == NULL) { 1348 safestats.st_nombuf++; 1349 err = sc->sc_nqchip ? ERESTART : ENOMEM; 1350 goto errout; 1351 } 1352 if (totlen >= MINCLSIZE) { 1353 MCLGET(m, M_DONTWAIT); 1354 if ((m->m_flags & M_EXT) == 0) { 1355 m_free(m); 1356 safestats.st_nomcl++; 1357 err = sc->sc_nqchip ? 1358 ERESTART : ENOMEM; 1359 goto errout; 1360 } 1361 len = MCLBYTES; 1362 } 1363 m->m_len = len; 1364 top = NULL; 1365 mp = ⊤ 1366 1367 while (totlen > 0) { 1368 if (top) { 1369 MGET(m, M_DONTWAIT, MT_DATA); 1370 if (m == NULL) { 1371 m_freem(top); 1372 safestats.st_nombuf++; 1373 err = sc->sc_nqchip ? 1374 ERESTART : ENOMEM; 1375 goto errout; 1376 } 1377 len = MLEN; 1378 } 1379 if (top && totlen >= MINCLSIZE) { 1380 MCLGET(m, M_DONTWAIT); 1381 if ((m->m_flags & M_EXT) == 0) { 1382 *mp = m; 1383 m_freem(top); 1384 safestats.st_nomcl++; 1385 err = sc->sc_nqchip ? 1386 ERESTART : ENOMEM; 1387 goto errout; 1388 } 1389 len = MCLBYTES; 1390 } 1391 m->m_len = len = min(totlen, len); 1392 totlen -= len; 1393 *mp = m; 1394 mp = &m->m_next; 1395 } 1396 re->re_dst_m = top; 1397 if (bus_dmamap_create(sc->sc_dstdmat, 1398 BUS_DMA_NOWAIT, &re->re_dst_map) != 0) { 1399 safestats.st_nomap++; 1400 err = ENOMEM; 1401 goto errout; 1402 } 1403 if (bus_dmamap_load_mbuf(sc->sc_dstdmat, 1404 re->re_dst_map, re->re_dst_m, 1405 safe_op_cb, &re->re_dst, 1406 BUS_DMA_NOWAIT) != 0) { 1407 bus_dmamap_destroy(sc->sc_dstdmat, 1408 re->re_dst_map); 1409 re->re_dst_map = NULL; 1410 safestats.st_noload++; 1411 err = ENOMEM; 1412 goto errout; 1413 } 1414 if (re->re_src.mapsize > oplen) { 1415 /* 1416 * There's data following what the 1417 * hardware will copy for us. If this 1418 * isn't just the ICV (that's going to 1419 * be written on completion), copy it 1420 * to the new mbufs 1421 */ 1422 if (!(maccrd && 1423 (re->re_src.mapsize-oplen) == 12 && 1424 maccrd->crd_inject == oplen)) 1425 safe_mcopy(re->re_src_m, 1426 re->re_dst_m, 1427 oplen); 1428 else 1429 safestats.st_noicvcopy++; 1430 } 1431 } 1432 } else { 1433 safestats.st_badflags++; 1434 err = EINVAL; 1435 goto errout; 1436 } 1437 1438 if (re->re_dst.nsegs > 1) { 1439 re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr + 1440 ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring); 1441 for (i = 0; i < re->re_dst_nsegs; i++) { 1442 pd = sc->sc_dpfree; 1443 KASSERT((pd->pd_flags&3) == 0 || 1444 (pd->pd_flags&3) == SAFE_PD_DONE, 1445 ("bogus dest particle descriptor; flags %x", 1446 pd->pd_flags)); 1447 if (++(sc->sc_dpfree) == sc->sc_dpringtop) 1448 sc->sc_dpfree = sc->sc_dpring; 1449 pd->pd_addr = re->re_dst_segs[i].ds_addr; 1450 pd->pd_flags = SAFE_PD_READY; 1451 } 1452 cmd0 |= SAFE_SA_CMD0_OSCATTER; 1453 } else { 1454 /* 1455 * No need for scatter, reference the operand directly. 1456 */ 1457 re->re_desc.d_dst = re->re_dst_segs[0].ds_addr; 1458 } 1459 } 1460 1461 /* 1462 * All done with setup; fillin the SA command words 1463 * and the packet engine descriptor. The operation 1464 * is now ready for submission to the hardware. 1465 */ 1466 sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI; 1467 sa->sa_cmd1 = cmd1 1468 | (coffset << SAFE_SA_CMD1_OFFSET_S) 1469 | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */ 1470 | SAFE_SA_CMD1_SRPCI 1471 ; 1472 /* 1473 * NB: the order of writes is important here. In case the 1474 * chip is scanning the ring because of an outstanding request 1475 * it might nab this one too. In that case we need to make 1476 * sure the setup is complete before we write the length 1477 * field of the descriptor as it signals the descriptor is 1478 * ready for processing. 1479 */ 1480 re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI; 1481 if (maccrd) 1482 re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL; 1483 re->re_desc.d_len = oplen 1484 | SAFE_PE_LEN_READY 1485 | (bypass << SAFE_PE_LEN_BYPASS_S) 1486 ; 1487 1488 safestats.st_ipackets++; 1489 safestats.st_ibytes += oplen; 1490 1491 if (++(sc->sc_front) == sc->sc_ringtop) 1492 sc->sc_front = sc->sc_ring; 1493 1494 /* XXX honor batching */ 1495 safe_feed(sc, re); 1496 mtx_unlock(&sc->sc_ringmtx); 1497 return (0); 1498 1499errout: 1500 if ((re->re_dst_m != NULL) && (re->re_src_m != re->re_dst_m)) 1501 m_freem(re->re_dst_m); 1502 1503 if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) { 1504 bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map); 1505 bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map); 1506 } 1507 if (re->re_src_map != NULL) { 1508 bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map); 1509 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1510 } 1511 mtx_unlock(&sc->sc_ringmtx); 1512 if (err != ERESTART) { 1513 crp->crp_etype = err; 1514 crypto_done(crp); 1515 } else { 1516 sc->sc_needwakeup |= CRYPTO_SYMQ; 1517 } 1518 return (err); 1519} 1520 1521static void 1522safe_callback(struct safe_softc *sc, struct safe_ringentry *re) 1523{ 1524 struct cryptop *crp = (struct cryptop *)re->re_crp; 1525 struct cryptodesc *crd; 1526 1527 safestats.st_opackets++; 1528 safestats.st_obytes += re->re_dst.mapsize; 1529 1530 safe_dma_sync(&sc->sc_ringalloc, 1531 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1532 if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) { 1533 device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n", 1534 re->re_desc.d_csr, 1535 re->re_sa.sa_cmd0, re->re_sa.sa_cmd1); 1536 safestats.st_peoperr++; 1537 crp->crp_etype = EIO; /* something more meaningful? */ 1538 } 1539 if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) { 1540 bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map, 1541 BUS_DMASYNC_POSTREAD); 1542 bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map); 1543 bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map); 1544 } 1545 bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_POSTWRITE); 1546 bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map); 1547 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1548 1549 /* 1550 * If result was written to a differet mbuf chain, swap 1551 * it in as the return value and reclaim the original. 1552 */ 1553 if ((crp->crp_flags & CRYPTO_F_IMBUF) && re->re_src_m != re->re_dst_m) { 1554 m_freem(re->re_src_m); 1555 crp->crp_buf = (caddr_t)re->re_dst_m; 1556 } 1557 1558 if (re->re_flags & SAFE_QFLAGS_COPYOUTIV) { 1559 /* copy out IV for future use */ 1560 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1561 int ivsize; 1562 1563 if (crd->crd_alg == CRYPTO_DES_CBC || 1564 crd->crd_alg == CRYPTO_3DES_CBC) { 1565 ivsize = 2*sizeof(u_int32_t); 1566 } else if (crd->crd_alg == CRYPTO_AES_CBC) { 1567 ivsize = 4*sizeof(u_int32_t); 1568 } else 1569 continue; 1570 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1571 m_copydata((struct mbuf *)crp->crp_buf, 1572 crd->crd_skip + crd->crd_len - ivsize, 1573 ivsize, 1574 (caddr_t) sc->sc_sessions[re->re_sesn].ses_iv); 1575 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1576 cuio_copydata((struct uio *)crp->crp_buf, 1577 crd->crd_skip + crd->crd_len - ivsize, 1578 ivsize, 1579 (caddr_t)sc->sc_sessions[re->re_sesn].ses_iv); 1580 } 1581 break; 1582 } 1583 } 1584 1585 if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) { 1586 /* copy out ICV result */ 1587 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1588 if (!(crd->crd_alg == CRYPTO_MD5_HMAC || 1589 crd->crd_alg == CRYPTO_SHA1_HMAC || 1590 crd->crd_alg == CRYPTO_NULL_HMAC)) 1591 continue; 1592 if (crd->crd_alg == CRYPTO_SHA1_HMAC) { 1593 /* 1594 * SHA-1 ICV's are byte-swapped; fix 'em up 1595 * before copy them to their destination. 1596 */ 1597 bswap32(re->re_sastate.sa_saved_indigest[0]); 1598 bswap32(re->re_sastate.sa_saved_indigest[1]); 1599 bswap32(re->re_sastate.sa_saved_indigest[2]); 1600 } 1601 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1602 m_copyback((struct mbuf *)crp->crp_buf, 1603 crd->crd_inject, 1604 sc->sc_sessions[re->re_sesn].ses_mlen, 1605 (caddr_t)re->re_sastate.sa_saved_indigest); 1606 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1607 cuio_copyback((struct uio *)crp->crp_buf, 1608 crd->crd_inject, 1609 sc->sc_sessions[re->re_sesn].ses_mlen, 1610 (caddr_t)re->re_sastate.sa_saved_indigest); 1611 } 1612 break; 1613 } 1614 } 1615 crypto_done(crp); 1616} 1617 1618/* 1619 * Copy all data past offset from srcm to dstm. 1620 */ 1621static void 1622safe_mcopy(struct mbuf *srcm, struct mbuf *dstm, u_int offset) 1623{ 1624 u_int j, dlen, slen; 1625 caddr_t dptr, sptr; 1626 1627 /* 1628 * Advance src and dst to offset. 1629 */ 1630 j = offset; 1631 while (j >= 0) { 1632 if (srcm->m_len > j) 1633 break; 1634 j -= srcm->m_len; 1635 srcm = srcm->m_next; 1636 if (srcm == NULL) 1637 return; 1638 } 1639 sptr = mtod(srcm, caddr_t) + j; 1640 slen = srcm->m_len - j; 1641 1642 j = offset; 1643 while (j >= 0) { 1644 if (dstm->m_len > j) 1645 break; 1646 j -= dstm->m_len; 1647 dstm = dstm->m_next; 1648 if (dstm == NULL) 1649 return; 1650 } 1651 dptr = mtod(dstm, caddr_t) + j; 1652 dlen = dstm->m_len - j; 1653 1654 /* 1655 * Copy everything that remains. 1656 */ 1657 for (;;) { 1658 j = min(slen, dlen); 1659 bcopy(sptr, dptr, j); 1660 if (slen == j) { 1661 srcm = srcm->m_next; 1662 if (srcm == NULL) 1663 return; 1664 sptr = srcm->m_data; 1665 slen = srcm->m_len; 1666 } else 1667 sptr += j, slen -= j; 1668 if (dlen == j) { 1669 dstm = dstm->m_next; 1670 if (dstm == NULL) 1671 return; 1672 dptr = dstm->m_data; 1673 dlen = dstm->m_len; 1674 } else 1675 dptr += j, dlen -= j; 1676 } 1677} 1678 1679#ifndef SAFE_NO_RNG 1680#define SAFE_RNG_MAXWAIT 1000 1681 1682static void 1683safe_rng_init(struct safe_softc *sc) 1684{ 1685 u_int32_t w, v; 1686 int i; 1687 1688 WRITE_REG(sc, SAFE_RNG_CTRL, 0); 1689 /* use default value according to the manual */ 1690 WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */ 1691 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1692 1693 /* 1694 * There is a bug in rev 1.0 of the 1140 that when the RNG 1695 * is brought out of reset the ready status flag does not 1696 * work until the RNG has finished its internal initialization. 1697 * 1698 * So in order to determine the device is through its 1699 * initialization we must read the data register, using the 1700 * status reg in the read in case it is initialized. Then read 1701 * the data register until it changes from the first read. 1702 * Once it changes read the data register until it changes 1703 * again. At this time the RNG is considered initialized. 1704 * This could take between 750ms - 1000ms in time. 1705 */ 1706 i = 0; 1707 w = READ_REG(sc, SAFE_RNG_OUT); 1708 do { 1709 v = READ_REG(sc, SAFE_RNG_OUT); 1710 if (v != w) { 1711 w = v; 1712 break; 1713 } 1714 DELAY(10); 1715 } while (++i < SAFE_RNG_MAXWAIT); 1716 1717 /* Wait Until data changes again */ 1718 i = 0; 1719 do { 1720 v = READ_REG(sc, SAFE_RNG_OUT); 1721 if (v != w) 1722 break; 1723 DELAY(10); 1724 } while (++i < SAFE_RNG_MAXWAIT); 1725} 1726 1727static __inline void 1728safe_rng_disable_short_cycle(struct safe_softc *sc) 1729{ 1730 WRITE_REG(sc, SAFE_RNG_CTRL, 1731 READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN); 1732} 1733 1734static __inline void 1735safe_rng_enable_short_cycle(struct safe_softc *sc) 1736{ 1737 WRITE_REG(sc, SAFE_RNG_CTRL, 1738 READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN); 1739} 1740 1741static __inline u_int32_t 1742safe_rng_read(struct safe_softc *sc) 1743{ 1744 int i; 1745 1746 i = 0; 1747 while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT) 1748 ; 1749 return READ_REG(sc, SAFE_RNG_OUT); 1750} 1751 1752static void 1753safe_rng(void *arg) 1754{ 1755 struct safe_softc *sc = arg; 1756 u_int32_t buf[SAFE_RNG_MAXBUFSIZ]; /* NB: maybe move to softc */ 1757 u_int maxwords; 1758 int i; 1759 1760 safestats.st_rng++; 1761 /* 1762 * Fetch the next block of data. 1763 */ 1764 maxwords = safe_rngbufsize; 1765 if (maxwords > SAFE_RNG_MAXBUFSIZ) 1766 maxwords = SAFE_RNG_MAXBUFSIZ; 1767retry: 1768 for (i = 0; i < maxwords; i++) 1769 buf[i] = safe_rng_read(sc); 1770 /* 1771 * Check the comparator alarm count and reset the h/w if 1772 * it exceeds our threshold. This guards against the 1773 * hardware oscillators resonating with external signals. 1774 */ 1775 if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) { 1776 u_int32_t freq_inc, w; 1777 1778 DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__, 1779 READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm)); 1780 safestats.st_rngalarm++; 1781 safe_rng_enable_short_cycle(sc); 1782 freq_inc = 18; 1783 for (i = 0; i < 64; i++) { 1784 w = READ_REG(sc, SAFE_RNG_CNFG); 1785 freq_inc = ((w + freq_inc) & 0x3fL); 1786 w = ((w & ~0x3fL) | freq_inc); 1787 WRITE_REG(sc, SAFE_RNG_CNFG, w); 1788 1789 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1790 1791 (void) safe_rng_read(sc); 1792 DELAY(25); 1793 1794 if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) { 1795 safe_rng_disable_short_cycle(sc); 1796 goto retry; 1797 } 1798 freq_inc = 1; 1799 } 1800 safe_rng_disable_short_cycle(sc); 1801 } else 1802 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1803 1804 (*sc->sc_harvest)(sc->sc_rndtest, buf, maxwords*sizeof (u_int32_t)); 1805 callout_reset(&sc->sc_rngto, 1806 hz * (safe_rnginterval ? safe_rnginterval : 1), safe_rng, sc); 1807} 1808#endif /* SAFE_NO_RNG */ 1809 1810static void 1811safe_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1812{ 1813 bus_addr_t *paddr = (bus_addr_t*) arg; 1814 *paddr = segs->ds_addr; 1815} 1816 1817static int 1818safe_dma_malloc( 1819 struct safe_softc *sc, 1820 bus_size_t size, 1821 struct safe_dma_alloc *dma, 1822 int mapflags 1823) 1824{ 1825 int r; 1826 1827 r = bus_dma_tag_create(NULL, /* parent */ 1828 sizeof(u_int32_t), 0, /* alignment, bounds */ 1829 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1830 BUS_SPACE_MAXADDR, /* highaddr */ 1831 NULL, NULL, /* filter, filterarg */ 1832 size, /* maxsize */ 1833 1, /* nsegments */ 1834 size, /* maxsegsize */ 1835 BUS_DMA_ALLOCNOW, /* flags */ 1836 NULL, NULL, /* locking */ 1837 &dma->dma_tag); 1838 if (r != 0) { 1839 device_printf(sc->sc_dev, "safe_dma_malloc: " 1840 "bus_dma_tag_create failed; error %u\n", r); 1841 goto fail_0; 1842 } 1843 1844 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map); 1845 if (r != 0) { 1846 device_printf(sc->sc_dev, "safe_dma_malloc: " 1847 "bus_dmamap_create failed; error %u\n", r); 1848 goto fail_1; 1849 } 1850 1851 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 1852 BUS_DMA_NOWAIT, &dma->dma_map); 1853 if (r != 0) { 1854 device_printf(sc->sc_dev, "safe_dma_malloc: " 1855 "bus_dmammem_alloc failed; size %zu, error %u\n", 1856 size, r); 1857 goto fail_2; 1858 } 1859 1860 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 1861 size, 1862 safe_dmamap_cb, 1863 &dma->dma_paddr, 1864 mapflags | BUS_DMA_NOWAIT); 1865 if (r != 0) { 1866 device_printf(sc->sc_dev, "safe_dma_malloc: " 1867 "bus_dmamap_load failed; error %u\n", r); 1868 goto fail_3; 1869 } 1870 1871 dma->dma_size = size; 1872 return (0); 1873 1874fail_3: 1875 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1876fail_2: 1877 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1878fail_1: 1879 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1880 bus_dma_tag_destroy(dma->dma_tag); 1881fail_0: 1882 dma->dma_map = NULL; 1883 dma->dma_tag = NULL; 1884 return (r); 1885} 1886 1887static void 1888safe_dma_free(struct safe_softc *sc, struct safe_dma_alloc *dma) 1889{ 1890 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1891 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1892 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1893 bus_dma_tag_destroy(dma->dma_tag); 1894} 1895 1896/* 1897 * Resets the board. Values in the regesters are left as is 1898 * from the reset (i.e. initial values are assigned elsewhere). 1899 */ 1900static void 1901safe_reset_board(struct safe_softc *sc) 1902{ 1903 u_int32_t v; 1904 /* 1905 * Reset the device. The manual says no delay 1906 * is needed between marking and clearing reset. 1907 */ 1908 v = READ_REG(sc, SAFE_PE_DMACFG) &~ 1909 (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET | 1910 SAFE_PE_DMACFG_SGRESET); 1911 WRITE_REG(sc, SAFE_PE_DMACFG, v 1912 | SAFE_PE_DMACFG_PERESET 1913 | SAFE_PE_DMACFG_PDRRESET 1914 | SAFE_PE_DMACFG_SGRESET); 1915 WRITE_REG(sc, SAFE_PE_DMACFG, v); 1916} 1917 1918/* 1919 * Initialize registers we need to touch only once. 1920 */ 1921static void 1922safe_init_board(struct safe_softc *sc) 1923{ 1924 u_int32_t v, dwords; 1925 1926 v = READ_REG(sc, SAFE_PE_DMACFG);; 1927 v &=~ SAFE_PE_DMACFG_PEMODE; 1928 v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */ 1929 | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ 1930 | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ 1931 | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ 1932 | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ 1933 | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ 1934 ; 1935 WRITE_REG(sc, SAFE_PE_DMACFG, v); 1936#if 0 1937 /* XXX select byte swap based on host byte order */ 1938 WRITE_REG(sc, SAFE_ENDIAN, 0x1b); 1939#endif 1940 if (sc->sc_chiprev == SAFE_REV(1,0)) { 1941 /* 1942 * Avoid large PCI DMA transfers. Rev 1.0 has a bug where 1943 * "target mode transfers" done while the chip is DMA'ing 1944 * >1020 bytes cause the hardware to lockup. To avoid this 1945 * we reduce the max PCI transfer size and use small source 1946 * particle descriptors (<= 256 bytes). 1947 */ 1948 WRITE_REG(sc, SAFE_DMA_CFG, 256); 1949 device_printf(sc->sc_dev, 1950 "Reduce max DMA size to %u words for rev %u.%u WAR\n", 1951 (READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff, 1952 SAFE_REV_MAJ(sc->sc_chiprev), 1953 SAFE_REV_MIN(sc->sc_chiprev)); 1954 } 1955 1956 /* NB: operands+results are overlaid */ 1957 WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr); 1958 WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr); 1959 /* 1960 * Configure ring entry size and number of items in the ring. 1961 */ 1962 KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0, 1963 ("PE ring entry not 32-bit aligned!")); 1964 dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t); 1965 WRITE_REG(sc, SAFE_PE_RINGCFG, 1966 (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE); 1967 WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */ 1968 1969 WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr); 1970 WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr); 1971 WRITE_REG(sc, SAFE_PE_PARTSIZE, 1972 (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART); 1973 /* 1974 * NB: destination particles are fixed size. We use 1975 * an mbuf cluster and require all results go to 1976 * clusters or smaller. 1977 */ 1978 WRITE_REG(sc, SAFE_PE_PARTCFG, SAFE_MAX_DSIZE); 1979 1980 /* it's now safe to enable PE mode, do it */ 1981 WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE); 1982 1983 /* 1984 * Configure hardware to use level-triggered interrupts and 1985 * to interrupt after each descriptor is processed. 1986 */ 1987 WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL); 1988 WRITE_REG(sc, SAFE_HI_DESC_CNT, 1); 1989 WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR); 1990} 1991 1992/* 1993 * Init PCI registers 1994 */ 1995static void 1996safe_init_pciregs(device_t dev) 1997{ 1998} 1999 2000/* 2001 * Clean up after a chip crash. 2002 * It is assumed that the caller in splimp() 2003 */ 2004static void 2005safe_cleanchip(struct safe_softc *sc) 2006{ 2007 2008 if (sc->sc_nqchip != 0) { 2009 struct safe_ringentry *re = sc->sc_back; 2010 2011 while (re != sc->sc_front) { 2012 if (re->re_desc.d_csr != 0) 2013 safe_free_entry(sc, re); 2014 if (++re == sc->sc_ringtop) 2015 re = sc->sc_ring; 2016 } 2017 sc->sc_back = re; 2018 sc->sc_nqchip = 0; 2019 } 2020} 2021 2022/* 2023 * free a safe_q 2024 * It is assumed that the caller is within splimp(). 2025 */ 2026static int 2027safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re) 2028{ 2029 struct cryptop *crp; 2030 2031 /* 2032 * Free header MCR 2033 */ 2034 if ((re->re_dst_m != NULL) && (re->re_src_m != re->re_dst_m)) 2035 m_freem(re->re_dst_m); 2036 2037 crp = (struct cryptop *)re->re_crp; 2038 2039 re->re_desc.d_csr = 0; 2040 2041 crp->crp_etype = EFAULT; 2042 crypto_done(crp); 2043 return(0); 2044} 2045 2046/* 2047 * Routine to reset the chip and clean up. 2048 * It is assumed that the caller is in splimp() 2049 */ 2050static void 2051safe_totalreset(struct safe_softc *sc) 2052{ 2053 safe_reset_board(sc); 2054 safe_init_board(sc); 2055 safe_cleanchip(sc); 2056} 2057 2058/* 2059 * Is the operand suitable aligned for direct DMA. Each 2060 * segment must be aligned on a 32-bit boundary and all 2061 * but the last segment must be a multiple of 4 bytes. 2062 */ 2063static int 2064safe_dmamap_aligned(const struct safe_operand *op) 2065{ 2066 int i; 2067 2068 for (i = 0; i < op->nsegs; i++) { 2069 if (op->segs[i].ds_addr & 3) 2070 return (0); 2071 if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3)) 2072 return (0); 2073 } 2074 return (1); 2075} 2076 2077/* 2078 * Is the operand suitable for direct DMA as the destination 2079 * of an operation. The hardware requires that each ``particle'' 2080 * but the last in an operation result have the same size. We 2081 * fix that size at SAFE_MAX_DSIZE bytes. This routine returns 2082 * 0 if some segment is not a multiple of of this size, 1 if all 2083 * segments are exactly this size, or 2 if segments are at worst 2084 * a multple of this size. 2085 */ 2086static int 2087safe_dmamap_uniform(const struct safe_operand *op) 2088{ 2089 int result = 1; 2090 2091 if (op->nsegs > 0) { 2092 int i; 2093 2094 for (i = 0; i < op->nsegs-1; i++) { 2095 if (op->segs[i].ds_len % SAFE_MAX_DSIZE) 2096 return (0); 2097 if (op->segs[i].ds_len != SAFE_MAX_DSIZE) 2098 result = 2; 2099 } 2100 } 2101 return (result); 2102} 2103 2104#ifdef SAFE_DEBUG 2105static void 2106safe_dump_dmastatus(struct safe_softc *sc, const char *tag) 2107{ 2108 printf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n" 2109 , tag 2110 , READ_REG(sc, SAFE_DMA_ENDIAN) 2111 , READ_REG(sc, SAFE_DMA_SRCADDR) 2112 , READ_REG(sc, SAFE_DMA_DSTADDR) 2113 , READ_REG(sc, SAFE_DMA_STAT) 2114 ); 2115} 2116 2117static void 2118safe_dump_intrstate(struct safe_softc *sc, const char *tag) 2119{ 2120 printf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n" 2121 , tag 2122 , READ_REG(sc, SAFE_HI_CFG) 2123 , READ_REG(sc, SAFE_HI_MASK) 2124 , READ_REG(sc, SAFE_HI_DESC_CNT) 2125 , READ_REG(sc, SAFE_HU_STAT) 2126 , READ_REG(sc, SAFE_HM_STAT) 2127 ); 2128} 2129 2130static void 2131safe_dump_ringstate(struct safe_softc *sc, const char *tag) 2132{ 2133 u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT); 2134 2135 /* NB: assume caller has lock on ring */ 2136 printf("%s: ERNGSTAT %x (next %u) back %lu front %lu\n", 2137 tag, 2138 estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S), 2139 (unsigned long)(sc->sc_back - sc->sc_ring), 2140 (unsigned long)(sc->sc_front - sc->sc_ring)); 2141} 2142 2143static void 2144safe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re) 2145{ 2146 int ix, nsegs; 2147 2148 ix = re - sc->sc_ring; 2149 printf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n" 2150 , tag 2151 , re, ix 2152 , re->re_desc.d_csr 2153 , re->re_desc.d_src 2154 , re->re_desc.d_dst 2155 , re->re_desc.d_sa 2156 , re->re_desc.d_len 2157 ); 2158 if (re->re_src.nsegs > 1) { 2159 ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) / 2160 sizeof(struct safe_pdesc); 2161 for (nsegs = re->re_src.nsegs; nsegs; nsegs--) { 2162 printf(" spd[%u] %p: %p size %u flags %x" 2163 , ix, &sc->sc_spring[ix] 2164 , (caddr_t)(uintptr_t) sc->sc_spring[ix].pd_addr 2165 , sc->sc_spring[ix].pd_size 2166 , sc->sc_spring[ix].pd_flags 2167 ); 2168 if (sc->sc_spring[ix].pd_size == 0) 2169 printf(" (zero!)"); 2170 printf("\n"); 2171 if (++ix == SAFE_TOTAL_SPART) 2172 ix = 0; 2173 } 2174 } 2175 if (re->re_dst.nsegs > 1) { 2176 ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) / 2177 sizeof(struct safe_pdesc); 2178 for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) { 2179 printf(" dpd[%u] %p: %p flags %x\n" 2180 , ix, &sc->sc_dpring[ix] 2181 , (caddr_t)(uintptr_t) sc->sc_dpring[ix].pd_addr 2182 , sc->sc_dpring[ix].pd_flags 2183 ); 2184 if (++ix == SAFE_TOTAL_DPART) 2185 ix = 0; 2186 } 2187 } 2188 printf("sa: cmd0 %08x cmd1 %08x staterec %x\n", 2189 re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec); 2190 printf("sa: key %x %x %x %x %x %x %x %x\n" 2191 , re->re_sa.sa_key[0] 2192 , re->re_sa.sa_key[1] 2193 , re->re_sa.sa_key[2] 2194 , re->re_sa.sa_key[3] 2195 , re->re_sa.sa_key[4] 2196 , re->re_sa.sa_key[5] 2197 , re->re_sa.sa_key[6] 2198 , re->re_sa.sa_key[7] 2199 ); 2200 printf("sa: indigest %x %x %x %x %x\n" 2201 , re->re_sa.sa_indigest[0] 2202 , re->re_sa.sa_indigest[1] 2203 , re->re_sa.sa_indigest[2] 2204 , re->re_sa.sa_indigest[3] 2205 , re->re_sa.sa_indigest[4] 2206 ); 2207 printf("sa: outdigest %x %x %x %x %x\n" 2208 , re->re_sa.sa_outdigest[0] 2209 , re->re_sa.sa_outdigest[1] 2210 , re->re_sa.sa_outdigest[2] 2211 , re->re_sa.sa_outdigest[3] 2212 , re->re_sa.sa_outdigest[4] 2213 ); 2214 printf("sr: iv %x %x %x %x\n" 2215 , re->re_sastate.sa_saved_iv[0] 2216 , re->re_sastate.sa_saved_iv[1] 2217 , re->re_sastate.sa_saved_iv[2] 2218 , re->re_sastate.sa_saved_iv[3] 2219 ); 2220 printf("sr: hashbc %u indigest %x %x %x %x %x\n" 2221 , re->re_sastate.sa_saved_hashbc 2222 , re->re_sastate.sa_saved_indigest[0] 2223 , re->re_sastate.sa_saved_indigest[1] 2224 , re->re_sastate.sa_saved_indigest[2] 2225 , re->re_sastate.sa_saved_indigest[3] 2226 , re->re_sastate.sa_saved_indigest[4] 2227 ); 2228} 2229 2230static void 2231safe_dump_ring(struct safe_softc *sc, const char *tag) 2232{ 2233 mtx_lock(&sc->sc_ringmtx); 2234 printf("\nSafeNet Ring State:\n"); 2235 safe_dump_intrstate(sc, tag); 2236 safe_dump_dmastatus(sc, tag); 2237 safe_dump_ringstate(sc, tag); 2238 if (sc->sc_nqchip) { 2239 struct safe_ringentry *re = sc->sc_back; 2240 do { 2241 safe_dump_request(sc, tag, re); 2242 if (++re == sc->sc_ringtop) 2243 re = sc->sc_ring; 2244 } while (re != sc->sc_front); 2245 } 2246 mtx_unlock(&sc->sc_ringmtx); 2247} 2248 2249static int 2250sysctl_hw_safe_dump(SYSCTL_HANDLER_ARGS) 2251{ 2252 char dmode[64]; 2253 int error; 2254 2255 strncpy(dmode, "", sizeof(dmode) - 1); 2256 dmode[sizeof(dmode) - 1] = '\0'; 2257 error = sysctl_handle_string(oidp, &dmode[0], sizeof(dmode), req); 2258 2259 if (error == 0 && req->newptr != NULL) { 2260 struct safe_softc *sc = safec; 2261 2262 if (!sc) 2263 return EINVAL; 2264 if (strncmp(dmode, "dma", 3) == 0) 2265 safe_dump_dmastatus(sc, "safe0"); 2266 else if (strncmp(dmode, "int", 3) == 0) 2267 safe_dump_intrstate(sc, "safe0"); 2268 else if (strncmp(dmode, "ring", 4) == 0) 2269 safe_dump_ring(sc, "safe0"); 2270 else 2271 return EINVAL; 2272 } 2273 return error; 2274} 2275SYSCTL_PROC(_hw_safe, OID_AUTO, dump, CTLTYPE_STRING | CTLFLAG_RW, 2276 0, 0, sysctl_hw_safe_dump, "A", "Dump driver state"); 2277#endif /* SAFE_DEBUG */ 2278