safe.c revision 125466
1117845Ssam/*- 2117845Ssam * Copyright (c) 2003 Sam Leffler, Errno Consulting 3117845Ssam * Copyright (c) 2003 Global Technology Associates, Inc. 4117845Ssam * All rights reserved. 5117845Ssam * 6117845Ssam * Redistribution and use in source and binary forms, with or without 7117845Ssam * modification, are permitted provided that the following conditions 8117845Ssam * are met: 9117845Ssam * 1. Redistributions of source code must retain the above copyright 10117845Ssam * notice, this list of conditions and the following disclaimer. 11117845Ssam * 2. Redistributions in binary form must reproduce the above copyright 12117845Ssam * notice, this list of conditions and the following disclaimer in the 13117845Ssam * documentation and/or other materials provided with the distribution. 14117845Ssam * 15117845Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16117845Ssam * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17117845Ssam * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18117845Ssam * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19117845Ssam * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20117845Ssam * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21117845Ssam * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22117845Ssam * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23117845Ssam * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24117845Ssam * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25117845Ssam * SUCH DAMAGE. 26117845Ssam */ 27117845Ssam 28117845Ssam#include <sys/cdefs.h> 29117845Ssam__FBSDID("$FreeBSD: head/sys/dev/safe/safe.c 125466 2004-02-05 01:35:33Z peter $"); 30117845Ssam 31117845Ssam/* 32117845Ssam * SafeNet SafeXcel-1141 hardware crypto accelerator 33117845Ssam */ 34117845Ssam#include "opt_safe.h" 35117845Ssam 36117845Ssam#include <sys/param.h> 37117845Ssam#include <sys/systm.h> 38117845Ssam#include <sys/proc.h> 39117845Ssam#include <sys/errno.h> 40117845Ssam#include <sys/malloc.h> 41117845Ssam#include <sys/kernel.h> 42117845Ssam#include <sys/mbuf.h> 43117845Ssam#include <sys/lock.h> 44117845Ssam#include <sys/mutex.h> 45117845Ssam#include <sys/sysctl.h> 46117845Ssam#include <sys/endian.h> 47117845Ssam 48117845Ssam#include <vm/vm.h> 49117845Ssam#include <vm/pmap.h> 50117845Ssam 51117845Ssam#include <machine/clock.h> 52117845Ssam#include <machine/bus.h> 53117845Ssam#include <machine/resource.h> 54117845Ssam#include <sys/bus.h> 55117845Ssam#include <sys/rman.h> 56117845Ssam 57117845Ssam#include <crypto/sha1.h> 58117845Ssam#include <opencrypto/cryptodev.h> 59117845Ssam#include <opencrypto/cryptosoft.h> 60117845Ssam#include <sys/md5.h> 61117845Ssam#include <sys/random.h> 62117845Ssam 63119287Simp#include <dev/pci/pcivar.h> 64119287Simp#include <dev/pci/pcireg.h> 65117845Ssam 66117845Ssam#ifdef SAFE_RNDTEST 67117845Ssam#include <dev/rndtest/rndtest.h> 68117845Ssam#endif 69117845Ssam#include <dev/safe/safereg.h> 70117845Ssam#include <dev/safe/safevar.h> 71117845Ssam 72117845Ssam#ifndef bswap32 73117845Ssam#define bswap32 NTOHL 74117845Ssam#endif 75117845Ssam 76117845Ssam/* 77117845Ssam * Prototypes and count for the pci_device structure 78117845Ssam */ 79117845Ssamstatic int safe_probe(device_t); 80117845Ssamstatic int safe_attach(device_t); 81117845Ssamstatic int safe_detach(device_t); 82117845Ssamstatic int safe_suspend(device_t); 83117845Ssamstatic int safe_resume(device_t); 84117845Ssamstatic void safe_shutdown(device_t); 85117845Ssam 86117845Ssamstatic device_method_t safe_methods[] = { 87117845Ssam /* Device interface */ 88117845Ssam DEVMETHOD(device_probe, safe_probe), 89117845Ssam DEVMETHOD(device_attach, safe_attach), 90117845Ssam DEVMETHOD(device_detach, safe_detach), 91117845Ssam DEVMETHOD(device_suspend, safe_suspend), 92117845Ssam DEVMETHOD(device_resume, safe_resume), 93117845Ssam DEVMETHOD(device_shutdown, safe_shutdown), 94117845Ssam 95117845Ssam /* bus interface */ 96117845Ssam DEVMETHOD(bus_print_child, bus_generic_print_child), 97117845Ssam DEVMETHOD(bus_driver_added, bus_generic_driver_added), 98117845Ssam 99117845Ssam { 0, 0 } 100117845Ssam}; 101117845Ssamstatic driver_t safe_driver = { 102117845Ssam "safe", 103117845Ssam safe_methods, 104117845Ssam sizeof (struct safe_softc) 105117845Ssam}; 106117845Ssamstatic devclass_t safe_devclass; 107117845Ssam 108117845SsamDRIVER_MODULE(safe, pci, safe_driver, safe_devclass, 0, 0); 109117845SsamMODULE_DEPEND(safe, crypto, 1, 1, 1); 110117845Ssam#ifdef SAFE_RNDTEST 111117845SsamMODULE_DEPEND(safe, rndtest, 1, 1, 1); 112117845Ssam#endif 113117845Ssam 114117845Ssamstatic void safe_intr(void *); 115117845Ssamstatic int safe_newsession(void *, u_int32_t *, struct cryptoini *); 116117845Ssamstatic int safe_freesession(void *, u_int64_t); 117117845Ssamstatic int safe_process(void *, struct cryptop *, int); 118117845Ssamstatic void safe_callback(struct safe_softc *, struct safe_ringentry *); 119117845Ssamstatic void safe_feed(struct safe_softc *, struct safe_ringentry *); 120117845Ssamstatic void safe_mcopy(struct mbuf *, struct mbuf *, u_int); 121117845Ssam#ifndef SAFE_NO_RNG 122117845Ssamstatic void safe_rng_init(struct safe_softc *); 123117845Ssamstatic void safe_rng(void *); 124117845Ssam#endif /* SAFE_NO_RNG */ 125117845Ssamstatic int safe_dma_malloc(struct safe_softc *, bus_size_t, 126117845Ssam struct safe_dma_alloc *, int); 127117845Ssam#define safe_dma_sync(_dma, _flags) \ 128117845Ssam bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags)) 129117845Ssamstatic void safe_dma_free(struct safe_softc *, struct safe_dma_alloc *); 130117845Ssamstatic int safe_dmamap_aligned(const struct safe_operand *); 131117845Ssamstatic int safe_dmamap_uniform(const struct safe_operand *); 132117845Ssam 133117845Ssamstatic void safe_reset_board(struct safe_softc *); 134117845Ssamstatic void safe_init_board(struct safe_softc *); 135117845Ssamstatic void safe_init_pciregs(device_t dev); 136117845Ssamstatic void safe_cleanchip(struct safe_softc *); 137117845Ssamstatic void safe_totalreset(struct safe_softc *); 138117845Ssam 139117845Ssamstatic int safe_free_entry(struct safe_softc *, struct safe_ringentry *); 140117845Ssam 141117845SsamSYSCTL_NODE(_hw, OID_AUTO, safe, CTLFLAG_RD, 0, "SafeNet driver parameters"); 142117845Ssam 143117845Ssam#ifdef SAFE_DEBUG 144117845Ssamstatic void safe_dump_dmastatus(struct safe_softc *, const char *); 145117845Ssamstatic void safe_dump_ringstate(struct safe_softc *, const char *); 146117845Ssamstatic void safe_dump_intrstate(struct safe_softc *, const char *); 147117845Ssamstatic void safe_dump_request(struct safe_softc *, const char *, 148117845Ssam struct safe_ringentry *); 149117845Ssam 150117845Ssamstatic struct safe_softc *safec; /* for use by hw.safe.dump */ 151117845Ssam 152117845Ssamstatic int safe_debug = 0; 153117845SsamSYSCTL_INT(_hw_safe, OID_AUTO, debug, CTLFLAG_RW, &safe_debug, 154117845Ssam 0, "control debugging msgs"); 155117845Ssam#define DPRINTF(_x) if (safe_debug) printf _x 156117845Ssam#else 157117845Ssam#define DPRINTF(_x) 158117845Ssam#endif 159117845Ssam 160117845Ssam#define READ_REG(sc,r) \ 161117845Ssam bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 162117845Ssam 163117845Ssam#define WRITE_REG(sc,reg,val) \ 164117845Ssam bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 165117845Ssam 166117845Ssamstruct safe_stats safestats; 167117845SsamSYSCTL_STRUCT(_hw_safe, OID_AUTO, stats, CTLFLAG_RD, &safestats, 168117845Ssam safe_stats, "driver statistics"); 169117845Ssam#ifndef SAFE_NO_RNG 170117845Ssamstatic int safe_rnginterval = 1; /* poll once a second */ 171117845SsamSYSCTL_INT(_hw_safe, OID_AUTO, rnginterval, CTLFLAG_RW, &safe_rnginterval, 172117845Ssam 0, "RNG polling interval (secs)"); 173117845Ssamstatic int safe_rngbufsize = 16; /* 64 bytes each poll */ 174117845SsamSYSCTL_INT(_hw_safe, OID_AUTO, rngbufsize, CTLFLAG_RW, &safe_rngbufsize, 175117845Ssam 0, "RNG polling buffer size (32-bit words)"); 176117845Ssamstatic int safe_rngmaxalarm = 8; /* max alarms before reset */ 177117845SsamSYSCTL_INT(_hw_safe, OID_AUTO, rngmaxalarm, CTLFLAG_RW, &safe_rngmaxalarm, 178117845Ssam 0, "RNG max alarms before reset"); 179117845Ssam#endif /* SAFE_NO_RNG */ 180117845Ssam 181117845Ssamstatic int 182117845Ssamsafe_probe(device_t dev) 183117845Ssam{ 184117845Ssam if (pci_get_vendor(dev) == PCI_VENDOR_SAFENET && 185117845Ssam pci_get_device(dev) == PCI_PRODUCT_SAFEXCEL) 186117845Ssam return (0); 187117845Ssam return (ENXIO); 188117845Ssam} 189117845Ssam 190117845Ssamstatic const char* 191117845Ssamsafe_partname(struct safe_softc *sc) 192117845Ssam{ 193117845Ssam /* XXX sprintf numbers when not decoded */ 194117845Ssam switch (pci_get_vendor(sc->sc_dev)) { 195117845Ssam case PCI_VENDOR_SAFENET: 196117845Ssam switch (pci_get_device(sc->sc_dev)) { 197117845Ssam case PCI_PRODUCT_SAFEXCEL: return "SafeNet SafeXcel-1141"; 198117845Ssam } 199117845Ssam return "SafeNet unknown-part"; 200117845Ssam } 201117845Ssam return "Unknown-vendor unknown-part"; 202117845Ssam} 203117845Ssam 204117845Ssam#ifndef SAFE_NO_RNG 205117845Ssamstatic void 206117845Ssamdefault_harvest(struct rndtest_state *rsp, void *buf, u_int count) 207117845Ssam{ 208117845Ssam random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 209117845Ssam} 210117845Ssam#endif /* SAFE_NO_RNG */ 211117845Ssam 212117845Ssamstatic int 213117845Ssamsafe_attach(device_t dev) 214117845Ssam{ 215117845Ssam struct safe_softc *sc = device_get_softc(dev); 216117845Ssam u_int32_t raddr; 217117845Ssam u_int32_t cmd, i, devinfo; 218117845Ssam int rid; 219117845Ssam 220117845Ssam bzero(sc, sizeof (*sc)); 221117845Ssam sc->sc_dev = dev; 222117845Ssam 223117845Ssam /* XXX handle power management */ 224117845Ssam 225117845Ssam cmd = pci_read_config(dev, PCIR_COMMAND, 4); 226117845Ssam cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 227117845Ssam pci_write_config(dev, PCIR_COMMAND, cmd, 4); 228117845Ssam cmd = pci_read_config(dev, PCIR_COMMAND, 4); 229117845Ssam 230117845Ssam if (!(cmd & PCIM_CMD_MEMEN)) { 231117845Ssam device_printf(dev, "failed to enable memory mapping\n"); 232117845Ssam goto bad; 233117845Ssam } 234117845Ssam 235117845Ssam if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 236117845Ssam device_printf(dev, "failed to enable bus mastering\n"); 237117845Ssam goto bad; 238117845Ssam } 239117845Ssam 240117845Ssam /* 241117845Ssam * Setup memory-mapping of PCI registers. 242117845Ssam */ 243117845Ssam rid = BS_BAR; 244117845Ssam sc->sc_sr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 245117845Ssam 0, ~0, 1, RF_ACTIVE); 246117845Ssam if (sc->sc_sr == NULL) { 247117845Ssam device_printf(dev, "cannot map register space\n"); 248117845Ssam goto bad; 249117845Ssam } 250117845Ssam sc->sc_st = rman_get_bustag(sc->sc_sr); 251117845Ssam sc->sc_sh = rman_get_bushandle(sc->sc_sr); 252117845Ssam 253117845Ssam /* 254117845Ssam * Arrange interrupt line. 255117845Ssam */ 256117845Ssam rid = 0; 257117845Ssam sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 258117845Ssam 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE); 259117845Ssam if (sc->sc_irq == NULL) { 260117845Ssam device_printf(dev, "could not map interrupt\n"); 261117845Ssam goto bad1; 262117845Ssam } 263117845Ssam /* 264117845Ssam * NB: Network code assumes we are blocked with splimp() 265117845Ssam * so make sure the IRQ is mapped appropriately. 266117845Ssam */ 267117845Ssam if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 268117845Ssam safe_intr, sc, &sc->sc_ih)) { 269117845Ssam device_printf(dev, "could not establish interrupt\n"); 270117845Ssam goto bad2; 271117845Ssam } 272117845Ssam 273117845Ssam sc->sc_cid = crypto_get_driverid(0); 274117845Ssam if (sc->sc_cid < 0) { 275117845Ssam device_printf(dev, "could not get crypto driver id\n"); 276117845Ssam goto bad3; 277117845Ssam } 278117845Ssam 279117845Ssam sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) & 280117845Ssam (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN); 281117845Ssam 282117845Ssam /* 283117845Ssam * Setup DMA descriptor area. 284117845Ssam */ 285117845Ssam if (bus_dma_tag_create(NULL, /* parent */ 286117845Ssam 1, /* alignment */ 287117845Ssam SAFE_DMA_BOUNDARY, /* boundary */ 288117845Ssam BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 289117845Ssam BUS_SPACE_MAXADDR, /* highaddr */ 290117845Ssam NULL, NULL, /* filter, filterarg */ 291117845Ssam SAFE_MAX_DMA, /* maxsize */ 292117845Ssam SAFE_MAX_PART, /* nsegments */ 293117845Ssam SAFE_MAX_SSIZE, /* maxsegsize */ 294117845Ssam BUS_DMA_ALLOCNOW, /* flags */ 295117845Ssam NULL, NULL, /* locking */ 296117845Ssam &sc->sc_srcdmat)) { 297117845Ssam device_printf(dev, "cannot allocate DMA tag\n"); 298117845Ssam goto bad4; 299117845Ssam } 300117845Ssam if (bus_dma_tag_create(NULL, /* parent */ 301117845Ssam sizeof(u_int32_t), /* alignment */ 302117845Ssam SAFE_MAX_DSIZE, /* boundary */ 303117845Ssam BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 304117845Ssam BUS_SPACE_MAXADDR, /* highaddr */ 305117845Ssam NULL, NULL, /* filter, filterarg */ 306117845Ssam SAFE_MAX_DMA, /* maxsize */ 307117845Ssam SAFE_MAX_PART, /* nsegments */ 308117845Ssam SAFE_MAX_DSIZE, /* maxsegsize */ 309117845Ssam BUS_DMA_ALLOCNOW, /* flags */ 310117845Ssam NULL, NULL, /* locking */ 311117845Ssam &sc->sc_dstdmat)) { 312117845Ssam device_printf(dev, "cannot allocate DMA tag\n"); 313117845Ssam goto bad4; 314117845Ssam } 315117845Ssam 316117845Ssam /* 317117845Ssam * Allocate packet engine descriptors. 318117845Ssam */ 319117845Ssam if (safe_dma_malloc(sc, 320117845Ssam SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), 321117845Ssam &sc->sc_ringalloc, 0)) { 322117845Ssam device_printf(dev, "cannot allocate PE descriptor ring\n"); 323117845Ssam bus_dma_tag_destroy(sc->sc_srcdmat); 324117845Ssam goto bad4; 325117845Ssam } 326117845Ssam /* 327117845Ssam * Hookup the static portion of all our data structures. 328117845Ssam */ 329117845Ssam sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr; 330117845Ssam sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE; 331117845Ssam sc->sc_front = sc->sc_ring; 332117845Ssam sc->sc_back = sc->sc_ring; 333117845Ssam raddr = sc->sc_ringalloc.dma_paddr; 334117845Ssam bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry)); 335117845Ssam for (i = 0; i < SAFE_MAX_NQUEUE; i++) { 336117845Ssam struct safe_ringentry *re = &sc->sc_ring[i]; 337117845Ssam 338117845Ssam re->re_desc.d_sa = raddr + 339117845Ssam offsetof(struct safe_ringentry, re_sa); 340117845Ssam re->re_sa.sa_staterec = raddr + 341117845Ssam offsetof(struct safe_ringentry, re_sastate); 342117845Ssam 343117845Ssam raddr += sizeof (struct safe_ringentry); 344117845Ssam } 345117845Ssam mtx_init(&sc->sc_ringmtx, device_get_nameunit(dev), 346117845Ssam "packet engine ring", MTX_DEF); 347117845Ssam 348117845Ssam /* 349117845Ssam * Allocate scatter and gather particle descriptors. 350117845Ssam */ 351117845Ssam if (safe_dma_malloc(sc, SAFE_TOTAL_SPART * sizeof (struct safe_pdesc), 352117845Ssam &sc->sc_spalloc, 0)) { 353117845Ssam device_printf(dev, "cannot allocate source particle " 354117845Ssam "descriptor ring\n"); 355117845Ssam mtx_destroy(&sc->sc_ringmtx); 356117845Ssam safe_dma_free(sc, &sc->sc_ringalloc); 357117845Ssam bus_dma_tag_destroy(sc->sc_srcdmat); 358117845Ssam goto bad4; 359117845Ssam } 360117845Ssam sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr; 361117845Ssam sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART; 362117845Ssam sc->sc_spfree = sc->sc_spring; 363117845Ssam bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc)); 364117845Ssam 365117845Ssam if (safe_dma_malloc(sc, SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), 366117845Ssam &sc->sc_dpalloc, 0)) { 367117845Ssam device_printf(dev, "cannot allocate destination particle " 368117845Ssam "descriptor ring\n"); 369117845Ssam mtx_destroy(&sc->sc_ringmtx); 370117845Ssam safe_dma_free(sc, &sc->sc_spalloc); 371117845Ssam safe_dma_free(sc, &sc->sc_ringalloc); 372117845Ssam bus_dma_tag_destroy(sc->sc_dstdmat); 373117845Ssam goto bad4; 374117845Ssam } 375117845Ssam sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr; 376117845Ssam sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART; 377117845Ssam sc->sc_dpfree = sc->sc_dpring; 378117845Ssam bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc)); 379117845Ssam 380117845Ssam device_printf(sc->sc_dev, "%s", safe_partname(sc)); 381117845Ssam 382117845Ssam devinfo = READ_REG(sc, SAFE_DEVINFO); 383117845Ssam if (devinfo & SAFE_DEVINFO_RNG) { 384117845Ssam sc->sc_flags |= SAFE_FLAGS_RNG; 385117845Ssam printf(" rng"); 386117845Ssam } 387117845Ssam if (devinfo & SAFE_DEVINFO_PKEY) { 388117845Ssam#if 0 389117845Ssam printf(" key"); 390117845Ssam sc->sc_flags |= SAFE_FLAGS_KEY; 391117845Ssam crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 392117845Ssam safe_kprocess, sc); 393117845Ssam crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 394117845Ssam safe_kprocess, sc); 395117845Ssam#endif 396117845Ssam } 397117845Ssam if (devinfo & SAFE_DEVINFO_DES) { 398117845Ssam printf(" des/3des"); 399117845Ssam crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 400117845Ssam safe_newsession, safe_freesession, safe_process, sc); 401117845Ssam crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 402117845Ssam safe_newsession, safe_freesession, safe_process, sc); 403117845Ssam } 404117845Ssam if (devinfo & SAFE_DEVINFO_AES) { 405117845Ssam printf(" aes"); 406117845Ssam crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0, 407117845Ssam safe_newsession, safe_freesession, safe_process, sc); 408117845Ssam } 409117845Ssam if (devinfo & SAFE_DEVINFO_MD5) { 410117845Ssam printf(" md5"); 411117845Ssam crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 412117845Ssam safe_newsession, safe_freesession, safe_process, sc); 413117845Ssam } 414117845Ssam if (devinfo & SAFE_DEVINFO_SHA1) { 415117845Ssam printf(" sha1"); 416117845Ssam crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 417117845Ssam safe_newsession, safe_freesession, safe_process, sc); 418117845Ssam } 419117845Ssam printf(" null"); 420117845Ssam crypto_register(sc->sc_cid, CRYPTO_NULL_CBC, 0, 0, 421117845Ssam safe_newsession, safe_freesession, safe_process, sc); 422117845Ssam crypto_register(sc->sc_cid, CRYPTO_NULL_HMAC, 0, 0, 423117845Ssam safe_newsession, safe_freesession, safe_process, sc); 424117845Ssam /* XXX other supported algorithms */ 425117845Ssam printf("\n"); 426117845Ssam 427117845Ssam safe_reset_board(sc); /* reset h/w */ 428117845Ssam safe_init_pciregs(dev); /* init pci settings */ 429117845Ssam safe_init_board(sc); /* init h/w */ 430117845Ssam 431117845Ssam#ifndef SAFE_NO_RNG 432117845Ssam if (sc->sc_flags & SAFE_FLAGS_RNG) { 433117845Ssam#ifdef SAFE_RNDTEST 434117845Ssam sc->sc_rndtest = rndtest_attach(dev); 435117845Ssam if (sc->sc_rndtest) 436117845Ssam sc->sc_harvest = rndtest_harvest; 437117845Ssam else 438117845Ssam sc->sc_harvest = default_harvest; 439117845Ssam#else 440117845Ssam sc->sc_harvest = default_harvest; 441117845Ssam#endif 442117845Ssam safe_rng_init(sc); 443117845Ssam 444119137Ssam callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); 445117845Ssam callout_reset(&sc->sc_rngto, hz*safe_rnginterval, safe_rng, sc); 446117845Ssam } 447117845Ssam#endif /* SAFE_NO_RNG */ 448117845Ssam#ifdef SAFE_DEBUG 449117845Ssam safec = sc; /* for use by hw.safe.dump */ 450117845Ssam#endif 451117845Ssam return (0); 452117845Ssambad4: 453117845Ssam crypto_unregister_all(sc->sc_cid); 454117845Ssambad3: 455117845Ssam bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 456117845Ssambad2: 457117845Ssam bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 458117845Ssambad1: 459117845Ssam bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 460117845Ssambad: 461117845Ssam return (ENXIO); 462117845Ssam} 463117845Ssam 464117845Ssam/* 465117845Ssam * Detach a device that successfully probed. 466117845Ssam */ 467117845Ssamstatic int 468117845Ssamsafe_detach(device_t dev) 469117845Ssam{ 470117845Ssam struct safe_softc *sc = device_get_softc(dev); 471117845Ssam 472117845Ssam /* XXX wait/abort active ops */ 473117845Ssam 474117845Ssam WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */ 475117845Ssam 476117845Ssam callout_stop(&sc->sc_rngto); 477117845Ssam 478117845Ssam crypto_unregister_all(sc->sc_cid); 479117845Ssam 480117845Ssam#ifdef SAFE_RNDTEST 481117845Ssam if (sc->sc_rndtest) 482117845Ssam rndtest_detach(sc->sc_rndtest); 483117845Ssam#endif 484117845Ssam 485117845Ssam safe_cleanchip(sc); 486117845Ssam safe_dma_free(sc, &sc->sc_dpalloc); 487117845Ssam safe_dma_free(sc, &sc->sc_spalloc); 488117845Ssam mtx_destroy(&sc->sc_ringmtx); 489117845Ssam safe_dma_free(sc, &sc->sc_ringalloc); 490117845Ssam 491117845Ssam bus_generic_detach(dev); 492117845Ssam bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 493117845Ssam bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 494117845Ssam 495117845Ssam bus_dma_tag_destroy(sc->sc_srcdmat); 496117845Ssam bus_dma_tag_destroy(sc->sc_dstdmat); 497117845Ssam bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 498117845Ssam 499117845Ssam return (0); 500117845Ssam} 501117845Ssam 502117845Ssam/* 503117845Ssam * Stop all chip i/o so that the kernel's probe routines don't 504117845Ssam * get confused by errant DMAs when rebooting. 505117845Ssam */ 506117845Ssamstatic void 507117845Ssamsafe_shutdown(device_t dev) 508117845Ssam{ 509117845Ssam#ifdef notyet 510117845Ssam safe_stop(device_get_softc(dev)); 511117845Ssam#endif 512117845Ssam} 513117845Ssam 514117845Ssam/* 515117845Ssam * Device suspend routine. 516117845Ssam */ 517117845Ssamstatic int 518117845Ssamsafe_suspend(device_t dev) 519117845Ssam{ 520117845Ssam struct safe_softc *sc = device_get_softc(dev); 521117845Ssam 522117845Ssam#ifdef notyet 523117845Ssam /* XXX stop the device and save PCI settings */ 524117845Ssam#endif 525117845Ssam sc->sc_suspended = 1; 526117845Ssam 527117845Ssam return (0); 528117845Ssam} 529117845Ssam 530117845Ssamstatic int 531117845Ssamsafe_resume(device_t dev) 532117845Ssam{ 533117845Ssam struct safe_softc *sc = device_get_softc(dev); 534117845Ssam 535117845Ssam#ifdef notyet 536117845Ssam /* XXX retore PCI settings and start the device */ 537117845Ssam#endif 538117845Ssam sc->sc_suspended = 0; 539117845Ssam return (0); 540117845Ssam} 541117845Ssam 542117845Ssam/* 543117845Ssam * SafeXcel Interrupt routine 544117845Ssam */ 545117845Ssamstatic void 546117845Ssamsafe_intr(void *arg) 547117845Ssam{ 548117845Ssam struct safe_softc *sc = arg; 549117845Ssam volatile u_int32_t stat; 550117845Ssam 551117845Ssam stat = READ_REG(sc, SAFE_HM_STAT); 552117845Ssam if (stat == 0) /* shared irq, not for us */ 553117845Ssam return; 554117845Ssam 555117845Ssam WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */ 556117845Ssam 557117845Ssam if ((stat & SAFE_INT_PE_DDONE)) { 558117845Ssam /* 559117845Ssam * Descriptor(s) done; scan the ring and 560117845Ssam * process completed operations. 561117845Ssam */ 562117845Ssam mtx_lock(&sc->sc_ringmtx); 563117845Ssam while (sc->sc_back != sc->sc_front) { 564117845Ssam struct safe_ringentry *re = sc->sc_back; 565117845Ssam#ifdef SAFE_DEBUG 566117845Ssam if (safe_debug) { 567117845Ssam safe_dump_ringstate(sc, __func__); 568117845Ssam safe_dump_request(sc, __func__, re); 569117845Ssam } 570117845Ssam#endif 571117845Ssam /* 572117845Ssam * safe_process marks ring entries that were allocated 573117845Ssam * but not used with a csr of zero. This insures the 574117845Ssam * ring front pointer never needs to be set backwards 575117845Ssam * in the event that an entry is allocated but not used 576117845Ssam * because of a setup error. 577117845Ssam */ 578117845Ssam if (re->re_desc.d_csr != 0) { 579117845Ssam if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr)) 580117845Ssam break; 581117845Ssam if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len)) 582117845Ssam break; 583117845Ssam sc->sc_nqchip--; 584117845Ssam safe_callback(sc, re); 585117845Ssam } 586117845Ssam if (++(sc->sc_back) == sc->sc_ringtop) 587117845Ssam sc->sc_back = sc->sc_ring; 588117845Ssam } 589117845Ssam mtx_unlock(&sc->sc_ringmtx); 590117845Ssam } 591117845Ssam 592117845Ssam /* 593117845Ssam * Check to see if we got any DMA Error 594117845Ssam */ 595117845Ssam if (stat & SAFE_INT_PE_ERROR) { 596117845Ssam DPRINTF(("dmaerr dmastat %08x\n", 597117845Ssam READ_REG(sc, SAFE_PE_DMASTAT))); 598117845Ssam safestats.st_dmaerr++; 599117845Ssam safe_totalreset(sc); 600117845Ssam#if 0 601117845Ssam safe_feed(sc); 602117845Ssam#endif 603117845Ssam } 604117845Ssam 605117845Ssam if (sc->sc_needwakeup) { /* XXX check high watermark */ 606117845Ssam int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 607117845Ssam DPRINTF(("%s: wakeup crypto %x\n", __func__, 608117845Ssam sc->sc_needwakeup)); 609117845Ssam sc->sc_needwakeup &= ~wakeup; 610117845Ssam crypto_unblock(sc->sc_cid, wakeup); 611117845Ssam } 612117845Ssam} 613117845Ssam 614117845Ssam/* 615117845Ssam * safe_feed() - post a request to chip 616117845Ssam */ 617117845Ssamstatic void 618117845Ssamsafe_feed(struct safe_softc *sc, struct safe_ringentry *re) 619117845Ssam{ 620117845Ssam bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_PREWRITE); 621117845Ssam if (re->re_dst_map != NULL) 622117845Ssam bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map, 623117845Ssam BUS_DMASYNC_PREREAD); 624117845Ssam /* XXX have no smaller granularity */ 625117845Ssam safe_dma_sync(&sc->sc_ringalloc, 626117845Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 627117845Ssam safe_dma_sync(&sc->sc_spalloc, BUS_DMASYNC_PREWRITE); 628117845Ssam safe_dma_sync(&sc->sc_dpalloc, BUS_DMASYNC_PREWRITE); 629117845Ssam 630117845Ssam#ifdef SAFE_DEBUG 631117845Ssam if (safe_debug) { 632117845Ssam safe_dump_ringstate(sc, __func__); 633117845Ssam safe_dump_request(sc, __func__, re); 634117845Ssam } 635117845Ssam#endif 636117845Ssam sc->sc_nqchip++; 637117845Ssam if (sc->sc_nqchip > safestats.st_maxqchip) 638117845Ssam safestats.st_maxqchip = sc->sc_nqchip; 639117845Ssam /* poke h/w to check descriptor ring, any value can be written */ 640117845Ssam WRITE_REG(sc, SAFE_HI_RD_DESCR, 0); 641117845Ssam} 642117845Ssam 643117845Ssam/* 644117845Ssam * Allocate a new 'session' and return an encoded session id. 'sidp' 645117845Ssam * contains our registration id, and should contain an encoded session 646117845Ssam * id on successful allocation. 647117845Ssam */ 648117845Ssamstatic int 649117845Ssamsafe_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 650117845Ssam{ 651117845Ssam#define N(a) (sizeof(a) / sizeof (a[0])) 652117845Ssam struct cryptoini *c, *encini = NULL, *macini = NULL; 653117845Ssam struct safe_softc *sc = arg; 654117845Ssam struct safe_session *ses = NULL; 655117845Ssam MD5_CTX md5ctx; 656117845Ssam SHA1_CTX sha1ctx; 657117845Ssam int i, sesn; 658117845Ssam 659117845Ssam if (sidp == NULL || cri == NULL || sc == NULL) 660117845Ssam return (EINVAL); 661117845Ssam 662117845Ssam for (c = cri; c != NULL; c = c->cri_next) { 663117845Ssam if (c->cri_alg == CRYPTO_MD5_HMAC || 664117845Ssam c->cri_alg == CRYPTO_SHA1_HMAC || 665117845Ssam c->cri_alg == CRYPTO_NULL_HMAC) { 666117845Ssam if (macini) 667117845Ssam return (EINVAL); 668117845Ssam macini = c; 669117845Ssam } else if (c->cri_alg == CRYPTO_DES_CBC || 670117845Ssam c->cri_alg == CRYPTO_3DES_CBC || 671117845Ssam c->cri_alg == CRYPTO_AES_CBC || 672117845Ssam c->cri_alg == CRYPTO_NULL_CBC) { 673117845Ssam if (encini) 674117845Ssam return (EINVAL); 675117845Ssam encini = c; 676117845Ssam } else 677117845Ssam return (EINVAL); 678117845Ssam } 679117845Ssam if (encini == NULL && macini == NULL) 680117845Ssam return (EINVAL); 681117845Ssam if (encini) { /* validate key length */ 682117845Ssam switch (encini->cri_alg) { 683117845Ssam case CRYPTO_DES_CBC: 684117845Ssam if (encini->cri_klen != 64) 685117845Ssam return (EINVAL); 686117845Ssam break; 687117845Ssam case CRYPTO_3DES_CBC: 688117845Ssam if (encini->cri_klen != 192) 689117845Ssam return (EINVAL); 690117845Ssam break; 691117845Ssam case CRYPTO_AES_CBC: 692117845Ssam if (encini->cri_klen != 128 && 693117845Ssam encini->cri_klen != 192 && 694117845Ssam encini->cri_klen != 256) 695117845Ssam return (EINVAL); 696117845Ssam break; 697117845Ssam } 698117845Ssam } 699117845Ssam 700117845Ssam if (sc->sc_sessions == NULL) { 701117845Ssam ses = sc->sc_sessions = (struct safe_session *)malloc( 702117845Ssam sizeof(struct safe_session), M_DEVBUF, M_NOWAIT); 703117845Ssam if (ses == NULL) 704117845Ssam return (ENOMEM); 705117845Ssam sesn = 0; 706117845Ssam sc->sc_nsessions = 1; 707117845Ssam } else { 708117845Ssam for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 709117845Ssam if (sc->sc_sessions[sesn].ses_used == 0) { 710117845Ssam ses = &sc->sc_sessions[sesn]; 711117845Ssam break; 712117845Ssam } 713117845Ssam } 714117845Ssam 715117845Ssam if (ses == NULL) { 716117845Ssam sesn = sc->sc_nsessions; 717117845Ssam ses = (struct safe_session *)malloc((sesn + 1) * 718117845Ssam sizeof(struct safe_session), M_DEVBUF, M_NOWAIT); 719117845Ssam if (ses == NULL) 720117845Ssam return (ENOMEM); 721117845Ssam bcopy(sc->sc_sessions, ses, sesn * 722117845Ssam sizeof(struct safe_session)); 723117845Ssam bzero(sc->sc_sessions, sesn * 724117845Ssam sizeof(struct safe_session)); 725117845Ssam free(sc->sc_sessions, M_DEVBUF); 726117845Ssam sc->sc_sessions = ses; 727117845Ssam ses = &sc->sc_sessions[sesn]; 728117845Ssam sc->sc_nsessions++; 729117845Ssam } 730117845Ssam } 731117845Ssam 732117845Ssam bzero(ses, sizeof(struct safe_session)); 733117845Ssam ses->ses_used = 1; 734117845Ssam 735117845Ssam if (encini) { 736117845Ssam /* get an IV */ 737117845Ssam /* XXX may read fewer than requested */ 738117845Ssam read_random(ses->ses_iv, sizeof(ses->ses_iv)); 739117845Ssam 740117845Ssam ses->ses_klen = encini->cri_klen; 741117845Ssam bcopy(encini->cri_key, ses->ses_key, ses->ses_klen / 8); 742117845Ssam 743117845Ssam /* PE is little-endian, insure proper byte order */ 744117845Ssam for (i = 0; i < N(ses->ses_key); i++) 745117845Ssam ses->ses_key[i] = htole32(ses->ses_key[i]); 746117845Ssam } 747117845Ssam 748117845Ssam if (macini) { 749117845Ssam for (i = 0; i < macini->cri_klen / 8; i++) 750117845Ssam macini->cri_key[i] ^= HMAC_IPAD_VAL; 751117845Ssam 752117845Ssam if (macini->cri_alg == CRYPTO_MD5_HMAC) { 753117845Ssam MD5Init(&md5ctx); 754117845Ssam MD5Update(&md5ctx, macini->cri_key, 755117845Ssam macini->cri_klen / 8); 756117845Ssam MD5Update(&md5ctx, hmac_ipad_buffer, 757117845Ssam HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 758117845Ssam bcopy(md5ctx.state, ses->ses_hminner, 759117845Ssam sizeof(md5ctx.state)); 760117845Ssam } else { 761117845Ssam SHA1Init(&sha1ctx); 762117845Ssam SHA1Update(&sha1ctx, macini->cri_key, 763117845Ssam macini->cri_klen / 8); 764117845Ssam SHA1Update(&sha1ctx, hmac_ipad_buffer, 765117845Ssam HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 766117845Ssam bcopy(sha1ctx.h.b32, ses->ses_hminner, 767117845Ssam sizeof(sha1ctx.h.b32)); 768117845Ssam } 769117845Ssam 770117845Ssam for (i = 0; i < macini->cri_klen / 8; i++) 771117845Ssam macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 772117845Ssam 773117845Ssam if (macini->cri_alg == CRYPTO_MD5_HMAC) { 774117845Ssam MD5Init(&md5ctx); 775117845Ssam MD5Update(&md5ctx, macini->cri_key, 776117845Ssam macini->cri_klen / 8); 777117845Ssam MD5Update(&md5ctx, hmac_opad_buffer, 778117845Ssam HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 779117845Ssam bcopy(md5ctx.state, ses->ses_hmouter, 780117845Ssam sizeof(md5ctx.state)); 781117845Ssam } else { 782117845Ssam SHA1Init(&sha1ctx); 783117845Ssam SHA1Update(&sha1ctx, macini->cri_key, 784117845Ssam macini->cri_klen / 8); 785117845Ssam SHA1Update(&sha1ctx, hmac_opad_buffer, 786117845Ssam HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 787117845Ssam bcopy(sha1ctx.h.b32, ses->ses_hmouter, 788117845Ssam sizeof(sha1ctx.h.b32)); 789117845Ssam } 790117845Ssam 791117845Ssam for (i = 0; i < macini->cri_klen / 8; i++) 792117845Ssam macini->cri_key[i] ^= HMAC_OPAD_VAL; 793117845Ssam 794117845Ssam /* PE is little-endian, insure proper byte order */ 795117845Ssam for (i = 0; i < N(ses->ses_hminner); i++) { 796117845Ssam ses->ses_hminner[i] = htole32(ses->ses_hminner[i]); 797117845Ssam ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]); 798117845Ssam } 799117845Ssam } 800117845Ssam 801117845Ssam *sidp = SAFE_SID(device_get_unit(sc->sc_dev), sesn); 802117845Ssam return (0); 803117845Ssam#undef N 804117845Ssam} 805117845Ssam 806117845Ssam/* 807117845Ssam * Deallocate a session. 808117845Ssam */ 809117845Ssamstatic int 810117845Ssamsafe_freesession(void *arg, u_int64_t tid) 811117845Ssam{ 812117845Ssam struct safe_softc *sc = arg; 813117845Ssam int session, ret; 814117845Ssam u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 815117845Ssam 816117845Ssam if (sc == NULL) 817117845Ssam return (EINVAL); 818117845Ssam 819117845Ssam session = SAFE_SESSION(sid); 820117845Ssam if (session < sc->sc_nsessions) { 821117845Ssam bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 822117845Ssam ret = 0; 823117845Ssam } else 824117845Ssam ret = EINVAL; 825117845Ssam return (ret); 826117845Ssam} 827117845Ssam 828117845Ssamstatic void 829117845Ssamsafe_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 830117845Ssam{ 831117845Ssam struct safe_operand *op = arg; 832117845Ssam 833117845Ssam DPRINTF(("%s: mapsize %u nsegs %d error %d\n", __func__, 834117845Ssam (u_int) mapsize, nsegs, error)); 835117845Ssam if (error != 0) 836117845Ssam return; 837117845Ssam op->mapsize = mapsize; 838117845Ssam op->nsegs = nsegs; 839117845Ssam bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 840117845Ssam} 841117845Ssam 842117845Ssamstatic int 843117845Ssamsafe_process(void *arg, struct cryptop *crp, int hint) 844117845Ssam{ 845117845Ssam int err = 0, i, nicealign, uniform; 846117845Ssam struct safe_softc *sc = arg; 847117845Ssam struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 848117845Ssam int bypass, oplen, ivsize; 849117845Ssam caddr_t iv; 850117845Ssam int16_t coffset; 851117845Ssam struct safe_session *ses; 852117845Ssam struct safe_ringentry *re; 853117845Ssam struct safe_sarec *sa; 854117845Ssam struct safe_pdesc *pd; 855117845Ssam u_int32_t cmd0, cmd1, staterec; 856117845Ssam 857117845Ssam if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 858117845Ssam safestats.st_invalid++; 859117845Ssam return (EINVAL); 860117845Ssam } 861117845Ssam if (SAFE_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 862117845Ssam safestats.st_badsession++; 863117845Ssam return (EINVAL); 864117845Ssam } 865117845Ssam 866117845Ssam mtx_lock(&sc->sc_ringmtx); 867117845Ssam if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) { 868117845Ssam safestats.st_ringfull++; 869117845Ssam sc->sc_needwakeup |= CRYPTO_SYMQ; 870117845Ssam mtx_unlock(&sc->sc_ringmtx); 871117845Ssam return (ERESTART); 872117845Ssam } 873117845Ssam re = sc->sc_front; 874117845Ssam 875117845Ssam staterec = re->re_sa.sa_staterec; /* save */ 876117845Ssam /* NB: zero everything but the PE descriptor */ 877117845Ssam bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc)); 878117845Ssam re->re_sa.sa_staterec = staterec; /* restore */ 879117845Ssam 880117845Ssam re->re_crp = crp; 881117845Ssam re->re_sesn = SAFE_SESSION(crp->crp_sid); 882117845Ssam 883117845Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 884117845Ssam re->re_src_m = (struct mbuf *)crp->crp_buf; 885117845Ssam re->re_dst_m = (struct mbuf *)crp->crp_buf; 886117845Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 887117845Ssam re->re_src_io = (struct uio *)crp->crp_buf; 888117845Ssam re->re_dst_io = (struct uio *)crp->crp_buf; 889117845Ssam } else { 890117845Ssam safestats.st_badflags++; 891117845Ssam err = EINVAL; 892117845Ssam goto errout; /* XXX we don't handle contiguous blocks! */ 893117845Ssam } 894117845Ssam 895117845Ssam sa = &re->re_sa; 896117845Ssam ses = &sc->sc_sessions[re->re_sesn]; 897117845Ssam 898117845Ssam crd1 = crp->crp_desc; 899117845Ssam if (crd1 == NULL) { 900117845Ssam safestats.st_nodesc++; 901117845Ssam err = EINVAL; 902117845Ssam goto errout; 903117845Ssam } 904117845Ssam crd2 = crd1->crd_next; 905117845Ssam 906117845Ssam cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */ 907117845Ssam cmd1 = 0; 908117845Ssam if (crd2 == NULL) { 909117845Ssam if (crd1->crd_alg == CRYPTO_MD5_HMAC || 910117845Ssam crd1->crd_alg == CRYPTO_SHA1_HMAC || 911117845Ssam crd1->crd_alg == CRYPTO_NULL_HMAC) { 912117845Ssam maccrd = crd1; 913117845Ssam enccrd = NULL; 914117845Ssam cmd0 |= SAFE_SA_CMD0_OP_HASH; 915117845Ssam } else if (crd1->crd_alg == CRYPTO_DES_CBC || 916117845Ssam crd1->crd_alg == CRYPTO_3DES_CBC || 917117845Ssam crd1->crd_alg == CRYPTO_AES_CBC || 918117845Ssam crd1->crd_alg == CRYPTO_NULL_CBC) { 919117845Ssam maccrd = NULL; 920117845Ssam enccrd = crd1; 921117845Ssam cmd0 |= SAFE_SA_CMD0_OP_CRYPT; 922117845Ssam } else { 923117845Ssam safestats.st_badalg++; 924117845Ssam err = EINVAL; 925117845Ssam goto errout; 926117845Ssam } 927117845Ssam } else { 928117845Ssam if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 929117845Ssam crd1->crd_alg == CRYPTO_SHA1_HMAC || 930117845Ssam crd1->crd_alg == CRYPTO_NULL_HMAC) && 931117845Ssam (crd2->crd_alg == CRYPTO_DES_CBC || 932117845Ssam crd2->crd_alg == CRYPTO_3DES_CBC || 933117845Ssam crd2->crd_alg == CRYPTO_AES_CBC || 934117845Ssam crd2->crd_alg == CRYPTO_NULL_CBC) && 935117845Ssam ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 936117845Ssam maccrd = crd1; 937117845Ssam enccrd = crd2; 938117845Ssam } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 939117845Ssam crd1->crd_alg == CRYPTO_3DES_CBC || 940117845Ssam crd1->crd_alg == CRYPTO_AES_CBC || 941117845Ssam crd1->crd_alg == CRYPTO_NULL_CBC) && 942117845Ssam (crd2->crd_alg == CRYPTO_MD5_HMAC || 943117845Ssam crd2->crd_alg == CRYPTO_SHA1_HMAC || 944117845Ssam crd2->crd_alg == CRYPTO_NULL_HMAC) && 945117845Ssam (crd1->crd_flags & CRD_F_ENCRYPT)) { 946117845Ssam enccrd = crd1; 947117845Ssam maccrd = crd2; 948117845Ssam } else { 949117845Ssam safestats.st_badalg++; 950117845Ssam err = EINVAL; 951117845Ssam goto errout; 952117845Ssam } 953117845Ssam cmd0 |= SAFE_SA_CMD0_OP_BOTH; 954117845Ssam } 955117845Ssam 956117845Ssam if (enccrd) { 957117845Ssam if (enccrd->crd_alg == CRYPTO_DES_CBC) { 958117845Ssam cmd0 |= SAFE_SA_CMD0_DES; 959117845Ssam cmd1 |= SAFE_SA_CMD1_CBC; 960117845Ssam ivsize = 2*sizeof(u_int32_t); 961117845Ssam } else if (enccrd->crd_alg == CRYPTO_3DES_CBC) { 962117845Ssam cmd0 |= SAFE_SA_CMD0_3DES; 963117845Ssam cmd1 |= SAFE_SA_CMD1_CBC; 964117845Ssam ivsize = 2*sizeof(u_int32_t); 965117845Ssam } else if (enccrd->crd_alg == CRYPTO_AES_CBC) { 966117845Ssam cmd0 |= SAFE_SA_CMD0_AES; 967117845Ssam cmd1 |= SAFE_SA_CMD1_CBC; 968117845Ssam if (ses->ses_klen == 128) 969117845Ssam cmd1 |= SAFE_SA_CMD1_AES128; 970117845Ssam else if (ses->ses_klen == 192) 971117845Ssam cmd1 |= SAFE_SA_CMD1_AES192; 972117845Ssam else 973117845Ssam cmd1 |= SAFE_SA_CMD1_AES256; 974117845Ssam ivsize = 4*sizeof(u_int32_t); 975117845Ssam } else { 976117845Ssam cmd0 |= SAFE_SA_CMD0_CRYPT_NULL; 977117845Ssam ivsize = 0; 978117845Ssam } 979117845Ssam 980117845Ssam /* 981117845Ssam * Setup encrypt/decrypt state. When using basic ops 982117845Ssam * we can't use an inline IV because hash/crypt offset 983117845Ssam * must be from the end of the IV to the start of the 984117845Ssam * crypt data and this leaves out the preceding header 985117845Ssam * from the hash calculation. Instead we place the IV 986117845Ssam * in the state record and set the hash/crypt offset to 987117845Ssam * copy both the header+IV. 988117845Ssam */ 989117845Ssam if (enccrd->crd_flags & CRD_F_ENCRYPT) { 990117845Ssam cmd0 |= SAFE_SA_CMD0_OUTBOUND; 991117845Ssam 992117845Ssam if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 993117845Ssam iv = enccrd->crd_iv; 994117845Ssam else 995117845Ssam iv = (caddr_t) ses->ses_iv; 996117845Ssam if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 997117845Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) 998117845Ssam m_copyback(re->re_src_m, 999117845Ssam enccrd->crd_inject, ivsize, iv); 1000117845Ssam else if (crp->crp_flags & CRYPTO_F_IOV) 1001117845Ssam cuio_copyback(re->re_src_io, 1002117845Ssam enccrd->crd_inject, ivsize, iv); 1003117845Ssam } 1004117845Ssam bcopy(iv, re->re_sastate.sa_saved_iv, ivsize); 1005117845Ssam cmd0 |= SAFE_SA_CMD0_IVLD_STATE | SAFE_SA_CMD0_SAVEIV; 1006117845Ssam re->re_flags |= SAFE_QFLAGS_COPYOUTIV; 1007117845Ssam } else { 1008117845Ssam cmd0 |= SAFE_SA_CMD0_INBOUND; 1009117845Ssam 1010117845Ssam if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1011117845Ssam bcopy(enccrd->crd_iv, 1012117845Ssam re->re_sastate.sa_saved_iv, ivsize); 1013117845Ssam else if (crp->crp_flags & CRYPTO_F_IMBUF) 1014117845Ssam m_copydata(re->re_src_m, enccrd->crd_inject, 1015117845Ssam ivsize, 1016117845Ssam (caddr_t)re->re_sastate.sa_saved_iv); 1017117845Ssam else if (crp->crp_flags & CRYPTO_F_IOV) 1018117845Ssam cuio_copydata(re->re_src_io, enccrd->crd_inject, 1019117845Ssam ivsize, 1020117845Ssam (caddr_t)re->re_sastate.sa_saved_iv); 1021117845Ssam cmd0 |= SAFE_SA_CMD0_IVLD_STATE; 1022117845Ssam } 1023117845Ssam /* 1024117845Ssam * For basic encryption use the zero pad algorithm. 1025117845Ssam * This pads results to an 8-byte boundary and 1026117845Ssam * suppresses padding verification for inbound (i.e. 1027117845Ssam * decrypt) operations. 1028117845Ssam * 1029117845Ssam * NB: Not sure if the 8-byte pad boundary is a problem. 1030117845Ssam */ 1031117845Ssam cmd0 |= SAFE_SA_CMD0_PAD_ZERO; 1032117845Ssam 1033117845Ssam /* XXX assert key bufs have the same size */ 1034117845Ssam bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key)); 1035117845Ssam } 1036117845Ssam 1037117845Ssam if (maccrd) { 1038117845Ssam if (maccrd->crd_alg == CRYPTO_MD5_HMAC) { 1039117845Ssam cmd0 |= SAFE_SA_CMD0_MD5; 1040117845Ssam cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ 1041117845Ssam } else if (maccrd->crd_alg == CRYPTO_SHA1_HMAC) { 1042117845Ssam cmd0 |= SAFE_SA_CMD0_SHA1; 1043117845Ssam cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ 1044117845Ssam } else { 1045117845Ssam cmd0 |= SAFE_SA_CMD0_HASH_NULL; 1046117845Ssam } 1047117845Ssam /* 1048117845Ssam * Digest data is loaded from the SA and the hash 1049117845Ssam * result is saved to the state block where we 1050117845Ssam * retrieve it for return to the caller. 1051117845Ssam */ 1052117845Ssam /* XXX assert digest bufs have the same size */ 1053117845Ssam bcopy(ses->ses_hminner, sa->sa_indigest, 1054117845Ssam sizeof(sa->sa_indigest)); 1055117845Ssam bcopy(ses->ses_hmouter, sa->sa_outdigest, 1056117845Ssam sizeof(sa->sa_outdigest)); 1057117845Ssam 1058117845Ssam cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH; 1059117845Ssam re->re_flags |= SAFE_QFLAGS_COPYOUTICV; 1060117845Ssam } 1061117845Ssam 1062117845Ssam if (enccrd && maccrd) { 1063117845Ssam /* 1064117845Ssam * The offset from hash data to the start of 1065117845Ssam * crypt data is the difference in the skips. 1066117845Ssam */ 1067117845Ssam bypass = maccrd->crd_skip; 1068117845Ssam coffset = enccrd->crd_skip - maccrd->crd_skip; 1069117845Ssam if (coffset < 0) { 1070117845Ssam DPRINTF(("%s: hash does not precede crypt; " 1071117845Ssam "mac skip %u enc skip %u\n", 1072117845Ssam __func__, maccrd->crd_skip, enccrd->crd_skip)); 1073117845Ssam safestats.st_skipmismatch++; 1074117845Ssam err = EINVAL; 1075117845Ssam goto errout; 1076117845Ssam } 1077117845Ssam oplen = enccrd->crd_skip + enccrd->crd_len; 1078117845Ssam if (maccrd->crd_skip + maccrd->crd_len != oplen) { 1079117845Ssam DPRINTF(("%s: hash amount %u != crypt amount %u\n", 1080117845Ssam __func__, maccrd->crd_skip + maccrd->crd_len, 1081117845Ssam oplen)); 1082117845Ssam safestats.st_lenmismatch++; 1083117845Ssam err = EINVAL; 1084117845Ssam goto errout; 1085117845Ssam } 1086117845Ssam#ifdef SAFE_DEBUG 1087117845Ssam if (safe_debug) { 1088117845Ssam printf("mac: skip %d, len %d, inject %d\n", 1089117845Ssam maccrd->crd_skip, maccrd->crd_len, 1090117845Ssam maccrd->crd_inject); 1091117845Ssam printf("enc: skip %d, len %d, inject %d\n", 1092117845Ssam enccrd->crd_skip, enccrd->crd_len, 1093117845Ssam enccrd->crd_inject); 1094117845Ssam printf("bypass %d coffset %d oplen %d\n", 1095117845Ssam bypass, coffset, oplen); 1096117845Ssam } 1097117845Ssam#endif 1098117845Ssam if (coffset & 3) { /* offset must be 32-bit aligned */ 1099117845Ssam DPRINTF(("%s: coffset %u misaligned\n", 1100117845Ssam __func__, coffset)); 1101117845Ssam safestats.st_coffmisaligned++; 1102117845Ssam err = EINVAL; 1103117845Ssam goto errout; 1104117845Ssam } 1105117845Ssam coffset >>= 2; 1106117845Ssam if (coffset > 255) { /* offset must be <256 dwords */ 1107117845Ssam DPRINTF(("%s: coffset %u too big\n", 1108117845Ssam __func__, coffset)); 1109117845Ssam safestats.st_cofftoobig++; 1110117845Ssam err = EINVAL; 1111117845Ssam goto errout; 1112117845Ssam } 1113117845Ssam /* 1114117845Ssam * Tell the hardware to copy the header to the output. 1115117845Ssam * The header is defined as the data from the end of 1116117845Ssam * the bypass to the start of data to be encrypted. 1117117845Ssam * Typically this is the inline IV. Note that you need 1118117845Ssam * to do this even if src+dst are the same; it appears 1119117845Ssam * that w/o this bit the crypted data is written 1120117845Ssam * immediately after the bypass data. 1121117845Ssam */ 1122117845Ssam cmd1 |= SAFE_SA_CMD1_HDRCOPY; 1123117845Ssam /* 1124117845Ssam * Disable IP header mutable bit handling. This is 1125117845Ssam * needed to get correct HMAC calculations. 1126117845Ssam */ 1127117845Ssam cmd1 |= SAFE_SA_CMD1_MUTABLE; 1128117845Ssam } else { 1129117845Ssam if (enccrd) { 1130117845Ssam bypass = enccrd->crd_skip; 1131117845Ssam oplen = bypass + enccrd->crd_len; 1132117845Ssam } else { 1133117845Ssam bypass = maccrd->crd_skip; 1134117845Ssam oplen = bypass + maccrd->crd_len; 1135117845Ssam } 1136117845Ssam coffset = 0; 1137117845Ssam } 1138117845Ssam /* XXX verify multiple of 4 when using s/g */ 1139117845Ssam if (bypass > 96) { /* bypass offset must be <= 96 bytes */ 1140117845Ssam DPRINTF(("%s: bypass %u too big\n", __func__, bypass)); 1141117845Ssam safestats.st_bypasstoobig++; 1142117845Ssam err = EINVAL; 1143117845Ssam goto errout; 1144117845Ssam } 1145117845Ssam 1146117845Ssam if (bus_dmamap_create(sc->sc_srcdmat, BUS_DMA_NOWAIT, &re->re_src_map)) { 1147117845Ssam safestats.st_nomap++; 1148117845Ssam err = ENOMEM; 1149117845Ssam goto errout; 1150117845Ssam } 1151117845Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1152117845Ssam if (bus_dmamap_load_mbuf(sc->sc_srcdmat, re->re_src_map, 1153117845Ssam re->re_src_m, safe_op_cb, 1154117845Ssam &re->re_src, BUS_DMA_NOWAIT) != 0) { 1155117845Ssam bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1156117845Ssam re->re_src_map = NULL; 1157117845Ssam safestats.st_noload++; 1158117845Ssam err = ENOMEM; 1159117845Ssam goto errout; 1160117845Ssam } 1161117845Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 1162117845Ssam if (bus_dmamap_load_uio(sc->sc_srcdmat, re->re_src_map, 1163117845Ssam re->re_src_io, safe_op_cb, 1164117845Ssam &re->re_src, BUS_DMA_NOWAIT) != 0) { 1165117845Ssam bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1166117845Ssam re->re_src_map = NULL; 1167117845Ssam safestats.st_noload++; 1168117845Ssam err = ENOMEM; 1169117845Ssam goto errout; 1170117845Ssam } 1171117845Ssam } 1172117845Ssam nicealign = safe_dmamap_aligned(&re->re_src); 1173117845Ssam uniform = safe_dmamap_uniform(&re->re_src); 1174117845Ssam 1175117845Ssam DPRINTF(("src nicealign %u uniform %u nsegs %u\n", 1176117845Ssam nicealign, uniform, re->re_src.nsegs)); 1177117845Ssam if (re->re_src.nsegs > 1) { 1178117845Ssam re->re_desc.d_src = sc->sc_spalloc.dma_paddr + 1179117845Ssam ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring); 1180117845Ssam for (i = 0; i < re->re_src_nsegs; i++) { 1181117845Ssam /* NB: no need to check if there's space */ 1182117845Ssam pd = sc->sc_spfree; 1183117845Ssam if (++(sc->sc_spfree) == sc->sc_springtop) 1184117845Ssam sc->sc_spfree = sc->sc_spring; 1185117845Ssam 1186117845Ssam KASSERT((pd->pd_flags&3) == 0 || 1187117845Ssam (pd->pd_flags&3) == SAFE_PD_DONE, 1188117845Ssam ("bogus source particle descriptor; flags %x", 1189117845Ssam pd->pd_flags)); 1190117845Ssam pd->pd_addr = re->re_src_segs[i].ds_addr; 1191117845Ssam pd->pd_size = re->re_src_segs[i].ds_len; 1192117845Ssam pd->pd_flags = SAFE_PD_READY; 1193117845Ssam } 1194117845Ssam cmd0 |= SAFE_SA_CMD0_IGATHER; 1195117845Ssam } else { 1196117845Ssam /* 1197117845Ssam * No need for gather, reference the operand directly. 1198117845Ssam */ 1199117845Ssam re->re_desc.d_src = re->re_src_segs[0].ds_addr; 1200117845Ssam } 1201117845Ssam 1202117845Ssam if (enccrd == NULL && maccrd != NULL) { 1203117845Ssam /* 1204117845Ssam * Hash op; no destination needed. 1205117845Ssam */ 1206117845Ssam } else { 1207117845Ssam if (crp->crp_flags & CRYPTO_F_IOV) { 1208117845Ssam if (!nicealign) { 1209117845Ssam safestats.st_iovmisaligned++; 1210117845Ssam err = EINVAL; 1211117845Ssam goto errout; 1212117845Ssam } 1213117845Ssam if (uniform != 1) { 1214117845Ssam /* 1215117845Ssam * Source is not suitable for direct use as 1216117845Ssam * the destination. Create a new scatter/gather 1217117845Ssam * list based on the destination requirements 1218117845Ssam * and check if that's ok. 1219117845Ssam */ 1220117845Ssam if (bus_dmamap_create(sc->sc_dstdmat, 1221117845Ssam BUS_DMA_NOWAIT, &re->re_dst_map)) { 1222117845Ssam safestats.st_nomap++; 1223117845Ssam err = ENOMEM; 1224117845Ssam goto errout; 1225117845Ssam } 1226117845Ssam if (bus_dmamap_load_uio(sc->sc_dstdmat, 1227117845Ssam re->re_dst_map, re->re_dst_io, 1228117845Ssam safe_op_cb, &re->re_dst, 1229117845Ssam BUS_DMA_NOWAIT) != 0) { 1230117845Ssam bus_dmamap_destroy(sc->sc_dstdmat, 1231117845Ssam re->re_dst_map); 1232117845Ssam re->re_dst_map = NULL; 1233117845Ssam safestats.st_noload++; 1234117845Ssam err = ENOMEM; 1235117845Ssam goto errout; 1236117845Ssam } 1237117845Ssam uniform = safe_dmamap_uniform(&re->re_dst); 1238117845Ssam if (!uniform) { 1239117845Ssam /* 1240117845Ssam * There's no way to handle the DMA 1241117845Ssam * requirements with this uio. We 1242117845Ssam * could create a separate DMA area for 1243117845Ssam * the result and then copy it back, 1244117845Ssam * but for now we just bail and return 1245117845Ssam * an error. Note that uio requests 1246117845Ssam * > SAFE_MAX_DSIZE are handled because 1247117845Ssam * the DMA map and segment list for the 1248117845Ssam * destination wil result in a 1249117845Ssam * destination particle list that does 1250117845Ssam * the necessary scatter DMA. 1251117845Ssam */ 1252117845Ssam safestats.st_iovnotuniform++; 1253117845Ssam err = EINVAL; 1254117845Ssam goto errout; 1255117845Ssam } 1256118882Ssam } else 1257118882Ssam re->re_dst = re->re_src; 1258117845Ssam } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1259117845Ssam if (nicealign && uniform == 1) { 1260117845Ssam /* 1261117845Ssam * Source layout is suitable for direct 1262117845Ssam * sharing of the DMA map and segment list. 1263117845Ssam */ 1264117845Ssam re->re_dst = re->re_src; 1265117845Ssam } else if (nicealign && uniform == 2) { 1266117845Ssam /* 1267117845Ssam * The source is properly aligned but requires a 1268117845Ssam * different particle list to handle DMA of the 1269117845Ssam * result. Create a new map and do the load to 1270117845Ssam * create the segment list. The particle 1271117845Ssam * descriptor setup code below will handle the 1272117845Ssam * rest. 1273117845Ssam */ 1274117845Ssam if (bus_dmamap_create(sc->sc_dstdmat, 1275117845Ssam BUS_DMA_NOWAIT, &re->re_dst_map)) { 1276117845Ssam safestats.st_nomap++; 1277117845Ssam err = ENOMEM; 1278117845Ssam goto errout; 1279117845Ssam } 1280117845Ssam if (bus_dmamap_load_mbuf(sc->sc_dstdmat, 1281117845Ssam re->re_dst_map, re->re_dst_m, 1282117845Ssam safe_op_cb, &re->re_dst, 1283117845Ssam BUS_DMA_NOWAIT) != 0) { 1284117845Ssam bus_dmamap_destroy(sc->sc_dstdmat, 1285117845Ssam re->re_dst_map); 1286117845Ssam re->re_dst_map = NULL; 1287117845Ssam safestats.st_noload++; 1288117845Ssam err = ENOMEM; 1289117845Ssam goto errout; 1290117845Ssam } 1291117845Ssam } else { /* !(aligned and/or uniform) */ 1292117845Ssam int totlen, len; 1293117845Ssam struct mbuf *m, *top, **mp; 1294117845Ssam 1295117845Ssam /* 1296117845Ssam * DMA constraints require that we allocate a 1297117845Ssam * new mbuf chain for the destination. We 1298117845Ssam * allocate an entire new set of mbufs of 1299117845Ssam * optimal/required size and then tell the 1300117845Ssam * hardware to copy any bits that are not 1301117845Ssam * created as a byproduct of the operation. 1302117845Ssam */ 1303117845Ssam if (!nicealign) 1304117845Ssam safestats.st_unaligned++; 1305117845Ssam if (!uniform) 1306117845Ssam safestats.st_notuniform++; 1307117845Ssam totlen = re->re_src_mapsize; 1308117845Ssam if (re->re_src_m->m_flags & M_PKTHDR) { 1309117845Ssam len = MHLEN; 1310117845Ssam MGETHDR(m, M_DONTWAIT, MT_DATA); 1311117845Ssam if (m && !m_dup_pkthdr(m, re->re_src_m, 1312117845Ssam M_DONTWAIT)) { 1313117845Ssam m_free(m); 1314117845Ssam m = NULL; 1315117845Ssam } 1316117845Ssam } else { 1317117845Ssam len = MLEN; 1318117845Ssam MGET(m, M_DONTWAIT, MT_DATA); 1319117845Ssam } 1320117845Ssam if (m == NULL) { 1321117845Ssam safestats.st_nombuf++; 1322117845Ssam err = sc->sc_nqchip ? ERESTART : ENOMEM; 1323117845Ssam goto errout; 1324117845Ssam } 1325117845Ssam if (totlen >= MINCLSIZE) { 1326117845Ssam MCLGET(m, M_DONTWAIT); 1327117845Ssam if ((m->m_flags & M_EXT) == 0) { 1328117845Ssam m_free(m); 1329117845Ssam safestats.st_nomcl++; 1330117845Ssam err = sc->sc_nqchip ? 1331117845Ssam ERESTART : ENOMEM; 1332117845Ssam goto errout; 1333117845Ssam } 1334117845Ssam len = MCLBYTES; 1335117845Ssam } 1336117845Ssam m->m_len = len; 1337117845Ssam top = NULL; 1338117845Ssam mp = ⊤ 1339117845Ssam 1340117845Ssam while (totlen > 0) { 1341117845Ssam if (top) { 1342117845Ssam MGET(m, M_DONTWAIT, MT_DATA); 1343117845Ssam if (m == NULL) { 1344117845Ssam m_freem(top); 1345117845Ssam safestats.st_nombuf++; 1346117845Ssam err = sc->sc_nqchip ? 1347117845Ssam ERESTART : ENOMEM; 1348117845Ssam goto errout; 1349117845Ssam } 1350117845Ssam len = MLEN; 1351117845Ssam } 1352117845Ssam if (top && totlen >= MINCLSIZE) { 1353117845Ssam MCLGET(m, M_DONTWAIT); 1354117845Ssam if ((m->m_flags & M_EXT) == 0) { 1355117845Ssam *mp = m; 1356117845Ssam m_freem(top); 1357117845Ssam safestats.st_nomcl++; 1358117845Ssam err = sc->sc_nqchip ? 1359117845Ssam ERESTART : ENOMEM; 1360117845Ssam goto errout; 1361117845Ssam } 1362117845Ssam len = MCLBYTES; 1363117845Ssam } 1364117845Ssam m->m_len = len = min(totlen, len); 1365117845Ssam totlen -= len; 1366117845Ssam *mp = m; 1367117845Ssam mp = &m->m_next; 1368117845Ssam } 1369117845Ssam re->re_dst_m = top; 1370117845Ssam if (bus_dmamap_create(sc->sc_dstdmat, 1371117845Ssam BUS_DMA_NOWAIT, &re->re_dst_map) != 0) { 1372117845Ssam safestats.st_nomap++; 1373117845Ssam err = ENOMEM; 1374117845Ssam goto errout; 1375117845Ssam } 1376117845Ssam if (bus_dmamap_load_mbuf(sc->sc_dstdmat, 1377117845Ssam re->re_dst_map, re->re_dst_m, 1378117845Ssam safe_op_cb, &re->re_dst, 1379117845Ssam BUS_DMA_NOWAIT) != 0) { 1380117845Ssam bus_dmamap_destroy(sc->sc_dstdmat, 1381117845Ssam re->re_dst_map); 1382117845Ssam re->re_dst_map = NULL; 1383117845Ssam safestats.st_noload++; 1384117845Ssam err = ENOMEM; 1385117845Ssam goto errout; 1386117845Ssam } 1387117845Ssam if (re->re_src.mapsize > oplen) { 1388117845Ssam /* 1389117845Ssam * There's data following what the 1390117845Ssam * hardware will copy for us. If this 1391117845Ssam * isn't just the ICV (that's going to 1392117845Ssam * be written on completion), copy it 1393117845Ssam * to the new mbufs 1394117845Ssam */ 1395117845Ssam if (!(maccrd && 1396117845Ssam (re->re_src.mapsize-oplen) == 12 && 1397117845Ssam maccrd->crd_inject == oplen)) 1398117845Ssam safe_mcopy(re->re_src_m, 1399117845Ssam re->re_dst_m, 1400117845Ssam oplen); 1401117845Ssam else 1402117845Ssam safestats.st_noicvcopy++; 1403117845Ssam } 1404117845Ssam } 1405117845Ssam } else { 1406117845Ssam safestats.st_badflags++; 1407117845Ssam err = EINVAL; 1408117845Ssam goto errout; 1409117845Ssam } 1410117845Ssam 1411117845Ssam if (re->re_dst.nsegs > 1) { 1412117845Ssam re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr + 1413117845Ssam ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring); 1414117845Ssam for (i = 0; i < re->re_dst_nsegs; i++) { 1415117845Ssam pd = sc->sc_dpfree; 1416117845Ssam KASSERT((pd->pd_flags&3) == 0 || 1417117845Ssam (pd->pd_flags&3) == SAFE_PD_DONE, 1418117845Ssam ("bogus dest particle descriptor; flags %x", 1419117845Ssam pd->pd_flags)); 1420117845Ssam if (++(sc->sc_dpfree) == sc->sc_dpringtop) 1421117845Ssam sc->sc_dpfree = sc->sc_dpring; 1422117845Ssam pd->pd_addr = re->re_dst_segs[i].ds_addr; 1423117845Ssam pd->pd_flags = SAFE_PD_READY; 1424117845Ssam } 1425117845Ssam cmd0 |= SAFE_SA_CMD0_OSCATTER; 1426117845Ssam } else { 1427117845Ssam /* 1428117845Ssam * No need for scatter, reference the operand directly. 1429117845Ssam */ 1430117845Ssam re->re_desc.d_dst = re->re_dst_segs[0].ds_addr; 1431117845Ssam } 1432117845Ssam } 1433117845Ssam 1434117845Ssam /* 1435117845Ssam * All done with setup; fillin the SA command words 1436117845Ssam * and the packet engine descriptor. The operation 1437117845Ssam * is now ready for submission to the hardware. 1438117845Ssam */ 1439117845Ssam sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI; 1440117845Ssam sa->sa_cmd1 = cmd1 1441117845Ssam | (coffset << SAFE_SA_CMD1_OFFSET_S) 1442117845Ssam | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */ 1443117845Ssam | SAFE_SA_CMD1_SRPCI 1444117845Ssam ; 1445117845Ssam /* 1446117845Ssam * NB: the order of writes is important here. In case the 1447117845Ssam * chip is scanning the ring because of an outstanding request 1448117845Ssam * it might nab this one too. In that case we need to make 1449117845Ssam * sure the setup is complete before we write the length 1450117845Ssam * field of the descriptor as it signals the descriptor is 1451117845Ssam * ready for processing. 1452117845Ssam */ 1453117845Ssam re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI; 1454117845Ssam if (maccrd) 1455117845Ssam re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL; 1456117845Ssam re->re_desc.d_len = oplen 1457117845Ssam | SAFE_PE_LEN_READY 1458117845Ssam | (bypass << SAFE_PE_LEN_BYPASS_S) 1459117845Ssam ; 1460117845Ssam 1461117845Ssam safestats.st_ipackets++; 1462117845Ssam safestats.st_ibytes += oplen; 1463117845Ssam 1464117845Ssam if (++(sc->sc_front) == sc->sc_ringtop) 1465117845Ssam sc->sc_front = sc->sc_ring; 1466117845Ssam 1467117845Ssam /* XXX honor batching */ 1468117845Ssam safe_feed(sc, re); 1469117845Ssam mtx_unlock(&sc->sc_ringmtx); 1470117845Ssam return (0); 1471117845Ssam 1472117845Ssamerrout: 1473117845Ssam if ((re->re_dst_m != NULL) && (re->re_src_m != re->re_dst_m)) 1474117845Ssam m_freem(re->re_dst_m); 1475117845Ssam 1476117845Ssam if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) { 1477117845Ssam bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map); 1478117845Ssam bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map); 1479117845Ssam } 1480117845Ssam if (re->re_src_map != NULL) { 1481117845Ssam bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map); 1482117845Ssam bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1483117845Ssam } 1484117845Ssam mtx_unlock(&sc->sc_ringmtx); 1485117845Ssam if (err != ERESTART) { 1486117845Ssam crp->crp_etype = err; 1487117845Ssam crypto_done(crp); 1488117845Ssam } else { 1489117845Ssam sc->sc_needwakeup |= CRYPTO_SYMQ; 1490117845Ssam } 1491117845Ssam return (err); 1492117845Ssam} 1493117845Ssam 1494117845Ssamstatic void 1495117845Ssamsafe_callback(struct safe_softc *sc, struct safe_ringentry *re) 1496117845Ssam{ 1497117845Ssam struct cryptop *crp = (struct cryptop *)re->re_crp; 1498117845Ssam struct cryptodesc *crd; 1499117845Ssam 1500117845Ssam safestats.st_opackets++; 1501117845Ssam safestats.st_obytes += re->re_dst.mapsize; 1502117845Ssam 1503117845Ssam safe_dma_sync(&sc->sc_ringalloc, 1504117845Ssam BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1505117845Ssam if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) { 1506117845Ssam device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n", 1507117845Ssam re->re_desc.d_csr, 1508117845Ssam re->re_sa.sa_cmd0, re->re_sa.sa_cmd1); 1509117845Ssam safestats.st_peoperr++; 1510117845Ssam crp->crp_etype = EIO; /* something more meaningful? */ 1511117845Ssam } 1512117845Ssam if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) { 1513117845Ssam bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map, 1514117845Ssam BUS_DMASYNC_POSTREAD); 1515117845Ssam bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map); 1516117845Ssam bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map); 1517117845Ssam } 1518117845Ssam bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_POSTWRITE); 1519117845Ssam bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map); 1520117845Ssam bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1521117845Ssam 1522117845Ssam /* 1523117845Ssam * If result was written to a differet mbuf chain, swap 1524117845Ssam * it in as the return value and reclaim the original. 1525117845Ssam */ 1526117845Ssam if ((crp->crp_flags & CRYPTO_F_IMBUF) && re->re_src_m != re->re_dst_m) { 1527117845Ssam m_freem(re->re_src_m); 1528117845Ssam crp->crp_buf = (caddr_t)re->re_dst_m; 1529117845Ssam } 1530117845Ssam 1531117845Ssam if (re->re_flags & SAFE_QFLAGS_COPYOUTIV) { 1532117845Ssam /* copy out IV for future use */ 1533117845Ssam for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1534117845Ssam int ivsize; 1535117845Ssam 1536117845Ssam if (crd->crd_alg == CRYPTO_DES_CBC || 1537117845Ssam crd->crd_alg == CRYPTO_3DES_CBC) { 1538117845Ssam ivsize = 2*sizeof(u_int32_t); 1539117845Ssam } else if (crd->crd_alg == CRYPTO_AES_CBC) { 1540117845Ssam ivsize = 4*sizeof(u_int32_t); 1541117845Ssam } else 1542117845Ssam continue; 1543117845Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1544117845Ssam m_copydata((struct mbuf *)crp->crp_buf, 1545117845Ssam crd->crd_skip + crd->crd_len - ivsize, 1546117845Ssam ivsize, 1547117845Ssam (caddr_t) sc->sc_sessions[re->re_sesn].ses_iv); 1548117845Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 1549117845Ssam cuio_copydata((struct uio *)crp->crp_buf, 1550117845Ssam crd->crd_skip + crd->crd_len - ivsize, 1551117845Ssam ivsize, 1552117845Ssam (caddr_t)sc->sc_sessions[re->re_sesn].ses_iv); 1553117845Ssam } 1554117845Ssam break; 1555117845Ssam } 1556117845Ssam } 1557117845Ssam 1558117845Ssam if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) { 1559117845Ssam /* copy out ICV result */ 1560117845Ssam for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1561117845Ssam if (!(crd->crd_alg == CRYPTO_MD5_HMAC || 1562117845Ssam crd->crd_alg == CRYPTO_SHA1_HMAC || 1563117845Ssam crd->crd_alg == CRYPTO_NULL_HMAC)) 1564117845Ssam continue; 1565117845Ssam if (crd->crd_alg == CRYPTO_SHA1_HMAC) { 1566117845Ssam /* 1567117845Ssam * SHA-1 ICV's are byte-swapped; fix 'em up 1568117845Ssam * before copy them to their destination. 1569117845Ssam */ 1570117845Ssam bswap32(re->re_sastate.sa_saved_indigest[0]); 1571117845Ssam bswap32(re->re_sastate.sa_saved_indigest[1]); 1572117845Ssam bswap32(re->re_sastate.sa_saved_indigest[2]); 1573117845Ssam } 1574117845Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1575117845Ssam m_copyback((struct mbuf *)crp->crp_buf, 1576117845Ssam crd->crd_inject, 12, 1577117845Ssam (caddr_t)re->re_sastate.sa_saved_indigest); 1578117845Ssam } else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) { 1579117845Ssam bcopy((caddr_t)re->re_sastate.sa_saved_indigest, 1580117845Ssam crp->crp_mac, 12); 1581117845Ssam } 1582117845Ssam break; 1583117845Ssam } 1584117845Ssam } 1585117845Ssam crypto_done(crp); 1586117845Ssam} 1587117845Ssam 1588117845Ssam/* 1589117845Ssam * Copy all data past offset from srcm to dstm. 1590117845Ssam */ 1591117845Ssamstatic void 1592117845Ssamsafe_mcopy(struct mbuf *srcm, struct mbuf *dstm, u_int offset) 1593117845Ssam{ 1594117845Ssam u_int j, dlen, slen; 1595117845Ssam caddr_t dptr, sptr; 1596117845Ssam 1597117845Ssam /* 1598117845Ssam * Advance src and dst to offset. 1599117845Ssam */ 1600117845Ssam j = offset; 1601117845Ssam while (j >= 0) { 1602117845Ssam if (srcm->m_len > j) 1603117845Ssam break; 1604117845Ssam j -= srcm->m_len; 1605117845Ssam srcm = srcm->m_next; 1606117845Ssam if (srcm == NULL) 1607117845Ssam return; 1608117845Ssam } 1609117845Ssam sptr = mtod(srcm, caddr_t) + j; 1610117845Ssam slen = srcm->m_len - j; 1611117845Ssam 1612117845Ssam j = offset; 1613117845Ssam while (j >= 0) { 1614117845Ssam if (dstm->m_len > j) 1615117845Ssam break; 1616117845Ssam j -= dstm->m_len; 1617117845Ssam dstm = dstm->m_next; 1618117845Ssam if (dstm == NULL) 1619117845Ssam return; 1620117845Ssam } 1621117845Ssam dptr = mtod(dstm, caddr_t) + j; 1622117845Ssam dlen = dstm->m_len - j; 1623117845Ssam 1624117845Ssam /* 1625117845Ssam * Copy everything that remains. 1626117845Ssam */ 1627117845Ssam for (;;) { 1628117845Ssam j = min(slen, dlen); 1629117845Ssam bcopy(sptr, dptr, j); 1630117845Ssam if (slen == j) { 1631117845Ssam srcm = srcm->m_next; 1632117845Ssam if (srcm == NULL) 1633117845Ssam return; 1634117845Ssam sptr = srcm->m_data; 1635117845Ssam slen = srcm->m_len; 1636117845Ssam } else 1637117845Ssam sptr += j, slen -= j; 1638117845Ssam if (dlen == j) { 1639117845Ssam dstm = dstm->m_next; 1640117845Ssam if (dstm == NULL) 1641117845Ssam return; 1642117845Ssam dptr = dstm->m_data; 1643117845Ssam dlen = dstm->m_len; 1644117845Ssam } else 1645117845Ssam dptr += j, dlen -= j; 1646117845Ssam } 1647117845Ssam} 1648117845Ssam 1649117845Ssam#ifndef SAFE_NO_RNG 1650117845Ssam#define SAFE_RNG_MAXWAIT 1000 1651117845Ssam 1652117845Ssamstatic void 1653117845Ssamsafe_rng_init(struct safe_softc *sc) 1654117845Ssam{ 1655117845Ssam u_int32_t w, v; 1656117845Ssam int i; 1657117845Ssam 1658117845Ssam WRITE_REG(sc, SAFE_RNG_CTRL, 0); 1659117845Ssam /* use default value according to the manual */ 1660117845Ssam WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */ 1661117845Ssam WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1662117845Ssam 1663117845Ssam /* 1664117845Ssam * There is a bug in rev 1.0 of the 1140 that when the RNG 1665117845Ssam * is brought out of reset the ready status flag does not 1666117845Ssam * work until the RNG has finished its internal initialization. 1667117845Ssam * 1668117845Ssam * So in order to determine the device is through its 1669117845Ssam * initialization we must read the data register, using the 1670117845Ssam * status reg in the read in case it is initialized. Then read 1671117845Ssam * the data register until it changes from the first read. 1672117845Ssam * Once it changes read the data register until it changes 1673117845Ssam * again. At this time the RNG is considered initialized. 1674117845Ssam * This could take between 750ms - 1000ms in time. 1675117845Ssam */ 1676117845Ssam i = 0; 1677117845Ssam w = READ_REG(sc, SAFE_RNG_OUT); 1678117845Ssam do { 1679117845Ssam v = READ_REG(sc, SAFE_RNG_OUT); 1680117845Ssam if (v != w) { 1681117845Ssam w = v; 1682117845Ssam break; 1683117845Ssam } 1684117845Ssam DELAY(10); 1685117845Ssam } while (++i < SAFE_RNG_MAXWAIT); 1686117845Ssam 1687117845Ssam /* Wait Until data changes again */ 1688117845Ssam i = 0; 1689117845Ssam do { 1690117845Ssam v = READ_REG(sc, SAFE_RNG_OUT); 1691117845Ssam if (v != w) 1692117845Ssam break; 1693117845Ssam DELAY(10); 1694117845Ssam } while (++i < SAFE_RNG_MAXWAIT); 1695117845Ssam} 1696117845Ssam 1697117845Ssamstatic __inline void 1698117845Ssamsafe_rng_disable_short_cycle(struct safe_softc *sc) 1699117845Ssam{ 1700117845Ssam WRITE_REG(sc, SAFE_RNG_CTRL, 1701117845Ssam READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN); 1702117845Ssam} 1703117845Ssam 1704117845Ssamstatic __inline void 1705117845Ssamsafe_rng_enable_short_cycle(struct safe_softc *sc) 1706117845Ssam{ 1707117845Ssam WRITE_REG(sc, SAFE_RNG_CTRL, 1708117845Ssam READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN); 1709117845Ssam} 1710117845Ssam 1711117845Ssamstatic __inline u_int32_t 1712117845Ssamsafe_rng_read(struct safe_softc *sc) 1713117845Ssam{ 1714117845Ssam int i; 1715117845Ssam 1716117845Ssam i = 0; 1717117845Ssam while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT) 1718117845Ssam ; 1719117845Ssam return READ_REG(sc, SAFE_RNG_OUT); 1720117845Ssam} 1721117845Ssam 1722117845Ssamstatic void 1723117845Ssamsafe_rng(void *arg) 1724117845Ssam{ 1725117845Ssam struct safe_softc *sc = arg; 1726117845Ssam u_int32_t buf[SAFE_RNG_MAXBUFSIZ]; /* NB: maybe move to softc */ 1727117845Ssam u_int maxwords; 1728117845Ssam int i; 1729117845Ssam 1730117845Ssam safestats.st_rng++; 1731117845Ssam /* 1732117845Ssam * Fetch the next block of data. 1733117845Ssam */ 1734117845Ssam maxwords = safe_rngbufsize; 1735117845Ssam if (maxwords > SAFE_RNG_MAXBUFSIZ) 1736117845Ssam maxwords = SAFE_RNG_MAXBUFSIZ; 1737117845Ssamretry: 1738117845Ssam for (i = 0; i < maxwords; i++) 1739117845Ssam buf[i] = safe_rng_read(sc); 1740117845Ssam /* 1741117845Ssam * Check the comparator alarm count and reset the h/w if 1742117845Ssam * it exceeds our threshold. This guards against the 1743117845Ssam * hardware oscillators resonating with external signals. 1744117845Ssam */ 1745117845Ssam if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) { 1746117845Ssam u_int32_t freq_inc, w; 1747117845Ssam 1748117845Ssam DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__, 1749117845Ssam READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm)); 1750117845Ssam safestats.st_rngalarm++; 1751117845Ssam safe_rng_enable_short_cycle(sc); 1752117845Ssam freq_inc = 18; 1753117845Ssam for (i = 0; i < 64; i++) { 1754117845Ssam w = READ_REG(sc, SAFE_RNG_CNFG); 1755117845Ssam freq_inc = ((w + freq_inc) & 0x3fL); 1756117845Ssam w = ((w & ~0x3fL) | freq_inc); 1757117845Ssam WRITE_REG(sc, SAFE_RNG_CNFG, w); 1758117845Ssam 1759117845Ssam WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1760117845Ssam 1761117845Ssam (void) safe_rng_read(sc); 1762117845Ssam DELAY(25); 1763117845Ssam 1764117845Ssam if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) { 1765117845Ssam safe_rng_disable_short_cycle(sc); 1766117845Ssam goto retry; 1767117845Ssam } 1768117845Ssam freq_inc = 1; 1769117845Ssam } 1770117845Ssam safe_rng_disable_short_cycle(sc); 1771117845Ssam } else 1772117845Ssam WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1773117845Ssam 1774117845Ssam (*sc->sc_harvest)(sc->sc_rndtest, buf, maxwords*sizeof (u_int32_t)); 1775117845Ssam callout_reset(&sc->sc_rngto, 1776117845Ssam hz * (safe_rnginterval ? safe_rnginterval : 1), safe_rng, sc); 1777117845Ssam} 1778117845Ssam#endif /* SAFE_NO_RNG */ 1779117845Ssam 1780117845Ssamstatic void 1781117845Ssamsafe_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1782117845Ssam{ 1783117845Ssam bus_addr_t *paddr = (bus_addr_t*) arg; 1784117845Ssam *paddr = segs->ds_addr; 1785117845Ssam} 1786117845Ssam 1787117845Ssamstatic int 1788117845Ssamsafe_dma_malloc( 1789117845Ssam struct safe_softc *sc, 1790117845Ssam bus_size_t size, 1791117845Ssam struct safe_dma_alloc *dma, 1792117845Ssam int mapflags 1793117845Ssam) 1794117845Ssam{ 1795117845Ssam int r; 1796117845Ssam 1797117845Ssam r = bus_dma_tag_create(NULL, /* parent */ 1798117845Ssam sizeof(u_int32_t), 0, /* alignment, bounds */ 1799117845Ssam BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1800117845Ssam BUS_SPACE_MAXADDR, /* highaddr */ 1801117845Ssam NULL, NULL, /* filter, filterarg */ 1802117845Ssam size, /* maxsize */ 1803117845Ssam 1, /* nsegments */ 1804117845Ssam size, /* maxsegsize */ 1805117845Ssam BUS_DMA_ALLOCNOW, /* flags */ 1806117845Ssam NULL, NULL, /* locking */ 1807117845Ssam &dma->dma_tag); 1808117845Ssam if (r != 0) { 1809117845Ssam device_printf(sc->sc_dev, "safe_dma_malloc: " 1810117845Ssam "bus_dma_tag_create failed; error %u\n", r); 1811117845Ssam goto fail_0; 1812117845Ssam } 1813117845Ssam 1814117845Ssam r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map); 1815117845Ssam if (r != 0) { 1816117845Ssam device_printf(sc->sc_dev, "safe_dma_malloc: " 1817117845Ssam "bus_dmamap_create failed; error %u\n", r); 1818117845Ssam goto fail_1; 1819117845Ssam } 1820117845Ssam 1821117845Ssam r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 1822117845Ssam BUS_DMA_NOWAIT, &dma->dma_map); 1823117845Ssam if (r != 0) { 1824117845Ssam device_printf(sc->sc_dev, "safe_dma_malloc: " 1825117845Ssam "bus_dmammem_alloc failed; size %zu, error %u\n", 1826117845Ssam size, r); 1827117845Ssam goto fail_2; 1828117845Ssam } 1829117845Ssam 1830117845Ssam r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 1831117845Ssam size, 1832117845Ssam safe_dmamap_cb, 1833117845Ssam &dma->dma_paddr, 1834117845Ssam mapflags | BUS_DMA_NOWAIT); 1835117845Ssam if (r != 0) { 1836117845Ssam device_printf(sc->sc_dev, "safe_dma_malloc: " 1837117845Ssam "bus_dmamap_load failed; error %u\n", r); 1838117845Ssam goto fail_3; 1839117845Ssam } 1840117845Ssam 1841117845Ssam dma->dma_size = size; 1842117845Ssam return (0); 1843117845Ssam 1844117845Ssamfail_3: 1845117845Ssam bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1846117845Ssamfail_2: 1847117845Ssam bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1848117845Ssamfail_1: 1849117845Ssam bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1850117845Ssam bus_dma_tag_destroy(dma->dma_tag); 1851117845Ssamfail_0: 1852117845Ssam dma->dma_map = NULL; 1853117845Ssam dma->dma_tag = NULL; 1854117845Ssam return (r); 1855117845Ssam} 1856117845Ssam 1857117845Ssamstatic void 1858117845Ssamsafe_dma_free(struct safe_softc *sc, struct safe_dma_alloc *dma) 1859117845Ssam{ 1860117845Ssam bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1861117845Ssam bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1862117845Ssam bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1863117845Ssam bus_dma_tag_destroy(dma->dma_tag); 1864117845Ssam} 1865117845Ssam 1866117845Ssam/* 1867117845Ssam * Resets the board. Values in the regesters are left as is 1868117845Ssam * from the reset (i.e. initial values are assigned elsewhere). 1869117845Ssam */ 1870117845Ssamstatic void 1871117845Ssamsafe_reset_board(struct safe_softc *sc) 1872117845Ssam{ 1873117845Ssam u_int32_t v; 1874117845Ssam /* 1875117845Ssam * Reset the device. The manual says no delay 1876117845Ssam * is needed between marking and clearing reset. 1877117845Ssam */ 1878117845Ssam v = READ_REG(sc, SAFE_PE_DMACFG) &~ 1879117845Ssam (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET | 1880117845Ssam SAFE_PE_DMACFG_SGRESET); 1881117845Ssam WRITE_REG(sc, SAFE_PE_DMACFG, v 1882117845Ssam | SAFE_PE_DMACFG_PERESET 1883117845Ssam | SAFE_PE_DMACFG_PDRRESET 1884117845Ssam | SAFE_PE_DMACFG_SGRESET); 1885117845Ssam WRITE_REG(sc, SAFE_PE_DMACFG, v); 1886117845Ssam} 1887117845Ssam 1888117845Ssam/* 1889117845Ssam * Initialize registers we need to touch only once. 1890117845Ssam */ 1891117845Ssamstatic void 1892117845Ssamsafe_init_board(struct safe_softc *sc) 1893117845Ssam{ 1894117845Ssam u_int32_t v, dwords; 1895117845Ssam 1896117845Ssam v = READ_REG(sc, SAFE_PE_DMACFG);; 1897117845Ssam v &=~ SAFE_PE_DMACFG_PEMODE; 1898117845Ssam v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */ 1899117845Ssam | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ 1900117845Ssam | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ 1901117845Ssam | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ 1902117845Ssam | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ 1903117845Ssam | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ 1904117845Ssam ; 1905117845Ssam WRITE_REG(sc, SAFE_PE_DMACFG, v); 1906117845Ssam#if 0 1907117845Ssam /* XXX select byte swap based on host byte order */ 1908117845Ssam WRITE_REG(sc, SAFE_ENDIAN, 0x1b); 1909117845Ssam#endif 1910117845Ssam if (sc->sc_chiprev == SAFE_REV(1,0)) { 1911117845Ssam /* 1912117845Ssam * Avoid large PCI DMA transfers. Rev 1.0 has a bug where 1913117845Ssam * "target mode transfers" done while the chip is DMA'ing 1914117845Ssam * >1020 bytes cause the hardware to lockup. To avoid this 1915117845Ssam * we reduce the max PCI transfer size and use small source 1916117845Ssam * particle descriptors (<= 256 bytes). 1917117845Ssam */ 1918117845Ssam WRITE_REG(sc, SAFE_DMA_CFG, 256); 1919117845Ssam device_printf(sc->sc_dev, 1920117845Ssam "Reduce max DMA size to %u words for rev %u.%u WAR\n", 1921117845Ssam (READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff, 1922117845Ssam SAFE_REV_MAJ(sc->sc_chiprev), 1923117845Ssam SAFE_REV_MIN(sc->sc_chiprev)); 1924117845Ssam } 1925117845Ssam 1926117845Ssam /* NB: operands+results are overlaid */ 1927117845Ssam WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr); 1928117845Ssam WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr); 1929117845Ssam /* 1930117845Ssam * Configure ring entry size and number of items in the ring. 1931117845Ssam */ 1932117845Ssam KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0, 1933117845Ssam ("PE ring entry not 32-bit aligned!")); 1934117845Ssam dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t); 1935117845Ssam WRITE_REG(sc, SAFE_PE_RINGCFG, 1936117845Ssam (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE); 1937117845Ssam WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */ 1938117845Ssam 1939117845Ssam WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr); 1940117845Ssam WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr); 1941117845Ssam WRITE_REG(sc, SAFE_PE_PARTSIZE, 1942117845Ssam (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART); 1943117845Ssam /* 1944117845Ssam * NB: destination particles are fixed size. We use 1945117845Ssam * an mbuf cluster and require all results go to 1946117845Ssam * clusters or smaller. 1947117845Ssam */ 1948117845Ssam WRITE_REG(sc, SAFE_PE_PARTCFG, SAFE_MAX_DSIZE); 1949117845Ssam 1950117845Ssam /* it's now safe to enable PE mode, do it */ 1951117845Ssam WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE); 1952117845Ssam 1953117845Ssam /* 1954117845Ssam * Configure hardware to use level-triggered interrupts and 1955117845Ssam * to interrupt after each descriptor is processed. 1956117845Ssam */ 1957117845Ssam WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL); 1958117845Ssam WRITE_REG(sc, SAFE_HI_DESC_CNT, 1); 1959117845Ssam WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR); 1960117845Ssam} 1961117845Ssam 1962117845Ssam/* 1963117845Ssam * Init PCI registers 1964117845Ssam */ 1965117845Ssamstatic void 1966117845Ssamsafe_init_pciregs(device_t dev) 1967117845Ssam{ 1968117845Ssam} 1969117845Ssam 1970117845Ssam/* 1971117845Ssam * Clean up after a chip crash. 1972117845Ssam * It is assumed that the caller in splimp() 1973117845Ssam */ 1974117845Ssamstatic void 1975117845Ssamsafe_cleanchip(struct safe_softc *sc) 1976117845Ssam{ 1977117845Ssam 1978117845Ssam if (sc->sc_nqchip != 0) { 1979117845Ssam struct safe_ringentry *re = sc->sc_back; 1980117845Ssam 1981117845Ssam while (re != sc->sc_front) { 1982117845Ssam if (re->re_desc.d_csr != 0) 1983117845Ssam safe_free_entry(sc, re); 1984117845Ssam if (++re == sc->sc_ringtop) 1985117845Ssam re = sc->sc_ring; 1986117845Ssam } 1987117845Ssam sc->sc_back = re; 1988117845Ssam sc->sc_nqchip = 0; 1989117845Ssam } 1990117845Ssam} 1991117845Ssam 1992117845Ssam/* 1993117845Ssam * free a safe_q 1994117845Ssam * It is assumed that the caller is within splimp(). 1995117845Ssam */ 1996117845Ssamstatic int 1997117845Ssamsafe_free_entry(struct safe_softc *sc, struct safe_ringentry *re) 1998117845Ssam{ 1999117845Ssam struct cryptop *crp; 2000117845Ssam 2001117845Ssam /* 2002117845Ssam * Free header MCR 2003117845Ssam */ 2004117845Ssam if ((re->re_dst_m != NULL) && (re->re_src_m != re->re_dst_m)) 2005117845Ssam m_freem(re->re_dst_m); 2006117845Ssam 2007117845Ssam crp = (struct cryptop *)re->re_crp; 2008117845Ssam 2009117845Ssam re->re_desc.d_csr = 0; 2010117845Ssam 2011117845Ssam crp->crp_etype = EFAULT; 2012117845Ssam crypto_done(crp); 2013117845Ssam return(0); 2014117845Ssam} 2015117845Ssam 2016117845Ssam/* 2017117845Ssam * Routine to reset the chip and clean up. 2018117845Ssam * It is assumed that the caller is in splimp() 2019117845Ssam */ 2020117845Ssamstatic void 2021117845Ssamsafe_totalreset(struct safe_softc *sc) 2022117845Ssam{ 2023117845Ssam safe_reset_board(sc); 2024117845Ssam safe_init_board(sc); 2025117845Ssam safe_cleanchip(sc); 2026117845Ssam} 2027117845Ssam 2028117845Ssam/* 2029117845Ssam * Is the operand suitable aligned for direct DMA. Each 2030117845Ssam * segment must be aligned on a 32-bit boundary and all 2031117845Ssam * but the last segment must be a multiple of 4 bytes. 2032117845Ssam */ 2033117845Ssamstatic int 2034117845Ssamsafe_dmamap_aligned(const struct safe_operand *op) 2035117845Ssam{ 2036117845Ssam int i; 2037117845Ssam 2038117845Ssam for (i = 0; i < op->nsegs; i++) { 2039117845Ssam if (op->segs[i].ds_addr & 3) 2040117845Ssam return (0); 2041117845Ssam if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3)) 2042117845Ssam return (0); 2043117845Ssam } 2044117845Ssam return (1); 2045117845Ssam} 2046117845Ssam 2047117845Ssam/* 2048117845Ssam * Is the operand suitable for direct DMA as the destination 2049117845Ssam * of an operation. The hardware requires that each ``particle'' 2050117845Ssam * but the last in an operation result have the same size. We 2051117845Ssam * fix that size at SAFE_MAX_DSIZE bytes. This routine returns 2052117845Ssam * 0 if some segment is not a multiple of of this size, 1 if all 2053117845Ssam * segments are exactly this size, or 2 if segments are at worst 2054117845Ssam * a multple of this size. 2055117845Ssam */ 2056117845Ssamstatic int 2057117845Ssamsafe_dmamap_uniform(const struct safe_operand *op) 2058117845Ssam{ 2059117845Ssam int result = 1; 2060117845Ssam 2061117845Ssam if (op->nsegs > 0) { 2062117845Ssam int i; 2063117845Ssam 2064118882Ssam for (i = 0; i < op->nsegs-1; i++) { 2065117845Ssam if (op->segs[i].ds_len % SAFE_MAX_DSIZE) 2066117845Ssam return (0); 2067117845Ssam if (op->segs[i].ds_len != SAFE_MAX_DSIZE) 2068117845Ssam result = 2; 2069118882Ssam } 2070117845Ssam } 2071117845Ssam return (result); 2072117845Ssam} 2073117845Ssam 2074117845Ssam#ifdef SAFE_DEBUG 2075117845Ssamstatic void 2076117845Ssamsafe_dump_dmastatus(struct safe_softc *sc, const char *tag) 2077117845Ssam{ 2078117845Ssam printf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n" 2079117845Ssam , tag 2080117845Ssam , READ_REG(sc, SAFE_DMA_ENDIAN) 2081117845Ssam , READ_REG(sc, SAFE_DMA_SRCADDR) 2082117845Ssam , READ_REG(sc, SAFE_DMA_DSTADDR) 2083117845Ssam , READ_REG(sc, SAFE_DMA_STAT) 2084117845Ssam ); 2085117845Ssam} 2086117845Ssam 2087117845Ssamstatic void 2088117845Ssamsafe_dump_intrstate(struct safe_softc *sc, const char *tag) 2089117845Ssam{ 2090117845Ssam printf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n" 2091117845Ssam , tag 2092117845Ssam , READ_REG(sc, SAFE_HI_CFG) 2093117845Ssam , READ_REG(sc, SAFE_HI_MASK) 2094117845Ssam , READ_REG(sc, SAFE_HI_DESC_CNT) 2095117845Ssam , READ_REG(sc, SAFE_HU_STAT) 2096117845Ssam , READ_REG(sc, SAFE_HM_STAT) 2097117845Ssam ); 2098117845Ssam} 2099117845Ssam 2100117845Ssamstatic void 2101117845Ssamsafe_dump_ringstate(struct safe_softc *sc, const char *tag) 2102117845Ssam{ 2103117845Ssam u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT); 2104117845Ssam 2105117845Ssam /* NB: assume caller has lock on ring */ 2106125466Speter printf("%s: ERNGSTAT %x (next %u) back %lu front %lu\n", 2107117845Ssam tag, 2108117845Ssam estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S), 2109125466Speter (unsigned long)(sc->sc_back - sc->sc_ring), 2110125466Speter (unsigned long)(sc->sc_front - sc->sc_ring)); 2111117845Ssam} 2112117845Ssam 2113117845Ssamstatic void 2114117845Ssamsafe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re) 2115117845Ssam{ 2116117845Ssam int ix, nsegs; 2117117845Ssam 2118117845Ssam ix = re - sc->sc_ring; 2119117845Ssam printf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n" 2120117845Ssam , tag 2121117845Ssam , re, ix 2122117845Ssam , re->re_desc.d_csr 2123117845Ssam , re->re_desc.d_src 2124117845Ssam , re->re_desc.d_dst 2125117845Ssam , re->re_desc.d_sa 2126117845Ssam , re->re_desc.d_len 2127117845Ssam ); 2128117845Ssam if (re->re_src.nsegs > 1) { 2129117845Ssam ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) / 2130117845Ssam sizeof(struct safe_pdesc); 2131117845Ssam for (nsegs = re->re_src.nsegs; nsegs; nsegs--) { 2132117845Ssam printf(" spd[%u] %p: %p size %u flags %x" 2133117845Ssam , ix, &sc->sc_spring[ix] 2134125466Speter , (caddr_t)(uintptr_t) sc->sc_spring[ix].pd_addr 2135117845Ssam , sc->sc_spring[ix].pd_size 2136117845Ssam , sc->sc_spring[ix].pd_flags 2137117845Ssam ); 2138117845Ssam if (sc->sc_spring[ix].pd_size == 0) 2139117845Ssam printf(" (zero!)"); 2140117845Ssam printf("\n"); 2141117845Ssam if (++ix == SAFE_TOTAL_SPART) 2142117845Ssam ix = 0; 2143117845Ssam } 2144117845Ssam } 2145117845Ssam if (re->re_dst.nsegs > 1) { 2146117845Ssam ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) / 2147117845Ssam sizeof(struct safe_pdesc); 2148117845Ssam for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) { 2149117845Ssam printf(" dpd[%u] %p: %p flags %x\n" 2150117845Ssam , ix, &sc->sc_dpring[ix] 2151125466Speter , (caddr_t)(uintptr_t) sc->sc_dpring[ix].pd_addr 2152117845Ssam , sc->sc_dpring[ix].pd_flags 2153117845Ssam ); 2154117845Ssam if (++ix == SAFE_TOTAL_DPART) 2155117845Ssam ix = 0; 2156117845Ssam } 2157117845Ssam } 2158117845Ssam printf("sa: cmd0 %08x cmd1 %08x staterec %x\n", 2159117845Ssam re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec); 2160117845Ssam printf("sa: key %x %x %x %x %x %x %x %x\n" 2161117845Ssam , re->re_sa.sa_key[0] 2162117845Ssam , re->re_sa.sa_key[1] 2163117845Ssam , re->re_sa.sa_key[2] 2164117845Ssam , re->re_sa.sa_key[3] 2165117845Ssam , re->re_sa.sa_key[4] 2166117845Ssam , re->re_sa.sa_key[5] 2167117845Ssam , re->re_sa.sa_key[6] 2168117845Ssam , re->re_sa.sa_key[7] 2169117845Ssam ); 2170117845Ssam printf("sa: indigest %x %x %x %x %x\n" 2171117845Ssam , re->re_sa.sa_indigest[0] 2172117845Ssam , re->re_sa.sa_indigest[1] 2173117845Ssam , re->re_sa.sa_indigest[2] 2174117845Ssam , re->re_sa.sa_indigest[3] 2175117845Ssam , re->re_sa.sa_indigest[4] 2176117845Ssam ); 2177117845Ssam printf("sa: outdigest %x %x %x %x %x\n" 2178117845Ssam , re->re_sa.sa_outdigest[0] 2179117845Ssam , re->re_sa.sa_outdigest[1] 2180117845Ssam , re->re_sa.sa_outdigest[2] 2181117845Ssam , re->re_sa.sa_outdigest[3] 2182117845Ssam , re->re_sa.sa_outdigest[4] 2183117845Ssam ); 2184117845Ssam printf("sr: iv %x %x %x %x\n" 2185117845Ssam , re->re_sastate.sa_saved_iv[0] 2186117845Ssam , re->re_sastate.sa_saved_iv[1] 2187117845Ssam , re->re_sastate.sa_saved_iv[2] 2188117845Ssam , re->re_sastate.sa_saved_iv[3] 2189117845Ssam ); 2190117845Ssam printf("sr: hashbc %u indigest %x %x %x %x %x\n" 2191117845Ssam , re->re_sastate.sa_saved_hashbc 2192117845Ssam , re->re_sastate.sa_saved_indigest[0] 2193117845Ssam , re->re_sastate.sa_saved_indigest[1] 2194117845Ssam , re->re_sastate.sa_saved_indigest[2] 2195117845Ssam , re->re_sastate.sa_saved_indigest[3] 2196117845Ssam , re->re_sastate.sa_saved_indigest[4] 2197117845Ssam ); 2198117845Ssam} 2199117845Ssam 2200117845Ssamstatic void 2201117845Ssamsafe_dump_ring(struct safe_softc *sc, const char *tag) 2202117845Ssam{ 2203117845Ssam mtx_lock(&sc->sc_ringmtx); 2204117845Ssam printf("\nSafeNet Ring State:\n"); 2205117845Ssam safe_dump_intrstate(sc, tag); 2206117845Ssam safe_dump_dmastatus(sc, tag); 2207117845Ssam safe_dump_ringstate(sc, tag); 2208117845Ssam if (sc->sc_nqchip) { 2209117845Ssam struct safe_ringentry *re = sc->sc_back; 2210117845Ssam do { 2211117845Ssam safe_dump_request(sc, tag, re); 2212117845Ssam if (++re == sc->sc_ringtop) 2213117845Ssam re = sc->sc_ring; 2214117845Ssam } while (re != sc->sc_front); 2215117845Ssam } 2216117845Ssam mtx_unlock(&sc->sc_ringmtx); 2217117845Ssam} 2218117845Ssam 2219117845Ssamstatic int 2220117845Ssamsysctl_hw_safe_dump(SYSCTL_HANDLER_ARGS) 2221117845Ssam{ 2222117845Ssam char dmode[64]; 2223117845Ssam int error; 2224117845Ssam 2225117845Ssam strncpy(dmode, "", sizeof(dmode) - 1); 2226117845Ssam dmode[sizeof(dmode) - 1] = '\0'; 2227117845Ssam error = sysctl_handle_string(oidp, &dmode[0], sizeof(dmode), req); 2228117845Ssam 2229117845Ssam if (error == 0 && req->newptr != NULL) { 2230117845Ssam struct safe_softc *sc = safec; 2231117845Ssam 2232117845Ssam if (!sc) 2233117845Ssam return EINVAL; 2234117845Ssam if (strncmp(dmode, "dma", 3) == 0) 2235117845Ssam safe_dump_dmastatus(sc, "safe0"); 2236117845Ssam else if (strncmp(dmode, "int", 3) == 0) 2237117845Ssam safe_dump_intrstate(sc, "safe0"); 2238117845Ssam else if (strncmp(dmode, "ring", 4) == 0) 2239117845Ssam safe_dump_ring(sc, "safe0"); 2240117845Ssam else 2241117845Ssam return EINVAL; 2242117845Ssam } 2243117845Ssam return error; 2244117845Ssam} 2245117845SsamSYSCTL_PROC(_hw_safe, OID_AUTO, dump, CTLTYPE_STRING | CTLFLAG_RW, 2246117845Ssam 0, 0, sysctl_hw_safe_dump, "A", "Dump driver state"); 2247117845Ssam#endif /* SAFE_DEBUG */ 2248