if_rlreg.h revision 50703
118334Speter/* 290075Sobrien * Copyright (c) 1997, 1998 3102780Skan * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 418334Speter * 518334Speter * Redistribution and use in source and binary forms, with or without 618334Speter * modification, are permitted provided that the following conditions 718334Speter * are met: 818334Speter * 1. Redistributions of source code must retain the above copyright 918334Speter * notice, this list of conditions and the following disclaimer. 1018334Speter * 2. Redistributions in binary form must reproduce the above copyright 1118334Speter * notice, this list of conditions and the following disclaimer in the 1218334Speter * documentation and/or other materials provided with the distribution. 1318334Speter * 3. All advertising materials mentioning features or use of this software 1418334Speter * must display the following acknowledgement: 1518334Speter * This product includes software developed by Bill Paul. 1618334Speter * 4. Neither the name of the author nor the names of any co-contributors 1718334Speter * may be used to endorse or promote products derived from this software 1818334Speter * without specific prior written permission. 1918334Speter * 2018334Speter * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2118334Speter * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2218334Speter * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2350397Sobrien * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2418334Speter * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2518334Speter * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2650397Sobrien * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2718334Speter * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2818334Speter * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2990075Sobrien * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3018334Speter * THE POSSIBILITY OF SUCH DAMAGE. 3118334Speter * 3218334Speter * $FreeBSD: head/sys/pci/if_rlreg.h 50703 1999-08-31 14:45:51Z wpaul $ 3350397Sobrien */ 3450397Sobrien 3590075Sobrien/* 3618334Speter * RealTek 8129/8139 register offsets 3790075Sobrien */ 3890075Sobrien#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 3990075Sobrien#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 4090075Sobrien#define RL_IDR2 0x0002 4190075Sobrien#define RL_IDR3 0x0003 4290075Sobrien#define RL_IDR4 0x0004 4390075Sobrien#define RL_IDR5 0x0005 4490075Sobrien /* 0006-0007 reserved */ 4590075Sobrien#define RL_MAR0 0x0008 /* Multicast hash table */ 4690075Sobrien#define RL_MAR1 0x0009 4790075Sobrien#define RL_MAR2 0x000A 4890075Sobrien#define RL_MAR3 0x000B 4990075Sobrien#define RL_MAR4 0x000C 5090075Sobrien#define RL_MAR5 0x000D 5190075Sobrien#define RL_MAR6 0x000E 5290075Sobrien#define RL_MAR7 0x000F 5390075Sobrien 5490075Sobrien#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 5590075Sobrien#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 5690075Sobrien#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 5790075Sobrien#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 5818334Speter 5918334Speter#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 6018334Speter#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 6118334Speter#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 6290075Sobrien#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 6318334Speter 6418334Speter#define RL_RXADDR 0x0030 /* RX ring start address */ 6518334Speter#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 6618334Speter#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 6718334Speter#define RL_COMMAND 0x0037 /* command register */ 6818334Speter#define RL_CURRXADDR 0x0038 /* current address of packet read */ 6918334Speter#define RL_CURRXBUF 0x003A /* current RX buffer address */ 7090075Sobrien#define RL_IMR 0x003C /* interrupt mask register */ 7190075Sobrien#define RL_ISR 0x003E /* interrupt status register */ 7290075Sobrien#define RL_TXCFG 0x0040 /* transmit config */ 7318334Speter#define RL_RXCFG 0x0044 /* receive config */ 7418334Speter#define RL_TIMERCNT 0x0048 /* timer count register */ 7590075Sobrien#define RL_MISSEDPKT 0x004C /* missed packet counter */ 7690075Sobrien#define RL_EECMD 0x0050 /* EEPROM command register */ 7718334Speter#define RL_CFG0 0x0051 /* config register #0 */ 7818334Speter#define RL_CFG1 0x0052 /* config register #1 */ 7990075Sobrien /* 0053-0057 reserved */ 8090075Sobrien#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 8190075Sobrien /* 0059-005A reserved */ 8290075Sobrien#define RL_MII 0x005A /* 8129 chip only */ 8390075Sobrien#define RL_HALTCLK 0x005B 8490075Sobrien#define RL_MULTIINTR 0x005C /* multiple interrupt */ 8590075Sobrien#define RL_PCIREV 0x005E /* PCI revision value */ 8690075Sobrien /* 005F reserved */ 8718334Speter#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 8890075Sobrien 8990075Sobrien/* Direct PHY access registers only available on 8139 */ 9090075Sobrien#define RL_BMCR 0x0062 /* PHY basic mode control */ 9190075Sobrien#define RL_BMSR 0x0064 /* PHY basic mode status */ 9290075Sobrien#define RL_ANAR 0x0066 /* PHY autoneg advert */ 9390075Sobrien#define RL_LPAR 0x0068 /* PHY link partner ability */ 9490075Sobrien#define RL_ANER 0x006A /* PHY autoneg expansion */ 9590075Sobrien 9690075Sobrien#define RL_DISCCNT 0x006C /* disconnect counter */ 9790075Sobrien#define RL_FALSECAR 0x006E /* false carrier counter */ 9890075Sobrien#define RL_NWAYTST 0x0070 /* NWAY test register */ 9990075Sobrien#define RL_RX_ER 0x0072 /* RX_ER counter */ 10090075Sobrien#define RL_CSCFG 0x0074 /* CS configuration register */ 10118334Speter 10290075Sobrien 10390075Sobrien/* 10418334Speter * TX config register bits 10590075Sobrien */ 10690075Sobrien#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 10790075Sobrien#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 10890075Sobrien#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 10950397Sobrien#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 11090075Sobrien#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 11190075Sobrien 11290075Sobrien#define RL_TXDMA_16BYTES 0x00000000 11390075Sobrien#define RL_TXDMA_32BYTES 0x00000100 11490075Sobrien#define RL_TXDMA_64BYTES 0x00000200 11596263Sobrien#define RL_TXDMA_128BYTES 0x00000300 11696263Sobrien#define RL_TXDMA_256BYTES 0x00000400 11796263Sobrien#define RL_TXDMA_512BYTES 0x00000500 11896263Sobrien#define RL_TXDMA_1024BYTES 0x00000600 11990075Sobrien#define RL_TXDMA_2048BYTES 0x00000700 12090075Sobrien 12190075Sobrien/* 12290075Sobrien * Transmit descriptor status register bits. 12390075Sobrien */ 12490075Sobrien#define RL_TXSTAT_LENMASK 0x00001FFF 12590075Sobrien#define RL_TXSTAT_OWN 0x00002000 12690075Sobrien#define RL_TXSTAT_TX_UNDERRUN 0x00004000 12790075Sobrien#define RL_TXSTAT_TX_OK 0x00008000 12890075Sobrien#define RL_TXSTAT_EARLY_THRESH 0x003F0000 12990075Sobrien#define RL_TXSTAT_COLLCNT 0x0F000000 13090075Sobrien#define RL_TXSTAT_CARR_HBEAT 0x10000000 13190075Sobrien#define RL_TXSTAT_OUTOFWIN 0x20000000 13290075Sobrien#define RL_TXSTAT_TXABRT 0x40000000 13390075Sobrien#define RL_TXSTAT_CARRLOSS 0x80000000 13490075Sobrien 13590075Sobrien/* 13690075Sobrien * Interrupt status register bits. 13790075Sobrien */ 13890075Sobrien#define RL_ISR_RX_OK 0x0001 13990075Sobrien#define RL_ISR_RX_ERR 0x0002 14090075Sobrien#define RL_ISR_TX_OK 0x0004 14190075Sobrien#define RL_ISR_TX_ERR 0x0008 14290075Sobrien#define RL_ISR_RX_OVERRUN 0x0010 14390075Sobrien#define RL_ISR_PKT_UNDERRUN 0x0020 14490075Sobrien#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 14590075Sobrien#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 14690075Sobrien#define RL_ISR_SYSTEM_ERR 0x8000 14790075Sobrien 14890075Sobrien#define RL_INTRS \ 14990075Sobrien (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 15090075Sobrien RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 15190075Sobrien RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 15290075Sobrien 15390075Sobrien/* 15490075Sobrien * Media status register. (8139 only) 15590075Sobrien */ 15690075Sobrien#define RL_MEDIASTAT_RXPAUSE 0x01 15790075Sobrien#define RL_MEDIASTAT_TXPAUSE 0x02 15890075Sobrien#define RL_MEDIASTAT_LINK 0x04 15918334Speter#define RL_MEDIASTAT_SPEED10 0x08 16090075Sobrien#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 16190075Sobrien#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 16218334Speter 16390075Sobrien/* 16490075Sobrien * Receive config register. 16518334Speter */ 16690075Sobrien#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 16790075Sobrien#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 16890075Sobrien#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 16990075Sobrien#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 17090075Sobrien#define RL_RXCFG_RX_RUNT 0x00000010 17190075Sobrien#define RL_RXCFG_RX_ERRPKT 0x00000020 17290075Sobrien#define RL_RXCFG_WRAP 0x00000080 17390075Sobrien#define RL_RXCFG_MAXDMA 0x00000700 17490075Sobrien#define RL_RXCFG_BUFSZ 0x00001800 17590075Sobrien#define RL_RXCFG_FIFOTHRESH 0x0000E000 17690075Sobrien#define RL_RXCFG_EARLYTHRESH 0x07000000 17790075Sobrien 17890075Sobrien#define RL_RXDMA_16BYTES 0x00000000 179102780Skan#define RL_RXDMA_32BYTES 0x00000100 180102780Skan#define RL_RXDMA_64BYTES 0x00000200 181102780Skan#define RL_RXDMA_128BYTES 0x00000300 182102780Skan#define RL_RXDMA_256BYTES 0x00000400 183102780Skan#define RL_RXDMA_512BYTES 0x00000500 184102780Skan#define RL_RXDMA_1024BYTES 0x00000600 185102780Skan#define RL_RXDMA_UNLIMITED 0x00000700 186102780Skan 187102780Skan#define RL_RXBUF_8 0x00000000 188102780Skan#define RL_RXBUF_16 0x00000800 189102780Skan#define RL_RXBUF_32 0x00001000 190102780Skan#define RL_RXBUF_64 0x00001800 191102780Skan 192102780Skan#define RL_RXFIFO_16BYTES 0x00000000 193102780Skan#define RL_RXFIFO_32BYTES 0x00002000 194102780Skan#define RL_RXFIFO_64BYTES 0x00004000 195102780Skan#define RL_RXFIFO_128BYTES 0x00006000 196102780Skan#define RL_RXFIFO_256BYTES 0x00008000 197102780Skan#define RL_RXFIFO_512BYTES 0x0000A000 198102780Skan#define RL_RXFIFO_1024BYTES 0x0000C000 199102780Skan#define RL_RXFIFO_NOTHRESH 0x0000E000 200102780Skan 201102780Skan/* 202102780Skan * Bits in RX status header (included with RX'ed packet 203102780Skan * in ring buffer). 204102780Skan */ 205102780Skan#define RL_RXSTAT_RXOK 0x00000001 206102780Skan#define RL_RXSTAT_ALIGNERR 0x00000002 207102780Skan#define RL_RXSTAT_CRCERR 0x00000004 208102780Skan#define RL_RXSTAT_GIANT 0x00000008 209102780Skan#define RL_RXSTAT_RUNT 0x00000010 210102780Skan#define RL_RXSTAT_BADSYM 0x00000020 211102780Skan#define RL_RXSTAT_BROAD 0x00002000 212102780Skan#define RL_RXSTAT_INDIV 0x00004000 213102780Skan#define RL_RXSTAT_MULTI 0x00008000 214102780Skan#define RL_RXSTAT_LENMASK 0xFFFF0000 215102780Skan 216102780Skan#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 21790075Sobrien/* 21890075Sobrien * Command register. 21990075Sobrien */ 22090075Sobrien#define RL_CMD_EMPTY_RXBUF 0x0001 22190075Sobrien#define RL_CMD_TX_ENB 0x0004 22290075Sobrien#define RL_CMD_RX_ENB 0x0008 22390075Sobrien#define RL_CMD_RESET 0x0010 22490075Sobrien 22590075Sobrien/* 22690075Sobrien * EEPROM control register 22790075Sobrien */ 22890075Sobrien#define RL_EE_DATAOUT 0x01 /* Data out */ 22990075Sobrien#define RL_EE_DATAIN 0x02 /* Data in */ 23090075Sobrien#define RL_EE_CLK 0x04 /* clock */ 23190075Sobrien#define RL_EE_SEL 0x08 /* chip select */ 23290075Sobrien#define RL_EE_MODE (0x40|0x80) 23390075Sobrien 23490075Sobrien#define RL_EEMODE_OFF 0x00 23590075Sobrien#define RL_EEMODE_AUTOLOAD 0x40 23690075Sobrien#define RL_EEMODE_PROGRAM 0x80 23790075Sobrien#define RL_EEMODE_WRITECFG (0x80|0x40) 23890075Sobrien 23990075Sobrien/* 9346 EEPROM commands */ 24090075Sobrien#define RL_EECMD_WRITE 0x140 24190075Sobrien#define RL_EECMD_READ 0x180 24290075Sobrien#define RL_EECMD_ERASE 0x1c0 24390075Sobrien 244102780Skan#define RL_EE_ID 0x00 24518334Speter#define RL_EE_PCI_VID 0x01 24690075Sobrien#define RL_EE_PCI_DID 0x02 24718334Speter/* Location of station address inside EEPROM */ 24850397Sobrien#define RL_EE_EADDR 0x07 24918334Speter 25090075Sobrien/* 25190075Sobrien * MII register (8129 only) 25218334Speter */ 25318334Speter#define RL_MII_CLK 0x01 25418334Speter#define RL_MII_DATAIN 0x02 25518334Speter#define RL_MII_DATAOUT 0x04 25618334Speter#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 25790075Sobrien 25850397Sobrien/* 25990075Sobrien * Config 0 register 26090075Sobrien */ 26190075Sobrien#define RL_CFG0_ROM0 0x01 26290075Sobrien#define RL_CFG0_ROM1 0x02 26390075Sobrien#define RL_CFG0_ROM2 0x04 26490075Sobrien#define RL_CFG0_PL0 0x08 26590075Sobrien#define RL_CFG0_PL1 0x10 26618334Speter#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 26790075Sobrien#define RL_CFG0_PCS 0x40 26890075Sobrien#define RL_CFG0_SCR 0x80 26990075Sobrien 27090075Sobrien/* 27190075Sobrien * Config 1 register 27290075Sobrien */ 27390075Sobrien#define RL_CFG1_PWRDWN 0x01 27490075Sobrien#define RL_CFG1_SLEEP 0x02 27590075Sobrien#define RL_CFG1_IOMAP 0x04 27690075Sobrien#define RL_CFG1_MEMMAP 0x08 27718334Speter#define RL_CFG1_RSVD 0x10 27818334Speter#define RL_CFG1_DRVLOAD 0x20 27990075Sobrien#define RL_CFG1_LED0 0x40 28018334Speter#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 28118334Speter#define RL_CFG1_LED1 0x80 28218334Speter 28318334Speter/* 28418334Speter * The RealTek doesn't use a fragment-based descriptor mechanism. 28518334Speter * Instead, there are only four register sets, each or which represents 28618334Speter * one 'descriptor.' Basically, each TX descriptor is just a contiguous 28718334Speter * packet buffer (32-bit aligned!) and we place the buffer addresses in 28890075Sobrien * the registers so the chip knows where they are. 28918334Speter * 29018334Speter * We can sort of kludge together the same kind of buffer management 29190075Sobrien * used in previous drivers, but we have to do buffer copies almost all 29218334Speter * the time, so it doesn't really buy us much. 29318334Speter * 29418334Speter * For reception, there's just one large buffer where the chip stores 29518334Speter * all received packets. 29618334Speter */ 29718334Speter 29818334Speter#define RL_RX_BUF_SZ RL_RXBUF_64 29990075Sobrien#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 30090075Sobrien#define RL_TX_LIST_CNT 4 30190075Sobrien#define RL_MIN_FRAMELEN 60 30290075Sobrien#define RL_TX_EARLYTHRESH (256 << 11) 30390075Sobrien#define RL_RX_FIFOTHRESH RL_RXFIFO_256BYTES 30418334Speter#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 30518334Speter#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 30690075Sobrien 30790075Sobrien#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 30818334Speter#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 30918334Speter 31018334Speter#define RL_ETHER_ALIGN 2 31118334Speter 31218334Speterstruct rl_chain_data { 31318334Speter u_int16_t cur_rx; 31418334Speter caddr_t rl_rx_buf; 31518334Speter caddr_t rl_rx_buf_ptr; 31618334Speter 31718334Speter struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 31818334Speter u_int8_t last_tx; 31918334Speter u_int8_t cur_tx; 32018334Speter}; 32118334Speter 32290075Sobrien#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 32390075Sobrien#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 32418334Speter#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 32518334Speter#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 32690075Sobrien#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 32718334Speter#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 32850397Sobrien#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 32950397Sobrien 33090075Sobrienstruct rl_type { 33150397Sobrien u_int16_t rl_vid; 33290075Sobrien u_int16_t rl_did; 33318334Speter char *rl_name; 33418334Speter}; 33518334Speter 33690075Sobrienstruct rl_mii_frame { 33790075Sobrien u_int8_t mii_stdelim; 33890075Sobrien u_int8_t mii_opcode; 33950397Sobrien u_int8_t mii_phyaddr; 34090075Sobrien u_int8_t mii_regaddr; 34190075Sobrien u_int8_t mii_turnaround; 34290075Sobrien u_int16_t mii_data; 34390075Sobrien}; 34490075Sobrien 34590075Sobrien/* 34690075Sobrien * MII constants 34790075Sobrien */ 34890075Sobrien#define RL_MII_STARTDELIM 0x01 34990075Sobrien#define RL_MII_READOP 0x02 35090075Sobrien#define RL_MII_WRITEOP 0x01 35190075Sobrien#define RL_MII_TURNAROUND 0x02 35290075Sobrien 35390075Sobrien#define RL_8129 1 35490075Sobrien#define RL_8139 2 35590075Sobrien 35690075Sobrienstruct rl_softc { 35790075Sobrien struct arpcom arpcom; /* interface info */ 35890075Sobrien bus_space_handle_t rl_bhandle; /* bus space handle */ 35990075Sobrien bus_space_tag_t rl_btag; /* bus space tag */ 36090075Sobrien struct resource *rl_res; 36190075Sobrien struct resource *rl_irq; 36290075Sobrien void *rl_intrhand; 36390075Sobrien device_t rl_miibus; 36490075Sobrien u_int8_t rl_unit; /* interface number */ 36590075Sobrien u_int8_t rl_type; 36690075Sobrien u_int8_t rl_stats_no_timeout; 36790075Sobrien struct rl_chain_data rl_cdata; 36890075Sobrien struct callout_handle rl_stat_ch; 36990075Sobrien}; 37090075Sobrien 37190075Sobrien/* 37290075Sobrien * register space access macros 37390075Sobrien */ 37490075Sobrien#define CSR_WRITE_4(sc, reg, val) \ 37590075Sobrien bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 37690075Sobrien#define CSR_WRITE_2(sc, reg, val) \ 37790075Sobrien bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 37890075Sobrien#define CSR_WRITE_1(sc, reg, val) \ 37990075Sobrien bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 38018334Speter 38190075Sobrien#define CSR_READ_4(sc, reg) \ 38290075Sobrien bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 38318334Speter#define CSR_READ_2(sc, reg) \ 38418334Speter bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 38590075Sobrien#define CSR_READ_1(sc, reg) \ 38690075Sobrien bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 38790075Sobrien 38890075Sobrien#define RL_TIMEOUT 1000 38990075Sobrien 39090075Sobrien/* 39118334Speter * General constants that are fun to know. 39218334Speter * 39390075Sobrien * RealTek PCI vendor ID 39418334Speter */ 39590075Sobrien#define RT_VENDORID 0x10EC 39618334Speter 39790075Sobrien/* 39890075Sobrien * RealTek chip device IDs. 39990075Sobrien */ 40090075Sobrien#define RT_DEVICEID_8129 0x8129 40118334Speter#define RT_DEVICEID_8139 0x8139 40290075Sobrien 40390075Sobrien/* 40490075Sobrien * Accton PCI vendor ID 40590075Sobrien */ 40690075Sobrien#define ACCTON_VENDORID 0x1113 40790075Sobrien 40890075Sobrien/* 40918334Speter * Accton MPX 5030/5038 device ID. 41090075Sobrien */ 41190075Sobrien#define ACCTON_DEVICEID_5030 0x1211 41218334Speter 41390075Sobrien/* 41490075Sobrien * Delta Electronics Vendor ID. 41590075Sobrien */ 41618334Speter#define DELTA_VENDORID 0x1500 41790075Sobrien 41890075Sobrien/* 41990075Sobrien * Delta device IDs. 42090075Sobrien */ 42190075Sobrien#define DELTA_DEVICEID_8139 0x1360 42290075Sobrien 42390075Sobrien/* 42490075Sobrien * Addtron vendor ID. 42590075Sobrien */ 42618334Speter#define ADDTRON_VENDORID 0x4033 42790075Sobrien 42890075Sobrien/* 42990075Sobrien * Addtron device IDs. 43090075Sobrien */ 43190075Sobrien#define ADDTRON_DEVICEID_8139 0x1360 43290075Sobrien 43390075Sobrien/* 43490075Sobrien * PCI low memory base and low I/O base register, and 43590075Sobrien * other PCI registers. 43690075Sobrien */ 43790075Sobrien 43890075Sobrien#define RL_PCI_VENDOR_ID 0x00 43990075Sobrien#define RL_PCI_DEVICE_ID 0x02 44090075Sobrien#define RL_PCI_COMMAND 0x04 44190075Sobrien#define RL_PCI_STATUS 0x06 44290075Sobrien#define RL_PCI_CLASSCODE 0x09 44390075Sobrien#define RL_PCI_LATENCY_TIMER 0x0D 44490075Sobrien#define RL_PCI_HEADER_TYPE 0x0E 44590075Sobrien#define RL_PCI_LOIO 0x10 44690075Sobrien#define RL_PCI_LOMEM 0x14 44790075Sobrien#define RL_PCI_BIOSROM 0x30 44890075Sobrien#define RL_PCI_INTLINE 0x3C 44990075Sobrien#define RL_PCI_INTPIN 0x3D 45090075Sobrien#define RL_PCI_MINGNT 0x3E 45190075Sobrien#define RL_PCI_MINLAT 0x0F 45290075Sobrien#define RL_PCI_RESETOPT 0x48 45390075Sobrien#define RL_PCI_EEPROM_DATA 0x4C 45490075Sobrien 45590075Sobrien#define RL_PCI_CAPID 0x50 /* 8 bits */ 45690075Sobrien#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 45790075Sobrien#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 45890075Sobrien#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 45990075Sobrien 46090075Sobrien#define RL_PSTATE_MASK 0x0003 46190075Sobrien#define RL_PSTATE_D0 0x0000 46290075Sobrien#define RL_PSTATE_D1 0x0002 46390075Sobrien#define RL_PSTATE_D2 0x0002 46490075Sobrien#define RL_PSTATE_D3 0x0003 46590075Sobrien#define RL_PME_EN 0x0010 46690075Sobrien#define RL_PME_STATUS 0x8000 46790075Sobrien 46890075Sobrien#ifdef __alpha__ 46990075Sobrien#undef vtophys 47090075Sobrien#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 47190075Sobrien#endif 47290075Sobrien