if_rlreg.h revision 40516
1234353Sdim/* 2234353Sdim * Copyright (c) 1997, 1998 3193323Sed * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4193323Sed * 5193323Sed * Redistribution and use in source and binary forms, with or without 6193323Sed * modification, are permitted provided that the following conditions 7234353Sdim * are met: 8193323Sed * 1. Redistributions of source code must retain the above copyright 9193323Sed * notice, this list of conditions and the following disclaimer. 10193323Sed * 2. Redistributions in binary form must reproduce the above copyright 11193323Sed * notice, this list of conditions and the following disclaimer in the 12193323Sed * documentation and/or other materials provided with the distribution. 13208599Srdivacky * 3. All advertising materials mentioning features or use of this software 14208599Srdivacky * must display the following acknowledgement: 15208599Srdivacky * This product includes software developed by Bill Paul. 16208599Srdivacky * 4. Neither the name of the author nor the names of any co-contributors 17208599Srdivacky * may be used to endorse or promote products derived from this software 18208599Srdivacky * without specific prior written permission. 19208599Srdivacky * 20208599Srdivacky * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21208599Srdivacky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22193323Sed * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23193323Sed * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24193323Sed * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25193323Sed * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26193323Sed * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27193323Sed * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28193323Sed * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29193323Sed * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30193323Sed * THE POSSIBILITY OF SUCH DAMAGE. 31193323Sed * 32193323Sed * $Id: if_rlreg.h,v 1.12 1998/10/07 22:52:34 wpaul Exp $ 33193323Sed */ 34193323Sed 35193323Sed/* 36193323Sed * RealTek 8129/8139 register offsets 37208599Srdivacky */ 38193323Sed#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39193323Sed#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40193323Sed#define RL_IDR2 0x0002 41193323Sed#define RL_IDR3 0x0003 42193323Sed#define RL_IDR4 0x0004 43193323Sed#define RL_IDR5 0x0005 44193323Sed /* 0006-0007 reserved */ 45193323Sed#define RL_MAR0 0x0008 /* Multicast hash table */ 46193323Sed#define RL_MAR1 0x0009 47193323Sed#define RL_MAR2 0x000A 48193323Sed#define RL_MAR3 0x000B 49193323Sed#define RL_MAR4 0x000C 50193323Sed#define RL_MAR5 0x000D 51193323Sed#define RL_MAR6 0x000E 52193323Sed#define RL_MAR7 0x000F 53193323Sed 54193323Sed#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55193323Sed#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56195340Sed#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57193323Sed#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 58195340Sed 59193323Sed#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60193323Sed#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61193323Sed#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62193323Sed#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 63193323Sed 64193323Sed#define RL_RXADDR 0x0030 /* RX ring start address */ 65193323Sed#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66193323Sed#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67193323Sed#define RL_COMMAND 0x0037 /* command register */ 68223017Sdim#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69223017Sdim#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70223017Sdim#define RL_IMR 0x003C /* interrupt mask register */ 71223017Sdim#define RL_ISR 0x003E /* interrupt status register */ 72223017Sdim#define RL_TXCFG 0x0040 /* transmit config */ 73223017Sdim#define RL_RXCFG 0x0044 /* receive config */ 74223017Sdim#define RL_TIMERCNT 0x0048 /* timer count register */ 75223017Sdim#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76223017Sdim#define RL_EECMD 0x0050 /* EEPROM command register */ 77223017Sdim#define RL_CFG0 0x0051 /* config register #0 */ 78223017Sdim#define RL_CFG1 0x0052 /* config register #1 */ 79223017Sdim /* 0053-0057 reserved */ 80223017Sdim#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 81223017Sdim /* 0059-005A reserved */ 82223017Sdim#define RL_MII 0x005A /* 8129 chip only */ 83223017Sdim#define RL_HALTCLK 0x005B 84223017Sdim#define RL_MULTIINTR 0x005C /* multiple interrupt */ 85223017Sdim#define RL_PCIREV 0x005E /* PCI revision value */ 86223017Sdim /* 005F reserved */ 87223017Sdim#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 88223017Sdim 89223017Sdim/* Direct PHY access registers only available on 8139 */ 90223017Sdim#define RL_BMCR 0x0062 /* PHY basic mode control */ 91223017Sdim#define RL_BMSR 0x0064 /* PHY basic mode status */ 92223017Sdim#define RL_ANAR 0x0066 /* PHY autoneg advert */ 93223017Sdim#define RL_LPAR 0x0068 /* PHY link partner ability */ 94223017Sdim#define RL_ANER 0x006A /* PHY autoneg expansion */ 95223017Sdim 96223017Sdim#define RL_DISCCNT 0x006C /* disconnect counter */ 97223017Sdim#define RL_FALSECAR 0x006E /* false carrier counter */ 98223017Sdim#define RL_NWAYTST 0x0070 /* NWAY test register */ 99223017Sdim#define RL_RX_ER 0x0072 /* RX_ER counter */ 100193323Sed#define RL_CSCFG 0x0074 /* CS configuration register */ 101193323Sed 102223017Sdim 103223017Sdim/* 104223017Sdim * TX config register bits 105223017Sdim */ 106223017Sdim#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 107223017Sdim#define RL_TXCFG_MXDMA0 0x00000100 /* max DMA burst size */ 108223017Sdim#define RL_TXCFG_MXDMA1 0x00000200 109223017Sdim#define RL_TXCFG_MXDMA2 0x00000400 110223017Sdim#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 111223017Sdim#define RL_TXCFG_LOOPBKTST0 0x00020000 /* loopback test */ 112223017Sdim#define RL_TXCFG_LOOPBKTST1 0x00040000 /* loopback test */ 113223017Sdim#define RL_TXCFG_IFG0 0x01000000 /* interframe gap */ 114223017Sdim#define RL_TXCFG_IFG1 0x02000000 /* interframe gap */ 115223017Sdim 116223017Sdim/* 117223017Sdim * Transmit descriptor status register bits. 118223017Sdim */ 119223017Sdim#define RL_TXSTAT_LENMASK 0x00001FFF 120223017Sdim#define RL_TXSTAT_OWN 0x00002000 121223017Sdim#define RL_TXSTAT_TX_UNDERRUN 0x00004000 122223017Sdim#define RL_TXSTAT_TX_OK 0x00008000 123223017Sdim#define RL_TXSTAT_EARLY_THRESH 0x003F0000 124223017Sdim#define RL_TXSTAT_COLLCNT 0x0F000000 125223017Sdim#define RL_TXSTAT_CARR_HBEAT 0x10000000 126223017Sdim#define RL_TXSTAT_OUTOFWIN 0x20000000 127223017Sdim#define RL_TXSTAT_TXABRT 0x40000000 128223017Sdim#define RL_TXSTAT_CARRLOSS 0x80000000 129223017Sdim 130223017Sdim/* 131223017Sdim * Interrupt status register bits. 132223017Sdim */ 133223017Sdim#define RL_ISR_RX_OK 0x0001 134193323Sed#define RL_ISR_RX_ERR 0x0002 135193323Sed#define RL_ISR_TX_OK 0x0004 136223017Sdim#define RL_ISR_TX_ERR 0x0008 137223017Sdim#define RL_ISR_RX_OVERRUN 0x0010 138223017Sdim#define RL_ISR_PKT_UNDERRUN 0x0020 139223017Sdim#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 140223017Sdim#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 141223017Sdim#define RL_ISR_SYSTEM_ERR 0x8000 142223017Sdim 143223017Sdim#define RL_INTRS \ 144223017Sdim (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 145223017Sdim RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 146223017Sdim RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 147223017Sdim 148223017Sdim/* 149223017Sdim * Media status register. (8139 only) 150223017Sdim */ 151223017Sdim#define RL_MEDIASTAT_RXPAUSE 0x01 152223017Sdim#define RL_MEDIASTAT_TXPAUSE 0x02 153223017Sdim#define RL_MEDIASTAT_LINK 0x04 154223017Sdim#define RL_MEDIASTAT_SPEED10 0x08 155223017Sdim#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 156223017Sdim#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 157223017Sdim 158223017Sdim/* 159223017Sdim * Receive config register. 160223017Sdim */ 161223017Sdim#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 162223017Sdim#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 163223017Sdim#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 164223017Sdim#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 165223017Sdim#define RL_RXCFG_RX_RUNT 0x00000010 166223017Sdim#define RL_RXCFG_RX_ERRPKT 0x00000020 167223017Sdim#define RL_RXCFG_WRAP 0x00000080 168193323Sed#define RL_RXCFG_MAXDMA (0x00000100|0x00000200|0x00000400) 169193323Sed#define RL_RXCFG_BUFSZ (0x00000800|0x00001000) 170223017Sdim#define RL_RXCFG_FIFOTHRESH (0x00002000|0x00004000|0x00008000) 171223017Sdim#define RL_RXCFG_EARLYTHRESH (0x01000000|0x02000000|0x04000000) 172223017Sdim 173223017Sdim#define RL_RXBUF_8 0x00000000 174223017Sdim#define RL_RXBUF_16 0x00000800 175223017Sdim#define RL_RXBUF_32 0x00001000 176223017Sdim#define RL_RXBUF_64 (0x00001000|0x00000800) 177223017Sdim 178223017Sdim/* 179223017Sdim * Bits in RX status header (included with RX'ed packet 180223017Sdim * in ring buffer). 181223017Sdim */ 182223017Sdim#define RL_RXSTAT_RXOK 0x00000001 183223017Sdim#define RL_RXSTAT_ALIGNERR 0x00000002 184223017Sdim#define RL_RXSTAT_CRCERR 0x00000004 185223017Sdim#define RL_RXSTAT_GIANT 0x00000008 186223017Sdim#define RL_RXSTAT_RUNT 0x00000010 187223017Sdim#define RL_RXSTAT_BADSYM 0x00000020 188223017Sdim#define RL_RXSTAT_BROAD 0x00002000 189223017Sdim#define RL_RXSTAT_INDIV 0x00004000 190223017Sdim#define RL_RXSTAT_MULTI 0x00008000 191223017Sdim#define RL_RXSTAT_LENMASK 0xFFFF0000 192223017Sdim 193223017Sdim#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 194223017Sdim/* 195223017Sdim * Command register. 196223017Sdim */ 197223017Sdim#define RL_CMD_EMPTY_RXBUF 0x0001 198223017Sdim#define RL_CMD_TX_ENB 0x0004 199223017Sdim#define RL_CMD_RX_ENB 0x0008 200223017Sdim#define RL_CMD_RESET 0x0010 201223017Sdim 202193323Sed/* 203193323Sed * EEPROM control register 204223017Sdim */ 205223017Sdim#define RL_EE_DATAOUT 0x01 /* Data out */ 206223017Sdim#define RL_EE_DATAIN 0x02 /* Data in */ 207223017Sdim#define RL_EE_CLK 0x04 /* clock */ 208223017Sdim#define RL_EE_SEL 0x08 /* chip select */ 209223017Sdim#define RL_EE_MODE (0x40|0x80) 210223017Sdim 211223017Sdim#define RL_EEMODE_OFF 0x00 212223017Sdim#define RL_EEMODE_AUTOLOAD 0x40 213223017Sdim#define RL_EEMODE_PROGRAM 0x80 214223017Sdim#define RL_EEMODE_WRITECFG (0x80|0x40) 215223017Sdim 216223017Sdim/* 9346 EEPROM commands */ 217223017Sdim#define RL_EECMD_WRITE 0x140 218223017Sdim#define RL_EECMD_READ 0x180 219223017Sdim#define RL_EECMD_ERASE 0x1c0 220223017Sdim 221223017Sdim#define RL_EE_ID 0x00 222223017Sdim#define RL_EE_PCI_VID 0x01 223223017Sdim#define RL_EE_PCI_DID 0x02 224223017Sdim/* Location of station address inside EEPROM */ 225223017Sdim#define RL_EE_EADDR 0x07 226223017Sdim 227223017Sdim/* 228223017Sdim * MII register (8129 only) 229223017Sdim */ 230223017Sdim#define RL_MII_CLK 0x01 231223017Sdim#define RL_MII_DATAIN 0x02 232223017Sdim#define RL_MII_DATAOUT 0x04 233223017Sdim#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 234223017Sdim 235223017Sdim/* 236193323Sed * Config 0 register 237195340Sed */ 238208599Srdivacky#define RL_CFG0_ROM0 0x01 239223017Sdim#define RL_CFG0_ROM1 0x02 240223017Sdim#define RL_CFG0_ROM2 0x04 241223017Sdim#define RL_CFG0_PL0 0x08 242223017Sdim#define RL_CFG0_PL1 0x10 243223017Sdim#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 244223017Sdim#define RL_CFG0_PCS 0x40 245223017Sdim#define RL_CFG0_SCR 0x80 246223017Sdim 247208599Srdivacky/* 248195340Sed * Config 1 register 249193323Sed */ 250223017Sdim#define RL_CFG1_PWRDWN 0x01 251193323Sed#define RL_CFG1_SLEEP 0x02 252223017Sdim#define RL_CFG1_IOMAP 0x04 253193323Sed#define RL_CFG1_MEMMAP 0x08 254193323Sed#define RL_CFG1_RSVD 0x10 255223017Sdim#define RL_CFG1_DRVLOAD 0x20 256223017Sdim#define RL_CFG1_LED0 0x40 257193323Sed#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 258193323Sed#define RL_CFG1_LED1 0x80 259223017Sdim 260193323Sed/* 261198090Srdivacky * The RealTek doesn't use a fragment-based descriptor mechanism. 262198090Srdivacky * Instead, there are only four register sets, each or which represents 263198090Srdivacky * one 'descriptor.' Basically, each TX descriptor is just a contiguous 264223017Sdim * packet buffer (32-bit aligned!) and we place the buffer addresses in 265198090Srdivacky * the registers so the chip knows where they are. 266193323Sed * 267193323Sed * We can sort of kludge together the same kind of buffer management 268193323Sed * used in previous drivers, but we have to do buffer copies almost all 269193323Sed * the time, so it doesn't really buy us much. 270193323Sed * 271193323Sed * For reception, there's just one large buffer where the chip stores 272193323Sed * all received packets. 273193323Sed */ 274223017Sdim 275193323Sed#define RL_RX_BUF_SZ RL_RXBUF_64 276193323Sed#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 277193323Sed#define RL_TX_LIST_CNT 4 278193323Sed#define RL_MIN_FRAMELEN 60 279224145Sdim#define RL_TX_EARLYTHRESH 0x80000 /* 256 << 11 */ 280224145Sdim#define RL_RX_FIFOTHRESH 0x8000 /* 4 << 13 */ 281224145Sdim#define RL_RX_MAXDMA 0x00000400 282223017Sdim 283224145Sdim#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_BUF_SZ) 284224145Sdim 285224145Sdimstruct rl_chain { 286193323Sed char rl_desc; /* descriptor register idx */ 287195340Sed struct mbuf *rl_mbuf; 288195340Sed struct rl_chain *rl_next; 289195340Sed}; 290195340Sed 291195340Sedstruct rl_chain_data { 292195340Sed u_int16_t cur_rx; 293195340Sed caddr_t rl_rx_buf; 294224145Sdim struct rl_chain rl_tx_chain[RL_TX_LIST_CNT]; 295224145Sdim 296224145Sdim int rl_tx_cnt; 297193323Sed struct rl_chain *rl_tx_cur; 298193323Sed struct rl_chain *rl_tx_free; 299224145Sdim}; 300224145Sdim 301224145Sdimstruct rl_type { 302193323Sed u_int16_t rl_vid; 303193323Sed u_int16_t rl_did; 304224145Sdim char *rl_name; 305224145Sdim}; 306224145Sdim 307224145Sdimstruct rl_mii_frame { 308224145Sdim u_int8_t mii_stdelim; 309224145Sdim u_int8_t mii_opcode; 310224145Sdim u_int8_t mii_phyaddr; 311224145Sdim u_int8_t mii_regaddr; 312193323Sed u_int8_t mii_turnaround; 313193323Sed u_int16_t mii_data; 314193323Sed}; 315193323Sed 316224145Sdim/* 317224145Sdim * MII constants 318208599Srdivacky */ 319195340Sed#define RL_MII_STARTDELIM 0x01 320193323Sed#define RL_MII_READOP 0x02 321224145Sdim#define RL_MII_WRITEOP 0x01 322224145Sdim#define RL_MII_TURNAROUND 0x02 323224145Sdim 324224145Sdim#define RL_FLAG_FORCEDELAY 1 325198090Srdivacky#define RL_FLAG_SCHEDDELAY 2 326198090Srdivacky#define RL_FLAG_DELAYTIMEO 3 327 328#define RL_8129 1 329#define RL_8139 2 330 331struct rl_softc { 332 struct arpcom arpcom; /* interface info */ 333 struct ifmedia ifmedia; /* media info */ 334 u_int32_t iobase; /* pointer to PIO space */ 335#ifndef RL_USEIOSPACE 336 volatile caddr_t csr; /* pointer to register map */ 337#endif 338 struct rl_type *rl_pinfo; /* phy info */ 339 u_int8_t rl_unit; /* interface number */ 340 u_int8_t rl_type; 341 u_int8_t rl_phy_addr; /* PHY address */ 342 u_int8_t rl_tx_pend; /* TX pending */ 343 u_int8_t rl_want_auto; 344 u_int8_t rl_autoneg; 345 u_int8_t rl_stats_no_timeout; 346 struct rl_chain_data rl_cdata; 347}; 348 349/* 350 * register space access macros 351 */ 352#ifdef RL_USEIOSPACE 353#define CSR_WRITE_4(sc, reg, val) \ 354 outl(sc->iobase + (u_int32_t)(reg), val) 355#define CSR_WRITE_2(sc, reg, val) \ 356 outw(sc->iobase + (u_int32_t)(reg), val) 357#define CSR_WRITE_1(sc, reg, val) \ 358 outb(sc->iobase + (u_int32_t)(reg), val) 359 360#define CSR_READ_4(sc, reg) \ 361 inl(sc->iobase + (u_int32_t)(reg)) 362#define CSR_READ_2(sc, reg) \ 363 inw(sc->iobase + (u_int32_t)(reg)) 364#define CSR_READ_1(sc, reg) \ 365 inb(sc->iobase + (u_int32_t)(reg)) 366#else 367#define CSR_WRITE_4(sc, reg, val) \ 368 ((*(u_int32_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int32_t)(val)) 369#define CSR_WRITE_2(sc, reg, val) \ 370 ((*(u_int16_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int16_t)(val)) 371#define CSR_WRITE_1(sc, reg, val) \ 372 ((*(u_int8_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int8_t)(val)) 373 374#define CSR_READ_4(sc, reg) \ 375 (*(u_int32_t *)((sc)->csr + (u_int32_t)(reg))) 376#define CSR_READ_2(sc, reg) \ 377 (*(u_int16_t *)((sc)->csr + (u_int32_t)(reg))) 378#define CSR_READ_1(sc, reg) \ 379 (*(u_int8_t *)((sc)->csr + (u_int32_t)(reg))) 380#endif 381 382#define RL_TIMEOUT 1000 383 384/* 385 * General constants that are fun to know. 386 * 387 * RealTek PCI vendor ID 388 */ 389#define RT_VENDORID 0x10EC 390#define RT_VENDORID_ALT 0x1211 391 392/* 393 * RealTek chip device IDs. 394 */ 395#define RT_DEVICEID_8129 0x8129 396#define RT_DEVICEID_8139 0x8139 397#define RT_DEVICEID_8139_ALT 0x1211 398 399/* 400 * Texas Instruments PHY identifiers 401 */ 402#define TI_PHY_VENDORID 0x4000 403#define TI_PHY_10BT 0x501F 404#define TI_PHY_100VGPMI 0x502F 405 406/* 407 * These ID values are for the NS DP83840A 10/100 PHY 408 */ 409#define NS_PHY_VENDORID 0x2000 410#define NS_PHY_83840A 0x5C0F 411 412/* 413 * Level 1 10/100 PHY 414 */ 415#define LEVEL1_PHY_VENDORID 0x7810 416#define LEVEL1_PHY_LXT970 0x000F 417 418/* 419 * Intel 82555 10/100 PHY 420 */ 421#define INTEL_PHY_VENDORID 0x0A28 422#define INTEL_PHY_82555 0x015F 423 424/* 425 * SEEQ 80220 10/100 PHY 426 */ 427#define SEEQ_PHY_VENDORID 0x0016 428#define SEEQ_PHY_80220 0xF83F 429 430 431/* 432 * PCI low memory base and low I/O base register, and 433 * other PCI registers. Note: some are only available on 434 * the 3c905B, in particular those that related to power management. 435 */ 436 437#define RL_PCI_VENDOR_ID 0x00 438#define RL_PCI_DEVICE_ID 0x02 439#define RL_PCI_COMMAND 0x04 440#define RL_PCI_STATUS 0x06 441#define RL_PCI_CLASSCODE 0x09 442#define RL_PCI_LATENCY_TIMER 0x0D 443#define RL_PCI_HEADER_TYPE 0x0E 444#define RL_PCI_LOIO 0x10 445#define RL_PCI_LOMEM 0x14 446#define RL_PCI_BIOSROM 0x30 447#define RL_PCI_INTLINE 0x3C 448#define RL_PCI_INTPIN 0x3D 449#define RL_PCI_MINGNT 0x3E 450#define RL_PCI_MINLAT 0x0F 451#define RL_PCI_RESETOPT 0x48 452#define RL_PCI_EEPROM_DATA 0x4C 453 454#define RL_PCI_CAPID 0xDC /* 8 bits */ 455#define RL_PCI_NEXTPTR 0xDD /* 8 bits */ 456#define RL_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 457#define RL_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 458 459#define RL_PSTATE_MASK 0x0003 460#define RL_PSTATE_D0 0x0000 461#define RL_PSTATE_D1 0x0002 462#define RL_PSTATE_D2 0x0002 463#define RL_PSTATE_D3 0x0003 464#define RL_PME_EN 0x0010 465#define RL_PME_STATUS 0x8000 466 467#define PHY_UNKNOWN 6 468 469#define RL_PHYADDR_MIN 0x00 470#define RL_PHYADDR_MAX 0x1F 471 472#define PHY_BMCR 0x00 473#define PHY_BMSR 0x01 474#define PHY_VENID 0x02 475#define PHY_DEVID 0x03 476#define PHY_ANAR 0x04 477#define PHY_LPAR 0x05 478#define PHY_ANEXP 0x06 479 480#define PHY_ANAR_NEXTPAGE 0x8000 481#define PHY_ANAR_RSVD0 0x4000 482#define PHY_ANAR_TLRFLT 0x2000 483#define PHY_ANAR_RSVD1 0x1000 484#define PHY_ANAR_RSVD2 0x0800 485#define PHY_ANAR_RSVD3 0x0400 486#define PHY_ANAR_100BT4 0x0200 487#define PHY_ANAR_100BTXFULL 0x0100 488#define PHY_ANAR_100BTXHALF 0x0080 489#define PHY_ANAR_10BTFULL 0x0040 490#define PHY_ANAR_10BTHALF 0x0020 491#define PHY_ANAR_PROTO4 0x0010 492#define PHY_ANAR_PROTO3 0x0008 493#define PHY_ANAR_PROTO2 0x0004 494#define PHY_ANAR_PROTO1 0x0002 495#define PHY_ANAR_PROTO0 0x0001 496 497/* 498 * These are the register definitions for the PHY (physical layer 499 * interface chip). 500 */ 501/* 502 * PHY BMCR Basic Mode Control Register 503 */ 504#define PHY_BMCR_RESET 0x8000 505#define PHY_BMCR_LOOPBK 0x4000 506#define PHY_BMCR_SPEEDSEL 0x2000 507#define PHY_BMCR_AUTONEGENBL 0x1000 508#define PHY_BMCR_RSVD0 0x0800 /* write as zero */ 509#define PHY_BMCR_ISOLATE 0x0400 510#define PHY_BMCR_AUTONEGRSTR 0x0200 511#define PHY_BMCR_DUPLEX 0x0100 512#define PHY_BMCR_COLLTEST 0x0080 513#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */ 514#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */ 515#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */ 516#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */ 517#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */ 518#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */ 519#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */ 520/* 521 * RESET: 1 == software reset, 0 == normal operation 522 * Resets status and control registers to default values. 523 * Relatches all hardware config values. 524 * 525 * LOOPBK: 1 == loopback operation enabled, 0 == normal operation 526 * 527 * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s 528 * Link speed is selected byt his bit or if auto-negotiation if bit 529 * 12 (AUTONEGENBL) is set (in which case the value of this register 530 * is ignored). 531 * 532 * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled 533 * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13 534 * determine speed and mode. Should be cleared and then set if PHY configured 535 * for no autoneg on startup. 536 * 537 * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation 538 * 539 * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation 540 * 541 * DUPLEX: 1 == full duplex mode, 0 == half duplex mode 542 * 543 * COLLTEST: 1 == collision test enabled, 0 == normal operation 544 */ 545 546/* 547 * PHY, BMSR Basic Mode Status Register 548 */ 549#define PHY_BMSR_100BT4 0x8000 550#define PHY_BMSR_100BTXFULL 0x4000 551#define PHY_BMSR_100BTXHALF 0x2000 552#define PHY_BMSR_10BTFULL 0x1000 553#define PHY_BMSR_10BTHALF 0x0800 554#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */ 555#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */ 556#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */ 557#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ 558#define PHY_BMSR_MFPRESUP 0x0040 559#define PHY_BMSR_AUTONEGCOMP 0x0020 560#define PHY_BMSR_REMFAULT 0x0010 561#define PHY_BMSR_CANAUTONEG 0x0008 562#define PHY_BMSR_LINKSTAT 0x0004 563#define PHY_BMSR_JABBER 0x0002 564#define PHY_BMSR_EXTENDED 0x0001 565