if_rlreg.h revision 263957
143014Swollman/*- 22742Swollman * Copyright (c) 1997, 1998-2003 32742Swollman * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 42742Swollman * 52742Swollman * Redistribution and use in source and binary forms, with or without 62742Swollman * modification, are permitted provided that the following conditions 72742Swollman * are met: 82742Swollman * 1. Redistributions of source code must retain the above copyright 92742Swollman * notice, this list of conditions and the following disclaimer. 102742Swollman * 2. Redistributions in binary form must reproduce the above copyright 112742Swollman * notice, this list of conditions and the following disclaimer in the 122742Swollman * documentation and/or other materials provided with the distribution. 132742Swollman * 3. All advertising materials mentioning features or use of this software 142742Swollman * must display the following acknowledgement: 152742Swollman * This product includes software developed by Bill Paul. 162742Swollman * 4. Neither the name of the author nor the names of any co-contributors 172742Swollman * may be used to endorse or promote products derived from this software 182742Swollman * without specific prior written permission. 192742Swollman * 202742Swollman * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 212742Swollman * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 222742Swollman * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 239908Swollman * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 242742Swollman * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2530711Swollman * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 262742Swollman * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 272742Swollman * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 289908Swollman * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 292742Swollman * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 302742Swollman * THE POSSIBILITY OF SUCH DAMAGE. 3114343Swollman * 3214343Swollman * $FreeBSD: head/sys/pci/if_rlreg.h 263957 2014-03-31 01:54:59Z yongari $ 3314343Swollman */ 3414343Swollman 3514343Swollman/* 3614343Swollman * RealTek 8129/8139 register offsets 372742Swollman */ 389908Swollman#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 3920094Swollman#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 4020094Swollman#define RL_IDR2 0x0002 4120094Swollman#define RL_IDR3 0x0003 4220094Swollman#define RL_IDR4 0x0004 4320094Swollman#define RL_IDR5 0x0005 4420094Swollman /* 0006-0007 reserved */ 4520094Swollman#define RL_MAR0 0x0008 /* Multicast hash table */ 4620094Swollman#define RL_MAR1 0x0009 4720094Swollman#define RL_MAR2 0x000A 4820094Swollman#define RL_MAR3 0x000B 4920094Swollman#define RL_MAR4 0x000C 5020094Swollman#define RL_MAR5 0x000D 5120094Swollman#define RL_MAR6 0x000E 5221217Swollman#define RL_MAR7 0x000F 5321217Swollman 5420094Swollman#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 5520094Swollman#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 562742Swollman#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 572742Swollman#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 5814343Swollman 5914343Swollman#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 6021217Swollman#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 6120094Swollman#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 6220094Swollman#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 6320094Swollman 6420094Swollman#define RL_RXADDR 0x0030 /* RX ring start address */ 6520094Swollman#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 662742Swollman#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 679908Swollman#define RL_COMMAND 0x0037 /* command register */ 682742Swollman#define RL_CURRXADDR 0x0038 /* current address of packet read */ 6914343Swollman#define RL_CURRXBUF 0x003A /* current RX buffer address */ 7014343Swollman#define RL_IMR 0x003C /* interrupt mask register */ 7114343Swollman#define RL_ISR 0x003E /* interrupt status register */ 7214343Swollman#define RL_TXCFG 0x0040 /* transmit config */ 7314343Swollman#define RL_RXCFG 0x0044 /* receive config */ 7414343Swollman#define RL_TIMERCNT 0x0048 /* timer count register */ 7514343Swollman#define RL_MISSEDPKT 0x004C /* missed packet counter */ 7614343Swollman#define RL_EECMD 0x0050 /* EEPROM command register */ 7714343Swollman 782742Swollman/* RTL8139/RTL8139C+ only */ 792742Swollman#define RL_8139_CFG0 0x0051 /* config register #0 */ 802742Swollman#define RL_8139_CFG1 0x0052 /* config register #1 */ 812742Swollman#define RL_8139_CFG3 0x0059 /* config register #3 */ 8214343Swollman#define RL_8139_CFG4 0x005A /* config register #4 */ 832742Swollman#define RL_8139_CFG5 0x00D8 /* config register #5 */ 842742Swollman 859908Swollman#define RL_CFG0 0x0051 /* config register #0 */ 862742Swollman#define RL_CFG1 0x0052 /* config register #1 */ 8714343Swollman#define RL_CFG2 0x0053 /* config register #2 */ 8814343Swollman#define RL_CFG3 0x0054 /* config register #3 */ 8914343Swollman#define RL_CFG4 0x0055 /* config register #4 */ 9014343Swollman#define RL_CFG5 0x0056 /* config register #5 */ 9114343Swollman /* 0057 reserved */ 9214343Swollman#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 9314343Swollman /* 0059-005A reserved */ 9414343Swollman#define RL_MII 0x005A /* 8129 chip only */ 9514343Swollman#define RL_HALTCLK 0x005B 9614343Swollman#define RL_MULTIINTR 0x005C /* multiple interrupt */ 9714343Swollman#define RL_PCIREV 0x005E /* PCI revision value */ 9814343Swollman /* 005F reserved */ 9914343Swollman#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 1002742Swollman 1012742Swollman/* Direct PHY access registers only available on 8139 */ 1022742Swollman#define RL_BMCR 0x0062 /* PHY basic mode control */ 10314343Swollman#define RL_BMSR 0x0064 /* PHY basic mode status */ 1042742Swollman#define RL_ANAR 0x0066 /* PHY autoneg advert */ 1052742Swollman#define RL_LPAR 0x0068 /* PHY link partner ability */ 1069908Swollman#define RL_ANER 0x006A /* PHY autoneg expansion */ 1072742Swollman 10814343Swollman#define RL_DISCCNT 0x006C /* disconnect counter */ 10914343Swollman#define RL_FALSECAR 0x006E /* false carrier counter */ 11014343Swollman#define RL_NWAYTST 0x0070 /* NWAY test register */ 11114343Swollman#define RL_RX_ER 0x0072 /* RX_ER counter */ 11214343Swollman#define RL_CSCFG 0x0074 /* CS configuration register */ 11314343Swollman 11414343Swollman/* 11514343Swollman * When operating in special C+ mode, some of the registers in an 1162742Swollman * 8139C+ chip have different definitions. These are also used for 1172742Swollman * the 8169 gigE chip. 1182742Swollman */ 11914343Swollman#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 1202742Swollman#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 1212742Swollman#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 1229908Swollman#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 1232742Swollman#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 12414343Swollman#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 12514343Swollman#define RL_CFG2 0x0053 12614343Swollman#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 12714343Swollman#define RL_TXSTART 0x00D9 /* 8 bits */ 12814343Swollman#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 12914343Swollman#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 13014343Swollman#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 13114343Swollman#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 13214343Swollman 13314343Swollman/* 1342742Swollman * Registers specific to the 8169 gigE chip 1352742Swollman */ 1362742Swollman#define RL_GTXSTART 0x0038 /* 8 bits */ 13714343Swollman#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 1382742Swollman#define RL_PHYAR 0x0060 1392742Swollman#define RL_TBICSR 0x0064 1402742Swollman#define RL_TBI_ANAR 0x0068 1412742Swollman#define RL_TBI_LPAR 0x006A 1422742Swollman#define RL_GMEDIASTAT 0x006C /* 8 bits */ 14314343Swollman#define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */ 1442742Swollman#define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */ 1458029Swollman#define RL_PMCH 0x006F /* 8 bits */ 14614343Swollman#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 14714343Swollman#define RL_INTRMOD 0x00E2 /* 16 bits */ 14814343Swollman#define RL_MISC 0x00F0 14914343Swollman 15014343Swollman/* 15114343Swollman * TX config register bits 15214343Swollman */ 15314343Swollman#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 15414343Swollman#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 15514343Swollman#define RL_TXCFG_QUEUE_EMPTY 0x00000800 /* 8168E-VL or higher */ 1562742Swollman#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 1572742Swollman#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 15814343Swollman#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 1598029Swollman#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 16014343Swollman#define RL_TXCFG_HWREV 0x7CC00000 1612742Swollman 1622742Swollman#define RL_LOOPTEST_OFF 0x00000000 16314343Swollman#define RL_LOOPTEST_ON 0x00020000 1642742Swollman#define RL_LOOPTEST_ON_CPLUS 0x00060000 1652742Swollman 16614343Swollman/* Known revision codes. */ 16714343Swollman#define RL_HWREV_8169 0x00000000 16814343Swollman#define RL_HWREV_8169S 0x00800000 16914343Swollman#define RL_HWREV_8110S 0x04000000 17030711Swollman#define RL_HWREV_8169_8110SB 0x10000000 17130711Swollman#define RL_HWREV_8169_8110SC 0x18000000 17230711Swollman#define RL_HWREV_8401E 0x24000000 1732742Swollman#define RL_HWREV_8102EL 0x24800000 17430711Swollman#define RL_HWREV_8102EL_SPIN1 0x24C00000 17530711Swollman#define RL_HWREV_8168D 0x28000000 17630711Swollman#define RL_HWREV_8168DP 0x28800000 1772742Swollman#define RL_HWREV_8168E 0x2C000000 17843014Swollman#define RL_HWREV_8168E_VL 0x2C800000 17943014Swollman#define RL_HWREV_8168B_SPIN1 0x30000000 18043014Swollman#define RL_HWREV_8100E 0x30800000 18143014Swollman#define RL_HWREV_8101E 0x34000000 1822742Swollman#define RL_HWREV_8102E 0x34800000 1832742Swollman#define RL_HWREV_8103E 0x34C00000 18443014Swollman#define RL_HWREV_8168B_SPIN2 0x38000000 1852742Swollman#define RL_HWREV_8168B_SPIN3 0x38400000 18619878Swollman#define RL_HWREV_8168C 0x3C000000 18743014Swollman#define RL_HWREV_8168C_SPIN2 0x3C400000 18843014Swollman#define RL_HWREV_8168CP 0x3C800000 1892742Swollman#define RL_HWREV_8105E 0x40800000 1902742Swollman#define RL_HWREV_8105E_SPIN1 0x40C00000 19119878Swollman#define RL_HWREV_8402 0x44000000 19219878Swollman#define RL_HWREV_8106E 0x44800000 1932742Swollman#define RL_HWREV_8168F 0x48000000 1942742Swollman#define RL_HWREV_8411 0x48800000 1952742Swollman#define RL_HWREV_8168G 0x4C000000 1962742Swollman#define RL_HWREV_8168EP 0x50000000 19719878Swollman#define RL_HWREV_8168GU 0x50800000 1982742Swollman#define RL_HWREV_8411B 0x5C800000 1992742Swollman#define RL_HWREV_8139 0x60000000 2002742Swollman#define RL_HWREV_8139A 0x70000000 2012742Swollman#define RL_HWREV_8139AG 0x70800000 20219878Swollman#define RL_HWREV_8139B 0x78000000 2032742Swollman#define RL_HWREV_8130 0x7C000000 2042742Swollman#define RL_HWREV_8139C 0x74000000 2052742Swollman#define RL_HWREV_8139D 0x74400000 2062742Swollman#define RL_HWREV_8139CPLUS 0x74800000 20719878Swollman#define RL_HWREV_8101 0x74C00000 2082742Swollman#define RL_HWREV_8100 0x78800000 20919878Swollman#define RL_HWREV_8169_8110SBL 0x7CC00000 2102742Swollman#define RL_HWREV_8169_8110SCE 0x98000000 21119878Swollman 21243014Swollman#define RL_TXDMA_16BYTES 0x00000000 21343014Swollman#define RL_TXDMA_32BYTES 0x00000100 2142742Swollman#define RL_TXDMA_64BYTES 0x00000200 2152742Swollman#define RL_TXDMA_128BYTES 0x00000300 2162742Swollman#define RL_TXDMA_256BYTES 0x00000400 2172742Swollman#define RL_TXDMA_512BYTES 0x00000500 2182742Swollman#define RL_TXDMA_1024BYTES 0x00000600 2192742Swollman#define RL_TXDMA_2048BYTES 0x00000700 2202742Swollman 2212742Swollman/* 2222742Swollman * Transmit descriptor status register bits. 22319878Swollman */ 2242742Swollman#define RL_TXSTAT_LENMASK 0x00001FFF 22519878Swollman#define RL_TXSTAT_OWN 0x00002000 22619878Swollman#define RL_TXSTAT_TX_UNDERRUN 0x00004000 22719878Swollman#define RL_TXSTAT_TX_OK 0x00008000 2282742Swollman#define RL_TXSTAT_EARLY_THRESH 0x003F0000 22919878Swollman#define RL_TXSTAT_COLLCNT 0x0F000000 23019878Swollman#define RL_TXSTAT_CARR_HBEAT 0x10000000 23119878Swollman#define RL_TXSTAT_OUTOFWIN 0x20000000 2322742Swollman#define RL_TXSTAT_TXABRT 0x40000000 23314343Swollman#define RL_TXSTAT_CARRLOSS 0x80000000 23414343Swollman 23514343Swollman/* 23619878Swollman * Interrupt status register bits. 23719878Swollman */ 23814343Swollman#define RL_ISR_RX_OK 0x0001 23914343Swollman#define RL_ISR_RX_ERR 0x0002 24014343Swollman#define RL_ISR_TX_OK 0x0004 24114343Swollman#define RL_ISR_TX_ERR 0x0008 24219878Swollman#define RL_ISR_RX_OVERRUN 0x0010 24319878Swollman#define RL_ISR_PKT_UNDERRUN 0x0020 24414343Swollman#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 24519878Swollman#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 24619878Swollman#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 24719878Swollman#define RL_ISR_SWI 0x0100 /* C+ only */ 24814343Swollman#define RL_ISR_CABLE_LEN_CHGD 0x2000 24914343Swollman#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 25014343Swollman#define RL_ISR_TIMEOUT_EXPIRED 0x4000 25114343Swollman#define RL_ISR_SYSTEM_ERR 0x8000 25219878Swollman 25319878Swollman#define RL_INTRS \ 25414343Swollman (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 25519878Swollman RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 25614343Swollman RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 25719878Swollman 25814343Swollman#ifdef RE_TX_MODERATION 25919878Swollman#define RL_INTRS_CPLUS \ 26019878Swollman (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 26114343Swollman RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 2622742Swollman RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 2632742Swollman#else 2642742Swollman#define RL_INTRS_CPLUS \ 26519878Swollman (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 2662742Swollman RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 26719878Swollman RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 26819878Swollman#endif 2692742Swollman 2702742Swollman/* 2712742Swollman * Media status register. (8139 only) 27219878Swollman */ 27319878Swollman#define RL_MEDIASTAT_RXPAUSE 0x01 27443014Swollman#define RL_MEDIASTAT_TXPAUSE 0x02 27543014Swollman#define RL_MEDIASTAT_LINK 0x04 2762742Swollman#define RL_MEDIASTAT_SPEED10 0x08 2772742Swollman#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 2782742Swollman#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 2792742Swollman 2802742Swollman/* 2812742Swollman * Receive config register. 2822742Swollman */ 2832742Swollman#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 2842742Swollman#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 2852742Swollman#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 2862742Swollman#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 2872742Swollman#define RL_RXCFG_RX_RUNT 0x00000010 28814343Swollman#define RL_RXCFG_RX_ERRPKT 0x00000020 2892742Swollman#define RL_RXCFG_WRAP 0x00000080 29014343Swollman#define RL_RXCFG_EARLYOFFV2 0x00000800 29114343Swollman#define RL_RXCFG_MAXDMA 0x00000700 2922742Swollman#define RL_RXCFG_BUFSZ 0x00001800 29314343Swollman#define RL_RXCFG_EARLYOFF 0x00003800 29443014Swollman#define RL_RXCFG_FIFOTHRESH 0x0000E000 29514343Swollman#define RL_RXCFG_EARLYTHRESH 0x07000000 29614343Swollman 29714343Swollman#define RL_RXDMA_16BYTES 0x00000000 2989908Swollman#define RL_RXDMA_32BYTES 0x00000100 2999908Swollman#define RL_RXDMA_64BYTES 0x00000200 3009908Swollman#define RL_RXDMA_128BYTES 0x00000300 3019908Swollman#define RL_RXDMA_256BYTES 0x00000400 3029908Swollman#define RL_RXDMA_512BYTES 0x00000500 3039908Swollman#define RL_RXDMA_1024BYTES 0x00000600 3049908Swollman#define RL_RXDMA_UNLIMITED 0x00000700 30520094Swollman 30620094Swollman#define RL_RXBUF_8 0x00000000 3072742Swollman#define RL_RXBUF_16 0x00000800 3082742Swollman#define RL_RXBUF_32 0x00001000 30914343Swollman#define RL_RXBUF_64 0x00001800 3102742Swollman 31120094Swollman#define RL_RXFIFO_16BYTES 0x00000000 3122742Swollman#define RL_RXFIFO_32BYTES 0x00002000 3138029Swollman#define RL_RXFIFO_64BYTES 0x00004000 31430711Swollman#define RL_RXFIFO_128BYTES 0x00006000 31530711Swollman#define RL_RXFIFO_256BYTES 0x00008000 3162742Swollman#define RL_RXFIFO_512BYTES 0x0000A000 31730711Swollman#define RL_RXFIFO_1024BYTES 0x0000C000 31830711Swollman#define RL_RXFIFO_NOTHRESH 0x0000E000 31930711Swollman 32030711Swollman/* 32130711Swollman * Bits in RX status header (included with RX'ed packet 3222742Swollman * in ring buffer). 3232742Swollman */ 3242742Swollman#define RL_RXSTAT_RXOK 0x00000001 3252742Swollman#define RL_RXSTAT_ALIGNERR 0x00000002 3262742Swollman#define RL_RXSTAT_CRCERR 0x00000004 3272742Swollman#define RL_RXSTAT_GIANT 0x00000008 32819878Swollman#define RL_RXSTAT_RUNT 0x00000010 32919878Swollman#define RL_RXSTAT_BADSYM 0x00000020 33019878Swollman#define RL_RXSTAT_BROAD 0x00002000 3312742Swollman#define RL_RXSTAT_INDIV 0x00004000 3322742Swollman#define RL_RXSTAT_MULTI 0x00008000 3332742Swollman#define RL_RXSTAT_LENMASK 0xFFFF0000 3342742Swollman#define RL_RXSTAT_UNFINISHED 0x0000FFF0 /* DMA still in progress */ 33519878Swollman 33619878Swollman/* 3372742Swollman * Command register. 3389908Swollman */ 3399908Swollman#define RL_CMD_EMPTY_RXBUF 0x0001 3409908Swollman#define RL_CMD_TX_ENB 0x0004 34119878Swollman#define RL_CMD_RX_ENB 0x0008 3429908Swollman#define RL_CMD_RESET 0x0010 3432742Swollman#define RL_CMD_STOPREQ 0x0080 3442742Swollman 3452742Swollman/* 34619878Swollman * Twister register values. These are completely undocumented and derived 34719878Swollman * from public sources. 3482742Swollman */ 3492742Swollman#define RL_CSCFG_LINK_OK 0x0400 3502742Swollman#define RL_CSCFG_CHANGE 0x0800 3512742Swollman#define RL_CSCFG_STATUS 0xf000 35219878Swollman#define RL_CSCFG_ROW3 0x7000 3532742Swollman#define RL_CSCFG_ROW2 0x3000 35414343Swollman#define RL_CSCFG_ROW1 0x1000 35514343Swollman#define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0 35614343Swollman#define RL_CSCFG_LINK_DOWN_CMD 0xf3c0 35719878Swollman 35814343Swollman#define RL_NWAYTST_RESET 0 35914343Swollman#define RL_NWAYTST_CBL_TEST 0x20 36014343Swollman 36114343Swollman#define RL_PARA78 0x78 36214343Swollman#define RL_PARA78_DEF 0x78fa8388 36314343Swollman#define RL_PARA7C 0x7C 36414343Swollman#define RL_PARA7C_DEF 0xcb38de43 36519878Swollman#define RL_PARA7C_RETUNE 0xfb38de03 36619878Swollman 36714343Swollman/* 3682742Swollman * EEPROM control register 3692742Swollman */ 3702742Swollman#define RL_EE_DATAOUT 0x01 /* Data out */ 3712742Swollman#define RL_EE_DATAIN 0x02 /* Data in */ 37219878Swollman#define RL_EE_CLK 0x04 /* clock */ 3732742Swollman#define RL_EE_SEL 0x08 /* chip select */ 3742742Swollman#define RL_EE_MODE (0x40|0x80) 3752742Swollman 3762742Swollman#define RL_EEMODE_OFF 0x00 37719878Swollman#define RL_EEMODE_AUTOLOAD 0x40 3782742Swollman#define RL_EEMODE_PROGRAM 0x80 3792742Swollman#define RL_EEMODE_WRITECFG (0x80|0x40) 3802742Swollman 3812742Swollman/* 9346 EEPROM commands */ 38219878Swollman#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 38319878Swollman#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 3842742Swollman 3852742Swollman#define RL_9346_WRITE 0x5 3862742Swollman#define RL_9346_READ 0x6 3872742Swollman#define RL_9346_ERASE 0x7 38819878Swollman#define RL_9346_EWEN 0x4 3892742Swollman#define RL_9346_EWEN_ADDR 0x30 39043014Swollman#define RL_9456_EWDS 0x4 39143014Swollman#define RL_9346_EWDS_ADDR 0x00 39243014Swollman 39343014Swollman#define RL_EECMD_WRITE 0x140 39443014Swollman#define RL_EECMD_READ_6BIT 0x180 39543014Swollman#define RL_EECMD_READ_8BIT 0x600 39643014Swollman#define RL_EECMD_ERASE 0x1c0 39743014Swollman 39843014Swollman#define RL_EE_ID 0x00 39943014Swollman#define RL_EE_PCI_VID 0x01 40043014Swollman#define RL_EE_PCI_DID 0x02 40143014Swollman/* Location of station address inside EEPROM */ 40243014Swollman#define RL_EE_EADDR 0x07 40343014Swollman 40443014Swollman/* 40543014Swollman * MII register (8129 only) 40643014Swollman */ 40743014Swollman#define RL_MII_CLK 0x01 40843014Swollman#define RL_MII_DATAIN 0x02 40943014Swollman#define RL_MII_DATAOUT 0x04 41043014Swollman#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 41143014Swollman 41243014Swollman/* 41343014Swollman * Config 0 register 41443014Swollman */ 41543014Swollman#define RL_CFG0_ROM0 0x01 41643014Swollman#define RL_CFG0_ROM1 0x02 41743014Swollman#define RL_CFG0_ROM2 0x04 41843014Swollman#define RL_CFG0_PL0 0x08 41943014Swollman#define RL_CFG0_PL1 0x10 42043014Swollman#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 42143014Swollman#define RL_CFG0_PCS 0x40 42243014Swollman#define RL_CFG0_SCR 0x80 4232742Swollman 4242742Swollman/* 42519878Swollman * Config 1 register 42619878Swollman */ 42719878Swollman#define RL_CFG1_PWRDWN 0x01 42820094Swollman#define RL_CFG1_PME 0x01 42920094Swollman#define RL_CFG1_SLEEP 0x02 43020094Swollman#define RL_CFG1_VPDEN 0x02 4312742Swollman#define RL_CFG1_IOMAP 0x04 4322742Swollman#define RL_CFG1_MEMMAP 0x08 43319878Swollman#define RL_CFG1_RSVD 0x10 4342742Swollman#define RL_CFG1_LWACT 0x10 4352742Swollman#define RL_CFG1_DRVLOAD 0x20 4362742Swollman#define RL_CFG1_LED0 0x40 4372742Swollman#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 43819878Swollman#define RL_CFG1_LED1 0x80 4392742Swollman 4402742Swollman/* 4412742Swollman * Config 2 register 4422742Swollman */ 4432742Swollman#define RL_CFG2_PCI33MHZ 0x00 4442742Swollman#define RL_CFG2_PCI66MHZ 0x01 4452742Swollman#define RL_CFG2_PCI64BIT 0x08 4462742Swollman#define RL_CFG2_AUXPWR 0x10 4472742Swollman#define RL_CFG2_MSI 0x20 44820094Swollman 4492742Swollman/* 45043014Swollman * Config 3 register 45143014Swollman */ 4522742Swollman#define RL_CFG3_GRANTSEL 0x80 45320094Swollman#define RL_CFG3_WOL_MAGIC 0x20 45420094Swollman#define RL_CFG3_WOL_LINK 0x10 45520094Swollman#define RL_CFG3_JUMBO_EN0 0x04 /* RTL8168C or later. */ 45620094Swollman#define RL_CFG3_FAST_B2B 0x01 45720094Swollman 45820094Swollman/* 45920094Swollman * Config 4 register 46020094Swollman */ 46120094Swollman#define RL_CFG4_LWPTN 0x04 4622742Swollman#define RL_CFG4_LWPME 0x10 4632742Swollman#define RL_CFG4_JUMBO_EN1 0x02 /* RTL8168C or later. */ 4642742Swollman 4652742Swollman/* 4662742Swollman * Config 5 register 4672742Swollman */ 4682742Swollman#define RL_CFG5_WOL_BCAST 0x40 4692742Swollman#define RL_CFG5_WOL_MCAST 0x20 4702742Swollman#define RL_CFG5_WOL_UCAST 0x10 4712742Swollman#define RL_CFG5_WOL_LANWAKE 0x02 4722742Swollman#define RL_CFG5_PME_STS 0x01 4732742Swollman 4742742Swollman/* 4752742Swollman * 8139C+ register definitions 4762742Swollman */ 4772742Swollman 4782742Swollman/* RL_DUMPSTATS_LO register */ 47919878Swollman#define RL_DUMPSTATS_START 0x00000008 4802742Swollman 4812742Swollman/* Transmit start register */ 48219878Swollman#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 4832742Swollman#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 48414343Swollman#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 4852742Swollman 48614343Swollman/* 4879908Swollman * Config 2 register, 8139C+/8169/8169S/8110S only 4882742Swollman */ 4892742Swollman#define RL_CFG2_BUSFREQ 0x07 4902742Swollman#define RL_CFG2_BUSWIDTH 0x08 4912742Swollman#define RL_CFG2_AUXPWRSTS 0x10 4922742Swollman 49319878Swollman#define RL_BUSFREQ_33MHZ 0x00 4942742Swollman#define RL_BUSFREQ_66MHZ 0x01 4952742Swollman 4962742Swollman#define RL_BUSWIDTH_32BITS 0x00 4972742Swollman#define RL_BUSWIDTH_64BITS 0x08 4982742Swollman 4992742Swollman/* C+ mode command register */ 5002742Swollman#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 5012742Swollman#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 5022742Swollman#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 5032742Swollman#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 5042742Swollman#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 5052742Swollman#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 5062742Swollman#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 5072742Swollman#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 5082742Swollman#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 5092742Swollman#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 5102742Swollman#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 5112742Swollman#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 5122742Swollman#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 5132742Swollman#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 5142742Swollman#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 5152742Swollman 5162742Swollman/* C+ early transmit threshold */ 51714343Swollman#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 5189908Swollman 5199908Swollman/* Timer interrupt register */ 5209908Swollman#define RL_TIMERINT_8169_VAL 0x00001FFF 5219908Swollman#define RL_TIMER_MIN 0 5229908Swollman#define RL_TIMER_MAX 65 /* 65.528us */ 52314343Swollman#define RL_TIMER_DEFAULT RL_TIMER_MAX 5242742Swollman#define RL_TIMER_PCIE_CLK 125 /* 125MHZ */ 52543014Swollman#define RL_USECS(x) ((x) * RL_TIMER_PCIE_CLK) 52643014Swollman 52743014Swollman/* 52843014Swollman * Gigabit PHY access register (8169 only) 52943014Swollman */ 53043014Swollman#define RL_PHYAR_PHYDATA 0x0000FFFF 53143014Swollman#define RL_PHYAR_PHYREG 0x001F0000 53243014Swollman#define RL_PHYAR_BUSY 0x80000000 53343014Swollman 53443014Swollman/* 53543014Swollman * Gigabit media status (8169 only) 53643014Swollman */ 53743014Swollman#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 53843014Swollman#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 53943014Swollman#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 54043014Swollman#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 54143014Swollman#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 54243014Swollman#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 54343014Swollman#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 5449908Swollman#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 5459908Swollman 54619878Swollman/* 5472742Swollman * The RealTek doesn't use a fragment-based descriptor mechanism. 5482742Swollman * Instead, there are only four register sets, each or which represents 5492742Swollman * one 'descriptor.' Basically, each TX descriptor is just a contiguous 5502742Swollman * packet buffer (32-bit aligned!) and we place the buffer addresses in 5519908Swollman * the registers so the chip knows where they are. 5522742Swollman * 55319878Swollman * We can sort of kludge together the same kind of buffer management 5542742Swollman * used in previous drivers, but we have to do buffer copies almost all 5552742Swollman * the time, so it doesn't really buy us much. 5562742Swollman * 5579908Swollman * For reception, there's just one large buffer where the chip stores 5582742Swollman * all received packets. 55919878Swollman */ 5602742Swollman#define RL_RX_BUF_SZ RL_RXBUF_64 5612742Swollman#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 5622742Swollman#define RL_TX_LIST_CNT 4 5632742Swollman#define RL_MIN_FRAMELEN 60 5642742Swollman#define RL_TX_8139_BUF_ALIGN 4 5652742Swollman#define RL_RX_8139_BUF_ALIGN 8 5662742Swollman#define RL_RX_8139_BUF_RESERVE sizeof(int64_t) 5672742Swollman#define RL_RX_8139_BUF_GUARD_SZ \ 5682742Swollman (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE) 5692742Swollman#define RL_TXTHRESH(x) ((x) << 11) 5702742Swollman#define RL_TX_THRESH_INIT 96 5712742Swollman#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 5722742Swollman#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 5732742Swollman#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 57419878Swollman 5752742Swollman#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 5762742Swollman#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 5772742Swollman 57819878Swollman#define RL_ETHER_ALIGN 2 5792742Swollman 5802742Swollman/* 5812742Swollman * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets. 5822742Swollman */ 5832742Swollman#define RL_IP4CSUMTX_MINLEN 28 5842742Swollman#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 58519878Swollman 5862742Swollmanstruct rl_chain_data { 5872742Swollman uint16_t cur_rx; 5882742Swollman uint8_t *rl_rx_buf; 5899908Swollman uint8_t *rl_rx_buf_ptr; 59019878Swollman 5912742Swollman struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 5922742Swollman bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 5932742Swollman bus_dma_tag_t rl_tx_tag; 5942742Swollman bus_dma_tag_t rl_rx_tag; 5952742Swollman bus_dmamap_t rl_rx_dmamap; 5962742Swollman bus_addr_t rl_rx_buf_paddr; 5972742Swollman uint8_t last_tx; 5982742Swollman uint8_t cur_tx; 5992742Swollman}; 6002742Swollman 60119878Swollman#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 6022742Swollman#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 6032742Swollman#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 6042742Swollman#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 60519878Swollman#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 6062742Swollman#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 6072742Swollman#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 6082742Swollman#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 6092742Swollman#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 61019878Swollman 6112742Swollmanstruct rl_type { 6122742Swollman uint16_t rl_vid; 6132742Swollman uint16_t rl_did; 6142742Swollman int rl_basetype; 61519878Swollman const char *rl_name; 6162742Swollman}; 6172742Swollman 6182742Swollmanstruct rl_hwrev { 6192742Swollman uint32_t rl_rev; 6202742Swollman int rl_type; 6212742Swollman const char *rl_desc; 6222742Swollman int rl_max_mtu; 62319878Swollman}; 6242742Swollman 6252742Swollman#define RL_8129 1 6269908Swollman#define RL_8139 2 6272742Swollman#define RL_8139CPLUS 3 62819878Swollman#define RL_8169 4 6292742Swollman 6302742Swollman#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 6312742Swollman (x)->rl_type == RL_8169) 6322742Swollman 6332742Swollman/* 6342742Swollman * The 8139C+ and 8160 gigE chips support descriptor-based TX 6352742Swollman * and RX. In fact, they even support TCP large send. Descriptors 6362742Swollman * must be allocated in contiguous blocks that are aligned on a 6372742Swollman * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 6382742Swollman */ 6392742Swollman 6402742Swollman/* 6412742Swollman * RX/TX descriptor definition. When large send mode is enabled, the 6422742Swollman * lower 11 bits of the TX rl_cmdstat word are used to hold the MSS, and 6432742Swollman * the checksum offload bits are disabled. The structure layout is 6442742Swollman * the same for RX and TX descriptors 6452742Swollman */ 64619878Swollmanstruct rl_desc { 6472742Swollman uint32_t rl_cmdstat; 6482742Swollman uint32_t rl_vlanctl; 6492742Swollman uint32_t rl_bufaddr_lo; 6502742Swollman uint32_t rl_bufaddr_hi; 6512742Swollman}; 6522742Swollman 6532742Swollman#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 6549908Swollman#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 6552742Swollman#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 65619878Swollman#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 6572742Swollman#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 6582742Swollman#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 6592742Swollman#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 6602742Swollman#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 66119878Swollman#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 6622742Swollman#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 6632742Swollman#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 6642742Swollman 6652742Swollman#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 6662742Swollman#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 6672742Swollman/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 6682742Swollman#define RL_TDESC_CMD_UDPCSUMV2 0x80000000 6692742Swollman#define RL_TDESC_CMD_TCPCSUMV2 0x40000000 6702742Swollman#define RL_TDESC_CMD_IPCSUMV2 0x20000000 6712742Swollman#define RL_TDESC_CMD_MSSVALV2 0x1FFC0000 67219878Swollman#define RL_TDESC_CMD_MSSVALV2_SHIFT 18 6732742Swollman 6742742Swollman/* 6752742Swollman * Error bits are valid only on the last descriptor of a frame 6762742Swollman * (i.e. RL_TDESC_CMD_EOF == 1) 67719878Swollman */ 6782742Swollman#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 6792742Swollman#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 6802742Swollman#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 6812742Swollman#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 6822742Swollman#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 68319878Swollman#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 6842742Swollman#define RL_TDESC_STAT_OWN 0x80000000 6852742Swollman 6862742Swollman/* 6872742Swollman * RX descriptor cmd/vlan definitions 68819878Swollman */ 6892742Swollman#define RL_RDESC_CMD_EOR 0x40000000 6902742Swollman#define RL_RDESC_CMD_OWN 0x80000000 6912742Swollman#define RL_RDESC_CMD_BUFLEN 0x00001FFF 6922742Swollman 6939908Swollman#define RL_RDESC_STAT_OWN 0x80000000 6949908Swollman#define RL_RDESC_STAT_EOR 0x40000000 6959908Swollman#define RL_RDESC_STAT_SOF 0x20000000 6969908Swollman#define RL_RDESC_STAT_EOF 0x10000000 6972742Swollman#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 6989908Swollman#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 6999908Swollman#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 70019878Swollman#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 7012742Swollman#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 7022742Swollman#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 7032742Swollman#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 70419878Swollman#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 7052742Swollman#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 7062742Swollman#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 7072742Swollman#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 7082742Swollman#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 7092742Swollman#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 7102742Swollman#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 7112742Swollman#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 7122742Swollman#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 7132742Swollman#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 7142742Swollman#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 7152742Swollman#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 7162742Swollman RL_RDESC_STAT_CRCERR) 7172742Swollman 7182742Swollman#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 7192742Swollman (rl_vlandata valid)*/ 7202742Swollman#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 7212742Swollman/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 7222742Swollman#define RL_RDESC_IPV6 0x80000000 7232742Swollman#define RL_RDESC_IPV4 0x40000000 7242742Swollman 72519878Swollman#define RL_PROTOID_NONIP 0x00000000 7262742Swollman#define RL_PROTOID_TCPIP 0x00010000 7272742Swollman#define RL_PROTOID_UDPIP 0x00020000 7282742Swollman#define RL_PROTOID_IP 0x00030000 7292742Swollman#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 7302742Swollman RL_PROTOID_TCPIP) 7312742Swollman#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 7322742Swollman RL_PROTOID_UDPIP) 7332742Swollman 7342742Swollman/* 7352742Swollman * Statistics counter structure (8139C+ and 8169 only) 73619878Swollman */ 7372742Swollmanstruct rl_stats { 7382742Swollman uint64_t rl_tx_pkts; 7392742Swollman uint64_t rl_rx_pkts; 7402742Swollman uint64_t rl_tx_errs; 7419908Swollman uint32_t rl_rx_errs; 7422742Swollman uint16_t rl_missed_pkts; 74319878Swollman uint16_t rl_rx_framealign_errs; 7442742Swollman uint32_t rl_tx_onecoll; 7452742Swollman uint32_t rl_tx_multicolls; 7462742Swollman uint64_t rl_rx_ucasts; 74719878Swollman uint64_t rl_rx_bcasts; 7482742Swollman uint32_t rl_rx_mcasts; 7492742Swollman uint16_t rl_tx_aborts; 7502742Swollman uint16_t rl_rx_underruns; 7512742Swollman}; 7522742Swollman 7532742Swollman/* 7542742Swollman * Rx/Tx descriptor parameters (8139C+ and 8169 only) 7552742Swollman * 7562742Swollman * 8139C+ 7572742Swollman * Number of descriptors supported : up to 64 7582742Swollman * Descriptor alignment : 256 bytes 7592742Swollman * Tx buffer : At least 4 bytes in length. 7602742Swollman * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 7619908Swollman * 7622742Swollman * 8169 7632742Swollman * Number of descriptors supported : up to 1024 7642742Swollman * Descriptor alignment : 256 bytes 7652742Swollman * Tx buffer : At least 4 bytes in length. 7662742Swollman * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 7672742Swollman */ 7682742Swollman#ifndef __NO_STRICT_ALIGNMENT 7692742Swollman#define RE_FIXUP_RX 1 7702742Swollman#endif 7712742Swollman 7722742Swollman#define RL_8169_TX_DESC_CNT 256 7732742Swollman#define RL_8169_RX_DESC_CNT 256 77419878Swollman#define RL_8139_TX_DESC_CNT 64 7752742Swollman#define RL_8139_RX_DESC_CNT 64 7762742Swollman#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT 7772742Swollman#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT 77819878Swollman#define RL_RX_JUMBO_DESC_CNT RL_RX_DESC_CNT 7792742Swollman#define RL_NTXSEGS 35 7802742Swollman 7812742Swollman#define RL_RING_ALIGN 256 78219878Swollman#define RL_DUMP_ALIGN 64 7832742Swollman#define RL_IFQ_MAXLEN 512 7842742Swollman#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 7852742Swollman#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 7862742Swollman#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1)) 7872742Swollman#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 7882742Swollman#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 78919878Swollman#define RL_PKTSZ(x) ((x)/* >> 3*/) 7902742Swollman#ifdef RE_FIXUP_RX 7912742Swollman#define RE_ETHER_ALIGN sizeof(uint64_t) 7922742Swollman#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 79319878Swollman#else 7942742Swollman#define RE_ETHER_ALIGN 0 7952742Swollman#define RE_RX_DESC_BUFLEN MCLBYTES 7962742Swollman#endif 79714343Swollman 79814343Swollman#define RL_MSI_MESSAGES 1 79914343Swollman 80014343Swollman#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 80130711Swollman#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 80230711Swollman 80330711Swollman/* 80430711Swollman * The number of bits reserved for MSS in RealTek controllers is 80530711Swollman * 11bits. This limits the maximum interface MTU size in TSO case 80630711Swollman * as upper stack should not generate TCP segments with MSS greater 8079908Swollman * than the limit. 8082742Swollman */ 80919878Swollman#define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN) 8102742Swollman 8112742Swollman/* see comment in dev/re/if_re.c */ 81219878Swollman#define RL_JUMBO_FRAMELEN 7440 8132742Swollman#define RL_JUMBO_MTU \ 8142742Swollman (RL_JUMBO_FRAMELEN-ETHER_VLAN_ENCAP_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 8152742Swollman#define RL_JUMBO_MTU_6K \ 81643014Swollman ((6 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 8172742Swollman#define RL_JUMBO_MTU_9K \ 8182742Swollman ((9 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 8192742Swollman#define RL_MTU \ 8202742Swollman (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 8212742Swollman 8222742Swollmanstruct rl_txdesc { 8232742Swollman struct mbuf *tx_m; 8242742Swollman bus_dmamap_t tx_dmamap; 8252742Swollman}; 8262742Swollman 8272742Swollmanstruct rl_rxdesc { 8289908Swollman struct mbuf *rx_m; 8292742Swollman bus_dmamap_t rx_dmamap; 83019878Swollman bus_size_t rx_size; 8312742Swollman}; 8322742Swollman 8332742Swollmanstruct rl_list_data { 8342742Swollman struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT]; 8352742Swollman struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT]; 83614343Swollman struct rl_rxdesc rl_jrx_desc[RL_RX_JUMBO_DESC_CNT]; 83743014Swollman int rl_tx_desc_cnt; 83814343Swollman int rl_rx_desc_cnt; 83914343Swollman int rl_tx_prodidx; 84014343Swollman int rl_rx_prodidx; 84114343Swollman int rl_tx_considx; 8422742Swollman int rl_tx_free; 8432742Swollman bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */ 8442742Swollman bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */ 8452742Swollman bus_dma_tag_t rl_jrx_mtag; /* mbuf RX mapping tag */ 8462742Swollman bus_dmamap_t rl_rx_sparemap; 84719878Swollman bus_dmamap_t rl_jrx_sparemap; 8482742Swollman bus_dma_tag_t rl_stag; /* stats mapping tag */ 8492742Swollman bus_dmamap_t rl_smap; /* stats map */ 8502742Swollman struct rl_stats *rl_stats; 8512742Swollman bus_addr_t rl_stats_addr; 8522742Swollman bus_dma_tag_t rl_rx_list_tag; 85319878Swollman bus_dmamap_t rl_rx_list_map; 8542742Swollman struct rl_desc *rl_rx_list; 8552742Swollman bus_addr_t rl_rx_list_addr; 8562742Swollman bus_dma_tag_t rl_tx_list_tag; 8572742Swollman bus_dmamap_t rl_tx_list_map; 8582742Swollman struct rl_desc *rl_tx_list; 8592742Swollman bus_addr_t rl_tx_list_addr; 8602742Swollman}; 8612742Swollman 8622742Swollmanenum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE }; 8632742Swollman 8642742Swollmanstruct rl_softc { 8652742Swollman struct ifnet *rl_ifp; /* interface info */ 8662742Swollman bus_space_handle_t rl_bhandle; /* bus space handle */ 86719878Swollman bus_space_tag_t rl_btag; /* bus space tag */ 8682742Swollman device_t rl_dev; 8692742Swollman struct resource *rl_res; 8702742Swollman int rl_res_id; 87114343Swollman int rl_res_type; 87214343Swollman struct resource *rl_res_pba; 87314343Swollman struct resource *rl_irq[RL_MSI_MESSAGES]; 87414343Swollman void *rl_intrhand[RL_MSI_MESSAGES]; 87514343Swollman device_t rl_miibus; 87614343Swollman bus_dma_tag_t rl_parent_tag; 87714343Swollman uint8_t rl_type; 87820094Swollman const struct rl_hwrev *rl_hwrev; 87920094Swollman uint32_t rl_macrev; 88020094Swollman int rl_eecmd_read; 88120094Swollman int rl_eewidth; 88220094Swollman int rl_expcap; 88314343Swollman int rl_txthresh; 8842742Swollman bus_size_t rl_cfg0; 8852742Swollman bus_size_t rl_cfg1; 8862742Swollman bus_size_t rl_cfg2; 8872742Swollman bus_size_t rl_cfg3; 8882742Swollman bus_size_t rl_cfg4; 8892742Swollman bus_size_t rl_cfg5; 8902742Swollman struct rl_chain_data rl_cdata; 8912742Swollman struct rl_list_data rl_ldata; 89214343Swollman struct callout rl_stat_callout; 89314343Swollman int rl_watchdog_timer; 89414343Swollman struct mtx rl_mtx; 89514343Swollman struct mbuf *rl_head; 89617200Swollman struct mbuf *rl_tail; 89717200Swollman uint32_t rl_rxlenmask; 89817200Swollman int rl_testmode; 89917200Swollman int rl_if_flags; 90017200Swollman int rl_twister_enable; 90117200Swollman enum rl_twist rl_twister; 90217200Swollman int rl_twist_row; 9032742Swollman int rl_twist_col; 9042742Swollman int suspended; /* 0 = normal 1 = suspended */ 9052742Swollman#ifdef DEVICE_POLLING 9062742Swollman int rxcycles; 90719878Swollman#endif 9082742Swollman 9092742Swollman struct task rl_inttask; 9102742Swollman 91114343Swollman int rl_txstart; 9122742Swollman int rl_int_rx_act; 9132742Swollman int rl_int_rx_mod; 9142742Swollman uint32_t rl_flags; 9152742Swollman#define RL_FLAG_MSI 0x00000001 9162742Swollman#define RL_FLAG_AUTOPAD 0x00000002 91714343Swollman#define RL_FLAG_PHYWAKE_PM 0x00000004 91817200Swollman#define RL_FLAG_PHYWAKE 0x00000008 91917200Swollman#define RL_FLAG_JUMBOV2 0x00000010 92017200Swollman#define RL_FLAG_PAR 0x00000020 92117200Swollman#define RL_FLAG_DESCV2 0x00000040 92217200Swollman#define RL_FLAG_MACSTAT 0x00000080 92317200Swollman#define RL_FLAG_FASTETHER 0x00000100 92417200Swollman#define RL_FLAG_CMDSTOP 0x00000200 92517200Swollman#define RL_FLAG_MACRESET 0x00000400 92617200Swollman#define RL_FLAG_MSIX 0x00000800 92714343Swollman#define RL_FLAG_WOLRXENB 0x00001000 92814343Swollman#define RL_FLAG_MACSLEEP 0x00002000 92914343Swollman#define RL_FLAG_WAIT_TXPOLL 0x00004000 93014343Swollman#define RL_FLAG_CMDSTOP_WAIT_TXQ 0x00008000 93114343Swollman#define RL_FLAG_WOL_MANLINK 0x00010000 93214343Swollman#define RL_FLAG_EARLYOFF 0x00020000 93317200Swollman#define RL_FLAG_EARLYOFFV2 0x00040000 93417200Swollman#define RL_FLAG_RXDV_GATED 0x00080000 93517200Swollman#define RL_FLAG_PCIE 0x40000000 93617200Swollman#define RL_FLAG_LINK 0x80000000 93717200Swollman}; 93817200Swollman 93917200Swollman#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 940#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 941#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 942 943/* 944 * register space access macros 945 */ 946#define CSR_WRITE_STREAM_4(sc, reg, val) \ 947 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 948#define CSR_WRITE_4(sc, reg, val) \ 949 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 950#define CSR_WRITE_2(sc, reg, val) \ 951 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 952#define CSR_WRITE_1(sc, reg, val) \ 953 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 954 955#define CSR_READ_4(sc, reg) \ 956 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 957#define CSR_READ_2(sc, reg) \ 958 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 959#define CSR_READ_1(sc, reg) \ 960 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 961 962#define CSR_BARRIER(sc, reg, length, flags) \ 963 bus_space_barrier(sc->rl_btag, sc->rl_bhandle, reg, length, flags) 964 965#define CSR_SETBIT_1(sc, offset, val) \ 966 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 967 968#define CSR_CLRBIT_1(sc, offset, val) \ 969 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 970 971#define CSR_SETBIT_2(sc, offset, val) \ 972 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 973 974#define CSR_CLRBIT_2(sc, offset, val) \ 975 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 976 977#define CSR_SETBIT_4(sc, offset, val) \ 978 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 979 980#define CSR_CLRBIT_4(sc, offset, val) \ 981 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 982 983#define RL_TIMEOUT 1000 984#define RL_PHY_TIMEOUT 2000 985 986/* 987 * General constants that are fun to know. 988 * 989 * RealTek PCI vendor ID 990 */ 991#define RT_VENDORID 0x10EC 992 993/* 994 * RealTek chip device IDs. 995 */ 996#define RT_DEVICEID_8139D 0x8039 997#define RT_DEVICEID_8129 0x8129 998#define RT_DEVICEID_8101E 0x8136 999#define RT_DEVICEID_8138 0x8138 1000#define RT_DEVICEID_8139 0x8139 1001#define RT_DEVICEID_8169SC 0x8167 1002#define RT_DEVICEID_8168 0x8168 1003#define RT_DEVICEID_8169 0x8169 1004#define RT_DEVICEID_8100 0x8100 1005 1006#define RT_REVID_8139CPLUS 0x20 1007 1008/* 1009 * Accton PCI vendor ID 1010 */ 1011#define ACCTON_VENDORID 0x1113 1012 1013/* 1014 * Accton MPX 5030/5038 device ID. 1015 */ 1016#define ACCTON_DEVICEID_5030 0x1211 1017 1018/* 1019 * Nortel PCI vendor ID 1020 */ 1021#define NORTEL_VENDORID 0x126C 1022 1023/* 1024 * Delta Electronics Vendor ID. 1025 */ 1026#define DELTA_VENDORID 0x1500 1027 1028/* 1029 * Delta device IDs. 1030 */ 1031#define DELTA_DEVICEID_8139 0x1360 1032 1033/* 1034 * Addtron vendor ID. 1035 */ 1036#define ADDTRON_VENDORID 0x4033 1037 1038/* 1039 * Addtron device IDs. 1040 */ 1041#define ADDTRON_DEVICEID_8139 0x1360 1042 1043/* 1044 * D-Link vendor ID. 1045 */ 1046#define DLINK_VENDORID 0x1186 1047 1048/* 1049 * D-Link DFE-530TX+ device ID 1050 */ 1051#define DLINK_DEVICEID_530TXPLUS 0x1300 1052 1053/* 1054 * D-Link DFE-520TX rev. C1 device ID 1055 */ 1056#define DLINK_DEVICEID_520TX_REVC1 0x4200 1057 1058/* 1059 * D-Link DFE-5280T device ID 1060 */ 1061#define DLINK_DEVICEID_528T 0x4300 1062#define DLINK_DEVICEID_530T_REVC 0x4302 1063 1064/* 1065 * D-Link DFE-690TXD device ID 1066 */ 1067#define DLINK_DEVICEID_690TXD 0x1340 1068 1069/* 1070 * Corega K.K vendor ID 1071 */ 1072#define COREGA_VENDORID 0x1259 1073 1074/* 1075 * Corega FEther CB-TXD device ID 1076 */ 1077#define COREGA_DEVICEID_FETHERCBTXD 0xa117 1078 1079/* 1080 * Corega FEtherII CB-TXD device ID 1081 */ 1082#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 1083 1084/* 1085 * Corega CG-LAPCIGT device ID 1086 */ 1087#define COREGA_DEVICEID_CGLAPCIGT 0xc107 1088 1089/* 1090 * Linksys vendor ID 1091 */ 1092#define LINKSYS_VENDORID 0x1737 1093 1094/* 1095 * Linksys EG1032 device ID 1096 */ 1097#define LINKSYS_DEVICEID_EG1032 0x1032 1098 1099/* 1100 * Linksys EG1032 rev 3 sub-device ID 1101 */ 1102#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 1103 1104/* 1105 * Peppercon vendor ID 1106 */ 1107#define PEPPERCON_VENDORID 0x1743 1108 1109/* 1110 * Peppercon ROL-F device ID 1111 */ 1112#define PEPPERCON_DEVICEID_ROLF 0x8139 1113 1114/* 1115 * Planex Communications, Inc. vendor ID 1116 */ 1117#define PLANEX_VENDORID 0x14ea 1118 1119/* 1120 * Planex FNW-3603-TX device ID 1121 */ 1122#define PLANEX_DEVICEID_FNW3603TX 0xab06 1123 1124/* 1125 * Planex FNW-3800-TX device ID 1126 */ 1127#define PLANEX_DEVICEID_FNW3800TX 0xab07 1128 1129/* 1130 * LevelOne vendor ID 1131 */ 1132#define LEVEL1_VENDORID 0x018A 1133 1134/* 1135 * LevelOne FPC-0106TX devide ID 1136 */ 1137#define LEVEL1_DEVICEID_FPC0106TX 0x0106 1138 1139/* 1140 * Compaq vendor ID 1141 */ 1142#define CP_VENDORID 0x021B 1143 1144/* 1145 * Edimax vendor ID 1146 */ 1147#define EDIMAX_VENDORID 0x13D1 1148 1149/* 1150 * Edimax EP-4103DL cardbus device ID 1151 */ 1152#define EDIMAX_DEVICEID_EP4103DL 0xAB06 1153 1154/* US Robotics vendor ID */ 1155 1156#define USR_VENDORID 0x16EC 1157 1158/* US Robotics 997902 device ID */ 1159 1160#define USR_DEVICEID_997902 0x0116 1161