if_rlreg.h revision 227916
155740Sphantom/*- 255740Sphantom * Copyright (c) 1997, 1998-2003 3265420Simp * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4156813Sru * 5280849Scy * Redistribution and use in source and binary forms, with or without 6280849Scy * modification, are permitted provided that the following conditions 788066Sru * are met: 855740Sphantom * 1. Redistributions of source code must retain the above copyright 9156813Sru * notice, this list of conditions and the following disclaimer. 10280849Scy * 2. Redistributions in binary form must reproduce the above copyright 11280849Scy * notice, this list of conditions and the following disclaimer in the 12280849Scy * documentation and/or other materials provided with the distribution. 13280849Scy * 3. All advertising materials mentioning features or use of this software 14280849Scy * must display the following acknowledgement: 15280849Scy * This product includes software developed by Bill Paul. 16280849Scy * 4. Neither the name of the author nor the names of any co-contributors 17280849Scy * may be used to endorse or promote products derived from this software 18280849Scy * without specific prior written permission. 19280849Scy * 20280849Scy * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21280849Scy * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22280849Scy * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23156736Sru * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2455740Sphantom * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2574816Sru * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26280849Scy * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2755857Ssheldonh * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28132458Sroberto * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29280849Scy * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30280849Scy * THE POSSIBILITY OF SUCH DAMAGE. 31280849Scy * 32280849Scy * $FreeBSD: head/sys/pci/if_rlreg.h 227916 2011-11-23 23:29:18Z yongari $ 3355740Sphantom */ 3455740Sphantom 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 41#define RL_IDR3 0x0003 42#define RL_IDR4 0x0004 43#define RL_IDR5 0x0005 44 /* 0006-0007 reserved */ 45#define RL_MAR0 0x0008 /* Multicast hash table */ 46#define RL_MAR1 0x0009 47#define RL_MAR2 0x000A 48#define RL_MAR3 0x000B 49#define RL_MAR4 0x000C 50#define RL_MAR5 0x000D 51#define RL_MAR6 0x000E 52#define RL_MAR7 0x000F 53 54#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 58 59#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 63 64#define RL_RXADDR 0x0030 /* RX ring start address */ 65#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67#define RL_COMMAND 0x0037 /* command register */ 68#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70#define RL_IMR 0x003C /* interrupt mask register */ 71#define RL_ISR 0x003E /* interrupt status register */ 72#define RL_TXCFG 0x0040 /* transmit config */ 73#define RL_RXCFG 0x0044 /* receive config */ 74#define RL_TIMERCNT 0x0048 /* timer count register */ 75#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76#define RL_EECMD 0x0050 /* EEPROM command register */ 77#define RL_CFG0 0x0051 /* config register #0 */ 78#define RL_CFG1 0x0052 /* config register #1 */ 79#define RL_CFG2 0x0053 /* config register #2 */ 80#define RL_CFG3 0x0054 /* config register #3 */ 81#define RL_CFG4 0x0055 /* config register #4 */ 82#define RL_CFG5 0x0056 /* config register #5 */ 83 /* 0057 reserved */ 84#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 85 /* 0059-005A reserved */ 86#define RL_MII 0x005A /* 8129 chip only */ 87#define RL_HALTCLK 0x005B 88#define RL_MULTIINTR 0x005C /* multiple interrupt */ 89#define RL_PCIREV 0x005E /* PCI revision value */ 90 /* 005F reserved */ 91#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 92 93/* Direct PHY access registers only available on 8139 */ 94#define RL_BMCR 0x0062 /* PHY basic mode control */ 95#define RL_BMSR 0x0064 /* PHY basic mode status */ 96#define RL_ANAR 0x0066 /* PHY autoneg advert */ 97#define RL_LPAR 0x0068 /* PHY link partner ability */ 98#define RL_ANER 0x006A /* PHY autoneg expansion */ 99 100#define RL_DISCCNT 0x006C /* disconnect counter */ 101#define RL_FALSECAR 0x006E /* false carrier counter */ 102#define RL_NWAYTST 0x0070 /* NWAY test register */ 103#define RL_RX_ER 0x0072 /* RX_ER counter */ 104#define RL_CSCFG 0x0074 /* CS configuration register */ 105 106/* 107 * When operating in special C+ mode, some of the registers in an 108 * 8139C+ chip have different definitions. These are also used for 109 * the 8169 gigE chip. 110 */ 111#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 112#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 113#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 114#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 115#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 116#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 117#define RL_CFG2 0x0053 118#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 119#define RL_TXSTART 0x00D9 /* 8 bits */ 120#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 121#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 122#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 123#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 124 125/* 126 * Registers specific to the 8169 gigE chip 127 */ 128#define RL_GTXSTART 0x0038 /* 8 bits */ 129#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 130#define RL_PHYAR 0x0060 131#define RL_TBICSR 0x0064 132#define RL_TBI_ANAR 0x0068 133#define RL_TBI_LPAR 0x006A 134#define RL_GMEDIASTAT 0x006C /* 8 bits */ 135#define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */ 136#define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */ 137#define RL_PMCH 0x006F /* 8 bits */ 138#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 139#define RL_INTRMOD 0x00E2 /* 16 bits */ 140 141/* 142 * TX config register bits 143 */ 144#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 145#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 146#define RL_TXCFG_QUEUE_EMPTY 0x00000800 /* 8168E-VL or higher */ 147#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 148#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 149#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 150#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 151#define RL_TXCFG_HWREV 0x7CC00000 152 153#define RL_LOOPTEST_OFF 0x00000000 154#define RL_LOOPTEST_ON 0x00020000 155#define RL_LOOPTEST_ON_CPLUS 0x00060000 156 157/* Known revision codes. */ 158 159#define RL_HWREV_8169 0x00000000 160#define RL_HWREV_8169S 0x00800000 161#define RL_HWREV_8110S 0x04000000 162#define RL_HWREV_8169_8110SB 0x10000000 163#define RL_HWREV_8169_8110SC 0x18000000 164#define RL_HWREV_8401E 0x24000000 165#define RL_HWREV_8102EL 0x24800000 166#define RL_HWREV_8102EL_SPIN1 0x24C00000 167#define RL_HWREV_8168D 0x28000000 168#define RL_HWREV_8168DP 0x28800000 169#define RL_HWREV_8168E 0x2C000000 170#define RL_HWREV_8168E_VL 0x2C800000 171#define RL_HWREV_8168B_SPIN1 0x30000000 172#define RL_HWREV_8100E 0x30800000 173#define RL_HWREV_8101E 0x34000000 174#define RL_HWREV_8102E 0x34800000 175#define RL_HWREV_8103E 0x34C00000 176#define RL_HWREV_8168B_SPIN2 0x38000000 177#define RL_HWREV_8168B_SPIN3 0x38400000 178#define RL_HWREV_8168C 0x3C000000 179#define RL_HWREV_8168C_SPIN2 0x3C400000 180#define RL_HWREV_8168CP 0x3C800000 181#define RL_HWREV_8105E 0x40800000 182#define RL_HWREV_8105E_SPIN1 0x40C00000 183#define RL_HWREV_8402 0x44000000 184#define RL_HWREV_8168F 0x48000000 185#define RL_HWREV_8411 0x48800000 186#define RL_HWREV_8139 0x60000000 187#define RL_HWREV_8139A 0x70000000 188#define RL_HWREV_8139AG 0x70800000 189#define RL_HWREV_8139B 0x78000000 190#define RL_HWREV_8130 0x7C000000 191#define RL_HWREV_8139C 0x74000000 192#define RL_HWREV_8139D 0x74400000 193#define RL_HWREV_8139CPLUS 0x74800000 194#define RL_HWREV_8101 0x74C00000 195#define RL_HWREV_8100 0x78800000 196#define RL_HWREV_8169_8110SBL 0x7CC00000 197#define RL_HWREV_8169_8110SCE 0x98000000 198 199#define RL_TXDMA_16BYTES 0x00000000 200#define RL_TXDMA_32BYTES 0x00000100 201#define RL_TXDMA_64BYTES 0x00000200 202#define RL_TXDMA_128BYTES 0x00000300 203#define RL_TXDMA_256BYTES 0x00000400 204#define RL_TXDMA_512BYTES 0x00000500 205#define RL_TXDMA_1024BYTES 0x00000600 206#define RL_TXDMA_2048BYTES 0x00000700 207 208/* 209 * Transmit descriptor status register bits. 210 */ 211#define RL_TXSTAT_LENMASK 0x00001FFF 212#define RL_TXSTAT_OWN 0x00002000 213#define RL_TXSTAT_TX_UNDERRUN 0x00004000 214#define RL_TXSTAT_TX_OK 0x00008000 215#define RL_TXSTAT_EARLY_THRESH 0x003F0000 216#define RL_TXSTAT_COLLCNT 0x0F000000 217#define RL_TXSTAT_CARR_HBEAT 0x10000000 218#define RL_TXSTAT_OUTOFWIN 0x20000000 219#define RL_TXSTAT_TXABRT 0x40000000 220#define RL_TXSTAT_CARRLOSS 0x80000000 221 222/* 223 * Interrupt status register bits. 224 */ 225#define RL_ISR_RX_OK 0x0001 226#define RL_ISR_RX_ERR 0x0002 227#define RL_ISR_TX_OK 0x0004 228#define RL_ISR_TX_ERR 0x0008 229#define RL_ISR_RX_OVERRUN 0x0010 230#define RL_ISR_PKT_UNDERRUN 0x0020 231#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 232#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 233#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 234#define RL_ISR_SWI 0x0100 /* C+ only */ 235#define RL_ISR_CABLE_LEN_CHGD 0x2000 236#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 237#define RL_ISR_TIMEOUT_EXPIRED 0x4000 238#define RL_ISR_SYSTEM_ERR 0x8000 239 240#define RL_INTRS \ 241 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 242 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 243 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 244 245#ifdef RE_TX_MODERATION 246#define RL_INTRS_CPLUS \ 247 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 248 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 249 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 250#else 251#define RL_INTRS_CPLUS \ 252 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 253 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 254 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 255#endif 256 257/* 258 * Media status register. (8139 only) 259 */ 260#define RL_MEDIASTAT_RXPAUSE 0x01 261#define RL_MEDIASTAT_TXPAUSE 0x02 262#define RL_MEDIASTAT_LINK 0x04 263#define RL_MEDIASTAT_SPEED10 0x08 264#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 265#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 266 267/* 268 * Receive config register. 269 */ 270#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 271#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 272#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 273#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 274#define RL_RXCFG_RX_RUNT 0x00000010 275#define RL_RXCFG_RX_ERRPKT 0x00000020 276#define RL_RXCFG_WRAP 0x00000080 277#define RL_RXCFG_MAXDMA 0x00000700 278#define RL_RXCFG_BUFSZ 0x00001800 279#define RL_RXCFG_FIFOTHRESH 0x0000E000 280#define RL_RXCFG_EARLYTHRESH 0x07000000 281 282#define RL_RXDMA_16BYTES 0x00000000 283#define RL_RXDMA_32BYTES 0x00000100 284#define RL_RXDMA_64BYTES 0x00000200 285#define RL_RXDMA_128BYTES 0x00000300 286#define RL_RXDMA_256BYTES 0x00000400 287#define RL_RXDMA_512BYTES 0x00000500 288#define RL_RXDMA_1024BYTES 0x00000600 289#define RL_RXDMA_UNLIMITED 0x00000700 290 291#define RL_RXBUF_8 0x00000000 292#define RL_RXBUF_16 0x00000800 293#define RL_RXBUF_32 0x00001000 294#define RL_RXBUF_64 0x00001800 295 296#define RL_RXFIFO_16BYTES 0x00000000 297#define RL_RXFIFO_32BYTES 0x00002000 298#define RL_RXFIFO_64BYTES 0x00004000 299#define RL_RXFIFO_128BYTES 0x00006000 300#define RL_RXFIFO_256BYTES 0x00008000 301#define RL_RXFIFO_512BYTES 0x0000A000 302#define RL_RXFIFO_1024BYTES 0x0000C000 303#define RL_RXFIFO_NOTHRESH 0x0000E000 304 305/* 306 * Bits in RX status header (included with RX'ed packet 307 * in ring buffer). 308 */ 309#define RL_RXSTAT_RXOK 0x00000001 310#define RL_RXSTAT_ALIGNERR 0x00000002 311#define RL_RXSTAT_CRCERR 0x00000004 312#define RL_RXSTAT_GIANT 0x00000008 313#define RL_RXSTAT_RUNT 0x00000010 314#define RL_RXSTAT_BADSYM 0x00000020 315#define RL_RXSTAT_BROAD 0x00002000 316#define RL_RXSTAT_INDIV 0x00004000 317#define RL_RXSTAT_MULTI 0x00008000 318#define RL_RXSTAT_LENMASK 0xFFFF0000 319 320#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 321/* 322 * Command register. 323 */ 324#define RL_CMD_EMPTY_RXBUF 0x0001 325#define RL_CMD_TX_ENB 0x0004 326#define RL_CMD_RX_ENB 0x0008 327#define RL_CMD_RESET 0x0010 328#define RL_CMD_STOPREQ 0x0080 329 330/* 331 * Twister register values. These are completely undocumented and derived 332 * from public sources. 333 */ 334#define RL_CSCFG_LINK_OK 0x0400 335#define RL_CSCFG_CHANGE 0x0800 336#define RL_CSCFG_STATUS 0xf000 337#define RL_CSCFG_ROW3 0x7000 338#define RL_CSCFG_ROW2 0x3000 339#define RL_CSCFG_ROW1 0x1000 340#define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0 341#define RL_CSCFG_LINK_DOWN_CMD 0xf3c0 342 343#define RL_NWAYTST_RESET 0 344#define RL_NWAYTST_CBL_TEST 0x20 345 346#define RL_PARA78 0x78 347#define RL_PARA78_DEF 0x78fa8388 348#define RL_PARA7C 0x7C 349#define RL_PARA7C_DEF 0xcb38de43 350#define RL_PARA7C_RETUNE 0xfb38de03 351/* 352 * EEPROM control register 353 */ 354#define RL_EE_DATAOUT 0x01 /* Data out */ 355#define RL_EE_DATAIN 0x02 /* Data in */ 356#define RL_EE_CLK 0x04 /* clock */ 357#define RL_EE_SEL 0x08 /* chip select */ 358#define RL_EE_MODE (0x40|0x80) 359 360#define RL_EEMODE_OFF 0x00 361#define RL_EEMODE_AUTOLOAD 0x40 362#define RL_EEMODE_PROGRAM 0x80 363#define RL_EEMODE_WRITECFG (0x80|0x40) 364 365/* 9346 EEPROM commands */ 366#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 367#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 368 369#define RL_9346_WRITE 0x5 370#define RL_9346_READ 0x6 371#define RL_9346_ERASE 0x7 372#define RL_9346_EWEN 0x4 373#define RL_9346_EWEN_ADDR 0x30 374#define RL_9456_EWDS 0x4 375#define RL_9346_EWDS_ADDR 0x00 376 377#define RL_EECMD_WRITE 0x140 378#define RL_EECMD_READ_6BIT 0x180 379#define RL_EECMD_READ_8BIT 0x600 380#define RL_EECMD_ERASE 0x1c0 381 382#define RL_EE_ID 0x00 383#define RL_EE_PCI_VID 0x01 384#define RL_EE_PCI_DID 0x02 385/* Location of station address inside EEPROM */ 386#define RL_EE_EADDR 0x07 387 388/* 389 * MII register (8129 only) 390 */ 391#define RL_MII_CLK 0x01 392#define RL_MII_DATAIN 0x02 393#define RL_MII_DATAOUT 0x04 394#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 395 396/* 397 * Config 0 register 398 */ 399#define RL_CFG0_ROM0 0x01 400#define RL_CFG0_ROM1 0x02 401#define RL_CFG0_ROM2 0x04 402#define RL_CFG0_PL0 0x08 403#define RL_CFG0_PL1 0x10 404#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 405#define RL_CFG0_PCS 0x40 406#define RL_CFG0_SCR 0x80 407 408/* 409 * Config 1 register 410 */ 411#define RL_CFG1_PWRDWN 0x01 412#define RL_CFG1_PME 0x01 413#define RL_CFG1_SLEEP 0x02 414#define RL_CFG1_VPDEN 0x02 415#define RL_CFG1_IOMAP 0x04 416#define RL_CFG1_MEMMAP 0x08 417#define RL_CFG1_RSVD 0x10 418#define RL_CFG1_LWACT 0x10 419#define RL_CFG1_DRVLOAD 0x20 420#define RL_CFG1_LED0 0x40 421#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 422#define RL_CFG1_LED1 0x80 423 424/* 425 * Config 2 register 426 */ 427#define RL_CFG2_PCI33MHZ 0x00 428#define RL_CFG2_PCI66MHZ 0x01 429#define RL_CFG2_PCI64BIT 0x08 430#define RL_CFG2_AUXPWR 0x10 431#define RL_CFG2_MSI 0x20 432 433/* 434 * Config 3 register 435 */ 436#define RL_CFG3_GRANTSEL 0x80 437#define RL_CFG3_WOL_MAGIC 0x20 438#define RL_CFG3_WOL_LINK 0x10 439#define RL_CFG3_JUMBO_EN0 0x04 /* RTL8168C or later. */ 440#define RL_CFG3_FAST_B2B 0x01 441 442/* 443 * Config 4 register 444 */ 445#define RL_CFG4_LWPTN 0x04 446#define RL_CFG4_LWPME 0x10 447#define RL_CFG4_JUMBO_EN1 0x02 /* RTL8168C or later. */ 448 449/* 450 * Config 5 register 451 */ 452#define RL_CFG5_WOL_BCAST 0x40 453#define RL_CFG5_WOL_MCAST 0x20 454#define RL_CFG5_WOL_UCAST 0x10 455#define RL_CFG5_WOL_LANWAKE 0x02 456#define RL_CFG5_PME_STS 0x01 457 458/* 459 * 8139C+ register definitions 460 */ 461 462/* RL_DUMPSTATS_LO register */ 463 464#define RL_DUMPSTATS_START 0x00000008 465 466/* Transmit start register */ 467 468#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 469#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 470#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 471 472/* 473 * Config 2 register, 8139C+/8169/8169S/8110S only 474 */ 475#define RL_CFG2_BUSFREQ 0x07 476#define RL_CFG2_BUSWIDTH 0x08 477#define RL_CFG2_AUXPWRSTS 0x10 478 479#define RL_BUSFREQ_33MHZ 0x00 480#define RL_BUSFREQ_66MHZ 0x01 481 482#define RL_BUSWIDTH_32BITS 0x00 483#define RL_BUSWIDTH_64BITS 0x08 484 485/* C+ mode command register */ 486 487#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 488#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 489#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 490#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 491#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 492#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 493#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 494#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 495#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 496#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 497#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 498#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 499#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 500#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 501#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 502 503/* C+ early transmit threshold */ 504 505#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 506 507/* Timer interrupt register */ 508#define RL_TIMERINT_8169_VAL 0x00001FFF 509#define RL_TIMER_MIN 0 510#define RL_TIMER_MAX 65 /* 65.528us */ 511#define RL_TIMER_DEFAULT RL_TIMER_MAX 512#define RL_TIMER_PCIE_CLK 125 /* 125MHZ */ 513#define RL_USECS(x) ((x) * RL_TIMER_PCIE_CLK) 514 515/* 516 * Gigabit PHY access register (8169 only) 517 */ 518 519#define RL_PHYAR_PHYDATA 0x0000FFFF 520#define RL_PHYAR_PHYREG 0x001F0000 521#define RL_PHYAR_BUSY 0x80000000 522 523/* 524 * Gigabit media status (8169 only) 525 */ 526#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 527#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 528#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 529#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 530#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 531#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 532#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 533#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 534 535/* 536 * The RealTek doesn't use a fragment-based descriptor mechanism. 537 * Instead, there are only four register sets, each or which represents 538 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 539 * packet buffer (32-bit aligned!) and we place the buffer addresses in 540 * the registers so the chip knows where they are. 541 * 542 * We can sort of kludge together the same kind of buffer management 543 * used in previous drivers, but we have to do buffer copies almost all 544 * the time, so it doesn't really buy us much. 545 * 546 * For reception, there's just one large buffer where the chip stores 547 * all received packets. 548 */ 549 550#define RL_RX_BUF_SZ RL_RXBUF_64 551#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 552#define RL_TX_LIST_CNT 4 553#define RL_MIN_FRAMELEN 60 554#define RL_TX_8139_BUF_ALIGN 4 555#define RL_RX_8139_BUF_ALIGN 8 556#define RL_RX_8139_BUF_RESERVE sizeof(int64_t) 557#define RL_RX_8139_BUF_GUARD_SZ \ 558 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE) 559#define RL_TXTHRESH(x) ((x) << 11) 560#define RL_TX_THRESH_INIT 96 561#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 562#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 563#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 564 565#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 566#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 567 568#define RL_ETHER_ALIGN 2 569 570/* 571 * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets. 572 */ 573#define RL_IP4CSUMTX_MINLEN 28 574#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 575 576struct rl_chain_data { 577 uint16_t cur_rx; 578 uint8_t *rl_rx_buf; 579 uint8_t *rl_rx_buf_ptr; 580 581 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 582 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 583 bus_dma_tag_t rl_tx_tag; 584 bus_dma_tag_t rl_rx_tag; 585 bus_dmamap_t rl_rx_dmamap; 586 bus_addr_t rl_rx_buf_paddr; 587 uint8_t last_tx; 588 uint8_t cur_tx; 589}; 590 591#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 592#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 593#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 594#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 595#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 596#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 597#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 598#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 599#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 600 601struct rl_type { 602 uint16_t rl_vid; 603 uint16_t rl_did; 604 int rl_basetype; 605 const char *rl_name; 606}; 607 608struct rl_hwrev { 609 uint32_t rl_rev; 610 int rl_type; 611 const char *rl_desc; 612 int rl_max_mtu; 613}; 614 615#define RL_8129 1 616#define RL_8139 2 617#define RL_8139CPLUS 3 618#define RL_8169 4 619 620#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 621 (x)->rl_type == RL_8169) 622 623/* 624 * The 8139C+ and 8160 gigE chips support descriptor-based TX 625 * and RX. In fact, they even support TCP large send. Descriptors 626 * must be allocated in contiguous blocks that are aligned on a 627 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 628 */ 629 630/* 631 * RX/TX descriptor definition. When large send mode is enabled, the 632 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 633 * the checksum offload bits are disabled. The structure layout is 634 * the same for RX and TX descriptors 635 */ 636 637struct rl_desc { 638 uint32_t rl_cmdstat; 639 uint32_t rl_vlanctl; 640 uint32_t rl_bufaddr_lo; 641 uint32_t rl_bufaddr_hi; 642}; 643 644#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 645#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 646#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 647#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 648#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 649#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 650#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 651#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 652#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 653#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 654#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 655 656#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 657#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 658/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 659#define RL_TDESC_CMD_UDPCSUMV2 0x80000000 660#define RL_TDESC_CMD_TCPCSUMV2 0x40000000 661#define RL_TDESC_CMD_IPCSUMV2 0x20000000 662#define RL_TDESC_CMD_MSSVALV2 0x1FFC0000 663#define RL_TDESC_CMD_MSSVALV2_SHIFT 18 664 665/* 666 * Error bits are valid only on the last descriptor of a frame 667 * (i.e. RL_TDESC_CMD_EOF == 1) 668 */ 669 670#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 671#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 672#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 673#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 674#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 675#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 676#define RL_TDESC_STAT_OWN 0x80000000 677 678/* 679 * RX descriptor cmd/vlan definitions 680 */ 681 682#define RL_RDESC_CMD_EOR 0x40000000 683#define RL_RDESC_CMD_OWN 0x80000000 684#define RL_RDESC_CMD_BUFLEN 0x00001FFF 685 686#define RL_RDESC_STAT_OWN 0x80000000 687#define RL_RDESC_STAT_EOR 0x40000000 688#define RL_RDESC_STAT_SOF 0x20000000 689#define RL_RDESC_STAT_EOF 0x10000000 690#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 691#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 692#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 693#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 694#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 695#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 696#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 697#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 698#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 699#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 700#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 701#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 702#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 703#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 704#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 705#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 706#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 707#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 708#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 709 RL_RDESC_STAT_CRCERR) 710 711#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 712 (rl_vlandata valid)*/ 713#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 714/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 715#define RL_RDESC_IPV6 0x80000000 716#define RL_RDESC_IPV4 0x40000000 717 718#define RL_PROTOID_NONIP 0x00000000 719#define RL_PROTOID_TCPIP 0x00010000 720#define RL_PROTOID_UDPIP 0x00020000 721#define RL_PROTOID_IP 0x00030000 722#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 723 RL_PROTOID_TCPIP) 724#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 725 RL_PROTOID_UDPIP) 726 727/* 728 * Statistics counter structure (8139C+ and 8169 only) 729 */ 730struct rl_stats { 731 uint64_t rl_tx_pkts; 732 uint64_t rl_rx_pkts; 733 uint64_t rl_tx_errs; 734 uint32_t rl_rx_errs; 735 uint16_t rl_missed_pkts; 736 uint16_t rl_rx_framealign_errs; 737 uint32_t rl_tx_onecoll; 738 uint32_t rl_tx_multicolls; 739 uint64_t rl_rx_ucasts; 740 uint64_t rl_rx_bcasts; 741 uint32_t rl_rx_mcasts; 742 uint16_t rl_tx_aborts; 743 uint16_t rl_rx_underruns; 744}; 745 746/* 747 * Rx/Tx descriptor parameters (8139C+ and 8169 only) 748 * 749 * 8139C+ 750 * Number of descriptors supported : up to 64 751 * Descriptor alignment : 256 bytes 752 * Tx buffer : At least 4 bytes in length. 753 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 754 * 755 * 8169 756 * Number of descriptors supported : up to 1024 757 * Descriptor alignment : 256 bytes 758 * Tx buffer : At least 4 bytes in length. 759 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 760 */ 761#ifndef __NO_STRICT_ALIGNMENT 762#define RE_FIXUP_RX 1 763#endif 764 765#define RL_8169_TX_DESC_CNT 256 766#define RL_8169_RX_DESC_CNT 256 767#define RL_8139_TX_DESC_CNT 64 768#define RL_8139_RX_DESC_CNT 64 769#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT 770#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT 771#define RL_RX_JUMBO_DESC_CNT RL_RX_DESC_CNT 772#define RL_NTXSEGS 32 773 774#define RL_RING_ALIGN 256 775#define RL_DUMP_ALIGN 64 776#define RL_IFQ_MAXLEN 512 777#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 778#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 779#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1)) 780#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 781#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 782#define RL_PKTSZ(x) ((x)/* >> 3*/) 783#ifdef RE_FIXUP_RX 784#define RE_ETHER_ALIGN sizeof(uint64_t) 785#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 786#else 787#define RE_ETHER_ALIGN 0 788#define RE_RX_DESC_BUFLEN MCLBYTES 789#endif 790 791#define RL_MSI_MESSAGES 1 792 793#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 794#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 795 796/* 797 * The number of bits reserved for MSS in RealTek controllers is 798 * 11bits. This limits the maximum interface MTU size in TSO case 799 * as upper stack should not generate TCP segments with MSS greater 800 * than the limit. 801 */ 802#define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN) 803 804/* see comment in dev/re/if_re.c */ 805#define RL_JUMBO_FRAMELEN 7440 806#define RL_JUMBO_MTU \ 807 (RL_JUMBO_FRAMELEN-ETHER_VLAN_ENCAP_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 808#define RL_JUMBO_MTU_6K \ 809 ((6 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 810#define RL_JUMBO_MTU_9K \ 811 ((9 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 812#define RL_MTU \ 813 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 814 815struct rl_txdesc { 816 struct mbuf *tx_m; 817 bus_dmamap_t tx_dmamap; 818}; 819 820struct rl_rxdesc { 821 struct mbuf *rx_m; 822 bus_dmamap_t rx_dmamap; 823 bus_size_t rx_size; 824}; 825 826struct rl_list_data { 827 struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT]; 828 struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT]; 829 struct rl_rxdesc rl_jrx_desc[RL_RX_JUMBO_DESC_CNT]; 830 int rl_tx_desc_cnt; 831 int rl_rx_desc_cnt; 832 int rl_tx_prodidx; 833 int rl_rx_prodidx; 834 int rl_tx_considx; 835 int rl_tx_free; 836 bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */ 837 bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */ 838 bus_dma_tag_t rl_jrx_mtag; /* mbuf RX mapping tag */ 839 bus_dmamap_t rl_rx_sparemap; 840 bus_dmamap_t rl_jrx_sparemap; 841 bus_dma_tag_t rl_stag; /* stats mapping tag */ 842 bus_dmamap_t rl_smap; /* stats map */ 843 struct rl_stats *rl_stats; 844 bus_addr_t rl_stats_addr; 845 bus_dma_tag_t rl_rx_list_tag; 846 bus_dmamap_t rl_rx_list_map; 847 struct rl_desc *rl_rx_list; 848 bus_addr_t rl_rx_list_addr; 849 bus_dma_tag_t rl_tx_list_tag; 850 bus_dmamap_t rl_tx_list_map; 851 struct rl_desc *rl_tx_list; 852 bus_addr_t rl_tx_list_addr; 853}; 854 855enum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE }; 856 857struct rl_softc { 858 struct ifnet *rl_ifp; /* interface info */ 859 bus_space_handle_t rl_bhandle; /* bus space handle */ 860 bus_space_tag_t rl_btag; /* bus space tag */ 861 device_t rl_dev; 862 struct resource *rl_res; 863 int rl_res_id; 864 int rl_res_type; 865 struct resource *rl_res_pba; 866 struct resource *rl_irq[RL_MSI_MESSAGES]; 867 void *rl_intrhand[RL_MSI_MESSAGES]; 868 device_t rl_miibus; 869 bus_dma_tag_t rl_parent_tag; 870 uint8_t rl_type; 871 const struct rl_hwrev *rl_hwrev; 872 int rl_eecmd_read; 873 int rl_eewidth; 874 int rl_expcap; 875 int rl_txthresh; 876 struct rl_chain_data rl_cdata; 877 struct rl_list_data rl_ldata; 878 struct callout rl_stat_callout; 879 int rl_watchdog_timer; 880 struct mtx rl_mtx; 881 struct mbuf *rl_head; 882 struct mbuf *rl_tail; 883 uint32_t rl_rxlenmask; 884 int rl_testmode; 885 int rl_if_flags; 886 int rl_twister_enable; 887 enum rl_twist rl_twister; 888 int rl_twist_row; 889 int rl_twist_col; 890 int suspended; /* 0 = normal 1 = suspended */ 891#ifdef DEVICE_POLLING 892 int rxcycles; 893#endif 894 895 struct task rl_inttask; 896 897 int rl_txstart; 898 int rl_int_rx_act; 899 int rl_int_rx_mod; 900 uint32_t rl_flags; 901#define RL_FLAG_MSI 0x00000001 902#define RL_FLAG_AUTOPAD 0x00000002 903#define RL_FLAG_PHYWAKE_PM 0x00000004 904#define RL_FLAG_PHYWAKE 0x00000008 905#define RL_FLAG_JUMBOV2 0x00000010 906#define RL_FLAG_PAR 0x00000020 907#define RL_FLAG_DESCV2 0x00000040 908#define RL_FLAG_MACSTAT 0x00000080 909#define RL_FLAG_FASTETHER 0x00000100 910#define RL_FLAG_CMDSTOP 0x00000200 911#define RL_FLAG_MACRESET 0x00000400 912#define RL_FLAG_MSIX 0x00000800 913#define RL_FLAG_WOLRXENB 0x00001000 914#define RL_FLAG_MACSLEEP 0x00002000 915#define RL_FLAG_WAIT_TXPOLL 0x00004000 916#define RL_FLAG_CMDSTOP_WAIT_TXQ 0x00008000 917#define RL_FLAG_WOL_MANLINK 0x00010000 918#define RL_FLAG_PCIE 0x40000000 919#define RL_FLAG_LINK 0x80000000 920}; 921 922#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 923#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 924#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 925 926/* 927 * register space access macros 928 */ 929#define CSR_WRITE_STREAM_4(sc, reg, val) \ 930 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 931#define CSR_WRITE_4(sc, reg, val) \ 932 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 933#define CSR_WRITE_2(sc, reg, val) \ 934 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 935#define CSR_WRITE_1(sc, reg, val) \ 936 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 937 938#define CSR_READ_4(sc, reg) \ 939 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 940#define CSR_READ_2(sc, reg) \ 941 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 942#define CSR_READ_1(sc, reg) \ 943 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 944 945#define CSR_BARRIER(sc, reg, length, flags) \ 946 bus_space_barrier(sc->rl_btag, sc->rl_bhandle, reg, length, flags) 947 948#define CSR_SETBIT_1(sc, offset, val) \ 949 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 950 951#define CSR_CLRBIT_1(sc, offset, val) \ 952 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 953 954#define CSR_SETBIT_2(sc, offset, val) \ 955 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 956 957#define CSR_CLRBIT_2(sc, offset, val) \ 958 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 959 960#define CSR_SETBIT_4(sc, offset, val) \ 961 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 962 963#define CSR_CLRBIT_4(sc, offset, val) \ 964 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 965 966#define RL_TIMEOUT 1000 967#define RL_PHY_TIMEOUT 2000 968 969/* 970 * General constants that are fun to know. 971 * 972 * RealTek PCI vendor ID 973 */ 974#define RT_VENDORID 0x10EC 975 976/* 977 * RealTek chip device IDs. 978 */ 979#define RT_DEVICEID_8139D 0x8039 980#define RT_DEVICEID_8129 0x8129 981#define RT_DEVICEID_8101E 0x8136 982#define RT_DEVICEID_8138 0x8138 983#define RT_DEVICEID_8139 0x8139 984#define RT_DEVICEID_8169SC 0x8167 985#define RT_DEVICEID_8168 0x8168 986#define RT_DEVICEID_8169 0x8169 987#define RT_DEVICEID_8100 0x8100 988 989#define RT_REVID_8139CPLUS 0x20 990 991/* 992 * Accton PCI vendor ID 993 */ 994#define ACCTON_VENDORID 0x1113 995 996/* 997 * Accton MPX 5030/5038 device ID. 998 */ 999#define ACCTON_DEVICEID_5030 0x1211 1000 1001/* 1002 * Nortel PCI vendor ID 1003 */ 1004#define NORTEL_VENDORID 0x126C 1005 1006/* 1007 * Delta Electronics Vendor ID. 1008 */ 1009#define DELTA_VENDORID 0x1500 1010 1011/* 1012 * Delta device IDs. 1013 */ 1014#define DELTA_DEVICEID_8139 0x1360 1015 1016/* 1017 * Addtron vendor ID. 1018 */ 1019#define ADDTRON_VENDORID 0x4033 1020 1021/* 1022 * Addtron device IDs. 1023 */ 1024#define ADDTRON_DEVICEID_8139 0x1360 1025 1026/* 1027 * D-Link vendor ID. 1028 */ 1029#define DLINK_VENDORID 0x1186 1030 1031/* 1032 * D-Link DFE-530TX+ device ID 1033 */ 1034#define DLINK_DEVICEID_530TXPLUS 0x1300 1035 1036/* 1037 * D-Link DFE-5280T device ID 1038 */ 1039#define DLINK_DEVICEID_528T 0x4300 1040#define DLINK_DEVICEID_530T_REVC 0x4302 1041 1042/* 1043 * D-Link DFE-690TXD device ID 1044 */ 1045#define DLINK_DEVICEID_690TXD 0x1340 1046 1047/* 1048 * Corega K.K vendor ID 1049 */ 1050#define COREGA_VENDORID 0x1259 1051 1052/* 1053 * Corega FEther CB-TXD device ID 1054 */ 1055#define COREGA_DEVICEID_FETHERCBTXD 0xa117 1056 1057/* 1058 * Corega FEtherII CB-TXD device ID 1059 */ 1060#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 1061 1062/* 1063 * Corega CG-LAPCIGT device ID 1064 */ 1065#define COREGA_DEVICEID_CGLAPCIGT 0xc107 1066 1067/* 1068 * Linksys vendor ID 1069 */ 1070#define LINKSYS_VENDORID 0x1737 1071 1072/* 1073 * Linksys EG1032 device ID 1074 */ 1075#define LINKSYS_DEVICEID_EG1032 0x1032 1076 1077/* 1078 * Linksys EG1032 rev 3 sub-device ID 1079 */ 1080#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 1081 1082/* 1083 * Peppercon vendor ID 1084 */ 1085#define PEPPERCON_VENDORID 0x1743 1086 1087/* 1088 * Peppercon ROL-F device ID 1089 */ 1090#define PEPPERCON_DEVICEID_ROLF 0x8139 1091 1092/* 1093 * Planex Communications, Inc. vendor ID 1094 */ 1095#define PLANEX_VENDORID 0x14ea 1096 1097/* 1098 * Planex FNW-3603-TX device ID 1099 */ 1100#define PLANEX_DEVICEID_FNW3603TX 0xab06 1101 1102/* 1103 * Planex FNW-3800-TX device ID 1104 */ 1105#define PLANEX_DEVICEID_FNW3800TX 0xab07 1106 1107/* 1108 * LevelOne vendor ID 1109 */ 1110#define LEVEL1_VENDORID 0x018A 1111 1112/* 1113 * LevelOne FPC-0106TX devide ID 1114 */ 1115#define LEVEL1_DEVICEID_FPC0106TX 0x0106 1116 1117/* 1118 * Compaq vendor ID 1119 */ 1120#define CP_VENDORID 0x021B 1121 1122/* 1123 * Edimax vendor ID 1124 */ 1125#define EDIMAX_VENDORID 0x13D1 1126 1127/* 1128 * Edimax EP-4103DL cardbus device ID 1129 */ 1130#define EDIMAX_DEVICEID_EP4103DL 0xAB06 1131 1132/* US Robotics vendor ID */ 1133 1134#define USR_VENDORID 0x16EC 1135 1136/* US Robotics 997902 device ID */ 1137 1138#define USR_DEVICEID_997902 0x0116 1139