if_rlreg.h revision 226995
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_rlreg.h 226995 2011-11-01 16:13:59Z marius $ 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 41#define RL_IDR3 0x0003 42#define RL_IDR4 0x0004 43#define RL_IDR5 0x0005 44 /* 0006-0007 reserved */ 45#define RL_MAR0 0x0008 /* Multicast hash table */ 46#define RL_MAR1 0x0009 47#define RL_MAR2 0x000A 48#define RL_MAR3 0x000B 49#define RL_MAR4 0x000C 50#define RL_MAR5 0x000D 51#define RL_MAR6 0x000E 52#define RL_MAR7 0x000F 53 54#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 58 59#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 63 64#define RL_RXADDR 0x0030 /* RX ring start address */ 65#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67#define RL_COMMAND 0x0037 /* command register */ 68#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70#define RL_IMR 0x003C /* interrupt mask register */ 71#define RL_ISR 0x003E /* interrupt status register */ 72#define RL_TXCFG 0x0040 /* transmit config */ 73#define RL_RXCFG 0x0044 /* receive config */ 74#define RL_TIMERCNT 0x0048 /* timer count register */ 75#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76#define RL_EECMD 0x0050 /* EEPROM command register */ 77#define RL_CFG0 0x0051 /* config register #0 */ 78#define RL_CFG1 0x0052 /* config register #1 */ 79#define RL_CFG2 0x0053 /* config register #2 */ 80#define RL_CFG3 0x0054 /* config register #3 */ 81#define RL_CFG4 0x0055 /* config register #4 */ 82#define RL_CFG5 0x0056 /* config register #5 */ 83 /* 0057 reserved */ 84#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 85 /* 0059-005A reserved */ 86#define RL_MII 0x005A /* 8129 chip only */ 87#define RL_HALTCLK 0x005B 88#define RL_MULTIINTR 0x005C /* multiple interrupt */ 89#define RL_PCIREV 0x005E /* PCI revision value */ 90 /* 005F reserved */ 91#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 92 93/* Direct PHY access registers only available on 8139 */ 94#define RL_BMCR 0x0062 /* PHY basic mode control */ 95#define RL_BMSR 0x0064 /* PHY basic mode status */ 96#define RL_ANAR 0x0066 /* PHY autoneg advert */ 97#define RL_LPAR 0x0068 /* PHY link partner ability */ 98#define RL_ANER 0x006A /* PHY autoneg expansion */ 99 100#define RL_DISCCNT 0x006C /* disconnect counter */ 101#define RL_FALSECAR 0x006E /* false carrier counter */ 102#define RL_NWAYTST 0x0070 /* NWAY test register */ 103#define RL_RX_ER 0x0072 /* RX_ER counter */ 104#define RL_CSCFG 0x0074 /* CS configuration register */ 105 106/* 107 * When operating in special C+ mode, some of the registers in an 108 * 8139C+ chip have different definitions. These are also used for 109 * the 8169 gigE chip. 110 */ 111#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 112#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 113#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 114#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 115#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 116#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 117#define RL_CFG2 0x0053 118#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 119#define RL_TXSTART 0x00D9 /* 8 bits */ 120#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 121#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 122#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 123#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 124 125/* 126 * Registers specific to the 8169 gigE chip 127 */ 128#define RL_GTXSTART 0x0038 /* 8 bits */ 129#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 130#define RL_PHYAR 0x0060 131#define RL_TBICSR 0x0064 132#define RL_TBI_ANAR 0x0068 133#define RL_TBI_LPAR 0x006A 134#define RL_GMEDIASTAT 0x006C /* 8 bits */ 135#define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */ 136#define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */ 137#define RL_PMCH 0x006F /* 8 bits */ 138#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 139#define RL_INTRMOD 0x00E2 /* 16 bits */ 140 141/* 142 * TX config register bits 143 */ 144#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 145#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 146#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 147#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 148#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 149#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 150#define RL_TXCFG_HWREV 0x7CC00000 151 152#define RL_LOOPTEST_OFF 0x00000000 153#define RL_LOOPTEST_ON 0x00020000 154#define RL_LOOPTEST_ON_CPLUS 0x00060000 155 156/* Known revision codes. */ 157 158#define RL_HWREV_8169 0x00000000 159#define RL_HWREV_8169S 0x00800000 160#define RL_HWREV_8110S 0x04000000 161#define RL_HWREV_8169_8110SB 0x10000000 162#define RL_HWREV_8169_8110SC 0x18000000 163#define RL_HWREV_8401E 0x24000000 164#define RL_HWREV_8102EL 0x24800000 165#define RL_HWREV_8102EL_SPIN1 0x24C00000 166#define RL_HWREV_8168D 0x28000000 167#define RL_HWREV_8168DP 0x28800000 168#define RL_HWREV_8168E 0x2C000000 169#define RL_HWREV_8168E_VL 0x2C800000 170#define RL_HWREV_8168B_SPIN1 0x30000000 171#define RL_HWREV_8100E 0x30800000 172#define RL_HWREV_8101E 0x34000000 173#define RL_HWREV_8102E 0x34800000 174#define RL_HWREV_8103E 0x34C00000 175#define RL_HWREV_8168B_SPIN2 0x38000000 176#define RL_HWREV_8168B_SPIN3 0x38400000 177#define RL_HWREV_8168C 0x3C000000 178#define RL_HWREV_8168C_SPIN2 0x3C400000 179#define RL_HWREV_8168CP 0x3C800000 180#define RL_HWREV_8105E 0x40800000 181#define RL_HWREV_8139 0x60000000 182#define RL_HWREV_8139A 0x70000000 183#define RL_HWREV_8139AG 0x70800000 184#define RL_HWREV_8139B 0x78000000 185#define RL_HWREV_8130 0x7C000000 186#define RL_HWREV_8139C 0x74000000 187#define RL_HWREV_8139D 0x74400000 188#define RL_HWREV_8139CPLUS 0x74800000 189#define RL_HWREV_8101 0x74C00000 190#define RL_HWREV_8100 0x78800000 191#define RL_HWREV_8169_8110SBL 0x7CC00000 192#define RL_HWREV_8169_8110SCE 0x98000000 193 194#define RL_TXDMA_16BYTES 0x00000000 195#define RL_TXDMA_32BYTES 0x00000100 196#define RL_TXDMA_64BYTES 0x00000200 197#define RL_TXDMA_128BYTES 0x00000300 198#define RL_TXDMA_256BYTES 0x00000400 199#define RL_TXDMA_512BYTES 0x00000500 200#define RL_TXDMA_1024BYTES 0x00000600 201#define RL_TXDMA_2048BYTES 0x00000700 202 203/* 204 * Transmit descriptor status register bits. 205 */ 206#define RL_TXSTAT_LENMASK 0x00001FFF 207#define RL_TXSTAT_OWN 0x00002000 208#define RL_TXSTAT_TX_UNDERRUN 0x00004000 209#define RL_TXSTAT_TX_OK 0x00008000 210#define RL_TXSTAT_EARLY_THRESH 0x003F0000 211#define RL_TXSTAT_COLLCNT 0x0F000000 212#define RL_TXSTAT_CARR_HBEAT 0x10000000 213#define RL_TXSTAT_OUTOFWIN 0x20000000 214#define RL_TXSTAT_TXABRT 0x40000000 215#define RL_TXSTAT_CARRLOSS 0x80000000 216 217/* 218 * Interrupt status register bits. 219 */ 220#define RL_ISR_RX_OK 0x0001 221#define RL_ISR_RX_ERR 0x0002 222#define RL_ISR_TX_OK 0x0004 223#define RL_ISR_TX_ERR 0x0008 224#define RL_ISR_RX_OVERRUN 0x0010 225#define RL_ISR_PKT_UNDERRUN 0x0020 226#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 227#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 228#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 229#define RL_ISR_SWI 0x0100 /* C+ only */ 230#define RL_ISR_CABLE_LEN_CHGD 0x2000 231#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 232#define RL_ISR_TIMEOUT_EXPIRED 0x4000 233#define RL_ISR_SYSTEM_ERR 0x8000 234 235#define RL_INTRS \ 236 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 237 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 238 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 239 240#ifdef RE_TX_MODERATION 241#define RL_INTRS_CPLUS \ 242 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 243 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 244 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 245#else 246#define RL_INTRS_CPLUS \ 247 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 248 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 249 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 250#endif 251 252/* 253 * Media status register. (8139 only) 254 */ 255#define RL_MEDIASTAT_RXPAUSE 0x01 256#define RL_MEDIASTAT_TXPAUSE 0x02 257#define RL_MEDIASTAT_LINK 0x04 258#define RL_MEDIASTAT_SPEED10 0x08 259#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 260#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 261 262/* 263 * Receive config register. 264 */ 265#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 266#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 267#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 268#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 269#define RL_RXCFG_RX_RUNT 0x00000010 270#define RL_RXCFG_RX_ERRPKT 0x00000020 271#define RL_RXCFG_WRAP 0x00000080 272#define RL_RXCFG_MAXDMA 0x00000700 273#define RL_RXCFG_BUFSZ 0x00001800 274#define RL_RXCFG_FIFOTHRESH 0x0000E000 275#define RL_RXCFG_EARLYTHRESH 0x07000000 276 277#define RL_RXDMA_16BYTES 0x00000000 278#define RL_RXDMA_32BYTES 0x00000100 279#define RL_RXDMA_64BYTES 0x00000200 280#define RL_RXDMA_128BYTES 0x00000300 281#define RL_RXDMA_256BYTES 0x00000400 282#define RL_RXDMA_512BYTES 0x00000500 283#define RL_RXDMA_1024BYTES 0x00000600 284#define RL_RXDMA_UNLIMITED 0x00000700 285 286#define RL_RXBUF_8 0x00000000 287#define RL_RXBUF_16 0x00000800 288#define RL_RXBUF_32 0x00001000 289#define RL_RXBUF_64 0x00001800 290 291#define RL_RXFIFO_16BYTES 0x00000000 292#define RL_RXFIFO_32BYTES 0x00002000 293#define RL_RXFIFO_64BYTES 0x00004000 294#define RL_RXFIFO_128BYTES 0x00006000 295#define RL_RXFIFO_256BYTES 0x00008000 296#define RL_RXFIFO_512BYTES 0x0000A000 297#define RL_RXFIFO_1024BYTES 0x0000C000 298#define RL_RXFIFO_NOTHRESH 0x0000E000 299 300/* 301 * Bits in RX status header (included with RX'ed packet 302 * in ring buffer). 303 */ 304#define RL_RXSTAT_RXOK 0x00000001 305#define RL_RXSTAT_ALIGNERR 0x00000002 306#define RL_RXSTAT_CRCERR 0x00000004 307#define RL_RXSTAT_GIANT 0x00000008 308#define RL_RXSTAT_RUNT 0x00000010 309#define RL_RXSTAT_BADSYM 0x00000020 310#define RL_RXSTAT_BROAD 0x00002000 311#define RL_RXSTAT_INDIV 0x00004000 312#define RL_RXSTAT_MULTI 0x00008000 313#define RL_RXSTAT_LENMASK 0xFFFF0000 314 315#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 316/* 317 * Command register. 318 */ 319#define RL_CMD_EMPTY_RXBUF 0x0001 320#define RL_CMD_TX_ENB 0x0004 321#define RL_CMD_RX_ENB 0x0008 322#define RL_CMD_RESET 0x0010 323#define RL_CMD_STOPREQ 0x0080 324 325/* 326 * Twister register values. These are completely undocumented and derived 327 * from public sources. 328 */ 329#define RL_CSCFG_LINK_OK 0x0400 330#define RL_CSCFG_CHANGE 0x0800 331#define RL_CSCFG_STATUS 0xf000 332#define RL_CSCFG_ROW3 0x7000 333#define RL_CSCFG_ROW2 0x3000 334#define RL_CSCFG_ROW1 0x1000 335#define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0 336#define RL_CSCFG_LINK_DOWN_CMD 0xf3c0 337 338#define RL_NWAYTST_RESET 0 339#define RL_NWAYTST_CBL_TEST 0x20 340 341#define RL_PARA78 0x78 342#define RL_PARA78_DEF 0x78fa8388 343#define RL_PARA7C 0x7C 344#define RL_PARA7C_DEF 0xcb38de43 345#define RL_PARA7C_RETUNE 0xfb38de03 346/* 347 * EEPROM control register 348 */ 349#define RL_EE_DATAOUT 0x01 /* Data out */ 350#define RL_EE_DATAIN 0x02 /* Data in */ 351#define RL_EE_CLK 0x04 /* clock */ 352#define RL_EE_SEL 0x08 /* chip select */ 353#define RL_EE_MODE (0x40|0x80) 354 355#define RL_EEMODE_OFF 0x00 356#define RL_EEMODE_AUTOLOAD 0x40 357#define RL_EEMODE_PROGRAM 0x80 358#define RL_EEMODE_WRITECFG (0x80|0x40) 359 360/* 9346 EEPROM commands */ 361#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 362#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 363 364#define RL_9346_WRITE 0x5 365#define RL_9346_READ 0x6 366#define RL_9346_ERASE 0x7 367#define RL_9346_EWEN 0x4 368#define RL_9346_EWEN_ADDR 0x30 369#define RL_9456_EWDS 0x4 370#define RL_9346_EWDS_ADDR 0x00 371 372#define RL_EECMD_WRITE 0x140 373#define RL_EECMD_READ_6BIT 0x180 374#define RL_EECMD_READ_8BIT 0x600 375#define RL_EECMD_ERASE 0x1c0 376 377#define RL_EE_ID 0x00 378#define RL_EE_PCI_VID 0x01 379#define RL_EE_PCI_DID 0x02 380/* Location of station address inside EEPROM */ 381#define RL_EE_EADDR 0x07 382 383/* 384 * MII register (8129 only) 385 */ 386#define RL_MII_CLK 0x01 387#define RL_MII_DATAIN 0x02 388#define RL_MII_DATAOUT 0x04 389#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 390 391/* 392 * Config 0 register 393 */ 394#define RL_CFG0_ROM0 0x01 395#define RL_CFG0_ROM1 0x02 396#define RL_CFG0_ROM2 0x04 397#define RL_CFG0_PL0 0x08 398#define RL_CFG0_PL1 0x10 399#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 400#define RL_CFG0_PCS 0x40 401#define RL_CFG0_SCR 0x80 402 403/* 404 * Config 1 register 405 */ 406#define RL_CFG1_PWRDWN 0x01 407#define RL_CFG1_PME 0x01 408#define RL_CFG1_SLEEP 0x02 409#define RL_CFG1_VPDEN 0x02 410#define RL_CFG1_IOMAP 0x04 411#define RL_CFG1_MEMMAP 0x08 412#define RL_CFG1_RSVD 0x10 413#define RL_CFG1_LWACT 0x10 414#define RL_CFG1_DRVLOAD 0x20 415#define RL_CFG1_LED0 0x40 416#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 417#define RL_CFG1_LED1 0x80 418 419/* 420 * Config 2 register 421 */ 422#define RL_CFG2_PCI33MHZ 0x00 423#define RL_CFG2_PCI66MHZ 0x01 424#define RL_CFG2_PCI64BIT 0x08 425#define RL_CFG2_AUXPWR 0x10 426#define RL_CFG2_MSI 0x20 427 428/* 429 * Config 3 register 430 */ 431#define RL_CFG3_GRANTSEL 0x80 432#define RL_CFG3_WOL_MAGIC 0x20 433#define RL_CFG3_WOL_LINK 0x10 434#define RL_CFG3_JUMBO_EN0 0x04 /* RTL8168C or later. */ 435#define RL_CFG3_FAST_B2B 0x01 436 437/* 438 * Config 4 register 439 */ 440#define RL_CFG4_LWPTN 0x04 441#define RL_CFG4_LWPME 0x10 442#define RL_CFG4_JUMBO_EN1 0x02 /* RTL8168C or later. */ 443 444/* 445 * Config 5 register 446 */ 447#define RL_CFG5_WOL_BCAST 0x40 448#define RL_CFG5_WOL_MCAST 0x20 449#define RL_CFG5_WOL_UCAST 0x10 450#define RL_CFG5_WOL_LANWAKE 0x02 451#define RL_CFG5_PME_STS 0x01 452 453/* 454 * 8139C+ register definitions 455 */ 456 457/* RL_DUMPSTATS_LO register */ 458 459#define RL_DUMPSTATS_START 0x00000008 460 461/* Transmit start register */ 462 463#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 464#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 465#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 466 467/* 468 * Config 2 register, 8139C+/8169/8169S/8110S only 469 */ 470#define RL_CFG2_BUSFREQ 0x07 471#define RL_CFG2_BUSWIDTH 0x08 472#define RL_CFG2_AUXPWRSTS 0x10 473 474#define RL_BUSFREQ_33MHZ 0x00 475#define RL_BUSFREQ_66MHZ 0x01 476 477#define RL_BUSWIDTH_32BITS 0x00 478#define RL_BUSWIDTH_64BITS 0x08 479 480/* C+ mode command register */ 481 482#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 483#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 484#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 485#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 486#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 487#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 488#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 489#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 490#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 491#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 492#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 493#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 494#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 495#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 496#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 497 498/* C+ early transmit threshold */ 499 500#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 501 502/* Timer interrupt register */ 503#define RL_TIMERINT_8169_VAL 0x00001FFF 504#define RL_TIMER_MIN 0 505#define RL_TIMER_MAX 65 /* 65.528us */ 506#define RL_TIMER_DEFAULT RL_TIMER_MAX 507#define RL_TIMER_PCIE_CLK 125 /* 125MHZ */ 508#define RL_USECS(x) ((x) * RL_TIMER_PCIE_CLK) 509 510/* 511 * Gigabit PHY access register (8169 only) 512 */ 513 514#define RL_PHYAR_PHYDATA 0x0000FFFF 515#define RL_PHYAR_PHYREG 0x001F0000 516#define RL_PHYAR_BUSY 0x80000000 517 518/* 519 * Gigabit media status (8169 only) 520 */ 521#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 522#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 523#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 524#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 525#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 526#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 527#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 528#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 529 530/* 531 * The RealTek doesn't use a fragment-based descriptor mechanism. 532 * Instead, there are only four register sets, each or which represents 533 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 534 * packet buffer (32-bit aligned!) and we place the buffer addresses in 535 * the registers so the chip knows where they are. 536 * 537 * We can sort of kludge together the same kind of buffer management 538 * used in previous drivers, but we have to do buffer copies almost all 539 * the time, so it doesn't really buy us much. 540 * 541 * For reception, there's just one large buffer where the chip stores 542 * all received packets. 543 */ 544 545#define RL_RX_BUF_SZ RL_RXBUF_64 546#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 547#define RL_TX_LIST_CNT 4 548#define RL_MIN_FRAMELEN 60 549#define RL_TX_8139_BUF_ALIGN 4 550#define RL_RX_8139_BUF_ALIGN 8 551#define RL_RX_8139_BUF_RESERVE sizeof(int64_t) 552#define RL_RX_8139_BUF_GUARD_SZ \ 553 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE) 554#define RL_TXTHRESH(x) ((x) << 11) 555#define RL_TX_THRESH_INIT 96 556#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 557#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 558#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 559 560#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 561#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 562 563#define RL_ETHER_ALIGN 2 564 565/* 566 * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets. 567 */ 568#define RL_IP4CSUMTX_MINLEN 28 569#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 570 571struct rl_chain_data { 572 uint16_t cur_rx; 573 uint8_t *rl_rx_buf; 574 uint8_t *rl_rx_buf_ptr; 575 576 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 577 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 578 bus_dma_tag_t rl_tx_tag; 579 bus_dma_tag_t rl_rx_tag; 580 bus_dmamap_t rl_rx_dmamap; 581 bus_addr_t rl_rx_buf_paddr; 582 uint8_t last_tx; 583 uint8_t cur_tx; 584}; 585 586#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 587#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 588#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 589#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 590#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 591#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 592#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 593#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 594#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 595 596struct rl_type { 597 uint16_t rl_vid; 598 uint16_t rl_did; 599 int rl_basetype; 600 const char *rl_name; 601}; 602 603struct rl_hwrev { 604 uint32_t rl_rev; 605 int rl_type; 606 const char *rl_desc; 607 int rl_max_mtu; 608}; 609 610#define RL_8129 1 611#define RL_8139 2 612#define RL_8139CPLUS 3 613#define RL_8169 4 614 615#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 616 (x)->rl_type == RL_8169) 617 618/* 619 * The 8139C+ and 8160 gigE chips support descriptor-based TX 620 * and RX. In fact, they even support TCP large send. Descriptors 621 * must be allocated in contiguous blocks that are aligned on a 622 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 623 */ 624 625/* 626 * RX/TX descriptor definition. When large send mode is enabled, the 627 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 628 * the checksum offload bits are disabled. The structure layout is 629 * the same for RX and TX descriptors 630 */ 631 632struct rl_desc { 633 uint32_t rl_cmdstat; 634 uint32_t rl_vlanctl; 635 uint32_t rl_bufaddr_lo; 636 uint32_t rl_bufaddr_hi; 637}; 638 639#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 640#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 641#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 642#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 643#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 644#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 645#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 646#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 647#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 648#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 649#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 650 651#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 652#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 653/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 654#define RL_TDESC_CMD_UDPCSUMV2 0x80000000 655#define RL_TDESC_CMD_TCPCSUMV2 0x40000000 656#define RL_TDESC_CMD_IPCSUMV2 0x20000000 657#define RL_TDESC_CMD_MSSVALV2 0x1FFC0000 658#define RL_TDESC_CMD_MSSVALV2_SHIFT 18 659 660/* 661 * Error bits are valid only on the last descriptor of a frame 662 * (i.e. RL_TDESC_CMD_EOF == 1) 663 */ 664 665#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 666#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 667#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 668#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 669#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 670#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 671#define RL_TDESC_STAT_OWN 0x80000000 672 673/* 674 * RX descriptor cmd/vlan definitions 675 */ 676 677#define RL_RDESC_CMD_EOR 0x40000000 678#define RL_RDESC_CMD_OWN 0x80000000 679#define RL_RDESC_CMD_BUFLEN 0x00001FFF 680 681#define RL_RDESC_STAT_OWN 0x80000000 682#define RL_RDESC_STAT_EOR 0x40000000 683#define RL_RDESC_STAT_SOF 0x20000000 684#define RL_RDESC_STAT_EOF 0x10000000 685#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 686#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 687#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 688#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 689#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 690#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 691#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 692#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 693#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 694#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 695#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 696#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 697#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 698#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 699#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 700#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 701#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 702#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 703#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 704 RL_RDESC_STAT_CRCERR) 705 706#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 707 (rl_vlandata valid)*/ 708#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 709/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 710#define RL_RDESC_IPV6 0x80000000 711#define RL_RDESC_IPV4 0x40000000 712 713#define RL_PROTOID_NONIP 0x00000000 714#define RL_PROTOID_TCPIP 0x00010000 715#define RL_PROTOID_UDPIP 0x00020000 716#define RL_PROTOID_IP 0x00030000 717#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 718 RL_PROTOID_TCPIP) 719#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 720 RL_PROTOID_UDPIP) 721 722/* 723 * Statistics counter structure (8139C+ and 8169 only) 724 */ 725struct rl_stats { 726 uint64_t rl_tx_pkts; 727 uint64_t rl_rx_pkts; 728 uint64_t rl_tx_errs; 729 uint32_t rl_rx_errs; 730 uint16_t rl_missed_pkts; 731 uint16_t rl_rx_framealign_errs; 732 uint32_t rl_tx_onecoll; 733 uint32_t rl_tx_multicolls; 734 uint64_t rl_rx_ucasts; 735 uint64_t rl_rx_bcasts; 736 uint32_t rl_rx_mcasts; 737 uint16_t rl_tx_aborts; 738 uint16_t rl_rx_underruns; 739}; 740 741/* 742 * Rx/Tx descriptor parameters (8139C+ and 8169 only) 743 * 744 * 8139C+ 745 * Number of descriptors supported : up to 64 746 * Descriptor alignment : 256 bytes 747 * Tx buffer : At least 4 bytes in length. 748 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 749 * 750 * 8169 751 * Number of descriptors supported : up to 1024 752 * Descriptor alignment : 256 bytes 753 * Tx buffer : At least 4 bytes in length. 754 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 755 */ 756#ifndef __NO_STRICT_ALIGNMENT 757#define RE_FIXUP_RX 1 758#endif 759 760#define RL_8169_TX_DESC_CNT 256 761#define RL_8169_RX_DESC_CNT 256 762#define RL_8139_TX_DESC_CNT 64 763#define RL_8139_RX_DESC_CNT 64 764#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT 765#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT 766#define RL_RX_JUMBO_DESC_CNT RL_RX_DESC_CNT 767#define RL_NTXSEGS 32 768 769#define RL_RING_ALIGN 256 770#define RL_DUMP_ALIGN 64 771#define RL_IFQ_MAXLEN 512 772#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 773#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 774#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1)) 775#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 776#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 777#define RL_PKTSZ(x) ((x)/* >> 3*/) 778#ifdef RE_FIXUP_RX 779#define RE_ETHER_ALIGN sizeof(uint64_t) 780#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 781#else 782#define RE_ETHER_ALIGN 0 783#define RE_RX_DESC_BUFLEN MCLBYTES 784#endif 785 786#define RL_MSI_MESSAGES 1 787 788#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 789#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 790 791/* 792 * The number of bits reserved for MSS in RealTek controllers is 793 * 11bits. This limits the maximum interface MTU size in TSO case 794 * as upper stack should not generate TCP segments with MSS greater 795 * than the limit. 796 */ 797#define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN) 798 799/* see comment in dev/re/if_re.c */ 800#define RL_JUMBO_FRAMELEN 7440 801#define RL_JUMBO_MTU \ 802 (RL_JUMBO_FRAMELEN-ETHER_VLAN_ENCAP_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 803#define RL_JUMBO_MTU_6K \ 804 ((6 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 805#define RL_JUMBO_MTU_9K \ 806 ((9 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 807#define RL_MTU \ 808 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 809 810struct rl_txdesc { 811 struct mbuf *tx_m; 812 bus_dmamap_t tx_dmamap; 813}; 814 815struct rl_rxdesc { 816 struct mbuf *rx_m; 817 bus_dmamap_t rx_dmamap; 818 bus_size_t rx_size; 819}; 820 821struct rl_list_data { 822 struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT]; 823 struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT]; 824 struct rl_rxdesc rl_jrx_desc[RL_RX_JUMBO_DESC_CNT]; 825 int rl_tx_desc_cnt; 826 int rl_rx_desc_cnt; 827 int rl_tx_prodidx; 828 int rl_rx_prodidx; 829 int rl_tx_considx; 830 int rl_tx_free; 831 bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */ 832 bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */ 833 bus_dma_tag_t rl_jrx_mtag; /* mbuf RX mapping tag */ 834 bus_dmamap_t rl_rx_sparemap; 835 bus_dmamap_t rl_jrx_sparemap; 836 bus_dma_tag_t rl_stag; /* stats mapping tag */ 837 bus_dmamap_t rl_smap; /* stats map */ 838 struct rl_stats *rl_stats; 839 bus_addr_t rl_stats_addr; 840 bus_dma_tag_t rl_rx_list_tag; 841 bus_dmamap_t rl_rx_list_map; 842 struct rl_desc *rl_rx_list; 843 bus_addr_t rl_rx_list_addr; 844 bus_dma_tag_t rl_tx_list_tag; 845 bus_dmamap_t rl_tx_list_map; 846 struct rl_desc *rl_tx_list; 847 bus_addr_t rl_tx_list_addr; 848}; 849 850enum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE }; 851 852struct rl_softc { 853 struct ifnet *rl_ifp; /* interface info */ 854 bus_space_handle_t rl_bhandle; /* bus space handle */ 855 bus_space_tag_t rl_btag; /* bus space tag */ 856 device_t rl_dev; 857 struct resource *rl_res; 858 int rl_res_id; 859 int rl_res_type; 860 struct resource *rl_res_pba; 861 struct resource *rl_irq[RL_MSI_MESSAGES]; 862 void *rl_intrhand[RL_MSI_MESSAGES]; 863 device_t rl_miibus; 864 bus_dma_tag_t rl_parent_tag; 865 uint8_t rl_type; 866 const struct rl_hwrev *rl_hwrev; 867 int rl_eecmd_read; 868 int rl_eewidth; 869 int rl_txthresh; 870 struct rl_chain_data rl_cdata; 871 struct rl_list_data rl_ldata; 872 struct callout rl_stat_callout; 873 int rl_watchdog_timer; 874 struct mtx rl_mtx; 875 struct mbuf *rl_head; 876 struct mbuf *rl_tail; 877 uint32_t rl_rxlenmask; 878 int rl_testmode; 879 int rl_if_flags; 880 int rl_twister_enable; 881 enum rl_twist rl_twister; 882 int rl_twist_row; 883 int rl_twist_col; 884 int suspended; /* 0 = normal 1 = suspended */ 885#ifdef DEVICE_POLLING 886 int rxcycles; 887#endif 888 889 struct task rl_inttask; 890 891 int rl_txstart; 892 int rl_int_rx_act; 893 int rl_int_rx_mod; 894 uint32_t rl_flags; 895#define RL_FLAG_MSI 0x0001 896#define RL_FLAG_AUTOPAD 0x0002 897#define RL_FLAG_PHYWAKE_PM 0x0004 898#define RL_FLAG_PHYWAKE 0x0008 899#define RL_FLAG_JUMBOV2 0x0010 900#define RL_FLAG_PAR 0x0020 901#define RL_FLAG_DESCV2 0x0040 902#define RL_FLAG_MACSTAT 0x0080 903#define RL_FLAG_FASTETHER 0x0100 904#define RL_FLAG_CMDSTOP 0x0200 905#define RL_FLAG_MACRESET 0x0400 906#define RL_FLAG_MSIX 0x0800 907#define RL_FLAG_WOLRXENB 0x1000 908#define RL_FLAG_MACSLEEP 0x2000 909#define RL_FLAG_PCIE 0x4000 910#define RL_FLAG_LINK 0x8000 911}; 912 913#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 914#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 915#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 916 917/* 918 * register space access macros 919 */ 920#define CSR_WRITE_STREAM_4(sc, reg, val) \ 921 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 922#define CSR_WRITE_4(sc, reg, val) \ 923 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 924#define CSR_WRITE_2(sc, reg, val) \ 925 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 926#define CSR_WRITE_1(sc, reg, val) \ 927 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 928 929#define CSR_READ_4(sc, reg) \ 930 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 931#define CSR_READ_2(sc, reg) \ 932 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 933#define CSR_READ_1(sc, reg) \ 934 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 935 936#define CSR_BARRIER(sc, reg, length, flags) \ 937 bus_space_barrier(sc->rl_btag, sc->rl_bhandle, reg, length, flags) 938 939#define CSR_SETBIT_1(sc, offset, val) \ 940 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 941 942#define CSR_CLRBIT_1(sc, offset, val) \ 943 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 944 945#define CSR_SETBIT_2(sc, offset, val) \ 946 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 947 948#define CSR_CLRBIT_2(sc, offset, val) \ 949 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 950 951#define CSR_SETBIT_4(sc, offset, val) \ 952 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 953 954#define CSR_CLRBIT_4(sc, offset, val) \ 955 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 956 957#define RL_TIMEOUT 1000 958#define RL_PHY_TIMEOUT 2000 959 960/* 961 * General constants that are fun to know. 962 * 963 * RealTek PCI vendor ID 964 */ 965#define RT_VENDORID 0x10EC 966 967/* 968 * RealTek chip device IDs. 969 */ 970#define RT_DEVICEID_8139D 0x8039 971#define RT_DEVICEID_8129 0x8129 972#define RT_DEVICEID_8101E 0x8136 973#define RT_DEVICEID_8138 0x8138 974#define RT_DEVICEID_8139 0x8139 975#define RT_DEVICEID_8169SC 0x8167 976#define RT_DEVICEID_8168 0x8168 977#define RT_DEVICEID_8169 0x8169 978#define RT_DEVICEID_8100 0x8100 979 980#define RT_REVID_8139CPLUS 0x20 981 982/* 983 * Accton PCI vendor ID 984 */ 985#define ACCTON_VENDORID 0x1113 986 987/* 988 * Accton MPX 5030/5038 device ID. 989 */ 990#define ACCTON_DEVICEID_5030 0x1211 991 992/* 993 * Nortel PCI vendor ID 994 */ 995#define NORTEL_VENDORID 0x126C 996 997/* 998 * Delta Electronics Vendor ID. 999 */ 1000#define DELTA_VENDORID 0x1500 1001 1002/* 1003 * Delta device IDs. 1004 */ 1005#define DELTA_DEVICEID_8139 0x1360 1006 1007/* 1008 * Addtron vendor ID. 1009 */ 1010#define ADDTRON_VENDORID 0x4033 1011 1012/* 1013 * Addtron device IDs. 1014 */ 1015#define ADDTRON_DEVICEID_8139 0x1360 1016 1017/* 1018 * D-Link vendor ID. 1019 */ 1020#define DLINK_VENDORID 0x1186 1021 1022/* 1023 * D-Link DFE-530TX+ device ID 1024 */ 1025#define DLINK_DEVICEID_530TXPLUS 0x1300 1026 1027/* 1028 * D-Link DFE-5280T device ID 1029 */ 1030#define DLINK_DEVICEID_528T 0x4300 1031#define DLINK_DEVICEID_530T_REVC 0x4302 1032 1033/* 1034 * D-Link DFE-690TXD device ID 1035 */ 1036#define DLINK_DEVICEID_690TXD 0x1340 1037 1038/* 1039 * Corega K.K vendor ID 1040 */ 1041#define COREGA_VENDORID 0x1259 1042 1043/* 1044 * Corega FEther CB-TXD device ID 1045 */ 1046#define COREGA_DEVICEID_FETHERCBTXD 0xa117 1047 1048/* 1049 * Corega FEtherII CB-TXD device ID 1050 */ 1051#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 1052 1053/* 1054 * Corega CG-LAPCIGT device ID 1055 */ 1056#define COREGA_DEVICEID_CGLAPCIGT 0xc107 1057 1058/* 1059 * Linksys vendor ID 1060 */ 1061#define LINKSYS_VENDORID 0x1737 1062 1063/* 1064 * Linksys EG1032 device ID 1065 */ 1066#define LINKSYS_DEVICEID_EG1032 0x1032 1067 1068/* 1069 * Linksys EG1032 rev 3 sub-device ID 1070 */ 1071#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 1072 1073/* 1074 * Peppercon vendor ID 1075 */ 1076#define PEPPERCON_VENDORID 0x1743 1077 1078/* 1079 * Peppercon ROL-F device ID 1080 */ 1081#define PEPPERCON_DEVICEID_ROLF 0x8139 1082 1083/* 1084 * Planex Communications, Inc. vendor ID 1085 */ 1086#define PLANEX_VENDORID 0x14ea 1087 1088/* 1089 * Planex FNW-3603-TX device ID 1090 */ 1091#define PLANEX_DEVICEID_FNW3603TX 0xab06 1092 1093/* 1094 * Planex FNW-3800-TX device ID 1095 */ 1096#define PLANEX_DEVICEID_FNW3800TX 0xab07 1097 1098/* 1099 * LevelOne vendor ID 1100 */ 1101#define LEVEL1_VENDORID 0x018A 1102 1103/* 1104 * LevelOne FPC-0106TX devide ID 1105 */ 1106#define LEVEL1_DEVICEID_FPC0106TX 0x0106 1107 1108/* 1109 * Compaq vendor ID 1110 */ 1111#define CP_VENDORID 0x021B 1112 1113/* 1114 * Edimax vendor ID 1115 */ 1116#define EDIMAX_VENDORID 0x13D1 1117 1118/* 1119 * Edimax EP-4103DL cardbus device ID 1120 */ 1121#define EDIMAX_DEVICEID_EP4103DL 0xAB06 1122 1123/* US Robotics vendor ID */ 1124 1125#define USR_VENDORID 0x16EC 1126 1127/* US Robotics 997902 device ID */ 1128 1129#define USR_DEVICEID_997902 0x0116 1130